Display panel mother board, preparation method thereof and evaporation equipment

Abstract

The invention provides a display panel mother board and a preparation method thereof and evaporation equipment, the display panel mother board comprises a substrate, a plurality of sub-panel groups, a first test bonding pad group, a second test bonding pad group and a baffle plate, the plurality of sub-panel groups are sequentially arranged along a first direction of the substrate, and each sub-panel group comprises a plurality of sub-panels, the plurality of sub-panels are sequentially arranged on the substrate along a second direction; a plurality of first test bonding pad groups are arranged, the plurality of first test bonding pad groups are connected with the plurality of sub-panels in a one-to-one correspondence manner, and the plurality of sub-panels in each sub-panel group receive a first test signal at the same time; and a plurality of second test bonding pad groups are arranged, the plurality of second test bonding pad groups and the plurality of sub-panel groups are arranged in a one-to-one correspondence manner, and the second test bonding pad groups are connected with the sub-panels in the corresponding sub-panel groups. According to the display panel mother board provided by the invention, the lighting test can be directly carried out on the second test bonding pad group after evaporation is completed, the time for confirming the evaporation effect is short, signal shunting is avoided, and the risk of abnormal lighting test is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a display panel mother board, a preparation method thereof, and an evaporation device. Background Art

[0002] Flat panel display devices based on technologies such as Organic Light Emitting Diode (OLED) and Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptop computers, and desktop computers due to advantages such as high picture quality, power saving, thin body, and wide application range, and have become the mainstream in display devices. In the process of preparing traditional display panels, the light-emitting pixel patterning is usually achieved through a Fine Metal Mask (FMM). The FMM technology is mature and has rich mass production experience. However, the FMM technology also has problems such as limited precision, high development cost, and long development cycle. The fine metal maskless technology eliminates the limitations of the traditional OLED process on the display screen size, resolution, and other screen body performances, and has the advantages of high performance, full-domain size, and agile delivery. Patents CN118251982A, CN116648095A, CN117062489A, CN118742138A, CN118678783A, CN118660598A, CN118675450A, CN118824188A, CN118781966A record the relevant content of the fine metal maskless technology for reference.

[0003] However, the process performance of current OLED display products needs to be improved. Summary of the Invention

[0004] In view of this, the purpose of the present disclosure is to provide a display panel mother board, a preparation method thereof, and an evaporation device to improve the test efficiency, avoid the shunting of the lighting test signal, and reduce the risk of abnormal lighting test.

[0005] To achieve the above purpose, the present disclosure discloses a display panel mother board. The display panel mother board includes a first edge extending in a first direction and a second edge extending in a second direction, the first direction being perpendicular to the second direction. The display panel mother board includes: A substrate; A sub-panel group. There are multiple sub-panel groups, and the multiple sub-panel groups are arranged in sequence along the first direction of the substrate. Each sub-panel group includes multiple sub-panels, and the multiple sub-panels in the same sub-panel group are arranged in sequence along the second direction on the substrate; The first test pad group, wherein a plurality of the first test pad groups are provided, and the plurality of the first test pad groups are respectively and correspondingly connected to the plurality of the sub-panels. The first test pad group is configured to input a first test signal to the corresponding sub-panel, and multiple sub-panels in each sub-panel group receive the first test signal simultaneously; The second test pad group, wherein a plurality of the second test pad groups are provided, and the plurality of the second test pad groups are respectively and correspondingly arranged with the plurality of the sub-panel groups. The second test pad group is simultaneously connected to the sub-panels in the corresponding sub-panel group, and the second test pad group is configured to input a second test signal different from the first test signal to the sub-panels in the corresponding sub-panel group.

[0006] Further, a plurality of signal lines are included, and the plurality of signal lines are respectively and correspondingly arranged with the plurality of the sub-panel groups, and the same signal line is simultaneously connected to the corresponding first test pad group and the second test pad group.

[0007] Further, each signal line includes a signal main line and a plurality of signal branch lines connected to the signal main line. The signal main line is connected to the second test pad group, and the plurality of signal branch lines are respectively and correspondingly connected to the plurality of the first test pad groups.

[0008] Further, the plurality of signal branch lines are arranged in parallel with each other, and the signal branch lines extend along a first direction. The plurality of signal branch lines are arranged in sequence along a second direction.

[0009] Further, the signal main line extends along the second direction, and the plurality of signal branch lines connected to the plurality of sub-panels in the same sub-panel group are connected to the same signal main line.

[0010] Further, the first test pad groups of the plurality of sub-panels arranged in the same row along the first direction are located in the same row.

[0011] Further, the second test pad group is located at both ends of the signal main line.

[0012] Further, the plurality of second test pad groups are located at positions close to the first edge, and the plurality of second test pad groups are arranged along the first direction. A plurality of second test pad groups connecting different signal main lines are arranged at intervals on the first edge; the second edge is adjacent to the first edge.

[0013] Further, the first test signal includes electric signals with different frequencies and different amplitudes, and / or the second test signal includes a constant voltage signal.

[0014] Further, a plurality of the sub-panel groups are arranged at equal intervals along a first direction.

[0015] Further, a plurality of the sub-panels are arranged at equal intervals along a second direction.

[0016] Further, the first test pad group is arranged in a rectangular array on the substrate.

[0017] Further, the materials of the first test pad group and the second test pad group include conductive metals; The conductive metal includes at least one of copper, silver, and aluminum.

[0018] A method for manufacturing the display panel mother board as described above, the display panel mother board includes a first edge and a second edge, and the manufacturing method includes the following steps: Using a baffle to block the second test pad group on the first edge of the display panel mother board; Performing evaporation coating on the blocked display panel mother board; After evaporation coating, removing the baffle and inputting a second test signal to the sub-panels in the corresponding sub-panel group through the second test pad group.

[0019] An evaporation coating device for evaporating the display panel mother board as described above, the evaporation coating device includes: An evaporation coating chamber; A support structure, the support structure is arranged in the evaporation coating chamber and is used for supporting the display panel mother board; An evaporation source, the evaporation source is arranged between a pair of the support structures and is used for evaporating the display panel mother board; A baffle, the baffle is configured to cover a plurality of second test pad groups on the first edge of the display panel mother board.

[0020] Compared with the prior art, after the evaporation coating and encapsulation of the display panel mother board provided by the present disclosure, lighting tests are performed on the sub-panel groups through the first test pads. Each sub-panel in each sub-panel group is connected in parallel, and each first test pad group corresponding to each sub-panel is connected to the same second test pad group. Each sub-panel in a column of sub-panels receives the first test signal simultaneously, effectively avoiding the shunting of the first test signal during the lighting test and reducing the risk of abnormal lighting tests. Description of the Drawings

[0021] To more clearly illustrate the technical solutions in the present disclosure or related technologies, the following will briefly introduce the drawings required for use in the embodiments or related technology descriptions. Obviously, the drawings in the following descriptions are only embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0022] Figure 1 It is a schematic diagram of the full-surface evaporation coating of the display panel mother board in the prior art; Figure 2 It is a schematic diagram of the direction of the lighting test signal in the display panel mother board in the prior art; Figure 3 It is a schematic cross-sectional view of a pixel structure in the sub-panel of the display panel mother board in the embodiment of the present application; Figure 4 It is a schematic diagram of the full-surface evaporation coating of the display panel mother board in the embodiment of the present application; Figure 5 It is a schematic diagram of the second test signal direction in the embodiment of the present application; Figure 6 It is a schematic diagram of the first test signal direction in the embodiment of the present application; Figure 7 It is a schematic diagram of the structure of the evaporation coating equipment in the embodiment of the present application; Figure 8 It is a schematic diagram of the evaporation coating process of the evaporation coating equipment in the embodiment of the present application. Detailed Embodiments

[0023] To make the purpose, technical solutions, and advantages of the present disclosure clearer, the following further details the present disclosure in combination with specific embodiments and with reference to the accompanying drawings.

[0024] It should be noted that unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the ordinary meaning understood by those of ordinary skill in the art to which the present disclosure belongs. The "first", "second", and similar terms used in the embodiments of the present disclosure do not indicate any order, quantity, or importance, but are only used to distinguish different components. Words such as "including" or "comprising" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0025] In the field of OLED (Organic Light-Emitting Diode) display technology, improving product resolution, reducing costs, and shortening the development cycle have always been important goals pursued by the industry. Traditional OLED manufacturing processes often use FMM (Fine Metal Mask) for RGB pixel preparation, but FMM has problems of high cost and long development cycle, seriously restricting the large-scale production and market competitiveness of OLED products. In recent years, an FMM-free RGB self-aligned pixelation technology has emerged, which has significant advantages, can achieve pixel-level encapsulation, effectively reduce the pixel definition layer gap (PDL Gap), and thus greatly improve the resolution of OLED products. However, there are still many deficiencies in the existing FMM-free RGB self-aligned pixelation technology in the manufacturing process.

[0026] In the light-emitting functional layer process of the existing FMM-free RGB self-aligned pixelation technology, after each pixel is evaporated and encapsulated, multiple processes such as yellow light, development, wet etching, and stripping need to be completed in sequence. After that, a lap impedance test is also required, and finally, it is shipped to the lighting station for the first lighting test. During the whole process, the evaporation evaluation cycle of one color is relatively long, ranging from 3 - 4 days at the shortest to 6 - 8 days at the longest. If the evaporation effect is not ideal, re-evaporation will further delay a large amount of time, seriously affecting production efficiency.

[0027] In order to improve the production efficiency of products using the FMM-free RGB self-aligned pixelation technology, the applicant studied the current manufacturing processes, such as Figure 1 、 Figure 2As shown in the figure, it is a schematic diagram of test points on an existing display panel mother board. Multiple unit test pad groups 101 and multiple lighting test pad groups 102 are arranged on the display panel mother board; the multiple lighting test pad groups 102 are connected to the sub-panels 210 one by one and are used to input a first test signal to the sub-panels 210 for lighting tests; the unit test pad groups 101 are arranged at both ends of multiple first test pad groups in the same row and are used to input a second test signal to the sub-panels 210 for unit tests. During evaporation, the unit test pad groups 101 are blocked by the baffle 500 to prevent evaporation materials from depositing on the unit test pad groups 101 during evaporation. Therefore, after evaporation is completed, the second test signal can be directly input through the unit test pad groups 101 for unit tests to test whether the light emission of the sub-panels 210 in the first direction X1 is normal, and the evaporation effect can be obtained in a timely manner, greatly improving production efficiency. However, there is a problem of signal shunt when the above display panel mother board is performing lighting tests. In the above related technology, when the display panel mother board is performing lighting tests, that is, a first test signal is input to the sub-panels 210 through the lighting test pad groups 102. In addition to flowing to the sub-panels 210 connected to the lighting test pad groups 102, the first test signal will also be shunted through the leads of the unit tests to other sub-panels 210 in the same second direction X2 as the sub-panels 210, resulting in the problem of signal shunt. And signal shunt easily leads to abnormal lighting tests, reducing production efficiency and being extremely prone to misjudgment.

[0028] Based on the above research findings of the applicant, a display panel mother board is proposed. See Figure 4, the mother board of the display panel includes a plurality of first test pad groups 300 and second test pad groups 400. The first test pad groups 300 are connected to the sub-panels 210 one by one. The first test pad groups 300 are used to input first test signals to the corresponding sub-panels 210, and multiple sub-panels 210 in each sub-panel group 200 receive the first test signals simultaneously; a plurality of second test pad groups 400 are arranged corresponding to the plurality of sub-panel groups 200 one by one. The second test pad groups 400 are connected to the sub-panels 210 in the corresponding sub-panel group 200 at the same time. The second test pad groups 400 are used to input second test signals to the sub-panels 210 in the corresponding sub-panel group 200. Compared with the mother board of the display panel in the related art provided by the present application, the position of the second test pads 400 is adjusted, and it is realized that the unit test can be carried out by inputting the second test signal to the sub-panel group 200 through the second test pads 400. During evaporation, the baffle 500 shields the second test pad groups 400 to prevent the evaporation material from being deposited on the second test pad groups 400 during evaporation. After evaporation is completed, the second test signal can be directly input through the second test pad groups 400 for unit test to test whether the light-emitting condition of the sub-panel group 200 in the second direction X2 is normal, and the evaporation effect can be obtained in time, greatly improving the production efficiency. At the same time, the problem of signal shunting existing in the mother board of the display panel in the related art is also solved. After evaporation and encapsulation are completed, the sub-panel group 200 is subjected to a lighting test through the first test pad groups 300. Since each sub-panel 210 in each sub-panel group 200 is connected in parallel, and the first test pad group 300 corresponding to each sub-panel 210 is connected to the same second test pad group 400, each sub-panel 210 in a column of sub-panels 210 can receive the first test signal simultaneously, effectively avoiding the shunting of the lighting test signal and reducing the risk of abnormal lighting test. Among them, the unit test is used to test whether the light-emitting function of the sub-panel group 200 is normal through the second test pad groups 400. One second test pad group 400 tests one sub-panel group 200, and one second test pad group 400 includes at least one second test pad; the lighting test is used to test whether the light-emitting function of each sub-panel 210 is normal through the first test pad groups 300. One first test pad group 300 tests one sub-panel 210, and one first test pad group 300 includes at least one first test pad.

[0029] Figure 3 It is a schematic cross-sectional view of a pixel structure in a sub-panel of the mother board of the display panel provided by an embodiment of the present invention. Refer to Figure 3, Exemplarily, the sub-panel may include: a substrate 10, a pixel definition layer PDL located on one side of the substrate 10, and an isolation structure 50 located on the side of the pixel definition layer PDL away from the substrate 10. The pixel definition layer PDL encloses a plurality of pixel openings, and the isolation structure 50 encloses a plurality of isolation openings, with each pixel opening corresponding to each isolation opening one by one. The display panel mother board may include at least one sub-panel, and the sub-panel is composed of a pixel circuit and a light-emitting device OLED. The pixel circuit may be disposed in the substrate 10; at least part of the light-emitting device OLED is disposed in the pixel opening, including a first electrode 41, a light-emitting layer 42, and a second electrode 43 stacked in sequence along the direction away from the substrate 10. Exemplarily, the first electrode 41 of the light-emitting device OLED is its anode, and the second electrode 43 is its cathode. Among them, based on the isolation effect of the isolation structure 50, a self-alignment pixelization technology without a fine metal mask (FMM) can be realized. Specifically, the isolation structure 50 may include a first isolation portion 51 and a second isolation portion 52 stacked in sequence along the direction away from the substrate 10. The orthographic projection of the first isolation portion 51 on the substrate 10 is located within the orthographic projection of the second isolation portion 52 on the substrate 10, and the area of the orthographic projection of the first isolation portion 51 on the substrate 10 is smaller than the area of the orthographic projection of the second isolation portion 52 on the substrate 10. Based on this setting of the isolation structure 50, each light-emitting layer 42 and each second electrode 43 can be evaporated into the corresponding pixel opening without the need for a fine metal mask. And based on the isolation effect of the isolation structure 50, a pixel encapsulation structure 44 can be formed on the side of each second electrode 43 away from the substrate 10, so that each light-emitting device OLED is independently encapsulated.

[0030] Figure 4 is a schematic diagram of the entire surface evaporation of a display panel mother board provided by an embodiment of the present invention. Refer to Figure 4, Exemplarily, a display panel mother board, the display panel mother board includes a first edge 110 extending along a first direction X1 and a second edge extending along a second direction X2, and the first direction X1 is perpendicular to the second direction X2. The display panel mother board includes a substrate 100, a sub-panel group 200, a first test pad group 300, and a second test pad group 400. Among them, the substrate 100 is used to provide a support structure for a certain component included in the display panel mother board; the sub-panel group 200 is the core component for the display panel mother board to achieve image display. There are multiple sub-panel groups 200, and the multiple sub-panel groups 200 are arranged in sequence along the first direction X1 of the substrate 100. Moreover, the sub-panel group 200 includes multiple sub-panels 210, and the multiple sub-panels 210 within the same sub-panel group 200 are arranged in sequence along the second direction X2 perpendicular to the first direction X1 on the substrate 100; there are multiple first test pad groups 300, and the multiple first test pad groups 300 are connected to the multiple sub-panels 210 in a one-to-one correspondence. The first test pad group 300 is used to input a first test signal to the corresponding sub-panel 200, and the multiple sub-panels 210 in each sub-panel group receive the first test signal simultaneously; there are multiple second test pad groups 400, and the multiple second test pad groups 400 are arranged in a one-to-one correspondence with the multiple sub-panel groups 200. The second test pad group 400 is simultaneously connected to the sub-panels 210 in the corresponding sub-panel group 200. The second test pad group 400 is used to input a second test signal different from the first test signal to the sub-panels 210 in the corresponding sub-panel group 200.

[0031] Specifically, the multiple sub-panel groups 200 are arranged at equal intervals along the first direction X1, and the multiple sub-panels 210 are arranged at equal intervals along the second direction X2, ensuring that the multiple sub-panels 210 are arranged on the substrate 100 in a rectangular array, thereby ensuring the overall uniformity of the display panel mother board. In this embodiment, the substrate 100 is rectangular, and the first edge 110 of the substrate 100 extends along the first direction X1. Among them, the display panel mother board includes a first edge 110 and a second edge. Multiple second test pad groups for connecting different signal main lines are arranged at intervals on the first edge 110; the multiple second test pad groups 400 are located at positions close to the first edge 110, and the multiple second test pad groups 400 are arranged in sequence along the first direction X1. Multiple second test pad groups 400 for connecting different signal main lines 411 are arranged at intervals on the first edge 110; the second edge is adjacent to the first edge.

[0032] For example, there are eight sub-panel groups 200, and the eight sub-panel groups 200 are arranged in sequence at equal intervals along the first direction X1 of the substrate 100. Each sub-panel group 200 includes four sub-panels 210 arranged in sequence along the second direction X2.

[0033] During the lighting test, a lighting test device needs to be matched. The lighting test device includes multiple test heads, and the multiple test heads are arranged in one-to-one correspondence with the first test pad groups 300 of each sub-panel 210 in the sub-panel group 200. When the lighting test is performed, the lighting test device can test each sub-panel 210 in the sub-panel group 200 simultaneously. Also, since each sub-panel 210 in the same sub-panel group 200 is connected in parallel, when the sub-panels 210 in the same sub-panel group 200 are tested for lighting simultaneously, there will be no problem of abnormal lighting caused by signal shunting. Specifically, in this embodiment, a sub-panel group 200 includes four sub-panels 210 arranged in sequence along the second direction X2, and the lighting test device includes four test heads arranged in sequence along the second direction X2. During the test process, the four test heads are simultaneously docked with the first test pad groups 300 of the four sub-panels 210 in the sub-panel group 200, and each sub-panel 210 in the same sub-panel group 200 is connected to each other. Therefore, there will be no problem of abnormal lighting caused by shunting among the four sub-panels 210 arranged in sequence along the second direction X2 during the lighting test. Among them, the first test pad group 300 is used for testing to test the lighting function and normality of each sub-panel.

[0034] The substrate 100 plays a key role in the performance and stability of the entire display panel mother board. For the substrate 100 used in this display panel mother board, a glass material with good flatness, insulation, and thermal stability is selected in terms of material. This is because the glass material can provide a stable attachment foundation for subsequent components such as sub-panel groups and test pads, ensuring that the relative positions of the components remain precise during the manufacturing and use of the display panel mother board, and avoiding display abnormalities caused by deformation of the substrate 100.

[0035] Figure 6This is the schematic diagram of the first test signal path in the embodiments of the present application. The first test pad group 300 is used to input the first test signal to the corresponding sub-panel 200 during the lighting test of the display panel mother board, for detecting the light-emitting performance of the sub-panel. Multiple first test pad groups 300 are connected to multiple sub-panels 210 in a one-to-one correspondence. This precise correspondence ensures that each sub-panel 210 can independently receive the test signal, thus realizing the individual detection of each sub-panel 210. The first test pad group 300 is made of metal materials with good electrical conductivity, such as copper, silver, aluminum, etc. These metal materials have low resistance and can effectively reduce the loss of the test signal during transmission, ensuring that the test signal can be accurately and stably transmitted to the sub-panel 210. In terms of manufacturing process, the first test pad group 300 is usually fabricated by photolithography and etching processes. First, a layer of photoresist is coated on the substrate 100, and then the designed pattern of the first test pad group is transferred to the photoresist by photolithography technology. Then, the unwanted metal layer is removed by the etching process, thus forming the precise structure of the first test pad group 300. During the etching process, it is necessary to strictly control the etching time and the concentration of the etching solution to ensure the dimensional accuracy and edge quality of the first test pad group 300. The accuracy of the photolithography process directly affects the size and shape of the first test pad group, while the control of the etching process is related to the surface flatness and edge perpendicularity of the pads. If the etching time is too long or the concentration of the etching solution is too high, it may cause the pad size to become smaller or the edge to be serrated; if the etching time is too short or the concentration of the etching solution is too low, there may be residual metal layers, affecting the conductivity and test accuracy of the pads.

[0036] The layout of the first test pad group 300 on the substrate 100 adopts a rectangular array arrangement. This layout has several advantages. On the one hand, since the sub-panels 210 are arranged on the substrate 100 in a rectangular array, the rectangular array arrangement of the first test pad group 300 is convenient for connecting with the sub-panels 210, ensuring the accuracy and stability of the connection. On the other hand, the rectangular array arrangement is beneficial to the wiring and transmission of the test signal, enabling the test signal to be evenly distributed to each first test pad group 300, improving the efficiency and accuracy of the test. With the continuous development of display technology, the performance requirements for the first test pad group are also getting higher and higher. To meet the higher-precision test requirements, a special conductive polymer can be coated on the surface of the first test pad group. These conductive polymers not only have good electrical conductivity but also can enhance the electrical connection stability between the test pad and the sub-panel, reduce the noise interference during signal transmission, and further improve the test accuracy.

[0037] During the testing process, the first test signal usually adopts electrical signals with different frequencies and amplitudes. By inputting different first test signals to the sub-panel 210, parameters such as the light-emitting performance, response speed, current-voltage characteristics of the sub-panel can be detected. For example, by inputting a pulse signal with a specific frequency, the response time of the sub-panel can be detected, that is, the time delay from receiving the signal to starting to emit light. By analyzing these test data, problems existing in the sub-panel, such as uneven light-emitting brightness, slow response speed, etc., can be discovered in time, so as to conduct quality screening and optimization on the mother board of the display panel.

[0038] The second test pad group 400 is used to be set corresponding to multiple sub-panel groups 200 one by one, and is simultaneously connected to the sub-panels 210 in the corresponding sub-panel group 200. Its function is to input a second test signal to the sub-panels 210 in the corresponding sub-panel group 200 for overall performance testing of the sub-panel group. Refer to Figure 5 , during unit testing, the second test signal is transmitted to the sub-panels 210 in the corresponding sub-panel group 200 through the second test pad group 400. Similar to the first test pad group 300, the material of the second test pad group 400 also selects at least one of metals with good electrical conductivity, such as copper, silver, and aluminum. In terms of the connection method, the second test pad group 400 is electrically connected to the sub-panel 210 through the signal line 410. Among them, the second test pad group 400 is used for unit testing to test whether the light-emitting function of each sub-panel is normal.

[0039] In order to improve the test accuracy and reliability of the second test pad group 400, the design of the second test pad group 400 can be optimized. For example, a multi-layer metal structure can be adopted. On the basis of the traditional metal pad, one or more metal layers with special properties are added. For example, a layer of gold (Au) is plated on the surface of the copper pad. Gold has good oxidation resistance and electrical conductivity, which can effectively improve the service life and signal transmission performance of the pad. At the same time, some tiny protrusions or grooves can also be set on the surface of the pad to increase the contact area between the pad and the test fixture and improve the connection stability. In addition, intelligent test pad technology can also be adopted. Some sensors or processors are integrated in the second test pad group 400 to monitor the transmission situation of the test signal and the performance parameters of the sub-panel in real time, and conduct preliminary analysis and processing on the test results to improve the intelligent level of the test.

[0040] The signal line 410 connects the second test pad group 400 and the first test pad group 300. Multiple signal lines 410 are set corresponding to multiple sub-panel groups 200 one by one to ensure that each sub-panel group 200 can independently receive the test signal.

[0041] Such as Figure 5As shown, each signal line 410 includes a signal main line 411 and a plurality of signal branch lines 412 connected to the signal main line 411. The signal main line 411 is connected to the second test pad group 400, and the plurality of signal branch lines 412 are connected to the plurality of first test pad groups 300 in a one-to-one correspondence. This structural design enables the second test signal to start from the second test pad group 400, be transmitted through the signal main line 411 to each signal branch line 412, and finally be transmitted to the sub-panel 210.

[0042] As Figure 5 shown, the signal branch lines 412 are arranged in parallel with each other, and the parallel connection method has multiple advantages. First of all, the parallel connection can ensure that each first test pad group 300 can obtain the same test signal voltage, avoiding signal differences caused by different signal transmission paths. Secondly, the parallel connection improves the reliability of test signal transmission to a certain extent. When a certain signal branch line 412 fails, the other branch lines can still transmit signals normally, without affecting the entire test process.

[0043] As Figure 5 shown, the signal branch lines 412 extend along the first direction X1, and the plurality of signal branch lines 412 are arranged in sequence along the second direction X2. This layout method matches the arrangement method of the sub-panel group 200 and the sub-panel 210, which is beneficial to the efficient transmission of test signals. The signal branch lines 412 extending along the first direction X1 can reduce the length of signal transmission and reduce the loss during signal transmission. The signal branch lines 412 arranged in sequence along the second direction X2 are convenient for connecting with the first test pad group 300, ensuring the accuracy and stability of the connection.

[0044] In addition, the signal main line 411 extends along the second direction X2. The plurality of signal branch lines 412 connected to the plurality of sub-panels 210 within the same sub-panel group 200 are connected to the same signal main line 411, and its length needs to be matched according to the width of the display panel mother board. The longer signal main line 411 can connect all the sub-panels 210 in a sub-panel group 200 at the same time. The second test pad group 400 is located at both ends of the signal main line 411 and is also located at the first edge 110 of the substrate 100, which is convenient for being protected by the baffle 500 during the evaporation process and reducing external interference. This layout also simplifies the wiring complexity of the signal lines and improves the overall test efficiency. By precisely controlling the length and position of the signal lines, the stability and consistency of the test signals are ensured, further optimizing the performance of the display panel mother board. In addition, the signal main line 411 is made of a highly conductive material, effectively reducing signal transmission loss and increasing signal transmission speed. The precise length design and material selection ensure the stability and efficiency of the test signals, further improving the overall performance and reliability of the display panel mother board.

[0045] In this embodiment, a plurality of signal lines 410 are provided in one-to-one correspondence with a plurality of sub-panel groups 200, and the same signal line 410 is simultaneously connected to the corresponding first test pad group 300 and second test pad group 400. In terms of the connection method, the second test pad group 400 is electrically connected to the sub-panel 210 through the signal line 410. The second test pad group 400 is located at both ends of the signal main line 411 and at the position of the first edge 110 of the substrate 100. Among them, the display panel mother board includes a first edge 110 and a second edge. A plurality of second test pad groups 400 are located close to the first edge 110, and the plurality of second test pad groups 400 are arranged along the first direction X1. A plurality of second test pad groups 400 for connecting different signal main lines 411 are arranged at intervals on the first edge 110; the second edge is adjacent to the first edge 110. This position design has multiple considerations. First, setting the second test pad group 400 at a position close to the first edge 110 of the substrate 100 facilitates the connection of the test interface during the manufacturing process of the display panel mother board. On the production line, the test equipment can be quickly and accurately connected to the second test pad group 400 located on the first edge 110 through a special test fixture, improving the test efficiency. During the test process, the type and parameters of the second test signal are set according to different test purposes. For example, when performing the brightness uniformity test of the sub-panel group, the second test signal can be a constant voltage signal. By detecting the luminous brightness of each sub-panel 210 under this voltage signal, it is judged whether the brightness uniformity of the sub-panel group meets the requirements. If it is found that the luminous brightness of a certain sub-panel is significantly different from that of other sub-panels, it indicates that there may be a problem with this sub-panel and further inspection and repair are required.

[0046] In this embodiment, the baffle 500 is configured at the position of the first edge 110 of the substrate 100, and its main function is to block the second test pad group 400. During the evaporation process of the display panel mother board, the baffle 500 plays a key role. When the entire surface of the display panel mother board is evaporated, the baffle 500 can effectively block the second test pad group 400, preventing the evaporation material from depositing on the second test pad group 400, thereby ensuring the conductivity and test accuracy of the second test pad group 400. The material selection of the baffle 500 needs to consider multiple factors, such as high temperature resistance, chemical stability, and mechanical strength. Usually, the baffle 500 is made of ceramic material or metal material. Ceramic materials have good high temperature resistance and chemical stability, can withstand high temperatures and chemical gas erosion during the evaporation process, and will not contaminate the test pads and other components. Metal materials have higher mechanical strength, which can ensure the stability and reliability of the baffle 500 during use. When designing the shape of the baffle, it is necessary to consider the outer shape of the display panel mother board and the position of the second test pad group to ensure that the baffle can completely cover the second test pad group.

[0047] During the production process of the display panel mother board, the installation and disassembly of the baffle 500 are carried out in accordance with the operating procedures. Before the evaporation process, the baffle 500 needs to be accurately installed at the position of the first edge 110 of the substrate 100 to ensure its shielding effect on the second test pad group 400. During the installation process, special fixtures or positioning devices are required to ensure the accurate position of the baffle. Specifically, a camera can be installed on the fixture, and through the camera, it can be accurately judged whether the baffle completely shields the second test pad group. After the evaporation is completed, the baffle 500 is disassembled, and damage to the display panel mother board should be avoided during disassembly. After each use, the baffle 500 can be cleaned and inspected to ensure that there is no residual evaporation material and impurities on its surface to ensure its performance during the next use. With the continuous progress of the manufacturing process of the display panel mother board, the performance requirements for the baffle are also constantly increasing. For example, in some high-precision evaporation processes, extremely high requirements are placed on the shielding accuracy of the baffle. To meet this requirement, laser processing technology can be used to manufacture the edge of the baffle 500. By precisely controlling the energy and processing parameters of the laser, a very smooth and precise edge can be obtained, effectively improving the shielding effect of the baffle 500. In addition, a self-cleaning coating can be applied to the surface of the baffle. Under light conditions, this coating can decompose the organic impurities on the surface, keep the baffle 500 clean, reduce the number of cleaning times, and improve production efficiency.

[0048] During operation, first, when the entire surface of the display panel mother board is evaporated, the baffle 500 is used to shield the second test pad group 400 at the first edge 110 of the substrate 100 to prevent the evaporation material from depositing on the second test pad group 400 during evaporation. In this way, unit testing can be directly carried out after evaporation is completed, quickly judging the evaporation effect, reducing the time cost of waiting for the test results, and improving production efficiency. And after the subsequent processes are completed, the lighting test is normally carried out. Since each sub-panel 200 in each group of sub-panel groups 200 is connected in parallel, and the first test pad group corresponding to each sub-panel is connected to the same second test pad group, each sub-panel 210 in a column of sub-panels 210 receives the first test signal simultaneously, effectively avoiding the shunt of the first test signal in the lighting test, reducing the risk of abnormal lighting test, and ensuring the accuracy of the test results. In addition, the design of the baffle 500 also needs to consider the high-temperature resistance performance to adapt to the high-temperature environment during the evaporation process, prevent deformation or damage, and thus further improve the overall manufacturing quality of the display panel mother board. In a high-temperature environment, the material selection of the baffle 500 is particularly crucial, and materials with high-temperature resistance and strong stability, such as ceramics or special alloys, need to be selected. At the same time, its structural design should take into account the heat dissipation performance to avoid performance degradation caused by excessive temperature. Through optimized design, the baffle 500 can not only effectively shield the pads but also remain stable during the high-temperature evaporation process, ensuring the smooth progress of the display panel mother board manufacturing process.

[0049] Based on the same inventive concept, the present invention further provides a method for preparing a display panel mother board as described above. The preparation method specifically includes the following steps: Use a baffle 500 to block the second test pad group 400 located on the first edge 110 of the display panel mother board; Perform evaporation coating on the blocked display panel mother board; After evaporation coating, remove the baffle 500 and input a second test signal to the sub-panel 210 in the corresponding sub-panel group 200 through the second test pad group 400.

[0050] In this application, during evaporation coating, the baffle 500 blocks the second test pad group 400, preventing evaporation coating materials from depositing on the second test pad group 400 during evaporation coating. After evaporation coating is completed, a second test signal can be directly input through the second test pad group 400 for unit testing to test whether the light emission of the sub-panel group 200 in the second direction X2 is normal, timely obtain the evaporation coating effect, and greatly improve production efficiency.

[0051] Based on the same inventive concept, as Figure 7 shown, the present invention further provides an evaporation coating device for evaporating the display panel mother board as described above. The evaporation coating device includes: an evaporation coating chamber 10, a support structure 30, an evaporation coating source 20, and a baffle 500; the support structure 30 is arranged in the evaporation coating chamber 10 for supporting the display panel mother board; the evaporation coating source 20 is arranged between a pair of support structures 30 for evaporating the display panel mother board; The baffle 500 is configured to cover a plurality of second test pad groups 400 on the first edge 110 of the display panel mother board.

[0052] It should be noted that the evaporation coating source 20 includes a rotatable nozzle, and the nozzle can control the ejection direction and range of the evaporation coating materials. As Figure 8 shown, in this embodiment, the evaporation coating source 20 can evaporate the display panel mother boards on the support structures 30 on both sides simultaneously or separately through the rotatable nozzle, improving the evaporation coating efficiency. The evaporation coating source 20 can be movably arranged to improve the uniformity of evaporation coating and effectively improve the evaporation coating quality. By using the baffle 500 to block the second test pad group 400 during evaporation coating, it is possible to prevent evaporation coating materials from depositing on the second test pad group 400 during evaporation coating, so as to directly perform unit testing after evaporation coating is completed, timely judge the evaporation coating effect, reduce the time cost of waiting for test results, and improve production efficiency.

[0053] Note that some embodiments of the present disclosure have been described above. Other embodiments are within the scope of the appended claims. In some cases, the acts or steps recited in the claims may be performed in a different order than in the above embodiments and still achieve the desired results. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0054] Embodiments of the present disclosure are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A display panel mother board, characterized in that, The display panel mother board includes a first edge extending in a first direction and a second edge extending in a second direction, the first direction being perpendicular to the second direction. The display panel mother board includes: a substrate; a sub-panel group, with multiple sub-panel groups provided. The multiple sub-panel groups are arranged in sequence along the first direction of the substrate, and each sub-panel group includes multiple sub-panels. The multiple sub-panels within the same sub-panel group are arranged in sequence along the second direction and disposed on the substrate; a first test pad group, with multiple first test pad groups provided. The multiple first test pad groups are connected to the multiple sub-panels in a one-to-one correspondence. The first test pad group is used to input a first test signal to the corresponding sub-panel, and the multiple sub-panels in each sub-panel group receive the first test signal simultaneously; a second test pad group, with multiple second test pad groups provided. The multiple second test pad groups are provided in a one-to-one correspondence with the multiple sub-panel groups. The second test pad group is simultaneously connected to the sub-panels in the corresponding sub-panel group. The second test pad group is used to input a second test signal different from the first test signal to the sub-panels in the corresponding sub-panel group.

2. The display panel mother board according to claim 1, characterized in that, It further includes multiple signal lines, the multiple signal lines being electrically connected to the multiple sub-panel groups, and the same signal line being simultaneously connected to the corresponding first test pad group and second test pad group.

3. The display panel mother board according to claim 2, characterized in that, Each signal line includes a signal main line and multiple signal branch lines connected to the signal main line. The signal main line is connected to the second test pad group, and the multiple signal branch lines are connected to the multiple first test pad groups in a one-to-one correspondence.

4. The display panel mother board according to claim 3, characterized in that, The multiple signal branch lines are arranged in parallel with each other, the signal branch lines extend along the first direction, and the multiple signal branch lines are arranged in sequence along the second direction.

5. The display panel mother board according to claim 3, characterized in that, The signal main line extends along the second direction, and the multiple signal branch lines connected to the multiple sub-panels within the same sub-panel group are connected to the same signal main line.

6. The display panel mother board according to claim 3, characterized in that, The second test pad group is located at both ends of the signal main line.

7. The display panel mother board according to claim 3, characterized in that, The multiple second test pad groups are located at positions close to the first edge. The multiple second test pad groups are arranged in sequence along the first direction, and multiple second test pad groups connecting different signal main lines are arranged at intervals on the first edge; the second edge is adjacent to the first edge.

8. The display panel mother board according to claim 1, characterized in that, The first test pad groups of the multiple sub-panels arranged in the same row along the first direction are located in the same row.

9. The display panel mother board according to claim 1, characterized in that, The first test signal includes electrical signals with different frequencies and different amplitudes, and / or the second test signal includes a constant voltage signal.

10. The display panel mother board according to claim 1, characterized in that, The multiple sub-panel groups are arranged at uniform intervals along the first direction.

11. The display panel mother board according to claim 1, characterized in that, The multiple sub-panels are arranged at uniform intervals along the second direction.

12. The display panel mother board according to claim 1, characterized in that, The first test pad group is arranged in a rectangular array on the substrate.

13. The display panel mother board according to claim 1, characterized in that, The materials of the first test pad group and the second test pad group include conductive metal; the conductive metal includes at least one of copper, silver, and aluminum.

14. A method for preparing a display panel mother board according to any one of claims 1-13, characterized in that, The preparation method includes the following steps: Use a baffle to block the second test pad group located on the first edge of the display panel mother board; Perform evaporation coating on the blocked display panel mother board; After evaporation coating, remove the baffle and input a second test signal to the sub-panel in the corresponding sub-panel group through the second test pad group.

15. A vapor deposition device, characterized in that, For evaporating the display panel mother board according to any one of claims 1-13, the evaporation coating device includes: An evaporation coating chamber; A support structure, which is arranged in the evaporation coating chamber and used to support the display panel mother board; An evaporation source, which is arranged between a pair of the support structures and used to perform evaporation coating on the display panel mother board; A baffle, which is configured to cover a plurality of second test pad groups on the first edge of the display panel mother board.

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