Common-source inductance extraction method, system and equipment based on double-pulse test and medium

Abstract

The embodiment of the invention provides a common-source inductance extraction method, system and equipment based on double-pulse test and a medium, and the method comprises the steps: firstly, carrying out the first detection of a constructed first half-bridge circuit, determining a prediction adjustment range of a gate drive resistor Rg through a first detection result, and carrying out the adjustment, and obtaining an adjusted second half-bridge circuit; and then carrying out second detection on the second half-bridge circuit, and extracting the common-source inductance by utilizing the detected gate-source voltage measurement value and gate-source voltage filtering value of the active tube and the change rate of the drain current. According to the embodiment of the invention, the power device is excited by using double-pulse signals, and the common-source inductance is extracted by combining the change of drain current and grid voltage. The method has the advantages of high precision, low cost, no need of disassembly and packaging and the like, and is particularly suitable for common-source inductance measurement of high-frequency power devices.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of the application of wide-bandgap power devices in power electronics, and particularly to a method, system, device and medium for extracting the common-source inductance based on double-pulse testing. Background Art

[0002] Wide-bandgap power devices, such as SiC MOSFETs and GaN-HEMTs (High Electron Mobility Transistors), have occupied a core position in high-power density power converters due to their excellent high-frequency switching performance and low on-resistance. Compared with traditional silicon-based devices, they offer faster switching speeds and lower conduction losses. However, with the increase in switching frequency, parasitic inductance, especially the common-source inductance (L s ), becomes particularly critical to the device performance. The common-source inductance is the parasitic inductance existing between the power loop and the drive loop, and its magnitude is affected by device packaging, layout and wiring design. In wide-bandgap semiconductor devices, the influence of the common-source inductance is particularly significant.

[0003] In high-frequency switching operations, the problems caused by the common-source inductance are particularly prominent, mainly manifested in three aspects: First, the common-source inductance will generate voltage noise during the switching process, and these noises will be superimposed on the DC bus voltage, increasing the voltage stress of the device; Second, the noise voltage will interfere with the drive signal, resulting in a decrease in the on-voltage, a reduction in the on-speed, and an increase in the on-loss; Finally, the noise voltage may also cause mis-triggering of the device, damaging its switching characteristics. Therefore, in order to improve the performance of high-frequency converters, accurately measuring the common-source inductance becomes crucial. By accurately evaluating the common-source inductance, the device design can be optimized, voltage noise can be reduced, the on-speed can be increased, losses can be decreased, and mis-triggering can be avoided, thus achieving more efficient and reliable power conversion.

[0004] Currently, the extraction of the common-source inductance faces a series of challenges. First, the source voltage is usually hidden inside the semiconductor package, making it difficult to directly measure the voltage across the common-source inductance. Second, the common-source inductance is not always in the form of a concentrated inductance, and the mutual inductance between the gate circuit and the power circuit may also constitute an equivalent common-source inductance, which increases the complexity of measurement. In addition, the common-source inductance cannot be simply defined by the stray inductance of the wiring path, making it difficult to effectively apply conventional measurement methods such as network analyzers, TDR (Time domain reflectometry) or resonance methods. These factors make the accurate extraction of the common-source inductance a challenging task.

[0005] At present, many studies rely on Finite Element Analysis (FEA) to extract the common-source inductance. However, this method requires accurate internal structure information of the device package, which is often not provided by manufacturers, limiting the application of FEA. To overcome this limitation, researchers have proposed an experimental-based method to measure the common-source inductance without disassembling the package, which is applicable to installed devices. This method uses a signal generator to provide a high-frequency current signal, but its application range is limited due to the high-frequency requirements and expensive equipment. Recent studies have used a double-pulse circuit to generate a high-frequency oscillating current signal to measure the common-source inductance of power devices. Although this method can effectively measure the common-source inductance, it requires additional circuit design, increasing the complexity of implementation. Summary of the Invention

[0006] To this end, embodiments of the present invention provide a method, system, device, and medium for extracting common-source inductance based on double-pulse testing to solve the technical problems in the prior art that the extraction of common-source inductance is easily interfered with, resulting in inability to ensure accuracy and poor applicability.

[0007] To achieve the above object, embodiments of the present invention provide the following technical solutions:

[0008] According to the first aspect of the embodiments of the present invention, embodiments of the present application provide a method for extracting common-source inductance based on double-pulse testing, the method comprising:

[0009] Construct a first half-bridge circuit including parasitic parameters using a passive transistor Q1 and an active transistor Q2;

[0010] Perform a first detection on the first half-bridge circuit to obtain a first detection result;

[0011] Determine a predicted adjustment range using the first detection result;

[0012] Adjust the gate drive resistance R of the active transistor Q2 based on the predicted adjustment range g to obtain an adjusted second half-bridge circuit;

[0013] Perform a second detection on the second half-bridge circuit to obtain a second detection result;

[0014] Extract the common-source inductance L of the active transistor Q2 based on the second detection result s The common-source inductance L s The target extraction formula is:

[0015]

[0016] where V gs_mea is the measured gate-source voltage of the active transistor Q2, V gs_filis the filtered value of the gate-source voltage of the active transistor Q2, is the drain current i of the active transistor Q2 d change rate.

[0017] Further, a first detection is performed on the first half-bridge circuit to obtain a first detection result, including:

[0018] Obtain the sum of the gate parasitic inductance L g and the common-source inductance L s of the active transistor Q2 in the first half-bridge circuit to obtain a first parameter;

[0019] Obtain the gate-source parasitic capacitance C gs and the gate-drain parasitic capacitance C gd of the active transistor Q2 in the first half-bridge circuit;

[0020] Calculate the sum of the gate-source parasitic capacitance C gs and the gate-drain parasitic capacitance C gd of the active transistor Q2 to obtain the input capacitance C iss of the active transistor Q2 as a second parameter;

[0021] Based on a preset condition, detect at least one oscillation frequency value F caused by the power loop in the oscillation stage during the switching process as a third parameter.

[0022] Further, use the first detection result to determine a prediction adjustment range, including:

[0023] Use the first parameter and the second parameter to calculate a first threshold K1 according to a first formula, and the first formula is:

[0024]

[0025] Based on the first threshold K1, determine the first adjustment range of the gate drive resistance R g of the active transistor Q2, and the first adjustment range is that the gate drive resistance R g is greater than the first threshold K1;

[0026] Use the first parameter, the second parameter, and each third parameter to calculate corresponding second thresholds K2 according to a second formula respectively, and the second formula is:

[0027]

[0028] Select the maximum value from each second threshold K2 as a third threshold K3;

[0029] Based on the third threshold K3, determine the gate drive resistance R gThe second adjustment range, where the second adjustment range is the gate drive resistor R g is greater than the third threshold K3;

[0030] Obtain the intersection of the first adjustment range and the second adjustment range as the third adjustment range;

[0031] Output the third adjustment range as the predicted adjustment range.

[0032] Further, using the first detection result to determine the predicted adjustment range includes:

[0033] Calculate the first threshold K1 using the first parameter and the second parameter according to the first formula, where the first formula is:

[0034]

[0035] Based on the first threshold K1, determine the first adjustment range of the gate drive resistor R g of the active transistor Q2, where the first adjustment range is that the gate drive resistor R g is greater than the first threshold K1;

[0036] Calculate the corresponding second thresholds K2 respectively using the first parameter, the second parameter and each third parameter according to the second formula, where the second formula is:

[0037]

[0038] Select the maximum value from each of the second thresholds K2 as the third threshold K3;

[0039] Based on the third threshold K3, determine the second adjustment range of the gate drive resistor R g of the active transistor Q2, where the second adjustment range is that the gate drive resistor R g is greater than the third threshold K3;

[0040] Based on a preset fourth threshold K4, determine the fourth adjustment range of the gate drive resistor R g of the active transistor Q2, where the fourth adjustment range is that the gate drive resistor R g is less than the fourth threshold K4;

[0041] Obtain the intersection of the first adjustment range, the second adjustment range and the fourth adjustment range as the fifth adjustment range;

[0042] Output the fifth adjustment range as the predicted adjustment range.

[0043] Further, perform a second detection on the second half-bridge circuit to obtain a second detection result, including:

[0044] Based on a preset condition, detect the measured value of the gate-source voltage V gs_mea and the drain current i d of the active transistor Q2, and use them as the fourth parameter and the fifth parameter respectively;

[0045] Based on each fifth parameter, obtain the change rate di d / dt of the drain current i d as the sixth parameter;

[0046] Use the measured value of the gate-source voltage V gs_mea as the original signal value V gs,raw (t) corresponding to the current detection time t, and process the original signal value V gs,raw (t) using a low-pass filtering algorithm to obtain the corresponding filtered value V gs_ture of the gate-source voltage as the seventh parameter. The third formula of the low-pass filtering algorithm is:

[0047]

[0048] where h(τ) is the impulse response of the Butterworth low-pass filter, that is, h(τ) is the inverse Laplace transform of the transfer function H(s) of the Butterworth low-pass filter, and τ is the time integration variable.

[0049] Further, the preset condition includes:

[0050] Set the first gate drive voltage V g1 of the passive transistor Q1 to zero;

[0051] Apply a double-pulse signal voltage to the gate-source of the active transistor Q2 using the second gate drive voltage V g ; and

[0052] Apply a DC bus voltage V DC to the bus terminal.

[0053] Further, the first pulse time of the second gate drive voltage V g is set to a fifth threshold t g . The calculation formula of the fifth threshold t g is:

[0054]

[0055] where L is the load inductance value, I L is the load inductance current, and V DC is the DC bus voltage.

[0056] According to the second aspect of the embodiments of the present invention, the embodiments of the present application provide a common-source inductance extraction system based on double-pulse testing. The system includes:

[0057] A first detection module, configured to perform a first detection on a first half-bridge circuit to obtain a first detection result. Wherein, the first half-bridge circuit includes parasitic parameters and is formed by a passive transistor Q1 and an active transistor Q2.

[0058] An adjustment module, configured to determine a predicted adjustment range by using the first detection result, and adjust the gate drive resistance R of the active transistor Q2 based on the predicted adjustment range g to obtain an adjusted second half-bridge circuit.

[0059] A second detection module, configured to perform a second detection on the second half-bridge circuit to obtain a second detection result.

[0060] An extraction module, configured to extract the common-source inductance L of the active transistor Q2 based on the second detection result s The target extraction formula of the common-source inductance L s is:

[0061]

[0062] Wherein, V gs_mea is the measured value of the gate-source voltage of the active transistor Q2, V gs_fil is the filtered value of the gate-source voltage of the active transistor Q2, is the rate of change of the drain current i d of the active transistor Q2.

[0063] According to the third aspect of the embodiments of the present invention, there is provided a common-source inductance extraction device based on double-pulse testing. The device includes: a processor and a memory;

[0064] The memory is used to store one or more program instructions;

[0065] The processor is configured to run one or more program instructions to execute the steps of the common-source inductance extraction method based on double-pulse testing as described in any one of the above.

[0066] According to the fourth aspect of the embodiments of the present invention, there is provided a computer-readable storage medium. A computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, the steps of the common-source inductance extraction method based on double-pulse testing as described in any one of the above are implemented.

[0067] Compared with the prior art, the common-source inductance extraction method, system, device and medium based on double-pulse testing provided by the embodiments of the present application first perform a first detection on the constructed first half-bridge circuit, and use the first detection result to determine the prediction adjustment range of the gate drive resistance R g and make adjustments to obtain the adjusted second half-bridge circuit; then perform a second detection on the second half-bridge circuit, and use the measured value of the gate-source voltage, the filtered value of the gate-source voltage and the change rate of the drain current of the active transistor detected to realize the extraction of the common-source inductance. The embodiments of the present invention use double-pulse signals to excite power devices, and combine the changes in drain current and gate voltage to extract the common-source inductance. It has the advantages of high precision, low cost and no need to disassemble the package, and is particularly suitable for the measurement of the common-source inductance of high-frequency power devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only exemplary, and for those of ordinary skill in the art, without creative efforts, other implementation drawings can be obtained according to the provided drawings.

[0069] The structures, ratios, sizes, etc. shown in this specification are only used to cooperate with the content disclosed in the specification for those who are familiar with this technology to understand and read, and are not used to limit the limited conditions under which the present invention can be implemented. Therefore, they do not have technical essence. Any modification of the structure, change of the proportional relationship or adjustment of the size should still fall within the scope that can be covered by the technical content disclosed by the present invention without affecting the effects that the present invention can produce and the purposes that can be achieved.

[0070] Figure 1 is the circuit diagram of the GaN HEMT double-pulse test half-bridge circuit considering parasitic parameters provided by the embodiments of the present invention;

[0071] Figure 2 is the logical structure diagram of the common-source inductance extraction system based on double-pulse testing provided by the embodiments of the present invention;

[0072] Figure 3 is the flow diagram of the common-source inductance extraction method based on double-pulse testing provided by the embodiments of the present invention;

[0073] Figure 4 is the flow diagram of the first detection of the first half-bridge circuit provided by the embodiments of the present invention;

[0074] Figure 5 is the flow diagram of determining the prediction adjustment range using the first detection result provided by an embodiment of the present invention;

[0075] Figure 6 The gate-source voltage V of the active transistor provided by the present invention under different gate drive resistances R g in the time domain waveform diagram; gs

[0076] Figure 7 The schematic diagram of the process for determining the prediction adjustment range using the first detection result provided by another embodiment of the present invention;

[0077] Figure 8 The schematic diagram of the process for performing the second detection on the second half-bridge circuit provided by the embodiment of the present invention;

[0078] Figure 9a and Figure 9b The verification and comparison diagrams of the gate-source voltage V of the active transistor and the common-source inductance L respectively under the first simulation condition provided by the embodiment of the present invention gs s ;

[0079] Figure 10a and Figure 10b The verification and comparison diagrams of the gate-source voltage V of the active transistor and the common-source inductance L respectively under the second simulation condition provided by the embodiment of the present invention gs s ;

[0080] Figure 11a and Figure 11b The verification and comparison diagrams of the gate-source voltage V of the active transistor and the common-source inductance L respectively under the third simulation condition provided by the embodiment of the present invention gs s ;

[0081] Figure 12a and Figure 12b The verification and comparison diagrams of the gate-source voltage V of the active transistor and the common-source inductance L respectively under the fourth simulation condition provided by the embodiment of the present invention gs s ;

[0082] Figure 13a and Figure 13b The verification and comparison diagrams of the gate-source voltage V of the active transistor and the common-source inductance L respectively under the fifth simulation condition provided by the embodiment of the present invention gs s ;

[0083] Figure 14a and Figure 14b The verification and comparison diagrams of the gate-source voltage V of the active transistor and the common-source inductance L respectively under the sixth simulation condition provided by the embodiment of the present invention gs s ;

[0084] Figure 15a and​​​​​​​Figure 15b are the verification and comparison diagrams of the gate-source voltage V of the active transistor and the common-source inductance L under the seventh simulation condition provided by the embodiments of the present invention; gs and the common-source inductance L s ;

[0085] Figure 16a and Figure 16b are the verification and comparison diagrams of the gate-source voltage V of the active transistor and the common-source inductance L under the eighth simulation condition provided by the embodiments of the present invention; gs and the common-source inductance L s ; Specific Embodiments

[0086] The following specific embodiments illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0087] The common-source inductance is an important parasitic inductance in power electronic devices. Especially in wide-bandgap semiconductor devices (such as SiC MOSFETs and GaN-HEMTs), it has a significant impact on device performance, especially at high switching frequencies. Existing measurement methods (such as network analyzers, TDRs, etc.) are difficult to accurately extract the common-source inductance due to low accuracy or limitations of the test environment.

[0088] The purpose of the embodiments of the present invention is to solve the problems of accuracy and feasibility in extracting the common-source inductance in the prior art.

[0089] To solve the above technical problems, the embodiments of the present application provide a common-source inductance extraction system based on double-pulse testing, which is applied to a half-bridge circuit including parasitic parameters.

[0090] As Figure 1 shown, in the embodiments of the present application, all key high-frequency components are considered, and it is particularly applicable to the GaN HEMT half-bridge test equivalent circuit with parasitic parameters. The half-bridge circuit is formed by a passive transistor Q1 and an active transistor Q2. The embodiments of the present invention are applicable to wide-bandgap semiconductor devices such as GaN and SiC, such as GaN HEMT (High Electron Mobility Transistors), SiC MOSFETs, etc. The passive transistor Q1 and the active transistor Q2 are wide-bandgap semiconductor power devices.

[0091] Figure 1 The circuit parameters used in DC are defined as follows: V DC: Voltage-stabilizing capacitor, L: Load inductor, L loop : Total parasitic inductance of the power loop except for the common-source inductor, R loop : Equivalent parasitic resistance of the power loop, C ds1 , C ds : Drain-source parasitic capacitance of the passive transistor Q1 and the active transistor Q2, C gd1 , C gd : Gate-drain parasitic capacitance of the passive transistor Q1 and the active transistor Q2, C gs1 , C gs : Gate-source parasitic capacitance of the passive transistor Q1 and the active transistor Q2, R g1 , R g : Gate drive resistance of the passive transistor Q1 and the active transistor Q2, L g1 , L g : Gate parasitic inductance of the passive transistor Q1 and the active transistor Q2, L s1 , L s : Common-source parasitic inductance of the passive transistor Q1 and the active transistor Q2.

[0092] The time-domain differential equation of the drive loop of the active transistor Q2 established based on KVL (Kirchhoff laws) is as follows:

[0093]

[0094] Among them, V g is the second gate drive voltage applied to the gate-source of the active transistor Q2, V gs is the gate-source voltage of the active transistor, i g is the equivalent current of the drive loop of the active transistor Q2, i d is the drain current of the active transistor Q2.

[0095] It can be seen from the above time-domain differential equation of the drive loop that during the turn-on process of the GaN HEMT, the gate-source voltage V gs of the active transistor Q2 is affected by the gate drive resistance R g , the gate parasitic inductance L g and the common-source parasitic inductance L s . Specifically, after turn-on, the second gate drive voltage V g is input as a step voltage and acts on the gate drive resistance R g , the gate parasitic inductance L g , the common-source parasitic inductance L s and the active transistor Q2. As the working region of the active transistor Q2 changes from the saturation region to the conduction region, it commutes with the load inductor, and the drain current i d rises rapidly, generating a voltage drop across the common-source inductor L s , forming an equivalent input voltage source, which in turn affects the gate-source voltage V gsIn addition, the non-linear capacitance effect and channel current inside the GaN HEMT also cause the gate-drain parasitic capacitance C gd (Miller capacitance) to play a role during the turn-on process. Since the drain-source voltage V ds rapidly decreases, a displacement current is generated on the gate-drain parasitic capacitance C gd (Miller capacitance). This displacement current feedback flows into the drive loop and serves as a coupled input, making the gate-source voltage V gs of the active transistor Q2 change complexly.

[0096] As described above, in the actual double-pulse test measurement, the measured gate-source voltage V gs_mea of the active transistor Q2 is not the true gate-source voltage V gs of the device. Therefore, in order to obtain the common-source inductance L s through the double-pulse test experiment, specifically, as Figure 2 shown, the common-source inductance extraction system based on double-pulse test provided by the embodiments of the present application includes: a first detection module 1, an adjustment module 2, a second detection module 3, and an extraction module 4.

[0097] The first detection module 1 is used to perform a first detection on the first half-bridge circuit to obtain a first detection result; wherein, the first half-bridge circuit includes parasitic parameters and is formed by the passive transistor Q1 and the active transistor Q2.

[0098] The adjustment module 2 is used to determine a predicted adjustment range by using the first detection result; and adjust the gate drive resistance R g of the active transistor Q2 based on the predicted adjustment range to obtain an adjusted second half-bridge circuit.

[0099] The second detection module 3 is used to perform a second detection on the second half-bridge circuit to obtain a second detection result.

[0100] The extraction module 4 is used to extract the common-source inductance L s of the active transistor Q2 based on the second detection result. The target extraction formula for the common-source inductance L s is:

[0101]

[0102] wherein, V gs_mea is the measured gate-source voltage of the active transistor Q2, V gs_fil is the filtered gate-source voltage of the active transistor Q2, is the change rate of the drain current i d of the active transistor Q2.

[0103] Compared with the prior art, the common-source inductance extraction system based on double-pulse testing provided by the embodiment of the present application first performs a first detection on the constructed first half-bridge circuit, and uses the first detection result to determine the prediction adjustment range of the gate drive resistance R g and make adjustments to obtain the adjusted second half-bridge circuit; then perform a second detection on the second half-bridge circuit, and use the measured value of the gate-source voltage, the filtered value of the gate-source voltage, and the change rate of the drain current of the active transistor detected to achieve the extraction of the common-source inductance. The embodiment of the present invention uses a double-pulse signal to excite the power device, combines the changes in the drain current and the gate voltage, and extracts the common-source inductance. It has the advantages of high precision, low cost, and no need to disassemble the package, and is particularly suitable for the measurement of the common-source inductance of high-frequency power devices.

[0104] Corresponding to the above-disclosed common-source inductance extraction system based on double-pulse testing, the embodiment of the present invention also discloses a common-source inductance extraction method based on double-pulse testing. The common-source inductance extraction method disclosed in the embodiment of the present invention will be introduced in detail below in combination with the above-described common-source inductance extraction system based on double-pulse testing.

[0105] As Figure 3 shown, the specific steps of the common-source inductance extraction method based on double-pulse testing provided by the embodiment of the present application will be described in detail below.

[0106] The first detection module 1 performs a first detection on the first half-bridge circuit to obtain a first detection result.

[0107] Further, the first detection result includes: a first parameter. Referring to Figure 4 , the above steps specifically include: obtaining the sum of the gate parasitic inductance L g of the active transistor Q2 in the first half-bridge circuit and the common-source inductance L s to obtain the first parameter. In the embodiment of the present application, for the first half-bridge circuit, the total parasitic inductance of the drive loop (the sum of the gate parasitic inductance L g and the common-source inductance L s , L g +L s ) is directly obtained as the first parameter. For EPC2045, the range of the total parasitic inductance of the drive loop (the sum of the gate parasitic inductance L g and the common-source inductance L s , L g +L s ) is generally between 1 nH and 2.5 nH.

[0108] In addition, the first detection result also includes: a second parameter. Referring to Figure 4 , the above steps further include: obtaining the gate-source parasitic capacitance C gs and the gate-drain parasitic capacitance C of the active transistor Q2 in the first half-bridge circuitgd ; calculate the gate-source parasitic capacitance C of the active transistor Q2 gs and the gate-drain parasitic capacitance C gd of the sum, to obtain the input capacitance C of the active transistor Q2 iss , as the second parameter.

[0109] In the embodiment of the present application, the first detection result further includes: a third parameter. Refer to Figure 4 , the above steps specifically further include: based on a preset condition, detecting at least one oscillation frequency value F caused by the power loop during the oscillation stage in the switching process, as the third parameter.

[0110] In the embodiment of the present application, the preset condition includes: setting the first gate drive voltage V of the passive transistor Q1 g1 to zero; applying a double-pulse signal voltage to the gate-source of the active transistor Q2 using the second gate drive voltage V g ; and applying a DC bus voltage V to the bus terminal of the first half-bridge circuit DC .

[0111] The preset value of the second gate drive voltage V g needs to refer to the withstand range of the gate-source voltage V of the active transistor Q2 gs . Taking EPC2045 as an example, since the withstand range of the gate-source voltage V of the active transistor Q2 gs is greater than or equal to -4V and less than or equal to 6V, therefore, the second gate drive voltage V g can be set to be greater than or equal to 0V and less than or equal to 5V. The preset value of the DC bus voltage V DC then needs to refer to the withstand range of the drain-source voltage V of the active transistor Q2 ds . For EPC2045, the maximum withstand value of the drain-source voltage V of the active transistor Q2 ds is 120V, so the DC bus voltage V DC can be set to typical values such as 12V, 24V, 36V or 48V. The preset value of the load inductor current I L needs to refer to the withstand range of the drain current i of the active transistor Q2 d . Taking EPC2045 as an example, its drain current i d 's continuous maximum withstand value is 16A, so the load inductor current I L should be set to a reasonable range below 16A.

[0112] In addition, considering the basic principle of the double-pulse test, that is, according to the set load inductor current I L , the DC bus voltage V DC and the size of the load inductor L, it is necessary to set the second gate drive voltage V gThe first pulse time. Further, the second gate drive voltage V g The first pulse time is set to the first preset threshold t g , and the calculation formula of the first preset threshold t g is:

[0113]

[0114] where L is the value of the load inductance, I L is the load inductance current, and V DC is the DC bus voltage.

[0115] The adjustment module 2 determines the predicted adjustment range by using the first detection result.

[0116] First, it is necessary to consider appropriately adjusting the gate drive resistance R g to ensure that the second gate drive voltage V g is input as a step voltage, and its influence on the gate-source voltage V gs is minimized, and the gate-source voltage V gs hardly oscillates. During the switching process, mainly the input capacitance C iss (C iss = C gs + C gd ) is connected to the drive circuit of the active transistor Q2. Therefore, this process can be considered as a series circuit of the gate drive resistance R g - the gate parasitic inductance L g and the common-source inductance L s sum (L g + L s ) - the input capacitance C iss . Thus, according to the damping relationship, when the gate drive resistance R g , the sum of the gate parasitic inductance L g and the common-source inductance L s sum (L g + L s ), and the input capacitance C iss satisfy the following fourth formula, the voltage across the input capacitance C iss no longer oscillates under pulse excitation:

[0117]

[0118] The above fourth formula is transformed to obtain the following fifth formula:

[0119]

[0120] Actually, due to the sum of the gate parasitic inductance L g and the common-source inductance L s sum (Lg +L s ) is between 1 nH and 2.5 nH. For the EPC2045 selected in the embodiment of the present application, the input capacitance C iss is equal to 767 pF. Therefore, as long as the gate drive resistance R g is greater than 3.6 Ω, it can ensure that the overdamped drive loop (gate drive resistance R g - gate parasitic inductance L g and the common-source inductance L s 's sum (L g +L s ) - input capacitance C iss ) satisfies the overdamped relationship. In the actual PCB design, since both the drive IC and the gallium nitride device itself have a certain drive resistance, it is easy to satisfy that the gate drive resistance R g is greater than 3.6 Ω.

[0121] Reference Figure 6 , meanwhile, to further verify this situation, for the series circuit of the gate drive resistance R g - gate parasitic inductance L g and the common-source inductance L s 's sum (L g +L s ) - input capacitance C iss under pulsed excitation, when the sum of the gate parasitic inductance L g and the common-source inductance L s (L g +L s ) is equal to 2.5 nH, time-domain simulations under different gate drive resistances R g are carried out. It can be further clearly seen from Figure 6 that for the EPC2045, when the gate drive resistance R g is greater than 5 Ω, in the series circuit of the gate drive resistance R g - gate parasitic inductance L g and the common-source inductance L s 's sum (L g +L s ) - input capacitance C iss , the voltage across the input capacitance C iss no longer exhibits oscillation phenomenon.

[0122] In addition, it is still necessary to consider appropriately adjusting the gate drive resistance R g so that the equivalent input voltage source generated by the drain current i d on the common-source inductance acts on the gate drive resistance R g , the gate parasitic inductance L g and the active transistor Q2 in turn. Since the gate drive resistance Rg has a relatively large resistance value, and this voltage source also has little influence on the gate-source voltage V gs , and the drain current i can be almost ignored d The equivalent input voltage source excitation generated on the common-source inductor can be regarded as a sinusoidal signal excitation. For this excitation, the focus needs to be on the oscillation of the drain current i caused by the LC resonance of the power loop in the fourth stage of the turn-on process d . Therefore, the drain current i d The equivalent input voltage source excitation generated on the common-source inductor can be regarded as a voltage source signal of the sine wave type acting on the gate drive resistor R g - gate parasitic inductance L g - input capacitance C iss . The amplitude and oscillation frequency of this signal are related to the parameters of the power loop

[0123] Specifically, in order to ensure that the gate-source voltage V of the active transistor Q2 hardly oscillates during the turn-on process, the gate drive resistor R gs needs to satisfy the following sixth formula g :

[0124]

[0125] where F is the oscillation frequency value caused by the power loop during the oscillation stage of the switching process

[0126] In the embodiment of the present application, for the fourth stage of the above turn-on process, the gate drive resistor R is determined by simulation g . Generally speaking, the current oscillation frequency caused by the power loop in the fourth stage of the turn-on process is about 50Mhz - 100Mhz, and the oscillation amplitude is assumed to be about 1V. Then, when this sinusoidal signal excitation acts on the gate drive resistor R g - gate parasitic inductance L g - input capacitance C iss circuit, the voltage amplitude across the input capacitance C iss varies with the gate drive resistor R g and the gate parasitic inductance L g . The simulation results are as follows

[0127] (a) When the total parasitic inductance L of the power loop except for the common-source inductor loop is 15.5n, the output capacitance C of the passive transistor Q1 oss1 is 295pf, the DC bus voltage V DC is 50v, and the oscillation frequency value F caused by the power loop is 75Mhz, when the voltage threshold across the input capacitance C iss is set to 0.05V, it is considered that the input capacitance C issThe voltage oscillation at both ends is approximately ignored, and the gate drive resistance R obtained by simulation at this time g is greater than 56 Ω;

[0128] (b) When the total parasitic inductance L of the power loop except for the common-source inductance loop is 10.5 n, the output capacitance C of the passive transistor Q1 oss1 is 295 pf, the DC bus voltage V DC is 50 v, and the oscillation frequency value F caused by the power loop is 90 MHz, the voltage threshold of the input capacitance C iss is set to 0.05 V, and it is considered that the voltage oscillation at both ends of the input capacitance C iss is approximately ignored. At this time, the gate drive resistance R obtained by simulation g is greater than 47 Ω.

[0129] Combining the above analysis of (a) and (b), for the existing EPC2045 dual-pulse test and evaluation board in the laboratory, when the gate drive resistance R g is greater than 56 Ω, it can ensure that the gate-source voltage V of the active transistor Q2 gs hardly oscillates during the turn-on process. At this time, the oscillation of the measured value V of the gate-source voltage of the active transistor Q2 gs_mea comes from to obtain the following seventh formula:

[0130]

[0131] Then, according to the above seventh formula, the extraction of the common-source inductance can adopt the following eighth formula:

[0132]

[0133] Among them, V gs_mea is the measured value of the gate-source voltage of the active transistor Q2, and V gs_rea is the true value of the gate-source voltage of the active transistor Q2, is the rate of change of the drain current of the active transistor Q2.

[0134] As described above, referring to Figure 5 , in an embodiment of the present application, the above specific steps include: calculating the first threshold K1 according to the first formula using the first parameter and the second parameter, and the first formula is:

[0135]

[0136] Based on the first threshold K1, determine the first adjustment range of the gate drive resistance R of the active transistor Q2 g , and the first adjustment range is that the gate drive resistance R g is greater than the first threshold K1.

[0137] Calculate the corresponding second threshold K2 according to the second formula by using the first parameter, the second parameter, and each third parameter. The second formula is:

[0138]

[0139] Select the maximum value from each second threshold K2 as the third threshold K3; based on the third threshold K3, determine the second adjustment range of the gate drive resistance R of the active transistor Q2. The second adjustment range is that the gate drive resistance R is greater than the third threshold K3; obtain the intersection of the first adjustment range and the second adjustment range as the third adjustment range; output the third adjustment range as the predicted adjustment range. g of g is greater than the third threshold K3; obtain the intersection of the first adjustment range and the second adjustment range as the third adjustment range; output the third adjustment range as the predicted adjustment range.

[0140] Reference Figure 7 , in another embodiment of the present application, the above specific steps include: calculate the first threshold K1 according to the first formula by using the first parameter and the second parameter. The first formula is:

[0141]

[0142] Based on the first threshold K1, determine the first adjustment range of the gate drive resistance R of the active transistor Q2. The first adjustment range is that the gate drive resistance R is greater than the first threshold K1. g of g is greater than the first threshold K1.

[0143] Calculate the corresponding second threshold K2 according to the second formula by using the first parameter, the second parameter, and each third parameter. The second formula is:

[0144]

[0145] Select the maximum value from each second threshold K2 as the third threshold K3; based on the third threshold K3, determine the second adjustment range of the gate drive resistance R of the active transistor Q2. The second adjustment range is that the gate drive resistance R is greater than the third threshold K3; based on a preset fourth threshold K4, determine the fourth adjustment range of the gate drive resistance R of the active transistor Q2. The fourth adjustment range is that the gate drive resistance R is less than the fourth threshold K4; obtain the intersection of the first adjustment range, the second adjustment range, and the fourth adjustment range as the fifth adjustment range; output the fifth adjustment range as the predicted adjustment range. g of g is greater than the third threshold K3; based on a preset fourth threshold K4, determine the fourth adjustment range of the gate drive resistance R of the active transistor Q2. The fourth adjustment range is that the gate drive resistance R is less than the fourth threshold K4; obtain the intersection of the first adjustment range, the second adjustment range, and the fourth adjustment range as the fifth adjustment range; output the fifth adjustment range as the predicted adjustment range. g of g is less than the fourth threshold K4; obtain the intersection of the first adjustment range, the second adjustment range, and the fourth adjustment range as the fifth adjustment range; output the fifth adjustment range as the predicted adjustment range.

[0146] In the embodiment of the present application, considering that when the gate drive resistance R g is too large (for example, exceeding 200 Ω), the drain current i d will not oscillate either. Therefore, the gate drive resistance R gThe value range can consider the upper limit threshold, that is, the fourth threshold K4 is set to 70Ω.

[0147] The adjustment module 2 adjusts the gate drive resistance R of the active transistor Q2 based on the predicted adjustment range g , and the adjusted second half-bridge circuit is obtained.

[0148] The second detection module 3 is used to perform a second detection on the second half-bridge circuit to obtain a second detection result.

[0149] Reference Figure 8 , and the specific steps of the above second detection are described below.

[0150] Based on the preset conditions, the measured value V of the gate-source voltage of the active transistor Q2 is detected gs_mea and the drain current i d , which are used as the fourth parameter and the fifth parameter respectively; based on each fifth parameter, the change rate di d / dt of the drain current i d is obtained as the sixth parameter.

[0151] In the embodiment of the present application, the preset conditions include: setting the first gate drive voltage V of the passive transistor Q1 g1 to zero; applying a double-pulse signal voltage to the gate-source of the active transistor Q2 using the second gate drive voltage V g ; and applying a DC bus voltage V DC to the bus terminal of the second half-bridge circuit.

[0152] Similarly, the preset value of the second gate drive voltage V g needs to refer to the withstand range of the gate-source voltage V of the active transistor Q2 gs . Taking EPC2045 as an example, since the withstand range of the gate-source voltage V of the active transistor Q2 gs is greater than or equal to -4V and less than or equal to 6V, therefore, the second gate drive voltage V g can be set to be greater than or equal to 0V and less than or equal to 5V. The preset value of the DC bus voltage V DC needs to refer to the withstand range of the drain-source voltage V of the active transistor Q2 ds . For EPC2045, the maximum withstand value of the drain-source voltage V of the active transistor Q2 ds is 120V, so the DC bus voltage V DC can be set to typical values such as 12V, 24V, 36V, or 48V. The preset value of the load inductor current I L needs to refer to the withstand range of the drain current i of the active transistor Q2 d . Taking EPC2045 as an example, the continuous maximum withstand value of its drain current i d is 16A, so the load inductor current IL It should be set within a reasonable range lower than 16A.

[0153] In addition, considering the basic principle of the double-pulse test, i.e., according to the load inductance current I set for the test L , the DC bus voltage V DC and the magnitude of the load inductance L, it is necessary to set the first pulse time of the second gate drive voltage V g . Further, the first pulse time of the second gate drive voltage V g is set to the first preset threshold t g , and the calculation formula for the first preset threshold t g is:

[0154]

[0155] where L is the load inductance value, I L is the load inductance current, and V DC is the DC bus voltage.

[0156] In the embodiments of the present application, based on the above-mentioned preset conditions, at the falling edge of the first pulse, the turn-off transient waveform of the device can be captured, and at the rising edge of the second pulse, the turn-on transient waveform of the device can be captured. To obtain the corresponding gate-source voltage measurement value V gs_mea , an oscilloscope and a passive probe can be used for measurement. At the same time, by using a coaxial shunt to measure the drain current i d , and directly calculating using the oscilloscope, the change rate di d / dt waveform of the drain current i d can be obtained.

[0157] Taking the gate-source voltage measurement value V gs_mea as the original signal value V gs,raw (t) corresponding to the current detection time t, the original signal value V gs,raw (t) is processed using a low-pass filtering algorithm to obtain the corresponding gate-source voltage filtered value V gs_fil , as the seventh parameter, the third formula of the low-pass filtering algorithm is:

[0158]

[0159] where h(τ) is the impulse response of the Butterworth low-pass filter, that is, h(τ) is the inverse Laplace transform of the transfer function H(s) of the Butterworth low-pass filter, and τ is the time integration variable.

[0160] The extraction module 4 extracts the common-source inductance L s of the active transistor Q2 based on the second detection result.

[0161] In the embodiment of the present application, the obtained gate-source voltage filtering value V gs_fil is used as the true value V gs_rea of the gate-source voltage. The aforementioned eighth formula is transformed into the target extraction formula for the common-source inductance L s . Further, the target extraction formula for the common-source inductance L s is as follows:

[0162]

[0163] where V gs_mea is the measured value of the gate-source voltage of the active transistor Q2, V gs_fil is the filtered value of the gate-source voltage of the active transistor Q2, is the change rate of the drain current i d of the active transistor Q2.

[0164] Compared with the prior art, the common-source inductance extraction method based on double-pulse testing provided by the embodiment of the present application first performs a first detection on the constructed first half-bridge circuit, and uses the first detection result to determine the predicted adjustment range of the gate drive resistance R g and makes adjustments to obtain the adjusted second half-bridge circuit; then performs a second detection on the second half-bridge circuit, and uses the measured value of the gate-source voltage, the filtered value of the gate-source voltage, and the change rate of the drain current of the detected active transistor to achieve the extraction of the common-source inductance. The embodiment of the present invention uses a double-pulse signal to excite the power device, and combines the changes in the drain current and the gate voltage to extract the common-source inductance. It has the advantages of high precision, low cost, and no need to disassemble the package, and is particularly suitable for measuring the common-source inductance of high-frequency power devices.

[0165] For the above-mentioned common-source inductance extraction scheme based on double-pulse testing disclosed in the embodiment of the present application, under the working conditions where the DC bus voltage V DC is 48V and the load inductor current I L is 11A, the double-pulse test simulation of the EPC2045 device is completed using the LTspice platform. During the simulation process, in order to verify the effectiveness of the scheme proposed in the embodiment of the present application, the cases where the common-source inductance L s is 0.5nH and 0.3nH are respectively set for simulation analysis. In addition, in order to more comprehensively verify this method, we further changed the total parasitic inductance L loop of the power loop except for the common-source inductance and used different gate drive resistances R g for simulation verification.

[0166] Refer to Figure 9a and Figure 9b , Figure 10a and Figure 10b , Figure 11a and Figure 11b ,Figure 12a and Figure 12b 、 Figure 13a and Figure 13b 、 Figure 14a and Figure 14b 、 Figure 15a and Figure 15b 、 Figure 16a and Figure 16b and, showing the above simulation verification results, respectively corresponding to the first to the eighth simulation conditions and the comparison results as shown in Table 1 below:

[0167] Table 1

[0168]

[0169]

[0170] From the results in Table 1 above, it can be seen that the error of the common-source inductance extraction scheme based on the double-pulse test in the above embodiments of the present application is very small. When the selected value of the gate drive resistance R g is greater than 56 Ω, the error of the common-source inductance L s obtained by using the target extraction formula of the common-source inductance L s can be below 5%. However, when the gate drive resistance R g is equal to 50 Ω and the total parasitic inductance L loop of the power loop except the common-source inductance is 15.5 n, the calculation result error is relatively large because when the total parasitic inductance L loop of the power loop except the common-source inductance is 15.5 n, the recommended value in the previous setting of the gate drive resistance R g is above 56 Ω. Therefore, there is a certain error in the result when the gate drive resistance R g is equal to 50 Ω. Therefore, the effectiveness of the common-source inductance extraction scheme based on the double-pulse test in the above embodiments of the present application is verified.

[0171] The embodiments of the present application realize the extraction of the common-source inductance based on the double-pulse test, avoiding the cumbersome disassembly and the need for high-frequency equipment, and can directly measure the common-source inductance without unpacking the package, with simple operation and being suitable for practical engineering applications.

[0172] In addition, the embodiments of the present invention also provide a common-source inductance extraction device based on the double-pulse test. The device includes: a processor and a memory; the memory is used to store one or more program instructions; the processor is used to run one or more program instructions to execute the steps of the common-source inductance extraction method as described in any one of the above.

[0173] In addition, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the common-source inductance extraction method based on double-pulse testing as described in any one of the above are implemented.

[0174] In an embodiment of the present invention, the processor may be an integrated circuit chip with signal processing capabilities. The processor may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0175] It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present invention may be directly embodied as being executed by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the art such as random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, register, etc. The processor reads the information in the storage medium and completes the steps of the above method in combination with its hardware.

[0176] The storage medium may be a memory, for example, it may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories.

[0177] Among them, the non-volatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), or a flash memory.

[0178] The volatile memory may be a Random Access Memory (RAM) which serves as an external cache. By way of example but not limitation, many forms of RAM are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DRRAM).

[0179] The storage media described in the embodiments of the present invention are intended to include, but not limited to, these and any other suitable types of memory.

[0180] Those skilled in the art should be aware that, in one or more of the above examples, the functions described in the present invention can be implemented by a combination of hardware and software. When applying software, the corresponding functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. The computer-readable medium includes computer storage media and communication media, where the communication media includes any medium that facilitates the transfer of a computer program from one place to another. The storage media can be any available medium accessible by a general-purpose or special-purpose computer.

[0181] Although the present invention has been described in detail above with general descriptions and specific embodiments, on the basis of the present invention, some modifications or improvements can be made, which are obvious to those skilled in the art. Therefore, these modifications or improvements made without departing from the spirit of the present invention all fall within the scope of the present invention claimed.

Claims

1. A common source inductance extraction method based on double pulse test, characterized in that: The method comprises: Performing a first detection on a first half-bridge circuit to obtain a first detection result; wherein the first half-bridge circuit includes parasitic parameters and is constructed by a passive tube Q1 and an active tube Q2; Determining a predicted adjustment range using the first detection result; The gate drive resistance R of the active transistor Q2 is adjusted based on the predicted adjustment range. g , and obtain the adjusted second half-bridge circuit; Performing a second detection on the second half-bridge circuit to obtain a second detection result; Extract the common source inductance L of the active tube Q2 based on the second detection result s , the common source inductance L s The target extraction formula is: Among them, V gs_mea is the gate-source voltage measurement value of the active tube Q2, V gs_fil is the gate-source voltage filtering value of the active tube Q2, is the drain current i of the active tube Q2 d The rate of change.

2. The common source inductance extraction method based on double pulse test according to claim 1, characterized in that: Performing a first detection on the first half-bridge circuit to obtain a first detection result includes: Obtain the gate parasitic inductance L of the active transistor Q2 in the first half-bridge circuit g With the common source inductance L s The sum of , gets the first parameter; Obtain the gate-source parasitic capacitance C of the active transistor Q2 in the first half-bridge circuit gs and gate-drain parasitic capacitance C gd ; Calculate the gate-source parasitic capacitance C of the active tube Q2 gs The gate-drain parasitic capacitance C gd The sum of the input capacitance C of the active tube Q2 is obtained. iss , as the second parameter; Based on the preset conditions, at least one oscillation frequency value F caused by the power circuit in the oscillation stage during the switching process is detected as the third parameter.

3. The common source inductance extraction method based on double pulse test according to claim 2, characterized in that: Determining a predicted adjustment range using the first detection result includes: The first threshold K1 is calculated using the first parameter and the second parameter according to a first formula, where the first formula is: Based on the first threshold value K1, the gate drive resistance R of the active transistor Q2 is determined. g The first adjustment range is the gate drive resistor R g is greater than the first threshold K1; The first parameter, the second parameter and each third parameter are used to calculate the corresponding second threshold K2 according to a second formula, where the second formula is: Select the maximum value from each second threshold value K2 as the third threshold value K3; Based on the third threshold value K3, the gate drive resistance R of the active transistor Q2 is determined. g The second adjustment range of the gate drive resistor R g is greater than the third threshold K3; Obtaining an intersection of the first adjustment range and the second adjustment range as a third adjustment range; The third adjustment range is output as a predicted adjustment range.

4. The common source inductance extraction method based on double pulse test according to claim 2, characterized in that: Determining a predicted adjustment range using the first detection result includes: The first threshold K1 is calculated using the first parameter and the second parameter according to a first formula, where the first formula is: Based on the first threshold value K1, the gate drive resistance R of the active transistor Q2 is determined. g The first adjustment range is the gate drive resistor R g is greater than the first threshold K1; The first parameter, the second parameter and each third parameter are used to calculate the corresponding second threshold K2 according to a second formula, where the second formula is: Select the maximum value from each second threshold value K2 as the third threshold value K3; Based on the third threshold value K3, the gate drive resistance R of the active transistor Q2 is determined. g The second adjustment range of the gate drive resistor R g is greater than the third threshold K3; Based on the preset fourth threshold value K4, the gate drive resistance R of the active transistor Q2 is determined. g The fourth adjustment range is the gate drive resistor R g is smaller than the fourth threshold K4; Obtaining an intersection of the first adjustment range, the second adjustment range, and the fourth adjustment range as a fifth adjustment range; The fifth adjustment range is output as a predicted adjustment range.

5. The common source inductance extraction method based on double pulse test according to claim 3 or 4, characterized in that: Performing a second detection on the second half-bridge circuit to obtain a second detection result includes: Based on the preset conditions, the gate-source voltage measurement value V of the active tube Q2 is detected. gs_mea and the drain current i d , as the fourth and fifth parameters respectively; The drain current i is obtained based on each fifth parameter d The rate of change of d / dt, as the sixth parameter; The gate-source voltage measurement value V gs_mea As the original signal value V corresponding to the current detection time t gs,raw (t), using low-pass filtering algorithm to filter the original signal value V gs,raw (t) is processed to obtain the corresponding gate-source voltage filtering value V gs_fil , as the seventh parameter, the third formula of the low-pass filtering algorithm is: Wherein, h(τ) is the impulse response of the Butterworth low-pass filter, that is, h(τ) is the inverse Laplace transform of the transfer function H(s) of the Butterworth low-pass filter, and τ is the time integral variable.

6. The common source inductance extraction method based on double pulse test according to claim 5, characterized in that: The preset conditions include: The first gate drive voltage V of the passive tube Q1 g1 Set to zero; Using the second gate drive voltage V g Apply a double pulse signal voltage to the gate source of the active transistor Q2; and Apply a DC bus voltage V at the bus end DC .

7. The common source inductance extraction method based on double pulse test according to claim 6, characterized in that: The second gate driving voltage V g The first pulse time is set to the fifth threshold value t g , the fifth threshold t g The calculation formula is: Where, L is the load inductance, I L is the load inductor current, V DC is the DC bus voltage.

8. Common source inductance extraction system based on double pulse test, characterized in that: The system comprises: A first detection module, used for performing a first detection on a first half-bridge circuit to obtain a first detection result; wherein the first half-bridge circuit includes parasitic parameters and is constructed by a passive tube Q1 and an active tube Q2; An adjustment module is used to determine a predicted adjustment range using the first detection result; and adjust the gate drive resistance R of the active tube Q2 based on the predicted adjustment range. g , and obtain the adjusted second half-bridge circuit; A second detection module, used for performing a second detection on the second half-bridge circuit to obtain a second detection result; An extraction module, used to extract the common source inductance L of the active tube Q2 based on the second detection result s , the common source inductance L s The target extraction formula is: Among them, V gs_mea is the gate-source voltage measurement value of the active tube Q2, V gs_fil is the gate-source voltage filtering value of the active tube Q2, is the drain current i of the active tube Q2 d The rate of change.

9. Common source inductance extraction equipment based on double pulse test, characterized in that: The device comprises: a processor and a memory; The memory is used to store one or more program instructions; The processor is used to run one or more program instructions to execute the steps of the common source inductance extraction method based on double pulse test as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the common source inductance extraction method based on double pulse testing as claimed in any one of claims 1 to 7 are implemented.

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