Optical interconnection method between large-scale photon chips and photon chip integration system

Abstract

The invention provides a large-scale photon chip inter-chip optical interconnection method and a photon chip integration system. The large-scale photon chip inter-chip optical interconnection method comprises the following steps: preparing a plurality of grooves in a substrate; preparing photon chips, and installing the photon chips in the plurality of grooves; preparing a covering layer on the substrate and the photon chip; preparing a reflector on the surface of the covering layer; and inputting an optical signal from the input port of one photon chip, outputting the optical signal processed by the photon chip into the covering layer at a specific diffraction angle from the output port of the photon chip, and finally reflecting the optical signal to other photon chips through the reflector and finally outputting the optical signal, thereby realizing inter-chip optical interconnection of the photon chips.

Description

Technical Field

[0001] The present disclosure relates to the technical field of photonic chips, and in particular, to a method for inter-chip optical interconnection of large-scale photonic chips and a photonic chip integration system, which can achieve inter-chip interconnection of up to hundreds of photonic chips. Background Art

[0002] In the post-Moore era, silicon photonics integration technology has developed rapidly. Due to the advantages of large scale, high precision of microelectronics technology and high speed, low power consumption of photonics technology, silicon photonics integration technology has great development potential. Optical coupling is a key technology for silicon photonics chips. With the rapid development of photonic chip technology, it has been increasingly widely used in many fields such as optical communication, optical computing, and optical sensing. However, the realization of optical coupling between photonic chips has always been a key problem restricting its development and performance improvement. Traditional coupling methods are limited by the alignment problem caused by the tiny size of waveguides and the mode mismatch between optical fibers and waveguides, and between waveguides and free-space light, which seriously hinders the performance improvement of photonic chip systems. Although there are some preliminary solutions available, further optimization and innovation are still needed to meet the requirements of increasingly complex application scenarios such as high-speed optical communication and precision optical sensing. Summary of the Invention

[0003] In view of this, in order to at least partially solve at least one of the above-mentioned technical problems, the present disclosure provides a method for inter-chip optical interconnection of large-scale photonic chips and a photonic chip integration system.

[0004] To achieve the above object, the technical solution of the present disclosure is as follows:

[0005] According to an embodiment of one aspect of the present disclosure, a method for inter-chip optical interconnection of large-scale photonic chips is provided, including:

[0006] Preparing a plurality of grooves on a substrate;

[0007] Fabricating photonic chips and mounting the photonic chips in the plurality of grooves;

[0008] Preparing a covering layer on the substrate and the photonic chips;

[0009] Preparing a mirror on the surface of the covering layer; and

[0010] Inputting an optical signal from an input port of one photonic chip, the optical signal processed by the photonic chip is output from the output port of the photonic chip at a specific diffraction angle into the covering layer, and finally reflected by the mirror to other photonic chips and finally output, realizing inter-chip optical interconnection of photonic chips.

[0011] According to an embodiment of the present disclosure, a photonic chip includes: a chip substrate; an optical signal processing module located on the chip substrate; and grating couplers located on both sides of the optical signal processing module and both connected to the optical signal processing module through optical waveguides, where one of the grating couplers serves as an input port of the photonic chip and the other grating coupler serves as an output port of the photonic chip.

[0012] According to an embodiment of the present disclosure, the grating coupler adopts a periodic sub-wavelength grating structure, and by optimizing the grating structure parameters, efficient coupling of the incident optical signal is achieved.

[0013] According to an embodiment of the present disclosure, the grating structure parameters include the grating period, the grating duty cycle, and the groove etching depth of the grating structure.

[0014] According to an embodiment of the present disclosure, the spacing Q between two-level photonic chips for optical interconnection is related to the thickness H0 of the cladding layer and the diffraction angle θ of the grating coupler in the photonic chip, and the expression is as follows:

[0015] Q = 2H0tanθ.

[0016] According to an embodiment of the present disclosure, the mirror is a metal coating with high reflectivity or a multi-layer dielectric film, and the mirror is a planar structure or a micro-curved surface structure.

[0017] According to an embodiment of the present disclosure, the optical signal undergoes mode conversion through the grating coupler serving as the input port, and then is transmitted to the optical signal processing module through the optical waveguide for processing, and then is transmitted to the mirror by the grating coupler serving as the output port and reflected to the input port of the next-level photonic chip, and so on to achieve inter-chip optical interconnection coupling of multiple-level photonic chips. Finally, the optical signal is output from the output port of the last-level photonic chip.

[0018] According to an embodiment of the present disclosure, a top cladding layer is further prepared between the photonic chip and the cladding layer, and the top cladding layer is used to reduce the scattering and loss of the optical signal.

[0019] According to an embodiment of the present disclosure, a buried oxide layer is further prepared between the photonic chip and the substrate, and the buried oxide layer is used to reduce the leakage of the optical signal to the substrate during transmission.

[0020] According to an embodiment of another aspect of the present disclosure, there is provided a photonic chip integration system implemented based on the above-described inter-chip optical interconnection method for photonic chips, including: a substrate on which a plurality of grooves are fabricated; a plurality of photonic chips mounted in the plurality of grooves; a cover layer covering the substrate and the photonic chips; and a mirror fabricated on the surface of the cover layer; wherein the photonic chip includes: a chip substrate, an optical signal processing module, an optical waveguide, and a grating coupler; the optical signal processing module is located on the chip substrate; the grating couplers are located on both sides of the optical signal processing module and are both connected to the optical signal processing module through optical waveguides, and one of the grating couplers serves as an input port of the photonic chip, and the other grating coupler serves as an output port of the photonic chip; an optical signal is input from the input port of one photonic chip, and the optical signal processed by this photonic chip is output from the output port of this photonic chip to the cover layer at a specific diffraction angle, and finally reflected by the mirror to other photonic chips and finally output. Description of the Drawings

[0021] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:

[0022] Figure 1 It is a flowchart of the large-scale inter-chip optical interconnection method for photonic chips according to the embodiments of the present disclosure.

[0023] Figure 2 It is a schematic diagram of a coupling structure fixed based on an optical fiber slot.

[0024] Figure 3 It is a schematic diagram of a tapered waveguide.

[0025] Figure 4 It is a schematic diagram of the inter-chip coupling effect of photonic chips fixed based on an optical fiber slot.

[0026] Figure 5 It is a schematic diagram of a coupling structure combining a superlens and an end-face coupler.

[0027] Figure 6 It is a schematic diagram of the inter-chip coupling effect of photonic chips based on end-face coupling of a superlens array.

[0028] Figure 7 It is a schematic diagram of the inter-chip coupling principle of a photonic chip combining a grating coupler and a mirror according to the embodiments of the present disclosure.

[0029] Figure 8 It is a schematic diagram of the inter-chip coupling of a photonic chip combining a grating coupler and a mirror according to the embodiments of the present disclosure.

[0030] Figure 9Schematic diagram of the principle of the large-scale photonic chip inter-chip coupling scheme based on chip slots according to the embodiments of the present disclosure.

[0031] Figure 10 Schematic diagram of the effect of the large-scale photonic chip inter-chip coupling based on chip slots according to the embodiments of the present disclosure. Detailed implementation manners

[0032] The present disclosure provides a method for optical interconnection between photonic chips based on a variety of efficient coupling structures. Focusing on the optical interconnection technology between photonic chips, it aims to overcome a series of key problems existing in the existing inter-chip coupling technology, so as to promote the development of photonic chip technology towards higher performance and wider applications.

[0033] In the process of implementing the present disclosure, the inventors found that there are many technical problems in the traditional coupling method when facing photonic chips with extremely small waveguide sizes (usually in the sub-micron and micron ranges), as follows:

[0034] 1. The alignment accuracy requirements for optical fibers and waveguides are extremely high. Due to their tiny sizes, it is extremely difficult to align them manually or by conventional mechanical means. Even a slight deviation will result in serious coupling losses.

[0035] 2. The mode mismatch problem between optical fibers and waveguide chips is prominent, which causes serious energy loss during the transmission of optical signals, greatly reducing the coupling efficiency between photonic chips and making it difficult to meet the requirements of modern high-speed and high-integration photonic systems.

[0036] 3. The energy loss caused by mode mismatch and the alignment difficulties brought about by the tiny sizes of optical fibers and waveguides result in a very low proportion of the optical energy that can be effectively coupled into adjacent chips when optical signals are transmitted between chips, seriously hindering the improvement of the overall performance of the photonic system.

[0037] 4. Traditional processes and schemes often require complex operation procedures and are difficult to process. For example, when dealing with the alignment of tiny-sized waveguides and optical fibers, manual operations can hardly meet the requirements, and there are more complex processes and high costs for the inter-chip coupling of multi-interface photonic chips.

[0038] Limited by the above-mentioned many technical problems, it is difficult to achieve the efficient integration of multiple photonic chips in a limited space, and it cannot meet the trend of modern photonic systems towards miniaturization and high integration. The present disclosure proposes an innovative photonic chip inter-chip coupling scheme, aiming at the above-mentioned technical problems, optimizing the optical interconnection performance between photonic chips in all aspects, striving to break through the existing bottlenecks, and laying a solid foundation for the practical application and extended application of photonic chip technology.

[0039] There are various forms of photonic chip inter-chip coupling schemes, such as Figures 2 to 4 the traditional coupling method based on the fixation of optical fiber card slots shown, orFigures 5 to 6 The scheme of end-face coupling using a metalens array shown can provide flexible choices for different application scenarios with these two inter-chip coupling schemes. Combining Figures 2 to 4 As shown, by designing a card slot to fix the optical fiber and combining it with a tapered waveguide structure, the alignment and mode matching problems between the optical fiber and the waveguide can be effectively solved, significantly improving the optical coupling efficiency between photonic chips. Figure 2 As shown in part (a) of [], the optical fiber is coupled to the waveguide of the photonic chip through a tapered waveguide; Figure 2 As shown in part (b) of [], for some key dimensions of the card slot and the tapered waveguide, considering the difference between the waveguide size and the core diameter D1 of the optical fiber, it is difficult to directly align the optical fiber. It is necessary to design a card slot to fix the optical fiber and a tapered waveguide to achieve mode matching to complete the end-face coupling between the optical fiber core and the waveguide. The shape of the card slot is designed as a groove structure that closely fits the outer shape of the optical fiber. For a circular optical fiber, the card slot can be a semi-circular groove with a diameter D3 slightly larger than the cladding diameter D2 of the optical fiber to ensure that the optical fiber can be inserted smoothly and has a certain margin of movement in the card slot for fine adjustment, while not being too loose to cause the optical fiber to shake and affect the coupling accuracy. The inner wall of the card slot needs to have a certain roughness to increase the friction with the optical fiber and prevent the optical fiber from sliding in the card slot. The roughness is controlled at the nanoscale using micro-nano processing technology, which can not only effectively fix the optical fiber but also not damage the surface of the optical fiber and affect the optical transmission performance. The inner wall of the card slot can be coated with a layer of colloid with a low refractive index and high adhesion to better fix the optical fiber. The depth L of the card slot should not only ensure that enough part of the optical fiber can be embedded in the card slot to achieve stable fixation but also make the core layer of the optical fiber as close as possible to the waveguide end face to reduce the coupling distance. Generally, the depth L of the card slot is between 0.8 and 1.2 times the cladding diameter D2 of the optical fiber, and the specific value is optimized and determined according to the size parameters of the optical fiber and the waveguide. The tapered waveguide is located between the optical fiber and the waveguide of the photonic chip. The detailed structure and dimensional parameter requirements of the tapered waveguide are as Figure 3As shown, its thickness H matches the thickness of the waveguide of the photonic chip, the terminal width W2 matches the width of the waveguide of the photonic chip, and the mode field diameter generated by the starting end width W1 matches the mode field diameter of the optical fiber. Usually, W1 < W2, and the length of the tapered waveguide is T. The above parameters need to be optimized according to the simulation results. The tapered waveguide is a compact mode converter between the optical fiber and the sub-micron waveguide, which can solve the mode mismatch problem between the optical fiber and the chip waveguide and realize the transition from the fiber mode to the waveguide mode. In the manufacturing process, waveguides and tapered waveguides are fabricated using processes such as photolithography, electron beam lithography, and reactive ion etching with an accuracy controlled at the sub-micron level. Then, a fiber slot is fabricated on the substrate through precision machining, and a nano-level cutting tool is used to ensure the dimensional accuracy and inner wall roughness of the slot. Then, in a clean environment, the pre-treated (cleaned, end face cut flat, etc.) optical fiber is slowly inserted into the slot using a micro-manipulation robotic arm combined with a microscope. With the guiding and fixing functions of the slot, the optical fiber and the waveguide are initially aligned. With the help of a high-precision microscope and a micro-manipulation platform, the position of the optical fiber is finely adjusted to the optimal coupling state, and then the optical fiber is fixed in the slot using ultraviolet curable glue to achieve a sub-micron-level alignment accuracy between the optical fiber core and the waveguide end face. This inter-chip coupling scheme of the photonic chip mainly consists of a previous-stage photonic chip, a fixed structure with a slot, an optical fiber, a tapered waveguide, and a subsequent-stage photonic chip. The optical signal of the previous-stage photonic chip will be output through the waveguide, coupled into the optical fiber, transmitted to the waveguide of the subsequent-stage photonic chip, and coupled into the subsequent-stage photonic chip. The schematic diagram of the coupling scheme is as Figure 4 shown. The optical fiber serves as an intermediate medium for optical signal transmission. One end of it is coupled to the waveguide of the previous photonic chip, and the other end is coupled to the waveguide of the subsequent photonic chip to achieve long-distance and low-loss transmission of optical signals. The optical signal is output from the waveguide of the front-end photonic chip and enters the tapered waveguide. Due to the tapered structure of the tapered waveguide, the mode of the optical signal is gradually adjusted and efficiently coupled into the optical fiber. The optical fiber transmits the optical signal to the vicinity of the rear-end photonic chip. After being fixed and aligned again through the slot, the optical signal is smoothly coupled into the waveguide of the rear-end photonic chip after the mode is converted by the tapered waveguide, completing the entire inter-chip coupling process.

[0040] As Figure 5 and Figure 6 shown, it shows an inter-chip coupling scheme of a photonic chip using end-face coupling of a superlens array. The superlens placed in the slot realizes the function of beam focusing. The superlens is placed at the edge of the photonic chip. Since the waveguides for inputting and outputting optical signals of the photonic chip are very small, they can be regarded as point light sources relative to the superlens array, and the light diverges outward. As Figure 5As shown in the figure, the metalens array is placed in a slot with a depth of D and a length of L2 at the edge of the photonic chip, which can achieve the function of beam convergence, making the waveguide located at the focus of the metalens. The focal length of the metalens is L1, which can converge the parallel light received in the light-receiving slot into a light spot with a size of S1. The light field S1 of the light spot matches the end-face mode field S2 of the tapered waveguide of the end-face coupler, realizing the conversion of free-space parallel light into waveguide mode and inputting it into the photonic chip. The metalens adopts a periodic nanostructure design. By precisely regulating parameters such as the size, shape, and spacing of the nanostructures, efficient focusing of light is achieved. For light of a specific wavelength, the size of the nanostructure unit is between dozens of nanometers and hundreds of nanometers, and the period is between hundreds of nanometers and several micrometers, which is determined by strict electromagnetic theory calculations and optimizations to meet the convergence requirements of the output light of the waveguide of the optical chip with different wavelengths and modes. The metalens array can adopt a material system with a high refractive index contrast, such as a silicon-silica composite structure, and is fabricated by advanced micro-nano processing technologies such as electron beam lithography and reactive ion etching to ensure the high precision and high consistency of the metalens, reduce optical aberration, and improve the coupling efficiency. The size of the metalens array needs to completely cover the beam diameter W3. Taking the silicon-silica metalens as an example, for a cylindrical unit structure, it is necessary to ensure that the height of the silicon nanocolumns is consistent, and the phase gradient distribution is achieved by changing its radius. The thickness of the silica layer is H1, and the height of the silicon nanocolumns is H2. In order to be able to place the metalens into the slot, it is necessary to ensure that H1 + H2 is slightly less than L2 for convenient assembly. The slot is used to fix the metalens array. The shape of the slot matches the outer shape of the metalens array. The depth D of the slot ensures that the metalens array can be firmly embedded, and at the same time ensures the precise alignment of the optical center of the metalens with the waveguide. The material of the slot matches the material of the photonic chip to ensure the same coefficient of thermal expansion and avoid deformation of the slot caused by temperature changes, which affects the optical path. The slot structure is fabricated by precision machining to ensure that the dimensional accuracy and surface finish meet the requirements. When assembling the metalens array into the slot, it is necessary to ensure that the metalens array is carefully embedded into the slot using a high-precision alignment device in a clean environment, and at the same time ensure the precise alignment of the metalens with the waveguide. The alignment accuracy can be verified by means such as optical interference measurement. The length of the light-receiving slot is L3, and the cross-section is approximately semi-circular with a diameter of W1, which is slightly larger than the physical size of the metalens to ensure sufficient light is received. After the waveguide of the output optical signal of the previous-stage photonic chip passes through end-face coupling and emits light as a point source, after the action of the metalens, it is converted into parallel light in free space for propagation, received by the metalens array at the slot of the next-stage photonic chip, converted into a converging light beam, focused on the waveguide for receiving the optical signal, and transmitted into the next-stage photonic chip through end-face coupling, thus realizing the transmission and coupling of optical signals between photonic chips. The schematic diagram of the coupling scheme is shown in Figure 6As shown in the figure. Since the transmission of optical signals between two photonic chips is in free space and no additional optical fibers or cladding materials are required, the mechanical stability is greatly improved. It is only necessary to ensure that the main optical axes of the metalenses of the front and rear stages of photonic chips are on the same straight line to ensure the normal operation of the optical path. Similar to the pins of an electronic chip, the input and output waveguides of different optical chips can be coupled through metalenses. By reasonably placing them on the substrate and keeping the optical path unobstructed, the coupled transmission of multiple photonic chips and multiple channels can be achieved.

[0041] As can be seen from the above, the optical fiber slot fixing scheme performs excellently in scenarios with short-distance and high-precision alignment requirements. It can achieve sub-micron alignment accuracy, and the optical signal can be transmitted bidirectionally with reciprocity; the metalens array end-face coupling scheme utilizes the free-space transmission characteristics, simplifies the structure, does not require filling materials, improves the mechanical stability, and is convenient for realizing multi-chip and multi-channel integration, and the transmission direction of the optical signal can be reciprocal. However, the processing and assembly difficulties of the above two technical solutions are high, and they have limitations when facing complex optical path layouts.

[0042] The inter-chip optical interconnection method of the present disclosure is based on the combination of a grating coupler and a mirror, and is combined with a chip slot. The scheme is suitable for occasions with complex optical path layouts and the need for flexible conversion between waveguides and free-space light. It can effectively solve the mismatch problem between waveguide chips and free-space light modes. The processing and assembly difficulties are less than those of the optical fiber slot fixing scheme, and it can achieve bidirectional transmission of optical signals with reciprocity; the chip slot large-scale standardized inter-chip coupling scheme for photonic chips is compatible with traditional CMOS processes, and realizes large-scale scalable inter-chip coupling through standardized and unified design and processing, and realizes the cascading between different functional chips. The present disclosure fixes the mirror with a silica filling material, greatly reducing the risk of optical path deviation caused by external vibrations, temperature changes and other factors, ensuring the long-term stability of optical signal transmission, and reducing the system maintenance cost. It comprehensively solves the key problems such as alignment, mode matching and optical path stability of inter-chip coupling of photonic chips, greatly improves the optical coupling efficiency, and promotes the practical application process of photonic chip technology. Whether it is a photonic chip made of different materials such as silicon-based or silicon nitride-based, the method of the present disclosure can be adapted by fine-tuning the parameters of key components. At the same time, it also solves the problem of inter-chip coupling integrated packaging of photonic chips, enabling different types and requirements of photonic chip integrated systems to be applied in optoelectronic systems, greatly expanding its application scope, and promoting the application process of small, high-speed, low-power-consumption, and high-integration photonic integrated systems.

[0043] To make the purpose, technical solution and advantages of the present disclosure clearer and more understandable, the following further details the present disclosure in combination with specific embodiments and with reference to the accompanying drawings.

[0044] In the embodiments of the present disclosure, in combination with Figure 1 、 Figures 8 - 10As shown, a method for inter-chip optical interconnection of a large-scale photonic chip is provided, including the following operation steps S1 - S5:

[0045] S1: Prepare a plurality of grooves on a substrate;

[0046] S2: Fabricate a photonic chip and install the photonic chip in the plurality of grooves;

[0047] S3: Prepare a cladding layer on the substrate and the photonic chip;

[0048] S4: Fabricate a mirror on the surface of the cladding layer; and

[0049] S5: Input an optical signal from the input port of one photonic chip. The optical signal processed by the photonic chip is output from the output port of the photonic chip to the cladding layer at a specific diffraction angle, and finally reflected by the mirror to other photonic chips and finally output, realizing inter-chip optical interconnection of the photonic chips.

[0050] According to an embodiment of the present disclosure, the photonic chip includes: a chip substrate; an optical signal processing module located on the chip substrate; and grating couplers located on both sides of the optical signal processing module and both connected to the optical signal processing module through optical waveguides. One of the grating couplers serves as the input port of the photonic chip, and the other grating coupler serves as the output port of the photonic chip.

[0051] According to an embodiment of the present disclosure, the grating coupler adopts a periodic sub-wavelength grating structure, and by optimizing the grating structure parameters, efficient coupling of the incident optical signal is achieved. The grating structure parameters include the grating period, the grating duty cycle, and the groove etching depth of the grating structure.

[0052] According to an embodiment of the present disclosure, the distance Q between two-stage photonic chips for optical interconnection is related to the thickness H0 of the cladding layer and the diffraction angle θ of the grating coupler in the photonic chip, and the expression is as follows:

[0053] Q = 2H0tanθ.

[0054] According to an embodiment of the present disclosure, the mirror is a high-reflectivity metal coating or a multi-layer dielectric film, and the mirror is a planar structure or a micro-curved surface structure.

[0055] According to an embodiment of the present disclosure, the optical signal undergoes mode conversion through the grating coupler serving as the input port, and then is transmitted through the optical waveguide to the optical signal processing module for processing, and then is transmitted by the grating coupler serving as the output port to the mirror and then reflected to the input port of the next-stage photonic chip. By analogy, inter-chip optical interconnection coupling of multiple-stage photonic chips is realized, and finally the optical signal is output from the output port of the last-stage photonic chip.

[0056] According to an embodiment of the present disclosure, a top cladding is further fabricated between the photonic chip and the cladding layer, and the top cladding is used to reduce the scattering and loss of optical signals.

[0057] According to an embodiment of the present disclosure, a buried oxide layer is further fabricated between the photonic chip and the substrate, and the buried oxide layer is used to reduce the leakage of optical signals to the substrate during transmission.

[0058] An embodiment of another aspect of the present disclosure further provides a photonic chip integrated system implemented based on the above-mentioned inter-chip optical interconnection method of the photonic chip, as Figure 9 and Figure 10 shown, the photonic chip integrated system includes:

[0059] A substrate, on which a plurality of grooves are fabricated;

[0060] A plurality of photonic chips, mounted in the plurality of grooves;

[0061] A cladding layer, covering the substrate and the photonic chips; and

[0062] A mirror, fabricated on the surface of the cladding layer;

[0063] Wherein, the photonic chip includes: a chip substrate, an optical signal processing module, an optical waveguide, and a grating coupler; the optical signal processing module is located on the chip substrate; the grating couplers are located on both sides of the optical signal processing module and are both connected to the optical signal processing module through the optical waveguide, and one of the grating couplers serves as the input port of the photonic chip, and the other grating coupler serves as the output port of the photonic chip; the optical signal is input from the input port of one photonic chip, and the optical signal processed by this photonic chip is output from the output port of this photonic chip at a specific diffraction angle into the cladding layer, and finally reflected by the mirror to other photonic chips and finally output.

[0064] Specifically, in combination with Figure 7 and Figure 8 shown, the optical signal of the previous-stage photonic chip enters the grating coupler through the waveguide to realize the conversion from the waveguide mode to the free-space optical mode. According to the diffraction characteristics of the grating, the light is emitted into the free space at a specific angle θ. After the optical signal is reflected by the mirror, it is incident on the grating coupler of the next-stage photonic chip at an appropriate angle θ. According to the grating coupling principle, the light is converted back to the waveguide mode, efficiently coupled into the waveguide, and then connected to the subsequent processing system to complete the optical signal transmission between the photonic chips.

[0065] According to an embodiment of the present disclosure, in combination with Figure 7 and Figure 8As shown, the grating coupler adopts a sub-wavelength grating structure. By optimizing parameters such as the grating period P, duty cycle, etching depth D, etc., efficient coupling of optical signals with specific wavelengths is achieved. The waveguide material can be materials with suitable optical properties such as silicon, silicon nitride, polymer, etc. Taking the commonly used silicon material as an example, the grating coupler consists of a periodic grating structure, and its material can also be the above-mentioned optical materials. The thickness H2 of the silicon layer is compatible with the waveguide, usually a 220-nm-thick silicon layer, which can achieve good optical field confinement and transmission characteristics. The thickness H1 of the top silica cladding is usually 1 - 2 μm. A suitable top cladding thickness can reduce light scattering and loss. The thickness H3 of the buried oxide layer of silica is generally about 2 - 3 μm, and its function is to isolate the silicon waveguide from the substrate, reduce the leakage of light to the substrate during transmission, and ensure that the optical field mainly propagates in the silicon waveguide and grating region. The grating period P is generally between several hundred nanometers and several micrometers, which is determined according to the target optical wavelength based on strict coupling theory calculations, so that light undergoes appropriate diffraction to ensure good matching with the waveguide mode and free-space light mode of the photon chip. The grating duty cycle can be represented by the trench width W1 and the tooth width W2. After determining the number of trenches N1 and the number of teeth N2, the trench width and tooth width can be optimized through simulation software to obtain a higher coupling efficiency. The grating length L is usually 10 - 50 μm, which is jointly determined by the trench width, tooth width, number of trenches, and number of teeth. A longer grating is beneficial to improving the coupling efficiency but will increase the chip area. A shorter grating is beneficial to realizing a compact structure design, but other parameters may need to be optimized to ensure the coupling performance. For a standard 220-nm-thick silicon waveguide, the etching depth D is usually 70 - 220 nm, and it needs to be adjusted according to the thickness of the silicon layer and the optimization of the coupling efficiency. A high-reflectivity material is selected to make the mirror, such as a metal-coated mirror or a multi-layer dielectric film mirror, and the reflectivity can reach more than 95% to ensure low loss during the reflection of the optical signal. The shape and size of the mirror are customized according to the optical path design requirements, generally a planar or micro-curved surface structure. In order to fix the mirror in the appropriate position, a silica filling material with a thickness of H0 can be filled between the grating coupler and the mirror, between the photon chips, effectively fixing and supporting the mirror to prevent it from affecting the optical path stability due to vibration or displacement. The distance between the grating couplers of the front and rear two-stage chips is Q, then there is , where is the thickness of the silica filling material, and θ is the diffraction angle of the grating coupler. The photonic chip uses silicon to fabricate waveguides and grating couplers, taking into account both waveguide performance and process compatibility. It is prepared using processes such as electron beam lithography and reactive ion etching to ensure the accuracy of the grating parameters. The silica filling material can be directly deposited with silica by methods such as PECVD, thermal evaporation, or electron beam evaporation, effectively controlling the thickness of the silica filling material. On this basis, the mirror can also be prepared using the photolithography process. A photoresist is spin-coated on the silica filling material, a suitable mask template is designed, the position of the mirror is determined under a microscope for exposure, and a silver or aluminum film mirror with a determined size and shape is obtained. The silver or aluminum film is deposited using processes such as chemical vapor deposition, thermal evaporation, or magnetron sputtering, precisely controlling the film thickness and uniformity.

[0066] According to an embodiment of the present disclosure, in combination with Figure 9 and Figure 10As shown, further, based on the inter-chip coupling scheme combining a grating coupler and a mirror, an inter-chip optical interconnection coupling scheme for large-scale standardized photonic chips based on chip slots is proposed, demonstrating the inter-chip coupling structure of the large-scale standardized photonic chips of the present disclosure. Light enters from the input port, undergoes mode conversion through the grating coupler, is transmitted to the optical signal processing module of the photonic chip for processing, then outputs through the grating coupler, enters the next-level photonic chip after being reflected by the mirror, and finally outputs from the output port, intuitively presenting the transmission path of the optical signal between chips. By adding the design of chip slots and combining with the unified and standardized design during chip fabrication, different chips can be placed in the chip slots. The chip slots provide precise positioning for the chips, facilitating large-scale integration and enabling more complex functions, such as optical computing, optical neural networks, etc. The specific process flow is as follows: (1) Design and fabrication of chip slots. In the early stage of chip fabrication, according to the type, size, and overall layout plan of the photonic chip, a layout is drawn to design the chip slots, determine the shape, size, and distribution position of the chip slots on the substrate, and use photolithography and etching processes to fabricate the chip slots on the substrate. First, a photoresist is uniformly coated on the substrate surface, and through steps such as exposure and development, the pattern of the chip slots is transferred from the mask to the photoresist to form a photoresist mask. Then, using etching techniques (such as reactive ion etching in dry etching, selecting appropriate etching gases according to the characteristics of the substrate material, and fluorine-containing gases can be used for silicon substrates), the substrate material is precisely etched according to the pattern of the photoresist mask to form the chip slots. During the etching process, parameters such as etching time and gas flow rate are strictly controlled to ensure the dimensional accuracy and vertical sidewalls of the chip slots. (2) Incorporation of photonic chips into the slots during chip fabrication. The design of photonic chips requires a standardized interface architecture, that is, the size of the photonic chips, the size and position of the grating couplers need to be unified standards, and the input and output interfaces are conveniently designed at the front and rear edges of two adjacent levels of the photonic chips. In the cleanroom, the cleaned photonic chips are accurately placed into the chip slots, paying attention to the direction and position of the input and output interfaces of each photonic chip. (3) Design and fabrication of the silica cladding layer. The thickness of the silica cladding layer is determined using the diffraction angle of the grating coupler and the chip pitch. The design of the grating coupler and the calculation method of the silica thickness are as described above. The range of the silica cladding layer is restricted by photolithography, and a silica material is deposited in the area where the mirror needs to be placed using growth methods such as PECVD. Taking PECVD as an example, the substrate with the placed chips is placed into the reaction chamber of the PECVD equipment, and reaction gases such as silane (SiH4) and oxygen (O2) are introduced. Under the action of radio frequency plasma, the reaction gases undergo decomposition, ionization, and other reactions to deposit a silica thin film on the substrate and the chip surface. By precisely controlling parameters such as the flow rate of the reaction gases, radio frequency power, reaction temperature, and deposition time, precise control of the thickness of the silica cladding layer is achieved, ensuring good uniformity of the film thickness. (4) Fabrication of the mirror.After the silicon dioxide covering layer is deposited and cured and stabilized, a photoresist is spin-coated uniformly on the surface of the silicon dioxide by using a spin-coating device. A suitable type of photoresist is selected according to the design requirements of the mirror, and parameters such as the rotation speed and time of spin-coating are controlled. The mask plate is placed on the mask plate stage of the photolithography machine, and the substrate (including the chip) spin-coated with the photoresist is placed on the working stage of the photolithography machine. Equipment such as a microscope is used to assist in observation to ensure that the mirror mask plate is accurately aligned with the predetermined position on the chip, and then exposure is carried out to transfer the pattern of the mask plate to the photoresist. Then, a metal reflective film is deposited by processes such as chemical vapor deposition, thermal evaporation, or magnetron sputtering. (5) Finally, an optical signal is input from the input port of a photon chip, and the optical signal processed by this photon chip is output from the output port of this photon chip to the covering layer at a specific diffraction angle, and finally is reflected by the mirror to other photon chips and finally output, realizing inter-chip optical interconnection of photon chips.

[0067] It should be noted that the coupling method based on fixing by an optical fiber slot is applicable to the scenario where a photon chip inputs and outputs optical signals through an optical fiber; the scheme of using end-face coupling of a superlens array is applicable to the application scenario where a photon chip receives, transmits, and outputs free-space light; and the coupling method based on the combination of a grating coupler and a mirror in the present disclosure is applicable to both the cases of optical fiber transceiver and free-space light transceiver.

[0068] So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It should be noted that, in the accompanying drawings or the main text of the specification, the implementation manners that are not depicted or described are all forms known to those of ordinary skill in the art and are not described in detail. In addition, the definitions of the above-mentioned various elements and methods are not limited to the specific structures, shapes, or manners mentioned in the embodiments, and those of ordinary skill in the art can make simple changes or replacements to them.

[0069] It should be noted that, in this article, unless otherwise specified, an element with "a" does not limit to having only one such element, but may have one or more such elements.

[0070] In addition, in this article, unless otherwise specified, ordinal numbers such as "first" and "second" are only used to distinguish multiple elements with the same name, and do not indicate that there is a rank, level, execution order, or process order between them. A "first" element and a "second" element may appear in the same component together, or may appear in different components separately. The existence of an element with a larger ordinal number does not necessarily mean the existence of another element with a smaller ordinal number.

[0071] In this document, unless otherwise specified, the so-called feature A "or" (or) or "and / or" (and / or) feature B means that A exists alone, B exists alone, or A and B exist simultaneously; the so-called feature A "and" (and) or "and" (and) or "and" (and) feature B means that A and B exist simultaneously; the so-called "comprising", "including", "having", "containing" means including but not limited to this.

[0072] In addition, in this document, terms such as "above", "below", "left", "right", "front", "rear", or "between" are only used to describe the relative positions between multiple components, and in the interpretation, it can be extended to include cases of translation, rotation, or mirror image. In addition, in this document, unless otherwise specified, the statement "a component is on another component" or a similar statement does not necessarily mean that the component contacts the other component.

[0073] In addition, unless the steps are specifically described or must occur in sequence, the order of the above steps is not limited to those listed above, and can be changed or rearranged according to the required design. And the above embodiments can be used in combination with each other or in combination with other embodiments based on considerations of design and reliability, that is, the technical features in different embodiments can be freely combined to form more embodiments.

[0074] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present disclosure. It should be understood that the above are only specific embodiments of the present disclosure and are not used to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A large-scale photonic chip-to-chip optical interconnection method, comprising: preparing a plurality of grooves on a substrate; preparing a photonic chip and installing the photonic chip in a plurality of grooves; preparing a cover layer on the substrate and the photonic chip; preparing a reflector on the surface of the cover layer; as well as An optical signal is input from the input port of a photonic chip. After being processed by the photonic chip, the optical signal is output from the output port of the photonic chip to the covering layer at a specific diffraction angle, and finally reflected by the reflector to other photonic chips and finally output, thereby realizing optical interconnection between photonic chips.

2. The method for optical interconnection between photonic chips according to claim 1, wherein the photonic chip comprises: Chip substrate; an optical signal processing module, located on the chip substrate; and The grating couplers are located on both sides of the optical signal processing module and are connected to the optical signal processing module through optical waveguides, wherein the grating coupler on one side serves as the input port of the photonic chip, and the grating coupler on the other side serves as the output port of the photonic chip.

3. According to the optical interconnection method between photonic chips according to claim 2, the grating coupler adopts a periodic sub-wavelength grating structure, and achieves efficient coupling of the incident light signal by optimizing the grating structure parameters.

4. According to the optical interconnection method between photonic chips according to claim 3, the grating structure parameters include grating period, grating duty cycle, and groove etching depth of the grating structure.

5. According to the optical interconnection method between photonic chips in claim 2, the spacing Q between the two-stage photonic chips of the optical interconnection is related to the thickness H0 of the cover layer and the diffraction angle θ of the grating coupler in the photonic chip, and the expression is as follows: Q=2H0tanθ. 6 . The method for optical interconnection between photonic chips according to claim 1 , wherein the reflector is a metal coating or a multi-layer dielectric film with high reflectivity, and the reflector is a planar structure or a micro-curved structure.

7. According to the method for optical interconnection between photonic chips as described in claim 2, the optical signal is mode-converted through a grating coupler as an input port, and then transmitted to an optical signal processing module through an optical waveguide for processing. It is then transmitted to a reflector by a grating coupler as an output port and then reflected to the input port of the next-level photonic chip. This process is repeated to realize optical interconnection coupling between multiple levels of photonic chips, and finally the optical signal is output from the output port of the photonic chip of the last level.

8. According to the method for optical interconnection between photonic chips as described in claim 2, a top cladding layer is also prepared between the photonic chip and the cover layer, and the top cladding layer is used to reduce scattering and loss of optical signals.

9. According to the method for optical interconnection between photonic chips as described in claim 2, a buried oxide layer is also prepared between the photonic chip and the substrate, and the buried oxide layer is used to reduce the leakage of optical signals to the substrate during transmission.

10. A photonic chip integration system implemented based on the photonic chip optical interconnection method according to any one of claims 1 to 9, comprising: A substrate having a plurality of grooves formed thereon; A plurality of photonic chips are installed in the plurality of grooves; A covering layer, covering the substrate and the photonic chip; as well as A reflector, prepared on the surface of the covering layer; The photonic chip comprises: a chip substrate, an optical signal processing module, an optical waveguide, and a grating coupler; the optical signal processing module is located on the chip substrate; the grating couplers are located on both sides of the optical signal processing module and are connected to the optical signal processing module through optical waveguides, wherein the grating coupler on one side serves as the input port of the photonic chip, and the grating coupler on the other side serves as the output port of the photonic chip; an optical signal is input from the input port of a photonic chip, and the optical signal processed by the photonic chip is output from the output port of the photonic chip to the covering layer at a specific diffraction angle, and finally reflected by the reflector to other photonic chips and finally output.

Images