SCM (Single Chip Microcomputer) and electronic device

Abstract

The invention discloses a single-chip microcomputer and an electronic device. The single-chip microcomputer has a controller area network (CAN) function. The single-chip microcomputer provides a communication controller corresponding to the CAN function and generates a sending signal in a digital form. A digital signal remapping circuit is further arranged in the single-chip microcomputer and used for remapping the sending signal into a first chip output signal and a second chip output signal. The single-chip microcomputer outputs the first chip output signal through a first pin so as to drive a differential positive end signal line of the CAN. The single-chip microcomputer outputs the second chip output signal through a second pin so as to drive a differential negative terminal signal line of the CAN.

Description

Technical Field

[0001] The present invention relates to the control of the transmission line of a controller area network (CAN). Background Art

[0002] The controller area network (CAN) is a bus standard with rich functions that can operate without a host, allowing microcontroller units (MCUs) and instruments on the network to communicate with each other.

[0003] In a traditional design, a microcontroller unit (MCU) needs to externally connect a CAN transceiver to convert the transmitted signal (CANTX) in digital form so as to drive a differential positive signal line (CANH) and a differential negative signal line (CANL) of the CAN.

[0004] However, CAN transceivers are quite expensive, which increases the cost of the overall electronic device. Summary of the Invention

[0005] In this case, the CAN transceiver is replaced in a low-cost manner.

[0006] A microcontroller unit (MCU) implemented according to an embodiment of this case includes a CAN communication controller (CANcontroller), a digital signal remapping circuit, a first pin, and a second pin corresponding to the CAN. The communication controller is used to generate a transmitted signal (CANTX) in digital form. The digital signal remapping circuit remaps the transmitted signal (CANTX) into a first chip output signal and a second chip output signal. The MCU outputs the first chip output signal through the first pin to drive a differential positive signal line (CANH) of the CAN. The MCU outputs the second chip output signal through the second pin to drive a differential negative signal line (CANL) of the CAN.

[0007] In one embodiment, the MCU further includes a third pin, a fourth pin, and a comparator. The MCU is coupled to the differential positive signal line (CANH) of the CAN through the third pin and to the differential negative signal line of the CAN through the fourth pin. The comparator receives signals from the third pin and the fourth pin for comparison and generates a received signal (CANRX) in digital form, which is input to the CAN communication controller of the CAN. In this way, the received signal (CANRX) can be converted inside the MCU and fed back to the CAN communication controller (CAN controller).

[0008] In traditional microcontrollers (MCUs), the transmission signal (CANTX) is output and processed by an expensive CAN transceiver to drive the CAN transmission line. In contrast, in this case, the transmission signal (CANTX) is preliminarily converted inside the microcontroller (MCU), replacing some functions of the CAN transceiver. Additionally, in traditional microcontrollers (MCUs), the received signal (CANRX) is converted by the CAN transceiver and then input into the microcontroller (MCU). In contrast, in this case, the microcontroller (MCU) itself converts the received signal (CANRX). This case can omit the expensive CAN transceiver.

[0009] This case further proposes an electronic device using the aforementioned microcontroller (MCU).

[0010] Specific embodiments are hereinafter given and, in conjunction with the accompanying drawings, the content of the present invention is described in detail. Description of the Drawings

[0011] Figure 1 It is a block diagram illustrating an electronic device 100 implemented according to an embodiment of this case, where a microcontroller unit (abbreviated as MCU) 102 is used; and

[0012] Figure 2 、 Figure 3 、 Figure 4 Illustrate electronic devices 200, 300, and 400 respectively according to different embodiments of this case.

[0013] Symbol Description

[0014] 100, 200, 300: Electronic devices

[0015] 102: Microcontroller

[0016] 104: Communication controller for Controller Area Network (CAN)

[0017] 106: Digital signal remapping circuit

[0018] CANH, CANL: Differential positive terminal signal line and differential negative terminal signal line of CAN

[0019] CAN_H_IO, CAN_L_IO: First and second chip output signals

[0020] CANTX: Transmission signal

[0021] CANRX: Received signal

[0022] cmp: Comparator

[0023] MUX1…MUX6: First…Sixth Multiplexers

[0024] pin1…pin4: First…Fourth Pins

[0025] R1…R6: First…Sixth Resistors

[0026] T1, T2: First, Second Transistors

[0027] VH: High Potential

[0028] VL: Low Potential Detailed Implementation Manner

[0029] The following description lists various embodiments of the present invention. The following description introduces the basic concepts of the present invention and is not intended to limit the content of the present invention. The actual scope of the invention should be defined according to the scope of the patent application. Various functional blocks are not limited to being implemented separately and can also be combined together to share certain functions.

[0030] Figure 1 FIG. is a block diagram illustrating an electronic device 100 implemented according to an embodiment of the present case, in which a microcontroller unit (MCU) 102 is used. The microcontroller 102 includes a communication controller (CAN controller) 104 that complies with a controller area network (CAN) specification. The communication controller 104 generates a transmission signal CANTX in digital form. The microcontroller 102 further includes a digital signal remapping circuit 106 that remaps the transmission signal CANTX into a first chip output signal CAN_H_IO and a second chip output signal CAN_L_IO. The microcontroller 102 outputs the first chip output signal CAN_H_IO through a first pin pin1 to drive a differential positive terminal signal line CANH of the controller area network (CAN), and outputs the first chip output signal CAN_H_IO through a second pin pin2 to drive a differential negative terminal signal line CANL of the controller area network (CAN).

[0031] A traditional microcontroller (MCU) directly outputs the transmission signal CANTX for further processing by an expensive controller area network transceiver (CAN transceiver). In contrast, in the present case, inside the microcontroller (MCU) 102, the digital signal remapping circuit 106 preliminarily converts the transmission signal CANTX into two signals (CAN_H_IO, CAN_L_IO), so that the differential positive terminal signal line CANH and the differential negative terminal signal line CANL of the controller area network (CAN) can be separately driven, and the driving timing can be better adjusted, which is conducive to realizing high-speed transmission.

[0032] As for the receiving function of the traditional CAN transceiver, the present case also proposes a solution.

[0033] As Figure 1 shown, the microcontroller (MCU) 102 further includes a third pin pin3, a fourth pin pin4, and a comparator cmp. The microcontroller (MCU) 102 is coupled to the differential positive terminal signal line CANH of the controller area network (CAN) through the third pin pin3, and is coupled to the differential negative terminal signal line CANL of the controller area network (CAN) through the fourth pin pin4. The comparator cmp is coupled to the third pin pin3 through the negative input terminal '-' and is coupled to the fourth pin pin4 through the positive input terminal '+', and compares the received signals to generate a received signal (CANRX) in digital form and inputs it to the communication controller 104. In this way, the microcontroller 102 itself can convert the received signal CANRX and feedback it to the communication controller 104, replacing the receiving function of the traditional CAN transceiver.

[0034] Table 1 shows the transmission line transmission rules of the controller area network (CAN).

[0035]

[0036] Table 1

[0037] The digital signal remapping circuit 106 of the present case, according to the first chip output signal CAN_H_IO and the second chip output signal CAN_L_IO remapped from the transmission signal CANTX, will cooperate with an external circuit to drive the differential positive terminal signal line CANH and the differential negative terminal signal line CANL according to the rules of Table 1.

[0038] Figure 2 An electronic device 200 is illustrated according to an embodiment of the present case.

[0039] The multiplexers MUX1 to MUX6 constitute the digital signal remapping circuit 106 specially provided inside the single-chip microcomputer 102 in this case. In particular, the multiplexers in the illustrated chip in this case are digital multiplexers. The first multiplexer MUX1 outputs the first chip output signal CAN_H_IO under the switching of the transmission signal CANTX. The second multiplexer MUX2 outputs the second chip output signal CAN_L_IO under the switching of the transmission signal CANTX. Each of the third to sixth multiplexers MUX3 to MUX6 has a first input terminal receiving a high potential VH, a second input terminal receiving a low potential VL, and a third input terminal floating. The output terminal of the third multiplexer MUX3 is coupled to a first input terminal '0' of the first multiplexer MUX1. The output terminal of the fourth multiplexer MUX4 is coupled to a second input terminal '1' of the first multiplexer MUX1. The output terminal of the fifth multiplexer MUX5 is coupled to a first input terminal '0' of the second multiplexer MUX2. The output terminal of the sixth multiplexer MUX6 is coupled to a second input terminal '1' of the second multiplexer MUX2.

[0040] With such a design, the digital signal remapping circuit 106 can flexibly provide the first chip output signal CAN_H_IO and the second chip output signal CAN_L_IO according to the design of the external circuit of the single-chip microcomputer (MCU) 102, so as to drive the differential positive terminal signal line CANH and the differential negative terminal signal line CANL in accordance with the rules in Table 1.

[0041] The control of the third multiplexer MUX3 and the fourth multiplexer MUX4 depends on how the first chip output signal CAN_H_IO output from the first pin pin1 drives the differential positive terminal signal line CANH. The control of the fifth multiplexer MUX5 and the sixth multiplexer MUX6 depends on how the second chip output signal CAN_L_IO output from the second pin pin2 drives the differential negative terminal signal line CANL.

[0042] Figure 2 In the implementation manner, the third multiplexer MUX3 selects the low potential VL to input the first input terminal '0' of the first multiplexer MUX1, the fourth multiplexer MUX4 selects the high potential VH to input the second input terminal '1' of the first multiplexer MUX1, the fifth multiplexer MUX5 selects the high potential VH to input the first input terminal '0' of the second multiplexer MUX2, and the sixth multiplexer MUX6 selects the low potential VL to input the second input terminal '1' of the second multiplexer MUX1.

[0043] corresponding to Figure 2For the operation of remapping (MUX1 to MUX6), in the electronic device 200, a first driving circuit (including a first transistor T1, a first resistor R1, and a second resistor R2) is installed on the first pin pin1 of the single-chip microcomputer 102 to drive the differential positive terminal signal line CANH, and a second driving circuit (including a second transistor T2, a third resistor R3, and a fourth resistor R4) is installed on the second pin pin2 to drive the differential negative terminal signal line CANL. The first transistor T1 has an emitter coupled to a voltage source (such as 3.3V shown in the figure, or others), a base coupled to the first output pin pin1 through the first resistor R1, and a collector coupled to the differential positive terminal signal line CANH through the second resistor R2. The second transistor T2 has an emitter grounded, a base coupled to the second output pin pin2 through the third resistor R3, and a collector coupled to the differential negative terminal signal line CANL through the fourth resistor R4. With such a design, the differential positive terminal signal line CANH and the differential negative terminal signal line CANL indeed follow the specifications in Table 1 and operate corresponding to the transmitted signal CANTX.

[0044] In particular, the first driving circuit (T1, R1, R2) and the second driving circuit (T2, R3, R4) are symmetrically designed to drive the differential positive terminal signal line CANH and the differential negative terminal signal line CANL with approximately no time difference. The electronic device 200 can be a high-speed device. The resistors R1 to R4 can also be simply fine-tuned to match the CAN specifications.

[0045] In the figure, the differential negative terminal signal line CANL is coupled to the fourth pin pin4 through a fifth resistor R5, and the differential positive terminal signal line CANH is coupled to the third pin pin3 through a voltage divider (formed by series connection of a sixth resistor R6 and a seventh resistor R7). The single-chip microcomputer 102 accurately compares the received signal CANRX internally and feeds it back to the CAN controller 104. The resistors R5 to R7 can also be simply fine-tuned to match the CAN specifications.

[0046] Figure 3 According to another embodiment of this case, an electronic device 300 is illustrated. Figure 3 In the embodiment, the input of the first multiplexer MUX1 is the same Figure 2 ... The fifth multiplexer MUX5 selects the low potential VL to input the first input terminal '0' of the second multiplexer MUX2, and the sixth multiplexer MUX6 selects to float the second input terminal '1' of the second multiplexer MUX1. Correspondingly, the second pin pin2 is directly connected to the differential negative terminal signal line CANL without passing through Figure 2 the second driving circuit (T2, R3, R4), and the driving force is stronger. With such a design, the differential negative terminal signal line CANL still follows the specifications in Table 1 and operates corresponding to the transmitted signal CANTX.

[0047] Figure 4 Illustrate another electronic device 400 according to an embodiment of this case. Figure 4 In the embodiment, the third multiplexer MUX3 selects the high potential VH to input the first input terminal '0' of the first multiplexer MUX1, and the fifth multiplexer MUX5 floats the second input terminal '1' of the first multiplexer MUX1. The inputs of the second multiplexer MUX2 are the same. Figure 3 Correspondingly, the first pin pin1 is directly connected to the differential positive terminal signal line CANH without passing through the first driving circuit (T1, R1, R2) in FIGS. 2 and 3, and the driving force is stronger. Figure 4 The electronic device 400 further drives the differential positive terminal signal line CANH and the differential negative terminal signal line CANL without a time difference. The electronic device 400 can be a high-speed device.

[0048] In other embodiments, the digital signal remapping circuit, the first driving circuit, and the second driving circuit may all have other variations. Any technology that provides the function of remapping the transmission signal CANTX inside the microcontroller (MCU) and outputs in two paths to drive the CAN transmission line by the microcontroller (MCU) belongs to the scope of protection of this case.

[0049] Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined by the claims.

Claims

1. A single chip microcomputer, characterized in that: include: a communication controller, corresponding to a controller area network, generating a transmission signal in digital form; a digital signal remapping circuit, remapping the transmission signal into a first chip output signal and a second chip output signal; A first pin, used to output the first chip output signal to drive a differential positive signal line of the controller area network; as well as A second pin is used to output the second chip output signal to drive a differential negative signal line of the controller area network.

2. The single chip microcomputer according to claim 1, characterized in that: It also includes: A third pin, for coupling to the differential positive signal line of the controller area network; A fourth pin, for coupling to the differential negative signal line of the controller area network; as well as A comparator receives signals from the third pin and the fourth pin for comparison and generates a receiving signal in digital form for input into the communication controller.

3. The single chip microcomputer according to claim 1, characterized in that: The digital signal remapping circuit comprises: a first multiplexer, outputting the first chip output signal under the switching of the sending signal; and A second multiplexer outputs the second chip output signal when the sending signal is switched.

4. The single chip microcomputer according to claim 3, characterized in that: The digital signal remapping circuit further comprises: a third multiplexer having a first input terminal receiving a high potential, a second input terminal receiving a low potential, a third input terminal being floating, and an output terminal coupled to a first input terminal of the first multiplexer; a fourth multiplexer having a first input terminal receiving the high potential, a second input terminal receiving the low potential, a third input terminal being floating, and an output terminal coupled to a second input terminal of the first multiplexer; a fifth multiplexer having a first input terminal receiving the high potential, a second input terminal receiving the low potential, a third input terminal being floating, and an output terminal coupled to a first input terminal of the second multiplexer; and a sixth multiplexer having a first input terminal receiving the high potential, a second input terminal receiving the low potential, a third input terminal being floating, and an output terminal coupled to a second input terminal of the second multiplexer; in: The control of the third multiplexer and the fourth multiplexer depends on how the first chip output signal output by the first pin drives the differential positive signal line; and The control of the fifth multiplexer and the sixth multiplexer depends on how the second chip output signal output by the second pin drives the differential negative signal line.

5. The single chip microcomputer according to claim 3, characterized in that: In the first multiplexer, a first input terminal corresponding to the 0 value of the transmitted signal receives a high potential; In the first multiplexer, a second input terminal corresponding to the 1 value of the sending signal is floating; In the second multiplexer, a first input terminal corresponding to the 0 value of the transmitted signal receives a low potential; and In the second multiplexer, a second input terminal corresponding to the 1 value of the sending signal is floating.

6. An electronic device, characterized in that: include: The single chip computer as claimed in claim 3, wherein in the first multiplexer, a first input terminal corresponding to the 0 value of the transmitted signal receives a low potential, in the first multiplexer, a second input terminal corresponding to the 1 value of the transmitted signal receives a high potential, in the second multiplexer, a first input terminal corresponding to the 0 value of the transmitted signal receives the high potential, and in the second multiplexer, a second input terminal corresponding to the 1 value of the transmitted signal receives the low potential; a first driving circuit coupled between the first pin and the differential positive signal line; and A second driving circuit is coupled between the second pin and the differential negative signal line.

7. The electronic device according to claim 6, wherein: The first driving circuit comprises: a first transistor; a first resistor; and a second resistor; The first transistor has an emitter coupled to a voltage source, a base coupled to the first output pin via the first resistor, and a collector coupled to the differential positive signal line via the second resistor.

8. An electronic device, characterized in that: include: The single chip computer as claimed in claim 3, wherein in the first multiplexer, a first input terminal corresponding to the 0 value of the transmitted signal receives a low potential, in the first multiplexer, a second input terminal corresponding to the 1 value of the transmitted signal receives a high potential, in the second multiplexer, a first input terminal corresponding to the 0 value of the transmitted signal receives the low potential, and in the second multiplexer, a second input terminal corresponding to the 1 value of the transmitted signal is floating; and A first driving circuit coupled between the first pin and the differential positive signal line; Wherein, the second pin is directly connected to the differential negative signal line.

9. An electronic device, characterized in that: include: The single chip computer as claimed in claim 3, wherein in the first multiplexer, a first input terminal corresponding to the 0 value of the transmitted signal receives a high potential, in the first multiplexer, a second input terminal corresponding to the 1 value of the transmitted signal is floating, in the second multiplexer, a first input terminal corresponding to the 0 value of the transmitted signal receives a low potential, and in the second multiplexer, a second input terminal corresponding to the 1 value of the transmitted signal is floating; in: The first pin is directly connected to the differential positive signal line; and The second pin is directly connected to the differential negative signal line.

10. An electronic device, characterized in that: include: The single chip computer as claimed in claim 2; a voltage divider, which divides a differential positive signal on the differential positive signal line and inputs the voltage into the third pin; as well as A fifth resistor couples the differential negative signal line to the fourth pin.

Images