Floating-point calculation device and method for processor, electronic device, and storage medium

Abstract

This application discloses a floating-point computing device and method for a processor, an electronic device, and a storage medium. The device includes: a mantissa alignment module, used to truncate the first mantissa of a first floating-point number based on the truncation bit to obtain a first addend, and to shift the second mantissa of a second floating-point number based on the shift bit to obtain a second addend, wherein the first addend and the second addend are two mantissas aligned with their exponents; the truncation bit and the shift bit are determined based on the exponent difference between the first exponent of the first floating-point number and the second exponent of the second floating-point number; an adder, used to add the first addend and the second addend to obtain a first mantissa sum; and a post-processing module, used to normalize and round the first mantissa sum to obtain a target mantissa. This reduces the selector processing step before shifting the mantissa during floating-point addition, shortens the calculation path, and improves the calculation speed.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a floating-point computing device and method for a processor, an electronic device, and a storage medium. Background Technology

[0002] Floating-point computation is an important type of data operation, characterized by high precision and a wide range of applications, finding broad applicability across various fields. For example, floating-point computation can be applied to scientific computing, graphics processing, deep learning in artificial intelligence, and multimedia data processing. Among these, floating-point addition is a common type of floating-point computation. In the process of floating-point addition, it is typically necessary to first select the mantissa of the first floating-point number from the mantissa of the third floating-point number, then align the two mantissas by shifting the selected mantissa with the smaller exponent, and finally add the aligned mantissas. In other words, the addition process requires sequential use of selectors, shifters, and adders; thus, the addition process is lengthy, impacting computation speed. Summary of the Invention

[0003] This application provides a floating-point computing device and method, electronic device, and storage medium for a processor, which can reduce the selector processing before shifting the mantissa in floating-point addition calculations, shorten the calculation path, and thus improve the calculation speed.

[0004] The technical solution of this application is implemented as follows:

[0005] This application provides a floating-point computing device for a processor, comprising:

[0006] The mantissa alignment module is used to truncate the first mantissa of a first floating-point number based on the number of truncation bits to obtain a first addend, and to shift the second mantissa of a second floating-point number based on the number of shift bits to obtain a second addend, wherein the first addend and the second addend are two mantissas aligned with the exponent; the number of truncation bits and the number of shift bits are determined based on the exponent difference between the first exponent of the first floating-point number and the second exponent of the second floating-point number;

[0007] An adder is used to add the first addend and the second addend to obtain a first sum of mantissas;

[0008] The post-processing module is used to perform normalization and rounding on the first mantissa to obtain the target mantissa.

[0009] This application provides a floating-point calculation method for a processor, including:

[0010] Based on the truncation bit, the first mantissa of the first floating-point number is truncated to obtain the first addend, and based on the shift bit, the second mantissa of the second floating-point number is shifted to obtain the second addend. The first addend and the second addend are two mantissas with exponents aligned. The truncation bit and the shift bit are determined based on the exponent difference between the first exponent of the first floating-point number and the second exponent of the second floating-point number.

[0011] Add the first addend and the second addend to obtain the first sum of the last digits;

[0012] The first mantissa is normalized and rounded to obtain the target mantissa.

[0013] This application provides an electronic device, including:

[0014] memory for storing computer programs;

[0015] A processor, used to execute the steps of the floating-point calculation method described above when running the computer program.

[0016] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described floating-point calculation method.

[0017] This application provides a floating-point computing device and method for a processor, an electronic device, and a computer-readable storage medium. Because in the process of calculating the sum of the mantissas of a first floating-point number and a second floating-point number, the shift bits and truncation bits can be determined in advance based on the exponent difference between the exponents of the first and second floating-point numbers, the mantissa of the first floating-point number can be truncated to obtain the first addend while the mantissa of the second floating-point number is shifted to obtain the second addend, thus aligning the exponents of the first and second addends. This allows for direct right shifting of the mantissa of the second floating-point number, without first selecting the mantissa with the smaller exponent from the mantissas of the first and second floating-point numbers and then right-shifting it. This reduces the selector processing before shifting, shortens the calculation path, and improves calculation speed. Attached Figure Description

[0018] Figure 1 A schematic diagram of a floating-point format data structure provided in an embodiment of this application;

[0019] Figure 2 A schematic diagram illustrating the implementation process of a floating-point multiplication and addition calculation method in a related art, provided for an embodiment of this application;

[0020] Figure 3This application provides a schematic diagram of the structure of a floating-point computing device in a related art.

[0021] Figure 4 A schematic diagram of the composition structure of a floating-point computing device provided in this application embodiment. Figure 1 ;

[0022] Figure 5 A schematic diagram of the composition structure of a floating-point computing device provided in this application embodiment. Figure 2 ;

[0023] Figure 6 A schematic diagram of the composition structure of a floating-point computing device provided in this application embodiment. Figure 3 ;

[0024] Figure 7 A schematic diagram of a data structure for a first addend and a second addend provided in an embodiment of this application. Figure 1 ;

[0025] Figure 8 A schematic diagram of the composition structure of a floating-point computing device provided in this application embodiment. Figure 4 ;

[0026] Figure 9 A schematic diagram of a data structure for a first addend and a second addend provided in an embodiment of this application. Figure 2 ;

[0027] Figure 10 A schematic diagram of a data structure for a first addend and a second addend provided in an embodiment of this application. Figure 3 ;

[0028] Figure 11 A schematic diagram of a data structure for a first addend and a second addend provided in an embodiment of this application. Figure 4 ;

[0029] Figure 12 A schematic diagram of the composition structure of a floating-point computing device provided in this application embodiment. Figure 5 ;

[0030] Figure 13 A schematic diagram illustrating the implementation process of a floating-point calculation method provided in this application embodiment;

[0031] Figure 14 This is a schematic diagram of the composition structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0034] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0036] To facilitate understanding of this solution, the application background of the embodiments of this application will be explained before describing the embodiments of this application.

[0037] Floating-point numbers have high precision and a wide calculation range. In related technologies, the commonly used floating-point number format is the Institute of Electrical and Electronics Engineers (IEEE) 754 standard, which means that a floating-point number consists of three parts: a sign bit (S), an exponent bit (Exp), and a mantissa bit (Mant). Figure 1 The structure of the single-precision floating-point number FP32 is shown, as follows: Figure 1 As shown, a single-precision floating-point number FP32 occupies 32 bits, of which the sign bit occupies 1 bit, the exponent bit occupies 8 bits, and the mantissa bit occupies 23 bits. It is understood that in the embodiments of this application, the structure of the floating-point number may include, but is not limited to, FP32, FP64, or FP16, etc., and the embodiments of this application do not limit it in this way.

[0038] Floating-point multiply-accumulate instructions are among the most common floating-point arithmetic instructions, with floating-point addition being a crucial computational process within this instruction set. Therefore, improving the speed of floating-point addition is essential for enhancing the overall performance of floating-point arithmetic operations.

[0039] The following section uses the calculation process of floating-point multiply-add instructions as an example to introduce floating-point addition calculation in related technologies.

[0040] Figure 2 This illustrates a floating-point multiplication and addition method in related technologies, including:

[0041] S21. Multiply the mantissa of floating-point number A1 and the mantissa of floating-point number B1 to obtain the multiplication number.

[0042] In this context, the mantissa of a floating-point number is a fractional part consisting of the hidden integer and the mantissa digits. The hidden integer is a hidden integer digit, usually consisting of 1s.

[0043] S22. Obtain the exponent difference by subtracting the exponent of the floating-point number C1 from the exponent of the multiplier.

[0044] S23. Based on the positive and negative properties of the exponent difference, select the one with the larger exponent from the mantissa of the multiplicand and the floating-point number C1 as addend 1, and select the one with the smaller exponent and shift it to the right to obtain addend 2.

[0045] S24. Add addend 1 and addend 2 to get the sum.

[0046] S25. Normalize the sum of addition to obtain the normalized sum;

[0047] S26. Round the specifications to get the sum of the last two digits.

[0048] The mantissa is the sum of the product of floating-point number A1 and floating-point number B1 and the sum of floating-point number C1.

[0049] The addition process includes S22-S24, which is the process of adding the multiplicand and the floating-point decimal of the floating-point number C1 to obtain the sum. The hardware device structure used in this process is as follows: Figure 3 As shown, the array includes: selector 31, selector 32, right shifter 33, and adder 34. Selectors 31 and 32 receive selection signals, which are determined based on the exponent difference. When the exponent difference is positive, the selection signal is low; in this case, selector 31 selects the multiplicand output, and selector 32 selects the mantissa of the floating-point number C1 for output to right shifter 33. When the exponent difference is negative, the selection signal is high; in this case, selector 31 selects the mantissa of the floating-point number C1 for output, and selector 32 selects the multiplicand output for output to right shifter 33. Adder 34 adds the data output from selector 31 and the data output from right shifter 33 to obtain the sum. It can be seen that to implement the addition calculation process in S22-S24, two selectors, one right shifter, and one adder are needed sequentially for processing, resulting in a long path and affecting the calculation speed.

[0050] This application provides a floating-point computing apparatus and method for a processor, an electronic device, and a computer-readable storage medium, which can reduce the selector processing before shifting the mantissa in floating-point addition calculations, shorten the calculation path, and thus improve the calculation speed. This apparatus can be applied to electronic devices that require floating-point addition calculations. In some embodiments, the electronic device includes a device that requires addition operations to be performed via a graphics processing unit (GPU). For example, the electronic device may be a server, laptop, tablet, desktop computer, smart TV, set-top box, mobile device (e.g., mobile phone, portable video player, personal digital assistant, dedicated messaging device, portable gaming device), etc.

[0051] Figure 4 A schematic diagram of the composition structure of an optional floating-point computing device provided in this application embodiment. Figure 1 ,like Figure 4 As shown, the floating-point computing device may include:

[0052] The mantissa alignment module 41 is used to truncate the first mantissa of the first floating-point number based on the number of truncation bits to obtain the first addend, and to shift the second mantissa of the second floating-point number based on the number of shift bits to obtain the second addend. The first addend and the second addend are two mantissas aligned with the exponent. The number of truncation bits and the number of shift bits are determined based on the exponent difference between the first exponent of the first floating-point number and the second exponent of the second floating-point number.

[0053] Adder 42 is used to add the first addend and the second addend to obtain the first sum of the last digits;

[0054] The post-processing module 43 is used to perform normalization and rounding on the first mantissa to obtain the target mantissa.

[0055] The mantissa of a floating-point number consists of a mantissa bit and a hidden integer bit, which can be either 0 or 1. The first floating-point number has a first mantissa and a first exponent, and the second floating-point number has a second mantissa and a second exponent. When adding the first and second floating-point numbers, their exponents must be aligned before addition.

[0056] It is understandable that truncating the first mantissa of the first floating-point number is equivalent to shifting it. Following this, shifting the second mantissa of the second floating-point number aligns the exponents of the first and second floating-point numbers, resulting in exponent-aligned mantissas, namely the first and second addends. Since the exponent difference between the first and second exponents characterizes the difference in exponents between the first and second mantissas, this exponent difference can be used to determine the truncation bits for the first mantissa and the shift bits for the second mantissa, thus obtaining the exponent-aligned first and second addends. The exponent difference between the first and second exponents can be positive, 0, or negative.

[0057] In some implementations, the first addend can be obtained by truncating a data segment starting from the most significant bit of the first mantissa, based on the number of truncation bits. The data width of the first addend is the number of truncation bits. That is, a data segment from the first mantissa starting from the most significant bit with a width equal to the number of truncation bits can be used as the first addend. For example, if the number of truncation bits is 0, the width of the truncated first addend is 0, i.e., 0 is determined as the first addend. Alternatively, if the number of truncation bits is greater than 0 and not greater than the data width of the first mantissa, a data segment from the first mantissa starting from the most significant bit with a width equal to the number of truncation bits can be used as the first addend. This achieves the same effect as right-shifting the first mantissa, and the sum of the right-shifted bits and the truncation bits equals the data width of the first mantissa. For example, if the number of bits to be truncated is greater than the data width of the first mantissa, zeros can be padded to the end of the first mantissa to make the data width of the first mantissa greater than or equal to the number of bits to be truncated. Based on the number of bits to be truncated, the data segment is truncated starting from the highest bit of the first mantissa after padding with zeros to obtain the first addend. In this way, the effect of shifting the first mantissa to the left can be achieved, and the number of bits shifted to the left is the same as the number of zeros padded to the end.

[0058] In some implementations, the shifting of the second mantissa can include a left shift or a right shift. For example, when the exponent difference is positive, the exponent of the first floating-point number is greater than the exponent of the second floating-point number. In this case, the second mantissa of the second floating-point number is shifted to the right, while the first mantissa of the first floating-point number remains unchanged, thus achieving exponent alignment. Conversely, when the exponent difference is negative, the exponent of the first floating-point number is less than the exponent of the second floating-point number. If the second mantissa of the second floating-point number contains multiple leading zeros, the second mantissa of the second floating-point number can be shifted to the left, with the shift number not exceeding the number of leading zeros. The first mantissa of the first floating-point number can remain unchanged or be shifted to the right through truncation to align with the exponent of the left-shifted second mantissa.

[0059] It should be noted that those skilled in the art can use any suitable truncation method to truncate the first mantissa and any suitable shifting method to shift the second mantissa, so that the exponents of the first addend and the second addend are aligned. This application does not limit this.

[0060] In some implementations, a data segment starting from the most significant bit and with a width equal to the truncated bit width can be extracted from the first mantissa as the first addend; the second mantissa is then right-shifted by the same number of bits to obtain the second addend. In this way, exponent alignment can be achieved by right-shifting the mantissa of the second floating-point number, which can be either the addend or the sum in an addition operation. For example, if the exponent difference is positive, the exponent of the first floating-point number is greater than the exponent of the second floating-point number. In this case, right-shifting the second mantissa of the second floating-point number while keeping the first mantissa of the first floating-point number unchanged achieves exponent alignment. Therefore, the truncated bit width used for the first mantissa can be the data width of the first mantissa, and the right-shifted bit width used for the second mantissa can be the exponent difference. For example, when the exponent difference is negative, the exponent of the first floating-point number is less than the exponent of the second floating-point number. In this case, if the second mantissa of the second floating-point number is shifted to the right while the first mantissa of the first floating-point number remains unchanged, the difference in exponents will be even greater. Therefore, in this situation, the first mantissa of the first floating-point number also needs to be shifted to the right, and the number of bits shifted to the right should be greater than the number of bits shifted to the right of the second mantissa of the second floating-point number. Only in this way can the exponents of the first mantissa and the second mantissa be aligned. That is, the number of bits used to truncate the first mantissa is less than or equal to the difference between the data width of the first mantissa and the absolute value of the exponent difference. The sum of the number of bits used to shift the second mantissa to the right, the number of bits truncated, and the absolute value of the exponent difference is the data width of the first mantissa. For example, if the exponent difference is 0, the first and second floating-point numbers are exponentially aligned. In this case, neither the first mantissa of the first floating-point number nor the second mantissa of the second floating-point number needs to be shifted. That is, the number of bits used to truncate the first mantissa can be the data width of the first mantissa, and the number of bits used to right-shift the second mantissa can be 0. Alternatively, the first mantissa of the first floating-point number and the second mantissa of the second floating-point number can be right-shifted by the same number of bits. That is, the number of bits used to truncate the first mantissa can be less than the data width of the first mantissa, and the sum of the number of bits used to right-shift the second mantissa and the number of bits truncated is the data width of the first mantissa.

[0061] For example, the highest bit of the adder 42's bit width is reserved for the sign bit. Taking the FP32 floating-point format as an example, the first mantissa of the first floating-point number and the second mantissa of the second floating-point number are both 24 bits, represented as "1.23". When the exponent difference is 2, if the second mantissa "1.23" of the second floating-point number is shifted right by 2 bits, then the first mantissa "1.23" of the first floating-point number does not need to be shifted right, that is, the truncated bit is 24 bits; if the second mantissa "1.23" of the second floating-point number is shifted right by 3 bits, then the first mantissa "1.23" of the first floating-point number needs to be shifted right by 1 bit, that is, the truncated bit is 23 bits. When the exponent difference is -5, if the second mantissa "1.23" of the second floating-point number is shifted 3 bits to the right, then the first mantissa "1.23" of the first floating-point number needs to be shifted 8 bits to the right, that is, the truncation bit is 16; if the second mantissa "1.23" of the second floating-point number is shifted 4 bits to the right, then the first mantissa "1.23" of the first floating-point number needs to be shifted 9 bits to the right, that is, the truncation bit is 15.

[0062] In some implementations, the first mantissa is right-shifted by truncating the most significant bits. The truncated bits can be set in conjunction with the exponent difference and the bit width of the data bits of adder 42. For example, if the exponent difference is -5, and the second mantissa of the second floating-point number is shifted right by 3 bits, in order to achieve a right shift of the first mantissa by 8 bits, the truncated bits are 16 bits when the bit width of the data bits of adder 42 is 24; 42 bits when the bit width of the data bits of adder 42 is 50; and 45 bits when the bit width of the data bits of adder 42 is 53.

[0063] In some implementations, the sign of the exponent difference differs, and the number of bits shifted to the right for the second mantissa of the second floating-point number can be different or the same. It should be noted that even if the number of bits shifted to the right for the second mantissa of the second floating-point number is the same, the number of bits truncated will also be different when the sign of the exponent difference is determined. When the sign of the exponent difference is determined, the number of shift bits and the number of bits truncated correspond, thus ensuring that the exponents of the first and second addends are aligned.

[0064] The post-processing module 43 can use any suitable normalization and rounding method to normalize and round the first mantissa. This embodiment of the application does not limit this.

[0065] Understandably, normalization is used to ensure that the representation of floating-point numbers conforms to a preset floating-point format. For example, normalization ensures that the representation conforms to the IEEE 754 standard, guaranteeing that the most significant bit is inverted compared to the sign bit. Without normalization, precision loss and calculation errors may occur. Normalization can include left normalization and / or right normalization. Left normalization means that if the most significant bit of the mantissa is not a valid value (e.g., there are multiple leading zeros), the mantissa is shifted left until the most significant bit is a valid value. Right normalization means that if the mantissa overflows, the mantissa is shifted right by one bit.

[0066] Rounding may include, but is not limited to, at least one of the following: nearest-neighbor rounding, forced 1, truncation, round to nearest (RNE), round toward zero (RTZ), round toward +infinity (RPI), and round toward +infinity (RNI).

[0067] In some implementations, the post-processing module 43 can first normalize the first mantissa sum, removing leading zeros to obtain the second mantissa sum; then, it can round the second mantissa sum according to a rounding method to obtain the target mantissa. The number of bits in the target mantissa is the same as the effective bit width of the floating-point mantissa. The effective bit width of the floating-point mantissa can be predetermined based on the actual application scenario.

[0068] In some embodiments, the rounding method used in the post-processing module 43 can be a pre-set rounding method. In some embodiments, the post-processing module 43 can be configured with multiple rounding methods, and upon receiving a rounding selection instruction, it performs rounding processing according to the rounding method indicated by the rounding selection instruction.

[0069] In some implementations, the post-processing module 43 can extract the most significant bits of the mantissa of the floating-point number from the second mantissa sum as the mantissa sum to be rounded (i.e., the valid bits of the second mantissa sum), and determine the rounding-related bits from the second mantissa sum, and perform rounding processing on the mantissa sum to be rounded according to the rounding-related bits to obtain the target mantissa.

[0070] In some implementations, the sum of mantissas to be rounded can be rounded based on the rounding-related bits in the second mantissa sum, the low-order discard bits (stick1) in the first mantissa excluding the truncated data fields, and the discard bits (stick2) after the rounding-related bits in the second mantissa sum, to obtain the target mantissa, such that the number of bits in the target mantissa is the same as the effective bit width of the floating-point mantissa. The rounding-related bits may include the least significant bit of the sum of mantissas to be rounded, or the rounding-related bits may include the least significant bit of the sum of mantissas to be rounded and at least one bit after that least significant bit. Here, the number of bits for the rounding-related bits can be set according to actual needs, and this application embodiment does not impose any limitations.

[0071] In some implementations, the rounding-related bits may include three bits: the least significant bit (lsd), the rounding bit (rnd), and the guard bit (gard). The least significant bit (lsd) is the lowest bit of the sum of the mantissas to be rounded, the bit following the least significant bit (lsd) is the rounding bit (rnd), and the bit following the rounding bit (gard) is the guard bit (gard). The post-processing module 43 can perform rounding processing on the sum of the mantissas to be rounded based on the least significant bit (lsd), the rounding bit (rnd), the guard bit (gard), the least significant bit (stick1), and the discard bit (stick2) to obtain the target mantissa.

[0072] In some implementations, the post-processing module 43 can determine the discard value based on the discard bits stick1 and stick2, and perform rounding processing on the mantissa to be rounded together with the last bit lsd, the rounding bit rnd, the guard bit gard, and the discard value to obtain the target mantissa.

[0073] In some implementations, if the rounding-related bits and the discard value satisfy the carry condition, the sum of the mantissa to be rounded is incremented by 1 to obtain the target mantissa; or if the rounding-related bits and the discard value do not satisfy the carry condition, the sum of the mantissa to be rounded is determined as the target mantissa. For example, the carry condition may include, but is not limited to: both the rounding-related bits and the discard value are 1, or one of the rounding-related bits and the discard value is 1.

[0074] In this embodiment, during the calculation of the sum of the mantissas of the first and second floating-point numbers, the shift bits and truncation bits can be determined in advance based on the exponent difference between the exponents of the first and second floating-point numbers. This allows for simultaneous truncation of the mantissa of the first floating-point number to obtain the first addend and shifting of the mantissa of the second floating-point number to obtain the second addend, ensuring exponent alignment between the first and second addends. Furthermore, the mantissa of the second floating-point number can be directly shifted to the right without first selecting the mantissa with the smaller exponent from the mantissas of the first and second floating-point numbers and then shifting it to the right. This reduces the selector processing before the shift, shortens the calculation path, and improves calculation speed.

[0075] In some embodiments, as Figure 5 As shown, the mantissa alignment module 41 may include:

[0076] The determination module 411 is used to determine the reference index, as well as the truncation bits and shift bits corresponding to the reference index, based on the index difference.

[0077] The truncation module 412 is used to truncate a data segment from the first mantissa, starting from the most significant bit and with a bit width equal to the number of bits to be truncated, as the first addend;

[0078] Shifter 413 is used to right-shift the second mantissa by the shift number to obtain the second addend, and the first addend and the second addend are aligned based on the reference exponent.

[0079] Here, the exponents corresponding to the first addend and the second addend are both the reference exponent, meaning that the first addend and the second addend are aligned based on the reference exponent.

[0080] It should be noted that those skilled in the art can determine the reference exponent, truncation bits, and shift bits based on the exponent difference in any suitable manner according to the actual application scenario, as long as the first addend obtained by truncating the first mantissa using the truncation bits and the second addend obtained by right-shifting the second mantissa using the shift bits are aligned based on the reference exponent. This application does not limit this.

[0081] In some implementations, a reference exponent can be determined based on the exponent difference, the truncation bits can be determined based on the reference exponent and the first exponent of the first floating-point number, and the shift bits can be determined based on the reference exponent and the second exponent of the second floating-point number. Here, since the first addend and the second addend are aligned based on the reference exponent, that is, the exponents corresponding to the first addend and the second addend are both the reference exponent, the truncation bits can be determined based on the reference exponent and the first exponent of the first floating-point number, and the shift bits can be determined based on the reference exponent and the second exponent of the second floating-point number. For example, when the exponent difference is greater than or equal to 0, the first exponent can be determined as the reference exponent. In this case, the first mantissa does not need to be shifted, and the exponent corresponding to the second mantissa after right shift (i.e., the second addend) is the first exponent. Thus, the truncation bits can be equal to the data width of the first mantissa, and the shift bits used to right shift the second mantissa can be the exponent difference. For example, when the exponent difference is less than 0, the second exponent can be determined as the reference exponent. In this case, the second mantissa does not need to be shifted. The exponent corresponding to the first mantissa after truncation (i.e. the first addend) is the second exponent. Thus, the number of bits to be truncated can be equal to the difference between the data bit width of the first mantissa and the absolute value of the exponent difference. The number of bits to be shifted to the right for the second mantissa can be 0.

[0082] In some implementations, shifter 413 may include a right shifter.

[0083] In the above embodiments, the determining module determines a reference exponent, as well as the truncation and shift bits corresponding to the reference exponent, based on the exponent difference. The truncation module truncates a data segment from the first mantissa, starting from the most significant bit and with a bit width equal to the truncation bit width, as the first addend. The shifter shifts the second mantissa right by the shift bit width to obtain the second addend. The first and second addends are aligned based on the reference exponent, which is determined based on the exponent difference. In this way, the first and second mantissas can be exponentially aligned efficiently and accurately to obtain exponentially aligned first and second addends.

[0084] In some embodiments, as Figure 6 As shown, the floating-point computing device also includes:

[0085] Multiplication module 44 is used to multiply the third mantissa of the third floating-point number and the fourth mantissa of the fourth floating-point number to obtain the first mantissa;

[0086] The exponent difference determination module 45 is used to sum the third exponent of the third floating-point number and the fourth exponent of the fourth floating-point number to obtain the first exponent, and then subtract the second exponent from the first exponent to obtain the exponent difference.

[0087] Here, the first floating-point number is the product of the third and fourth floating-point numbers. The third floating-point number has a third exponent and a third mantissa, and the fourth floating-point number has a fourth exponent and a fourth mantissa.

[0088] In calculating the product of the third and fourth floating-point numbers, the exponent (i.e., the first exponent) and the mantissa (i.e., the first mantissa) of the product can be calculated separately. The third and fourth mantissas can be input into the multiplication module 44 to obtain the first mantissa; the first exponent can be obtained by adding the third and fourth exponents. After obtaining the first exponent, the exponent difference determination module 45 can subtract the second exponent from the first exponent to obtain the exponent difference.

[0089] In some implementations, the multiplication module 44 includes a multiplier. For example, the highest bit of both the multiplier and adder 42 is reserved for the sign bit. Taking the FP32 floating-point format as an example, the mantissa of both the first and second floating-point numbers is 24 bits, represented as "1.23". The multiplier has a 50-bit width, where the first high bit is the sign bit "a" and the second high bit is a reserved overflow bit "b", and the multiplied number is represented as "b.48".

[0090] In some implementations, the exponent difference determination module 45 may include: an addition module for summing the third exponent of the third floating-point number and the fourth exponent of the fourth floating-point number to obtain a first exponent; and a subtraction module for subtracting the second exponent from the first exponent to obtain the exponent difference. The addition module may include any suitable adder, and the subtraction module may include any suitable subtractor; this application embodiment does not limit the specific implementation.

[0091] In some implementations, the highest bit of the exponent difference output by the exponent difference determination module 45 is the sign bit, which can characterize the positive or negative nature of the exponent difference.

[0092] In some implementations, the exponent difference determination module 45 can send the exponent difference to the mantissa alignment module 41, which can then determine the truncation and shift bits based on the exponent difference. Different exponent differences correspond to different truncation and shift bits, and the shift bits and truncation bits must correspond to ensure exponent alignment of the first and second addends.

[0093] In some implementations, the exponent difference determination module 45 can send the exponent difference to the determination module 411 in the mantissa alignment module 41. The determination module 411 can determine a reference exponent, as well as the truncation bits and shift bits corresponding to the reference exponent, based on the exponent difference.

[0094] In the above embodiment, the multiplication module multiplies the third mantissa of the third floating-point number and the fourth mantissa of the fourth floating-point number to obtain the first mantissa; the exponent difference determination module sums the third exponent of the third floating-point number and the fourth exponent of the fourth floating-point number to obtain the first exponent, and subtracts the second exponent from the first exponent to obtain the exponent difference. This shortens the calculation path of floating-point multiplication and addition operations, improves calculation speed, and allows for the determination of the exponent difference through a simple hardware structure, reducing costs.

[0095] In some embodiments of this application, the bit width of the data bits of the adder 42 is twice a preset threshold; the preset threshold is the sum of the preset mantissa effective bit width and the preset rounding-related bit width minus 1.

[0096] The adder 42 has a bit width including a sign bit and data bits; the sign bit has a bit width of 1 bit, and the data bit width is twice the preset threshold. The preset threshold can be set in advance based on the mantissa significant bit width and the rounding-related bit width, or it can be calculated based on the preset mantissa significant bit width and the preset rounding-related bit width.

[0097] The mantissa valid bit width refers to the data bit width of the valid bits of the mantissa, and the rounding related bit width refers to the data bit width of the rounding related bits. Both the mantissa valid bit width and the rounding related bit width can be preset by those skilled in the art according to the actual application scenario, and the embodiments of this application do not limit them. For example, the mantissa valid bit width can be 24 bits or 25 bits, etc., and the rounding related bits can be 1 bit, 2 bits or 3 bits, etc.

[0098] It is understandable that the preset threshold can represent the number of consecutive digits from the first of the effective digits of the mantissa to the last of the rounding-related digits when rounding the mantissa with the effective digit width of the mantissa as preset. Since the last of the effective digits of the mantissa is the starting digit of the rounding-related digits, the preset threshold is the sum of the preset effective digit width of the mantissa and the preset rounding-related digit width minus 1.

[0099] Furthermore, since the first addend may be much smaller than the second addend or vice versa during the shifting process, by setting the bit width of the adder's data bits to twice the preset threshold, more mantissa bits can be retained to improve the accuracy of multiplication and addition operations, while minimizing the bit width of the adder 42 and reducing hardware costs.

[0100] For example, taking FP32 as an example, the preset mantissa width of floating-point numbers is 24, the width of rounding related bits is 3, then the preset threshold is 26, the width of the data bits of the adder is 52, and the width of the adder is 52 bits of data bits and 1 bit of sign bit, that is, 53.

[0101] In some embodiments, the multiplication module 44 includes a multiplier whose bit width includes the width of the sign bit and the width of the multiplication data. The width of the multiplication data includes twice the preset mantissa valid bit width of the floating-point number plus 1, and the added 1 bit is an overflow bit. In this way, while ensuring the accuracy of the multiplication calculation result, the bit width of the multiplier can be minimized to the greatest extent, thereby reducing hardware costs.

[0102] In some embodiments, the determining module 411 is further configured to: determine the first exponent as the reference exponent when the exponent difference is greater than or equal to 0, determine the bit width of the data bits of the adder 42 as the truncation bit width, and determine the exponent difference as the shift bit width.

[0103] In this embodiment, if the exponent difference is non-negative, shifting the second mantissa of the second floating-point number right by one unit of the exponent difference will align its exponent with the first mantissa of the first floating-point number. The number of shifts is the exponent difference, and the number of truncations is the bit width of the adder 42, which is the bit width of the adder 42 minus 1. Here, the subtracted 1 is the highest bit (sign bit). This is equivalent to shifting the second mantissa right by 0 bits, meaning the first addend is the second mantissa itself.

[0104] It should be noted that if the number of bits in the second mantissa is less than the bit width of the data bits of adder 42, adder 42 can pad the end of the second mantissa until the number of bits in the padded second mantissa is the same as the bit width of the data bits of adder 42. The value of the padded part, either 0 or 1, can be determined based on the sign of the second mantissa. For example, if the second mantissa is positive, 0 can be padded to the end; if the second mantissa is negative, 1 can be padded to the end.

[0105] For example, Figure 7 A schematic diagram of a data structure for a first addend and a second addend is shown. Figure 1 ,like Figure 7 As shown, the highest bit of the adder is the sign bit S. The exponent difference is 3. The first mantissa is "b.48" and the second mantissa is "1.23". Therefore, the first addend is "b.48" after the sign bit S, and the second addend is "1.23" shifted right by 3 bits.

[0106] It is understandable that when the exponent difference is greater than or equal to 0, the second mantissa can be directly right-shifted by the units digit of the exponent difference to align with the first mantissa. This reduces the number of operations in the exponent alignment process and improves the efficiency of exponent alignment.

[0107] In some embodiments of this application, such as Figure 8 As shown, the post-processing module 43 includes a normalization module 431 and a rounding module 432;

[0108] The shifter 413 is also used to: when the exponent difference is greater than or equal to 0, to transmit the data segment shifted out by the second mantissa as the first discard bit to the rounding module 432;

[0109] Normalization module 431 is used to remove leading zeros from the first mantissa sum to obtain the second mantissa sum;

[0110] The rounding module 432 is used to round the second mantissa based on the first discard bit to obtain the target mantissa.

[0111] Understandably, by shifting the second mantissa to the right by the shift number, the least significant data bit segment with a width equal to the shift number can be shifted out of the shifter. If the exponent difference is greater than or equal to 0, the shifted least significant data bit segment can be transmitted to the rounding module 432 as the first discard bit.

[0112] For example, if the second mantissa is recorded as "1.23" and the exponent difference is 3, then the second addend is "1.23" after shifting right by 3 bits. The lowest 3 bits of the second mantissa are the lowest bit data segment shifted out from the shifter, which is also the first discard bit.

[0113] The normalization module 431 can remove leading zeros from the first mantissa sum to obtain the second mantissa sum, and output the second mantissa sum to the rounding module 432.

[0114] The rounding module 432 can round the second mantissa based on the first discard bit and use any suitable rounding method to obtain the target mantissa. This application embodiment does not limit this.

[0115] In some implementations, if the first discard bit is greater than 0, the valid bits of the second mantissa sum can be carried over (i.e., added by 1) to obtain the target mantissa bit; if the first discard bit is 0, the valid bits of the second mantissa sum can be determined as the target mantissa bit.

[0116] In some implementations, the second mantissa sum can be rounded based on the first discard bit and the rounding-related bits in the second mantissa sum to obtain the target mantissa. For example, if both the first discard bit and the rounding-related bits are greater than 0, the significant bits of the second mantissa sum are carried over (i.e., incremented by 1) to obtain the target mantissa; if either the first discard bit or the rounding-related bits are 0, the significant bits of the second mantissa sum are determined as the target mantissa. Alternatively, if at least one of the first discard bit and the rounding-related bits is greater than 0, the significant bits of the second mantissa sum are carried over (i.e., incremented by 1) to obtain the target mantissa; if both the first discard bit and the rounding-related bits are 0, the significant bits of the second mantissa sum are determined as the target mantissa.

[0117] In the above embodiment, when the exponent difference is greater than or equal to 0, the shifter transmits the data segment shifted out by the second mantissa by the number of shifts to the right as the first discard bit to the rounding module; the normalization module removes leading zeros from the first mantissa sum to obtain the second mantissa sum; the rounding module rounds the second mantissa sum based on the first discard bit to obtain the target mantissa. In this way, normalization and rounding can be performed efficiently and accurately when the exponent difference is greater than or equal to 0, improving calculation accuracy and simplifying the rounding logic.

[0118] In some embodiments, the determining module 411 is also used for at least one of the following:

[0119] If the exponential difference is less than 0 and the absolute value of the exponential difference is greater than or equal to a preset threshold, the second exponent is determined as the reference exponent, and the truncation bits and shift bits are both determined to be 0.

[0120] When the exponential difference is less than 0 and the absolute value of the exponential difference is less than the preset threshold, the sum of the first exponent and the preset threshold is determined as the reference exponent, the preset threshold is determined as the truncation number, and the difference between the preset threshold and the absolute value of the exponential difference is determined as the shift number.

[0121] Here, when the exponent difference is less than 0, the determining module can determine the reference exponent and the truncation and shift bits corresponding to the reference exponent based on the relationship between the absolute value of the exponent difference and the preset threshold.

[0122] Understandably, when the exponent difference is less than 0, if the absolute value of the exponent difference is greater than or equal to a preset threshold, it indicates that the difference between the second and first exponents is greater than or equal to the preset threshold. In this case, the second exponent can be used as the reference exponent. Therefore, the number of bits used for right-shifting the second mantissa is 0, meaning the second mantissa is not shifted to the right. Furthermore, the first mantissa will not affect the preset threshold of data bits starting from the highest bit in the unshifted second mantissa. Therefore, the first mantissa can be directly used as the low-order discard bits. In other words, the number of bits truncated can be 0. In this way, normalization and rounding can be performed efficiently and accurately when the exponent difference is less than 0 and the absolute value of the exponent difference is greater than or equal to the preset threshold, improving calculation accuracy and simplifying the rounding logic.

[0123] For example, Figure 9 A schematic diagram of a data structure for a first addend and a second addend is shown. Figure 2 ,like Figure 9 As shown, the adder has a bit width of 53, with the highest bit being the sign bit S; the preset threshold is 26. If the exponent difference is -27, then the truncation and shift bits are both 0. Thus, the first mantissa is represented as "b.48", and the whole is used as the low-order discard bit stick1, making the first addend 0; the second mantissa is represented as "1.23", and the second addend is the second mantissa itself.

[0124] When the exponent difference is less than 0, if the absolute value of the exponent difference is less than a preset threshold, it indicates that the difference between the second exponent and the first exponent is less than the preset threshold. In this case, the sum of the first exponent and the preset threshold can be used as the reference exponent. Thus, the truncation bits can be the preset threshold, meaning that a data segment with a width equal to the preset threshold can be truncated from the highest bit of the first mantissa as the low bit of the first addend. This is equivalent to shifting the first mantissa right by the bit width of the adder 42 (twice the preset threshold) minus the preset threshold, which is the preset threshold. At this point, the right shift of the second mantissa is the preset threshold minus the absolute value of the exponent difference. This is equivalent to shifting the second mantissa left relative to the truncated first mantissa by the units digit of the absolute value of the exponent difference. In this way, the first and second addends can be exponentially aligned. This allows for efficient and accurate normalization and rounding when the exponent difference is less than 0 and its absolute value is less than the preset threshold, improving calculation accuracy and simplifying rounding logic.

[0125] For example, Figure 10A schematic diagram of a data structure for a first addend and a second addend is shown. Figure 3 ,like Figure 10 As shown, the adder has a bit width of 53, with the highest bit being the sign bit S; the preset threshold is 26. If the exponent difference is -5, the first mantissa is represented as "b.48" and the second mantissa as "1.23". The truncation bit is 26, meaning the lower bits of the first addend are "b.25", and the higher bits, except for the sign bit, are padded with 0s. In this case, the right shift of the second mantissa is 21 bits, meaning the second addend is obtained by right-shifting the second mantissa "1.23" by 21 bits. This is equivalent to left-shifting the second mantissa by 5 bits relative to the lower 26 bits of the first addend, "b.25".

[0126] It is understandable that by truncating the first last digit and shifting it to the right to align its exponent with that of the shifted second last digit, the number of selectors can be reduced, the calculation path can be shortened, and the calculation speed can be improved.

[0127] In some embodiments, see continue to see Figure 8 The post-processing module 43 includes a normalization module 431 and a rounding module 432;

[0128] The truncation module 412 is also used to: transmit the first mantissa as the first discard bit to the rounding module 432 when the exponent difference is less than 0 and the absolute value of the exponent difference is greater than or equal to a preset threshold; and / or, when the exponent difference is less than 0 and the absolute value of the exponent difference is less than a preset threshold, truncate the remaining data bit segment from the first mantissa as the first discard bit and transmit it to the rounding module 432.

[0129] Normalization module 431 is used to remove leading zeros from the first mantissa sum to obtain the second mantissa sum;

[0130] The rounding module 432 is used to round the second mantissa based on the first discard bit to obtain the target mantissa.

[0131] Understandably, when the exponent difference is less than 0 and the absolute value of the exponent difference is greater than or equal to the preset threshold, the second exponent is used as the reference exponent, and the number of bits truncated and the number of bits shifted are both 0. At this time, the first addend will not affect the preset threshold number of data bits starting from the highest bit in the unshifted second mantissa. Therefore, the first mantissa can be directly transmitted to the rounding module 432 as the first discard bit.

[0132] When the exponent difference is less than 0 and the absolute value of the exponent difference is less than a preset threshold, the sum of the first exponent and the preset threshold is used as the reference exponent, the preset threshold is used as the truncation bit, and the difference between the preset threshold and the absolute value of the exponent difference is used as the shift bit. In this case, a data segment starting from the highest bit and with a bit width equal to the preset threshold can be truncated from the first mantissa as the low bit of the first addend, which is equivalent to shifting the first mantissa to the right by a preset threshold unit number. The second addend is obtained by shifting the second mantissa to the left relative to the truncated first mantissa by a left shift of the absolute value of the exponent difference unit number. Therefore, the remaining data segment truncated from the first mantissa can be transmitted to the rounding module 432 as the first discard bit, which is equivalent to using the preset threshold unit number shifted to the right from the first mantissa as the first discard bit.

[0133] In the above embodiments, when the exponent difference is less than 0 and the absolute value of the exponent difference is greater than or equal to a preset threshold, the truncation module transmits the first mantissa as the first discard bit to the rounding module; and / or, when the exponent difference is less than 0 and the absolute value of the exponent difference is less than a preset threshold, the remaining data segment truncated from the first mantissa is transmitted as the first discard bit to the rounding module; the normalization module removes leading zeros from the sum of the first mantissa to obtain the sum of the second mantissa; the rounding module rounds the sum of the second mantissa based on the first discard bit to obtain the target mantissa. In this way, normalization and rounding can be performed efficiently and accurately when the exponent difference is less than 0, improving calculation accuracy and simplifying the rounding logic.

[0134] In some embodiments of this application, the rounding module 432 is further configured to extract a data segment from the second mantissa sum starting from the most significant bit and having a bit width equal to the effective bit width of the mantissa, as the mantissa sum to be rounded; determine at least two consecutive rounding-related bits from the second mantissa sum, starting from the least significant bit of the mantissa sum to be rounded; and perform rounding processing on the mantissa sum to be rounded according to the target input condition based on the first discard bit, the rounding-related bits, and the second discard bit after the rounding-related bits, to obtain the target mantissa.

[0135] The rounding-related bits can be at least two consecutive data bits in the second mantissa sum, starting with the least significant bit of the mantissa sum to be rounded. The number of rounding-related bits can include a preset rounding-related bit width, which can be pre-set according to the actual application scenario. For example, the rounding-related bit width can be 2 bits or 3 bits.

[0136] The second discard bit can be at least one data bit in the second mantissa sum, starting from the bit following the last bit of the relevant rounding bit.

[0137] In some implementations, the first discard bit may be, for example, but not limited to, the aforementioned low-order discard bit stick1, and the second discard bit may be, for example, but not limited to, the aforementioned discard bit stick2.

[0138] The target input value condition can be determined by those skilled in the art based on the rounding method used in the actual application scenario, and this application embodiment does not limit it in this way. For example, the target input value condition may include at least one of the first discard bit, the rounding-related bit, and the rounding-related bit being greater than 0. As another example, the target input value condition may include the first discard bit, the rounding-related bit, and the rounding-related bit all being greater than 0.

[0139] In some implementations, it can be determined whether the first discard bit, the rounding-related bit, and the second discard bit satisfy the target input condition, and based on the determination result, the sum of the mantissas to be rounded is rounded to obtain the target mantissa. For example, if the first discard bit, the rounding-related bit, and the second discard bit satisfy the target input condition, the sum of the mantissas to be rounded plus 1 can be used as the target mantissa. Alternatively, if the first discard bit, the rounding-related bit, and the second discard bit do not satisfy the target input condition, the sum of the mantissas to be rounded can be used as the target mantissa.

[0140] In the above embodiments, by comprehensively considering the first discard bit, the rounding-related bit, and the second discard bit after the rounding-related bit, the rounding mantissa can be treated and rounded more accurately, resulting in a more precise target mantissa and improving calculation accuracy.

[0141] In some embodiments, the rounding module 432 is further configured to:

[0142] Determine the target discard value based on the first and second discard bits;

[0143] If the target discard value and the rounding-related bits meet the target input value condition, the input value is determined to be 1; or, if the target discard value and the rounding-related bits do not meet the target input value condition, the input value is determined to be 0.

[0144] Add the sum of the decimal part to be rounded to the input value to obtain the target decimal part.

[0145] In some implementations, the rounding module 432 may include a rounding logic module, an adder, and a selector. The rounding logic module is used to determine the target discard value based on a first discard bit and a second discard bit.

[0146] In some implementations, the rounding logic module can determine the target discard value as 0 if both the first discard bit and the second discard bit are 0; otherwise, it can determine the target discard value as 1.

[0147] In some implementations, the rounding logic module may determine a first discard value of 1 when the first discard bit contains at least one 1, otherwise determine a first discard value of 0; and determine a second discard value of 1 when the second discard bit contains at least one 1, otherwise determine a second discard value of 0; and determine a target discard value of 0 when both the first and second discard values ​​are 0, otherwise determine a target discard value of 1.

[0148] In some implementations, the rounding logic module can generate a first input selection signal when the target discard value and the rounding-related bits meet the target input value condition. The selector responds to the first input selection signal by selecting 1 as the input value and outputting it to the adder. Otherwise, the rounding logic module can generate a second input selection signal, and the selector responds to the second input selection signal by selecting 0 as the input value and outputting it to the adder. The adder then adds the input value from the selector to the mantissa to be rounded, obtaining the target mantissa.

[0149] In some implementations, the rounding module 432 can process the rounding process as adding the sum of the mantissas to be rounded to 0, or adding the sum of the mantissas to be rounded to 1. This allows the rounding module 432 to easily implement the rounding process through hardware logic.

[0150] In some embodiments of this application, the rounding-related bits include the last minor bit lsd, the rounding bit rnd, and the guard bit gard; the rounding processing method includes rounding to even numbers; the target input condition includes: the rounding bit rnd is 1, and the last minor bit lsd, the target discard value, and the guard bit include at least one 1.

[0151] In some implementations, the rounding module 432 can determine the input value to be 1 if the rounding bit rnd is 1 and the last minor bit lsd, the target discard value, and the guard bit include at least one 1. The target mantissa is obtained by adding the mantissa to be rounded to 1.

[0152] In some implementations, if the rounding bit is 0, the rounding module 432 can determine that the rounding-related bits and the target discard value do not meet the target input value condition, and thus determine that the input value is 0.

[0153] In some implementations, if the rounding bit is 1, but the last little bit lsd, the target discard value, and the guard bit are all 0, then the rounding module 432 can determine that the rounding-related bits and the target discard value do not meet the target input value condition, and thus determine that the input value is 0.

[0154] Understandably, by setting the target discard value and the target input value conditions corresponding to the rounding processing method that the relevant bits of the rounding must meet, the rounding module 432 can perform rounding operations on the mantissa to be rounded, achieve the rounding processing effect corresponding to the rounding processing method, and improve the accuracy of the calculation.

[0155] For example, the following shows three FP32 floating-point numbers: operand A, operand B, and operand C. Operand A is the third floating-point number, operand B is the fourth floating-point number, and operand C is the second floating-point number.

[0156] Operand A: 0 10000011 000_0010_0000_0011_0000_0000 (hexadecimal 32'h41820300);

[0157] Operand B: 0 10000100 000_0001_0100_0000_0101_0000 (hexadecimal 32'h42014050); Operand C: 0 10001111 100_0000_0100_0000_0000_0000 (hexadecimal 32'h47c04000);

[0158] The multiplier has a bit width of 50, with the highest bit being the sign bit; the adder has a bit width of 53, with the highest bit being the sign bit. The preset threshold is 26.

[0159] Multiplying operand A and operand B yields product AB (i.e., the first floating-point number). The mantissa of product AB is the first mantissa, and the exponent of product AB is... (i.e., the first index) is shown in formula (1).

[0160]

[0161]

[0162] (1);

[0163] Wherein, the exponent part of operand A The exponent part of operand B and the exponent part of operand C All used a biased exponent, where the bias value The value is 127 (0111_1111 in binary), meaning the actual exponent in decimal needs to be increased by 127. Only then is it equal to the corresponding biased exponent.

[0164] The exponent difference is the exponent of the product AB. Subtract the exponent of operand C See formula (2).

[0165]

[0166]

[0167] (2);

[0168] in, The decimal value of the result is -6. Since the exponent difference is negative and its absolute value is less than 26, the truncation bit can be determined to be 26. The difference between the preset threshold and 6, i.e., 20, is the shift bit. In other words, adder 42 needs to place the high 26 bits (0100 0001 1010 0100 0010 1100 01) of the 48-bit mantissa AB (i.e., the first mantissa) into the low 26 bits of the 53-bit adder. That is, the high 25 bits of "b.48" are truncated as the low bits of the first addend, and the remaining low 22 bits "100000 1111 0000 0000 0000" are denoted as stick1. The right shifter performs a right shift operation on the mantissa C, shifting by 20 bits, to obtain the second addend, as shown below. Figure 11 As shown. Adder 42 obtains the first mantissa sum as "00000000000000000000110000010100011010010000 1011000". Rounding module 432 removes leading zeros from the first mantissa sum, obtaining the second mantissa sum as "110000010100011010010000 1011000". The remaining 24-bit mantissa sum is "110000010100011010010000", lsd is "0", rnd is "1", gard is "0", and the remaining "11000" is denoted as stick2. It can be seen that both stick1 and stick2 contain "1", and the target discard value is 1. Following the rounding method towards even numbers, rnd in the relevant rounding bits is 1, while among lsd, gard, and the target discard value, the target discard value is 1. Therefore, the input value is determined to be 1. The target mantissa is the sum of the mantissa to be rounded and 1, "110000010100011010010001".

[0169] In the above embodiments, the rounding-related bits include the least significant bit (lsd), the rounding bit (rnd), and the guard bit (gard); the rounding processing method includes rounding towards even numbers; the target input condition includes: the rounding bit (rnd) is 1, and the least significant bit (lsd), the target discard value, and the guard bit include at least one 1. Thus, rounding towards even numbers can be used to accurately achieve the rounding processing of the sum of the mantissas to be rounded.

[0170] In some embodiments, the target mantissa is the mantissa of the target floating-point number, such as... Figure 12 As shown, the floating-point computing device also includes an exponent calculation module 46;

[0171] Post-processing module 43 is used to normalize and round the first mantissa to obtain the target mantissa and the exponent correction number.

[0172] The index calculation module 46 is used to correct the reference index based on the index correction number to obtain the target index of the target floating-point number.

[0173] Here, during the normalization and rounding process of the first mantissa sum to obtain the target mantissa, the shifting operation performed by the post-processing module 43 affects the exponent of the final target floating-point number. Specifically, a right shift moves the decimal point of the mantissa to the left, requiring a corresponding increase in the exponent; a left shift moves the decimal point of the mantissa to the right, requiring a corresponding decrease in the exponent. For each digit shifted in the mantissa, the exponent changes by 1 (decimal). Therefore, during the normalization and rounding process of the first mantissa sum to obtain the target mantissa, the post-processing module 43 can also generate a corresponding exponent correction number based on the shifting operations during the normalization and rounding processes. This exponent correction number characterizes the amount of exponent change corresponding to the target mantissa during the normalization and rounding processes.

[0174] In some implementations, the index calculation module 46 can be used to add an index correction number to a reference index to obtain the target index of the target floating-point number.

[0175] In some implementations, the exponent calculation module 46 is also used to obtain the first exponent of the first floating-point number based on the sum of the exponents of the third floating-point number and the fourth floating-point number.

[0176] In some implementations, the sign of the exponent correction number can characterize the shift direction of the mantissa; thus, the exponent calculation module 46 can adjust the reference exponent according to the exponent correction number to obtain the target exponent, which is the exponent of the product of the third and fourth floating-point numbers and the sum of the second floating-point number. Based on the target exponent and the target mantissa, the target floating-point number can be obtained, which is the floating-point format number of the product of the third and fourth floating-point numbers and the sum of the product and the third floating-point number.

[0177] In the above embodiments, the exponent calculation module corrects the reference exponent based on the exponent correction number output by the post-processing module, thereby obtaining a more accurate target exponent and improving the calculation accuracy of the target floating-point number.

[0178] It is understood that the floating-point computing device provided in this application embodiment can perform multiplication and addition calculations between any three floating-point numbers. Thus, by reducing the selector processing before shifting during the calculation process, the calculation path is shortened, thereby improving the calculation speed of floating-point multiplication and addition calculations.

[0179] Based on the above embodiments, this application provides a floating-point calculation method for a processor. This method can be applied to the floating-point calculation device described in the above embodiments. Figure 13 As shown, the method may include the following steps S101 to S103.

[0180] S101. Based on the truncation bits, the first mantissa of the first floating-point number is truncated to obtain the first addend. Based on the shift bits, the second mantissa of the second floating-point number is shifted to obtain the second addend. The first addend and the second addend are two mantissas with exponents aligned. The truncation bits and shift bits are determined based on the exponent difference between the first exponent of the first floating-point number and the second exponent of the second floating-point number.

[0181] S102. Add the first addend and the second addend to get the sum of the first last digit;

[0182] S103. Normalize and round the first mantissa to obtain the target mantissa.

[0183] In some embodiments, step S101 is performed by the mantissa alignment module in the floating-point computing device, step S102 is performed by the adder in the floating-point computing device, and step S103 is performed by the post-processing module in the floating-point computing device.

[0184] In some embodiments, the mantissa alignment module includes: a determining module, a truncation module, and a shifter; step S101 above may include the following steps S111 to S113:

[0185] Step S111: The module determines the reference index, the truncation bit and the shift bit corresponding to the reference index based on the exponential difference.

[0186] Step S112: The truncation module truncates a data segment from the first mantissa, starting from the most significant bit and with a width equal to the number of bits to be truncated, and uses it as the first addend;

[0187] In step S113, the shifter shifts the second mantissa to the right by the shift number to obtain the second addend. The first addend and the second addend are aligned based on the reference exponent.

[0188] In some embodiments, the floating-point calculation device further includes: a multiplication module and an exponent difference determination module; the above floating-point calculation method may further include the following steps S121 to S122:

[0189] Step S121: The multiplication module multiplies the third mantissa of the third floating-point number with the fourth mantissa of the fourth floating-point number to obtain the first mantissa.

[0190] Step S122: The exponent difference determination module sums the third exponent of the third floating-point number and the fourth exponent of the fourth floating-point number to obtain the first exponent, and subtracts the second exponent from the first exponent to obtain the exponent difference.

[0191] In some embodiments, the bit width of the data bits of the adder is twice a preset threshold; the preset threshold is the sum of the preset mantissa effective bit width and the preset rounding-related bit width minus 1.

[0192] In some embodiments, step S111 above may include step S131 as follows:

[0193] Step S131: When the exponent difference is greater than or equal to 0, the module determines the first exponent as the reference exponent, the bit width of the data bits of the adder as the truncation bit width, and the exponent difference as the shift bit width.

[0194] In some embodiments, the post-processing module includes a normalization module and a rounding module; the above floating-point calculation method may further include the following step S141:

[0195] When the exponent difference is greater than or equal to 0, the shifter transmits the data segment shifted out by the second mantissa by the number of shifts as the first discard bit to the rounding module;

[0196] Step S103 above may include the following steps S142 and S143:

[0197] Step S142: The normalization module removes leading zeros from the first mantissa sum to obtain the second mantissa sum;

[0198] In step S143, the rounding module performs rounding on the second mantissa based on the first discard bit to obtain the target mantissa.

[0199] In some embodiments, step S111 above may include step S151 or step S152:

[0200] Step S151: When the exponential difference is less than 0 and the absolute value of the exponential difference is greater than or equal to a preset threshold, the determining module determines the second exponent as the reference exponent and determines that the truncation bits and shift bits are both 0.

[0201] Step S152: When the exponential difference is less than 0 and the absolute value of the exponential difference is less than a preset threshold, the sum of the first exponent and the preset threshold is determined as the reference exponent, the preset threshold is determined as the truncation number, and the difference between the preset threshold and the absolute value of the exponential difference is determined as the shift number.

[0202] In some embodiments, the post-processing module includes a normalization module and a rounding module; the above floating-point calculation method may further include the following steps S161 or S162:

[0203] Step S161: When the exponent difference is less than 0 and the absolute value of the exponent difference is greater than or equal to a preset threshold, the truncation module transmits the first mantissa as the first discard bit to the rounding module.

[0204] In step S162, when the exponent difference is less than 0 and the absolute value of the exponent difference is less than a preset threshold, the truncation module extracts the remaining data segments from the first mantissa as the first discard bits and transmits them to the rounding module.

[0205] Step S103 above may include the following steps S163 and S164:

[0206] Step S163: The normalization module removes leading zeros from the first mantissa sum to obtain the second mantissa sum;

[0207] In step S164, the rounding module performs rounding on the second mantissa based on the first discard bit to obtain the target mantissa.

[0208] In some embodiments, step S164 may include steps S171 to S173 as follows:

[0209] Step S171: The rounding module extracts the data segment from the second mantissa sum starting from the most significant bit and whose bit width is equal to the effective bit width of the mantissa, as the mantissa sum to be rounded.

[0210] Step S172: The rounding module takes the least bit of the sum of mantissas to be rounded as the starting bit and determines at least two consecutive rounding-related bits from the second sum of mantissas.

[0211] In step S173, the rounding module performs rounding processing on the mantissa to be rounded according to the target input condition, based on the first discard bit, the rounding related bit, and the second discard bit after the rounding related bit, to obtain the target mantissa.

[0212] In some embodiments, step S173 may include steps S181 to S183 as follows:

[0213] Step S181: The rounding module determines the target discard value based on the first discard bit and the second discard bit;

[0214] In step S182, the rounding module determines the input value to be 1 if the target discard value and the rounding-related bits meet the target input value condition; or, if the target discard value and the rounding-related bits do not meet the target input value condition, it determines the input value to be 0.

[0215] In step S183, the rounding module adds the sum of the decimal part to be rounded to the input value to obtain the target decimal part.

[0216] In some embodiments, the rounding-related bits include a last digit, a rounding bit, and a guard bit; the rounding process includes rounding to an even number; the target value condition includes: the rounding bit is 1, and the last digit, the target discard value, and the guard bit include at least one 1.

[0217] In some embodiments, the target mantissa is the mantissa of the target floating-point number, and the floating-point computing device further includes an exponent calculation module; the above floating-point calculation method further includes the following steps S191 to S192:

[0218] Step S191: The post-processing module performs normalization and rounding on the first mantissa to obtain the target mantissa and the exponent correction number.

[0219] In step S192, the index calculation module corrects the reference index based on the index correction number to obtain the target index of the target floating-point number.

[0220] Figure 14 The structure of an electronic device is shown, such as Figure 14 As shown, the electronic device 1700 includes a memory 1707, a processor 1708, and a computer program stored in the memory 1707 and executable on the processor 1708; wherein, when the processor 1708 runs the computer program, it executes the floating-point calculation method as described in the foregoing embodiments.

[0221] It is understood that the electronic device 1700 also includes a bus system 1709; the various components in the electronic device 1700 are coupled together through the bus system 1709. It is understood that the bus system 1709 is used to realize the connection and communication between these components. In addition to a data bus, the bus system 1709 also includes a power bus, a control bus, and a status signal bus.

[0222] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or both. Specifically, non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM); magnetic surface memory can be disk storage or magnetic tape storage. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), SyncLink Dynamic Random Access Memory (SLDRAM), and Direct Rambus Random Access Memory (DRRAM).The memories described in the embodiments of this application are intended to include, but are not limited to, these and any other suitable types of memories.

[0223] The methods disclosed in the embodiments of this application can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor may be a general-purpose processor, a DSP, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this application can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory. The processor reads signals from the memory and, in conjunction with its hardware, completes the steps of the aforementioned method.

[0224] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described method.

[0225] This application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium; in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0226] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referred to interchangeably. In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple modules or components can be combined, or integrated into another system, or some features can be ignored or not executed. Furthermore, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces; the indirect coupling or communication connection between devices or modules can be electrical, mechanical, or other forms.

[0227] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A floating-point computing device for a processor, characterized in that, include: The mantissa alignment module is used to truncate the first mantissa of a first floating-point number based on the number of truncation bits to obtain a first addend, and to shift the second mantissa of a second floating-point number based on the number of shift bits to obtain a second addend, wherein the first addend and the second addend are two mantissas aligned with the exponent; the number of truncation bits and the number of shift bits are determined based on the exponent difference between the first exponent of the first floating-point number and the second exponent of the second floating-point number; A hardware adder is used to add the first addend and the second addend to obtain a first mantissa sum; The post-processing module is used to perform normalization and rounding on the first mantissa to obtain the target mantissa; The mantissa alignment module is further configured to: determine a reference exponent, a truncation bit length, and a shift bit length corresponding to the reference exponent based on the exponent difference; truncate a data segment from the first mantissa starting from the most significant bit and with a bit width equal to the truncation bit length as the first addend; right-shift the second mantissa by the shift bit length to obtain the second addend, wherein the first addend and the second addend are aligned based on the reference exponent; when the exponent difference is less than 0, the reference exponent, the truncation bit length, and the shift bit length are determined based on the relationship between the absolute value of the exponent difference and a preset threshold; the preset threshold represents the number of consecutive bits in the mantissa of the floating-point number, starting from the first significant bit and ending at the last rounding bit.

2. The floating-point computing device according to claim 1, characterized in that, The mantissa alignment module includes: The determining module is used to determine a reference index, as well as the truncation bits and shift bits corresponding to the reference index, based on the index difference. The truncation module is used to truncate a data segment from the first mantissa, starting from the most significant bit and with a bit width equal to the number of bits to be truncated, as the first addend; A shifter is used to right-shift the second mantissa by the shift number to obtain the second addend, wherein the first addend and the second addend are aligned based on the reference exponent.

3. The floating-point computing device according to claim 2, characterized in that, The floating-point computing device further includes: The multiplication module is used to multiply the third mantissa of the third floating-point number and the fourth mantissa of the fourth floating-point number to obtain the first mantissa; The exponent difference determination module is used to sum the third exponent of the third floating-point number and the fourth exponent of the fourth floating-point number to obtain the first exponent, and to subtract the second exponent from the first exponent to obtain the exponent difference.

4. The floating-point computing device according to claim 3, characterized in that, The bit width of the data bits of the adder is twice a preset threshold; the preset threshold is the sum of the preset mantissa effective bit width and the preset rounding related bit width minus 1.

5. The floating-point computing device according to claim 4, characterized in that, The determining module is further configured to: determine the first exponent as the reference exponent when the exponent difference is greater than or equal to 0, determine the bit width of the data bits of the adder as the truncation bit width, and determine the exponent difference as the shift bit width.

6. The floating-point computing device according to claim 5, characterized in that, The post-processing module includes a normalization module and a rounding module; The shifter is also used to: when the exponent difference is greater than or equal to 0, transmit the data segment shifted out by the shift number after right shifting the second mantissa as the first discard bit to the rounding module; The normalization module is used to remove leading zeros from the first sum of mantissas to obtain the second sum of mantissas; The rounding module is used to round the second mantissa based on the first discard bit to obtain the target mantissa.

7. The floating-point computing device according to claim 4, characterized in that, The determining module is also used for at least one of the following: If the exponential difference is less than 0 and the absolute value of the exponential difference is greater than or equal to the preset threshold, the second exponent is determined as the reference exponent, and the truncation bits and the shift bits are both determined to be 0. When the exponential difference is less than 0 and the absolute value of the exponential difference is less than the preset threshold, the sum of the first exponent and the preset threshold is determined as the reference exponent, the preset threshold is determined as the truncation bit, and the difference between the preset threshold and the absolute value of the exponential difference is determined as the shift bit.

8. The floating-point computing device according to claim 7, characterized in that, The post-processing module includes a normalization module and a rounding module; The interception module is further configured to: transmit the first mantissa as the first discard bit to the rounding module when the exponent difference is less than 0 and the absolute value of the exponent difference is greater than or equal to the preset threshold. And / or, if the exponent difference is less than 0 and the absolute value of the exponent difference is less than the preset threshold, the remaining data segment truncated from the first mantissa is transmitted to the rounding module as the first discard bit. The normalization module is used to remove leading zeros from the first sum of mantissas to obtain the second sum of mantissas; The rounding module is used to round the second mantissa based on the first discard bit to obtain the target mantissa.

9. The floating-point computing device according to claim 6 or 8, characterized in that, The rounding module is further configured to: extract a data segment from the second mantissa sum starting from the most significant bit and having a bit width equal to the effective bit width of the mantissa, as the mantissa sum to be rounded; determine at least two consecutive rounding-related bits from the second mantissa sum, starting from the least significant bit of the mantissa sum to be rounded; and perform rounding processing on the mantissa sum to be rounded according to the target input condition, based on the first discard bit, the rounding-related bits, and the second discard bit following the rounding-related bits, to obtain the target mantissa.

10. The floating-point computing device according to claim 9, characterized in that, The rounding module is also used for: The target discard value is determined based on the first discard bit and the second discard bit; If the target discard value and the rounding-related bits satisfy the target input condition, the input value is determined to be 1; or, if the target discard value and the rounding-related bits do not satisfy the target input condition, the input value is determined to be 0. The target number is obtained by adding the sum of the numbers to be rounded to the input value.

11. The floating-point computing device according to claim 10, characterized in that, The rounding-related bits include the least significant bit, the rounding bit, and the guard bit; the rounding processing method includes rounding to even numbers; the target input value condition includes: the rounding bit is 1, and the least significant bit, the target discard value, and the guard bit include at least one 1.

12. The floating-point computing device according to any one of claims 2 to 8, 10, and 11, characterized in that, The target mantissa is the mantissa of the target floating-point number, and the floating-point calculation device further includes an exponent calculation module; The post-processing module is used to perform normalization and rounding on the first mantissa to obtain the target mantissa and the exponent correction number. The index calculation module is used to correct the reference index based on the index correction number to obtain the target index of the target floating-point number.

13. A floating-point calculation method for a processor, characterized in that, include: Based on the truncation bit, the first mantissa of the first floating-point number is truncated to obtain the first addend, and based on the shift bit, the second mantissa of the second floating-point number is shifted to obtain the second addend. The first addend and the second addend are two mantissas with exponents aligned. The truncation bit and the shift bit are determined based on the exponent difference between the first exponent of the first floating-point number and the second exponent of the second floating-point number. The first addend and the second addend are added using a hardware adder to obtain the first sum of the last digits; The first mantissa is normalized and rounded to obtain the target mantissa. The floating-point calculation method further includes: determining a reference exponent, and the truncation bits and shift bits corresponding to the reference exponent based on the exponent difference; The truncation process includes truncating a data segment from the first mantissa, starting from the most significant bit and with a bit width equal to the truncation bit width, as the first addend; the shifting process includes right-shifting the second mantissa by the shift bit width to obtain the second addend. When the exponent difference is less than 0, the reference exponent, the truncation bits, and the shift bits are determined based on the relationship between the absolute value of the exponent difference and a preset threshold; the preset threshold represents the number of consecutive bits in the mantissa of the floating-point number, starting from the first significant bit and ending at the last rounding bit.

14. An electronic device, characterized in that, include: memory for storing computer programs; A processor, when running the computer program, performs the floating-point calculation method as described in claim 13.

15. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the steps of the floating-point calculation method as described in claim 13.

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