Interrupt Verification Method, Device, Storage Medium and Equipment for C2F

Abstract

An embodiment of the present application provides an interrupt verification method, apparatus, storage medium and device for C2F, including: obtaining test constraint conditions, and generating global configuration information and interrupt configuration information of the interrupt signal to be tested based on the test condition; generating a configuration file based on the two configuration information, the file containing a global configuration code, an interrupt configuration code and a program configuration code of an interrupt verification program, which are respectively used to configure the global registers of the simulation processor and the interrupt controller, the interrupt registers corresponding to the interrupt signal to be tested and the interrupt verification program; then, sending the configuration file to the simulation processor to complete the configuration; after the configuration is completed, sending the interrupt signal to be tested that meets the interrupt configuration information to the interrupt controller, and the interrupt controller sends the interrupt request to the simulation processor after processing; when it is detected that the simulation processor enters the interrupt verification program, obtaining the interrupt signal identifier and interrupt level, if the two are consistent with the interrupt configuration information, the verification is passed, thereby improving the test efficiency.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a C2F interrupt verification method, apparatus, storage medium, and device. Background Art

[0002] The Consumer to Factory (C2F) industry model is driven by customer demand, enabling highly customized and flexible production and supply chains. In traditional industries, product design and production processes are often driven one-way by manufacturers based on market forecasts. In the C2F model, customer needs are communicated directly to the factory, allowing the entire production process to be adjusted in real time based on individual customer needs. The core advantage of the C2F model is that it significantly improves production flexibility and responsiveness, reduces intermediate logistics links, reduces inventory backlogs, improves production efficiency, and enables rapid response to market changes and consumer demand.

[0003] The fifth-generation Reduced Instruction Set Computer (RISC-V), an open-source, customizable, and scalable central processing unit (CPU) architecture, has multiple applications in C2F scenarios. RISC-V CPUs can function as programmable logic controllers (PLCs) to provide precise motion control for industrial robots, receiving and efficiently processing sensor data in real time, enabling rapid decision-making and precise operations. Furthermore, the low power consumption of RISC-V chips enables efficient operation even in power-constrained environments, reducing energy consumption and operating costs.

[0004] Traditional chip interrupt verification typically requires manually writing software code, compiling it into an executable file, and running it in a simulation environment. The verification environment then generates interrupt signals for verification. Changes to the test content require manually rewriting the software and repeating the entire test process. This is not only inefficient but also prone to human error, increasing verification complexity and cost. Therefore, an interrupt verification method is urgently needed to address these technical issues. Summary of the Invention

[0005] The main purpose of this application is to provide a C2F interrupt verification method, device, storage medium and equipment, which can automatically perform interrupt testing according to constraint conditions, avoid manual software writing, and improve testing efficiency.

[0006] In a first aspect, an embodiment of the present application provides a method for verifying a C2F interruption, including:

[0007] Acquire test constraints, and generate global configuration information and interrupt configuration information of the interrupt signal to be tested according to the test constraints;

[0008] Generate a configuration file based on the global configuration information and the interrupt configuration information, the configuration file including a global configuration code for configuring the simulation processor and the global registers of the interrupt controller according to the global configuration information, an interrupt configuration code for configuring the interrupt register corresponding to the interrupt signal to be tested according to the interrupt configuration information, and a program configuration code for an interrupt verification program;

[0009] Sending the configuration file to the simulation processor so that the simulation processor executes the configuration file to configure a global register of the simulation processor, a global register of the interrupt controller, an interrupt register corresponding to the interrupt signal to be tested in the interrupt controller, and an interrupt verification program;

[0010] When the simulation processor is configured, the interrupt signal to be tested that conforms to the interrupt configuration information is sent to the interrupt controller, so that the interrupt controller processes the interrupt signal to be tested according to the interrupt register and sends the interrupt request obtained by the processing to the simulation processor;

[0011] When detecting that the simulation processor enters an interrupt verification program in the process of responding to the interrupt request, obtaining an interrupt signal identifier and an interrupt level;

[0012] When the interrupt signal identifier and the interrupt level conform to the interrupt configuration information, it is determined that the verification is passed.

[0013] In a second aspect, an embodiment of the present application provides a C2F interrupt verification device, including:

[0014] a first acquiring unit, configured to acquire test constraints, and generate global configuration information and interrupt configuration information of the interrupt signal to be tested according to the test constraints;

[0015] a generating unit, configured to generate a configuration file based on the global configuration information and the interrupt configuration information, the configuration file including a global configuration code for configuring the global registers of the simulation processor and the interrupt controller according to the global configuration information, an interrupt configuration code for configuring the interrupt register corresponding to the interrupt signal to be tested according to the interrupt configuration information, and a program configuration code for an interrupt verification program;

[0016] a first sending unit, configured to send the configuration file to the simulation processor, so that the simulation processor executes the configuration file to configure a global register of the simulation processor, a global register of the interrupt controller, an interrupt register corresponding to the interrupt signal to be tested in the interrupt controller, and an interrupt verification program;

[0017] a second sending unit, configured to send, when the configuration of the simulation processor is completed, an interrupt signal to be tested that conforms to the interrupt configuration information to the interrupt controller, so that the interrupt controller processes the interrupt signal to be tested according to the interrupt register and sends an interrupt request obtained by the processing to the simulation processor;

[0018] A second acquiring unit is configured to acquire an interrupt signal identifier and an interrupt level when detecting that the simulation processor enters an interrupt verification program in the process of responding to the interrupt request;

[0019] The verification unit is configured to determine that the verification is passed when the interrupt signal identifier and the interrupt level conform to the interrupt configuration information.

[0020] In a third aspect, an embodiment of the present application provides a storage medium, wherein the computer-readable storage medium stores a plurality of instructions suitable for loading by a processor to execute any one of the above interrupt verification methods for C2F.

[0021] In a fourth aspect, an embodiment of the present application provides a computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the interruption verification method for C2F as described in any one of the above items is implemented.

[0022] In an embodiment of the present application, by obtaining test constraints, global configuration information and interrupt configuration information of the interrupt signal to be tested are generated according to the test constraints; based on the global configuration information and the interrupt configuration information, a configuration file is generated, the configuration file including a global configuration code for configuring the simulation processor and the global registers of the interrupt controller according to the global configuration information, an interrupt configuration code for configuring the interrupt register corresponding to the interrupt signal to be tested according to the interrupt configuration information, and a program configuration code for the interrupt verification program; the configuration file is sent to the simulation processor so that the simulation processor executes the configuration file to configure the global registers of the simulation processor, the global registers of the interrupt controller, the interrupt register corresponding to the interrupt signal to be tested in the interrupt controller, and the interrupt verification program; when the simulation processor configures When the test is completed, the interrupt signal to be tested that meets the interrupt configuration information is sent to the interrupt controller, so that the interrupt controller processes the interrupt signal to be tested according to the interrupt register, and sends the processed interrupt request to the simulation processor; when it is detected that the simulation processor enters the interrupt verification program in the process of responding to the interrupt request, the interrupt signal identifier and the interrupt level are obtained; when the interrupt signal identifier and the interrupt level meet the interrupt configuration information, it is determined that the verification is passed. Compared with the related art, each test requires manual software writing and repeating the entire test process, the embodiment of the present application generates a configuration file through global configuration information and interrupt configuration information generated by constraint conditions for configuration of the simulation processor, and automatically verifies the interrupt signal to be tested after the configuration is completed, avoiding manual software writing and improving test efficiency.

[0023] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. The purposes and other advantages of the present disclosure can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A schematic diagram of a scenario for a C2F interruption verification system provided in an embodiment of the present application.

[0026] Figure 2A flowchart of a C2F interrupt verification method provided in an embodiment of the present application.

[0027] Figure 3 A schematic diagram of the structure of a global register provided in an embodiment of the present application.

[0028] Figure 4 A schematic diagram of the register structure related to a single interrupt signal in the interrupt controller provided in an embodiment of the present application.

[0029] Figure 5 A flowchart of determining an interrupt verification method provided in an embodiment of the present application.

[0030] Figure 6 Another flowchart for determining an interrupt verification method provided in an embodiment of the present application.

[0031] Figure 7 A schematic diagram of the structure of a C2F interruption verification device provided in an embodiment of the present application.

[0032] Figure 8 A schematic diagram of the structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the solutions of this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of this application.

[0034] It should be noted that some processes described in the specification, claims, and figures above include multiple steps that appear in a specific order. However, it should be understood that these steps may be executed in a different order than the order in which they appear herein or in parallel. The step numbers are used solely to distinguish between the different steps and do not themselves represent any order of execution. Furthermore, terms such as "first," "second," or "target" are used herein to distinguish similar objects and are not necessarily used to describe a specific order or precedence.

[0035] Before further explaining the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are explained. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0036] The Core-Local Interrupt Controller (CLIC) is a key component in the RISC-V architecture for handling interrupts. In computer systems, interrupts are a crucial mechanism for handling requests from external devices or internal exceptions. As the interrupt controller in the RISC-V architecture, CLIC manages and coordinates interrupt requests from multiple sources, ensuring that the processor responds to these requests in a timely and orderly manner.

[0037] Rich interrupt source support: CLIC supports a large number of external interrupt sources, each of which can be independently configured and managed. This enables the system to connect to a wider variety and number of external devices, such as sensors and communication interfaces, and provides dedicated processing for each device's interrupt request.

[0038] Flexible priority management: The introduction of multi-level interrupt priority allows each interrupt source to be assigned a different priority. When multiple interrupts occur simultaneously, the processor processes them sequentially according to their priority, ensuring that high-priority interrupts are promptly addressed, which is particularly important for real-time systems.

[0039] Diverse trigger modes: Supports multiple interrupt trigger modes, including level triggering and edge triggering. Different trigger modes are suitable for different types of external devices and application scenarios, increasing system flexibility.

[0040] Interrupt vector table mechanism: An interrupt vector table is used to manage the entry address of the interrupt verification routine. Each interrupt source corresponds to a unique interrupt vector. When an interrupt occurs, the processor can quickly locate the corresponding interrupt verification routine by searching the interrupt vector table, reducing interrupt response latency and improving interrupt processing efficiency.

[0041] The Executable and Linkable Format (ELF) is a file format used to represent executable files, object files, shared libraries, core dump files, and more. ELF is a binary file format standard designed to provide a unified, flexible, and extensible file format to support program execution and linking on different architectures and operating systems. Today, ELF has become a widely used standard file format in Linux, Unix-like systems, and many embedded systems.

[0042] Please refer to the following specific embodiments for details.

[0043] See also Figure 1 , Figure 1This is a schematic diagram of a scenario of a C2F interruption verification system provided in an embodiment of the present application, which includes a terminal 140, the Internet 130, a gateway 120, a server 110, and the like.

[0044] Terminal 140 includes, but is not limited to, pre-configured electronic devices with data reporting capabilities, such as laptops, tablets, and desktop computers. Furthermore, it can be a single device or a collection of multiple devices. Terminal 140 can communicate with Internet 130 via wired or wireless means to exchange data.

[0045] Terminal 140 refers to a computer system capable of submitting data to server 110. Compared to common terminals, server 110 requires higher levels of stability, security, and performance. Server 110 can be a single high-performance computer within a network platform, a cluster of multiple high-performance computers, a portion of a single high-performance computer (e.g., a virtual machine), or a combination of portions of multiple high-performance computers (e.g., virtual machines).

[0046] Gateway 120, also known as a gateway or protocol converter, implements network interconnection at the transport layer and is a computer system or device that performs a conversion function. It acts as a translator between two systems using different communication protocols, data formats, languages, or even completely different architectures. Gateways can also provide filtering and security functions. Messages sent from terminal 140 to server 110 are sent through gateway 120 to the corresponding server 110. Messages sent from server 110 to terminal 140 are also sent through gateway 120 to the corresponding terminal 140.

[0047] The interruption verification method of the embodiment of the present disclosure may be implemented on the server 110 .

[0048] It should be noted that Figure 1 The scenario diagram of the C2F interruption verification system shown is only an example. The interruption verification system and scenario described in the embodiment of the present application are intended to more clearly illustrate the technical solution of the embodiment of the present application, and do not constitute a limitation on the technical solution provided by the embodiment of the present application. Ordinary technicians in this field can know that with the evolution of image processing technology and the emergence of new business scenarios, the technical solution provided by the embodiment of the present application is also applicable to similar technical problems.

[0049] In this embodiment, the description will be made from the perspective of an interrupt verification device, which can be integrated into a computer device having a storage unit and a microprocessor installed therein and having computing capabilities.

[0050] See also Figure 2 , Figure 2A flowchart of a C2F interruption verification method provided in an embodiment of the present application. The C2F interruption verification method includes:

[0051] In step 201, test constraints are acquired, and global configuration information and interrupt configuration information of an interrupt signal to be tested are generated according to the test constraints.

[0052] Constraints are a set of restrictions and requirements placed on the simulation test process, defining the scope and objectives of the test and ensuring the validity and reliability of the test results. Global configuration information is a collection of configuration parameters that affect the operation of the entire simulation system, encompassing global settings for multiple components such as the simulation processor and interrupt controller. Tested interrupt signals are interrupt signals that require testing and verification, typically originating from the test environment's driver. Interrupt configuration information is detailed configuration parameters for a specific interrupt signal, controlling its triggering, processing, and priority.

[0053] Specifically, relevant information is collected from test cases, requirements documents, or user input. This information specifies the specific requirements for the simulation test, such as the operating mode of the simulated processor, interrupt triggering conditions, and priority settings. Based on the test constraints, configuration parameters related to the entire simulation system are determined, such as the privileged mode of the simulated processor and the interrupt enable status. For the interrupt signal to be tested, the corresponding configuration information is generated based on the test constraints, including the interrupt number, trigger mode (level triggering or edge triggering), and priority.

[0054] In step 202, a configuration file is generated based on the global configuration information and the interrupt configuration information. The configuration file includes a global configuration code for configuring the global registers of the simulation processor and the interrupt controller according to the global configuration information, an interrupt configuration code for configuring the interrupt register corresponding to the interrupt signal to be tested according to the interrupt configuration information, and a program configuration code for the interrupt verification program.

[0055] Among them, since the global configuration information and interrupt configuration information are generated according to the constraints, in order to achieve the purpose of automated testing, these configuration information needs to be automatically configured to the simulation processor and interrupt controller. Therefore, it is necessary to generate an ELF format configuration file based on the global configuration information and the interrupt configuration information for execution by the simulation processor to achieve automated configuration.

[0056] Specifically, the CLIC standard defines that CPU design code also needs to be modified. These modifications include the xstatus, xedeleg / xideleg, xie / xip, xtvec, and xcause control and status registers (CSRs). Furthermore, the xtvt, xnxti, xintstatus, and xintthresh CSRs need to be added. Therefore, the design under test (DUT) in this application's implementation verifies the CLIC interrupt controller and the modified simulated processor as a whole. Otherwise, the modified and added CPU code cannot be verified, and the design quality cannot be guaranteed. However, interrupts are generated by the verification environment, rather than by the individual functional modules within the System on a Chip (SOC) verification environment. This significantly improves the flexibility and controllability of interrupt generation and greatly reduces the cost of generating interrupts. Therefore, it is necessary to configure both the simulation processor and the interrupt controller. Therefore, the configuration file includes global configuration code for the simulation processor's global registers and the interrupt controller's global registers, as well as interrupt configuration code for the interrupt registers corresponding to the interrupt signal to be tested, and program configuration code for the interrupt verification program. The program configuration code is used to configure the interrupt verification program, which is used to verify whether the simulation processor correctly responds to interrupt requests. These codes are usually written in assembly language or a high-level programming language, and the configuration is completed by writing corresponding values to specific registers and building an interrupt verification program.

[0057] In some implementations, generating a configuration file based on the global configuration information and the interrupt configuration information includes:

[0058] (1) Obtaining the first interrupt privilege mode, parent interrupt control mode, and child interrupt control mode required for the current test from the global configuration information and the interrupt configuration information;

[0059] (2) Obtain the second interrupt privilege mode currently running in the simulation processor;

[0060] (3) determining a target interrupt verification mode for the interrupt signal to be tested based on the first interrupt privilege mode, the parent interrupt control mode, the child interrupt control mode, and the second interrupt privilege mode;

[0061] (4) determining a target code template corresponding to the interrupt verification program based on a mapping relationship between the interrupt verification method and the code template of the interrupt verification program;

[0062] (5) Obtaining the content to be replaced included in the target code template and the content type corresponding to each of the content to be replaced;

[0063] (6) obtaining replacement content corresponding to each content type from the interruption configuration information, and replacing the replacement content with the corresponding content type in the target code template to obtain the program configuration code of the interruption verification program;

[0064] (7) Obtaining a first register configuration content of the simulation processor and a second register configuration content of the interrupt controller from the global configuration information;

[0065] (8) Generate a global configuration code based on the configuration content of the first register and the configuration content of the second register;

[0066] (9) obtaining, from the interrupt configuration information, a third register configuration content of the interrupt register corresponding to the interrupt signal to be measured in the interrupt controller;

[0067] (10) generating an interrupt configuration code according to the configuration content of the third register;

[0068] (11) Combining the program configuration code, the global configuration code, and the interrupt configuration code, a configuration file is obtained.

[0069] Among them, such as Figure 3 As shown, Figure 3A structural diagram of the global register provided for an embodiment of the present application. The global registers include cliccfg, Xtvec, Xinthresh, and Xie, where cliccfg is the CLIC Configuration Register. It is located in the CLIC interrupt controller and is used to configure and set the CLIC interrupt controller as a whole. For example, it can configure the operating mode, global enable status, etc. of the interrupt controller to determine how to handle incoming interrupt signals. xtvec is the Exception Vector Table Base Address Register. In the RISC-V architecture, when an exception or interrupt occurs, the processor needs to jump to the corresponding handler for execution. The xtvec register stores the starting address of the exception vector table. The processor finds the corresponding exception or interrupt verification program entry based on this address, and then performs subsequent processing operations. xinthresh is the Interrupt Threshold Register. It is used to set the priority threshold of the interrupt. Only when the priority of an interrupt is higher than the value set in the xinthresh register will the interrupt be responded to and processed by the processor. By adjusting the value of this register, you can flexibly control which interrupts can be processed promptly and which need to wait. xie stands for InterruptEnable. xstatus is a CSR, and xie is a specific field in the xstatus register that is used to globally control the enabling or disabling of interrupts. When the xie bit is enabled, the processor can respond to external or internal interrupts. When it is disabled, all interrupts are masked, and the processor will not respond to them.

[0070] See also Figure 4 , Figure 4 Schematic diagram of the register structure related to a single interrupt signal in the interrupt controller provided in the embodiment of the present application. Each interrupt signal in the interrupt controller corresponds to Figure 4As shown, clicintie, clicintattr, clicintctl, and intid are shown. clicintie is the Core-Local Interrupt Controller Individual Interrupt Enable Register. In the CLIC architecture, the system may have multiple interrupt sources, each corresponding to a unique interrupt. The clicintie register is used to individually control whether each interrupt is enabled. By setting the corresponding interrupt bit in this register, you can determine whether a specific interrupt can be responded to and handled by the system. For example, if the clicintie bit corresponding to an interrupt generated by a device is set to 1, the interrupt is enabled and the system will handle it at the appropriate time; if it is set to 0, the interrupt is disabled and the system will not respond to it. clicintattr is the Core-Local Interrupt Controller Individual Interrupt Attribute Register. This register is used to configure the attributes of each interrupt, including the interrupt trigger mode (such as rising edge trigger, falling edge trigger, high level trigger, low level trigger, etc.) and the privilege mode (i.e., the privilege level at which the interrupt is handled). Different attribute settings affect interrupt handling and the system's response strategy. clicintctl stands for the Core-Local Interrupt Controller Individual Interrupt Control Register. It provides more detailed control and management of individual interrupts, including information such as interrupt priority and whether to use hardware vectoring. Priority determines the order in which the system handles multiple interrupts simultaneously; hardware vectoring improves interrupt handling efficiency and reduces software overhead. intid stands for Interrupt Identifier. In a system, each interrupt source is assigned a unique number, known as the interrupt number. When an interrupt occurs, the system identifies the interrupt source by identifying its intid. It then uses the intid to locate the corresponding interrupt verification routine entry point and execute the appropriate interrupt handling operations. For example, in a system with multiple peripherals, an interrupt generated by keyboard input might be assigned intid 10, while an interrupt generated by mouse movement might be assigned intid 11. The system uses different intids to distinguish and handle different interrupt events.

[0071] Specifically, in the process of generating the configuration file, since it involves the generation of the program configuration code of the interrupt verification program, it is necessary to determine the specific target interrupt verification method for the interrupt signal to be tested based on the relevant configuration of the interrupt signal to be tested and the relevant information of the current operation of the simulation processor.

[0072] Among them, the main factors affecting the interrupt verification method include privileged mode, parent interrupt control mode, and child interrupt control mode. The RISC-V architecture defines multiple privileged modes, the most common of which are machine mode (M-mode), supervisor mode (S-mode), and user mode (U-mode), with privileges decreasing in order. Machine mode has the highest privileges and can access all system resources and execute all instructions. It is often used for system startup and hardware initialization. Supervisor mode is used for the operating system kernel and can execute some privileged instructions and manage system resources. User mode has the lowest privileges and can only execute non-privileged instructions. It is used to run ordinary user programs. Parent interrupt control mode includes two different interrupt handling modes: CLINT (Core-Local Interruptor) and CLIC (Core-Local Interrupt Controller). Both CLINT mode and CLIC mode include two different child interrupt control modes: direct mode and hardware vector mode.

[0073] Specifically, xtvec in the global configuration information is configured with a parent interrupt control mode (such as CLINT mode or CLIC mode), clicintattr in the interrupt configuration information is configured with the first interrupt privilege mode (such as machine mode, supervisor mode, user mode) required for the current test of the interrupt signal to be tested, and clicintctl is configured with a child interrupt control mode (such as Direct mode or hardware vector mode). Because the privilege mode and other information currently running in the simulation processor are known, it is possible to identify whether it is necessary to enter the interrupt verification program and which interrupt verification mode to enter. Different interrupt verification modes correspond to different code templates for the interrupt verification program. Therefore, after determining the target interrupt verification mode for the interrupt signal to be tested, the target code template corresponding to the interrupt verification program can be determined based on the mapping relationship. The code template reserves content to be replaced with specific content. By obtaining the content to be replaced included in the target code template and the content type corresponding to each content to be replaced, the replacement content corresponding to each content type is obtained from the interrupt configuration information, and the replacement content is replaced with the corresponding content type in the target code template to obtain the program configuration code of the interrupt verification program.

[0074] Among them, according to Figure 3 and Figure 4, it is also necessary to separately configure the emulation processor's global registers (first registers xtvec, xinthresh, and xstatus.xie), the interrupt controller's global registers (second register cliccfg), and the interrupt controller's interrupt registers corresponding to the interrupt signal to be tested (third registers clicintie, clicintattr, clicintctl, and intid). Therefore, it is necessary to obtain the configuration content of the emulation processor's first register and the interrupt controller's second register from the global configuration information; generate global configuration code based on the first and second register configuration contents; obtain the third register configuration content of the interrupt register corresponding to the interrupt signal to be tested in the interrupt controller from the interrupt configuration information; generate interrupt configuration code based on the third register configuration content; and finally, combine the program configuration code, global configuration code, and interrupt configuration code to obtain a configuration file.

[0075] In some embodiments, determining the target interrupt verification mode of the interrupt signal to be tested based on the first interrupt privilege mode, the parent interrupt control mode, the child interrupt control mode, and the second interrupt privilege mode includes:

[0076] (1.1) comparing the first interrupt privilege mode with the second interrupt privilege mode to obtain a comparison result;

[0077] (1.2) When the comparison result indicates that the first interrupt privilege mode is greater than the second interrupt privilege mode, determining that the interrupt signal to be tested is processed as a vertical interrupt;

[0078] (1.3) When the parent interrupt control mode is the CLINT mode and the child interrupt control mode is the Direct mode, determining the interrupt verification mode of the Direct mode as the target interrupt verification mode of the interrupt signal to be tested;

[0079] (1.4) When the parent interrupt control mode is the CLINT mode and the child interrupt control mode is not the Direct mode, the interrupt verification mode of the vector mode is determined as the target interrupt verification mode of the interrupt signal to be tested.

[0080] Among them, see Figure 5 , Figure 5A flowchart for determining an interrupt verification method is provided for an embodiment of the present application. First, the privilege mode of the interrupt (first interrupt privilege mode) is compared with the current privilege mode of the emulated processor (second interrupt privilege mode) to obtain a comparison result; when the comparison result indicates that the first interrupt privilege mode is less than the second interrupt privilege mode, the interrupt is ignored; when the comparison result indicates that the first interrupt privilege mode is greater than the second interrupt privilege mode, it is determined that the current interrupt is processed as a vertical interrupt; when the parent interrupt control mode is CLINT mode and the child interrupt control mode is Direct mode, the interrupt verification mode of Direct mode is determined as the target interrupt verification mode of the interrupt signal to be tested; when the parent interrupt control mode is CLINT mode and the child interrupt control mode is not Direct mode, the interrupt verification mode of vector mode is determined as the target interrupt verification mode of the interrupt signal to be tested.

[0081] In some embodiments, the method further comprises:

[0082] (1.1) When the parent interrupt control mode is the CLIC mode and the child interrupt control mode is the hardware vector mode, determining the interrupt verification mode of the vector mode as the target interrupt verification mode of the interrupt signal to be tested;

[0083] (1.2) When the parent interrupt control mode is the CLIC mode and the child interrupt control mode is not the hardware vector mode, the interrupt verification mode of the non-vectored mode is determined as the target interrupt verification mode of the interrupt signal to be tested.

[0084] Among them, continue to refer to Figure 5 When the parent interrupt control mode is CLIC mode and the child interrupt control mode is hardware vector mode, the interrupt verification mode of the vector mode is determined as the target interrupt verification mode of the interrupt signal to be tested; when the parent interrupt control mode is CLIC mode and the child interrupt control mode is not hardware vector mode, the interrupt verification mode of the non-vector mode is determined as the target interrupt verification mode of the interrupt signal to be tested.

[0085] In some embodiments, the method further comprises:

[0086] (1.1) When the comparison result indicates that the first interrupt privilege mode is equal to the second interrupt privilege mode, determining that the interrupt signal to be tested is to be processed as a horizontal interrupt;

[0087] (1.2) When the parent interrupt control mode is the CLINT mode and the child interrupt control mode is the Direct mode, determining the interrupt verification mode of the Direct mode as the target interrupt verification mode of the interrupt signal to be tested;

[0088] (1.3) When the parent interrupt control mode is the CLINT mode and the child interrupt control mode is not the Direct mode, the interrupt verification mode of the vector mode is determined as the target interrupt verification mode of the interrupt signal to be tested.

[0089] Among them, see Figure 6 , Figure 6 Another flowchart for determining an interrupt verification method provided in an embodiment of the present application. If the comparison result indicates that the first interrupt privilege mode is equal to the second interrupt privilege mode, the interrupt is determined to be handled as a horizontal interrupt. When the parent interrupt control mode is CLINT mode and the child interrupt control mode is Direct mode, the interrupt verification method of Direct mode is determined as the target interrupt verification method for the interrupt signal to be tested. When the parent interrupt control mode is CLINT mode and the child interrupt control mode is not Direct mode, the interrupt verification method of vector mode is determined as the target interrupt verification method for the interrupt signal to be tested.

[0090] In some embodiments, the method further comprises:

[0091] (1.1) When the parent interrupt control mode is the CLIC mode, obtaining a global enable state from the global configuration information, and obtaining an interrupt enable state of the interrupt signal to be tested from the interrupt configuration information;

[0092] (1.2) When the global enable state and the interrupt enable state are enabled, obtaining a priority threshold from the global configuration information, and obtaining an interrupt priority of the interrupt signal to be tested from the interrupt configuration information;

[0093] (1.3) determining a target priority that is the highest of the priority threshold and the current priority of the simulation processor;

[0094] (1.4) When the interrupt priority is higher than the target priority and the sub-interrupt control mode is a hardware vector mode, the interrupt verification mode of the vector mode is determined as the target interrupt verification mode of the interrupt signal to be tested.

[0095] When the parent interrupt control mode is CLIC mode, the global enable status (e.g., enabled or disabled) is obtained from the global configuration information, and the interrupt enable status of the interrupt signal to be tested is obtained from the interrupt configuration information (e.g., whether the interrupt signal to be tested is configured to be enabled or disabled). If at least one of the two is 0, indicating that the interrupt is disabled, the interrupt is not enabled and invalid; if both are 1, indicating that the enable status is enabled, the interrupt is processed. Whether the interrupt is processed is determined by whether the interrupt priority of the interrupt signal to be tested is higher than L, where L is the highest target priority between the priority threshold xintstatus.xil in the global configuration information and the current priority xintthresh.th of the emulated processor, which can be expressed as max(xintstatus.xil, xintthresh.th). Therefore, it is necessary to obtain the priority threshold from the global configuration information, and the interrupt priority of the interrupt signal to be tested from the interrupt configuration information, and determine the highest target priority L between the priority threshold and the current priority of the simulation processor; when the interrupt priority is higher than the target priority L, and the sub-interrupt control mode is the hardware vector mode, the interrupt verification method of the vector mode is determined as the target interrupt verification method of the interrupt signal to be tested.

[0096] In some embodiments, the method further comprises:

[0097] When the interrupt priority is higher than the target priority and the sub-interrupt control mode is not the hardware vector mode, the interrupt verification mode of the non-vector mode is determined as the target interrupt verification mode of the interrupt signal to be tested.

[0098] Among them, if the interrupt priority is higher than the target priority, it means that the interrupt can be processed, and when the sub-interrupt control mode is not the hardware vector mode, it means that the sub-interrupt control mode is not the vector mode, so the interrupt verification method of the non-vector mode is determined as the target interrupt verification method of the interrupt signal to be tested.

[0099] In step 203, the configuration file is sent to the simulation processor so that the simulation processor executes the configuration file to configure the global registers of the simulation processor, the global registers of the interrupt controller, the interrupt register corresponding to the interrupt signal to be tested in the interrupt controller, and the interrupt verification program.

[0100] The ELF-formatted configuration file is sent to the emulation processor, which then configures the global registers, the interrupt controller's global registers, the interrupt registers, and the interrupt verification routine according to the configuration code in the file. The emulation processor is a software or hardware model that simulates the behavior of a real processor, executing the configuration file to implement the corresponding functions and configurations.

[0101] In step 204, when the simulation processor is configured, a test interrupt signal that complies with the interrupt configuration information is sent to the interrupt controller, so that the interrupt controller processes the test interrupt signal according to the interrupt register and sends the processed interrupt request to the simulation processor.

[0102] After the simulation processor is configured, it writes to the drv_start flag register. When the flag register reads the write flag, the driver sends a test interrupt signal that matches the interrupt configuration information to the interrupt controller. The interrupt controller processes the test interrupt signal according to the interrupt register and sends the resulting interrupt request to the simulation processor. An interrupt request is a signal generated by the interrupt controller after receiving an interrupt signal and requesting the processor to handle the interrupt.

[0103] In step 205, when it is detected that the simulation processor enters an interrupt verification program in the process of responding to the interrupt request, an interrupt signal identifier and an interrupt level are obtained.

[0104] Among them, it is judged whether it is possible to enter the interrupt verification program. If it is possible to enter the interrupt verification program, the interrupt level, interrupt ID, etc. are judged and pass (PASS) or fail (FAIL) is printed.

[0105] Specifically, the interrupt verification program checks whether the exccode field in the xcause CSR register is the same as the specified interrupt number, and whether the xil field (i.e., interrupt level) in the xintstatus CSR register is correct. If correct, PASS is printed; if incorrect, FAIL is printed. The xcause register is a special control and status register. Its main function is to record the cause of the most recent exception or interrupt. When the system encounters an exception (such as an illegal instruction, out-of-bounds access, etc.) or receives an interrupt signal, the hardware automatically writes the relevant exception or interrupt information to the xcause register. The exccode field is part of the xcause register and is used to store specific exception or interrupt codes. The highest bit of the xcause register is used to distinguish between an exception (value 0) and an interrupt (value 1), and the remaining low bits constitute the exccode field. Different exception or interrupt types correspond to different exccode values. By parsing this value, the software can determine which specific exception or interrupt has occurred.

[0106] In step 206 , when the interrupt signal identifier and the interrupt level comply with the interrupt configuration information, it is determined that the verification is successful.

[0107] If the interrupt signal identifier and the interrupt level match the signal identifier and the interrupt level of the interrupt signal to be tested in the interrupt configuration information, it is determined that the verification is successful.

[0108] In some embodiments, the method further comprises:

[0109] (1) when it is detected that the simulation processor does not enter the interrupt verification program in the process of responding to the interrupt request, checking through a monitor whether the interrupt signal to be tested sent to the interrupt controller and the interrupt request sent by the interrupt controller to the simulation processor comply with the global configuration information and the interrupt configuration information;

[0110] (2) If it meets the requirements, the verification is confirmed to be successful;

[0111] (3) If not, the verification is determined to be unsuccessful.

[0112] If the interrupt verification program cannot be entered, the monitor can be used to check whether the signals sent by the driver to the CLIC interrupt controller and by the CLIC interrupt controller to the simulation processor are as expected, and a PASS or FAIL message can be printed in the monitor.

[0113] As can be seen from the above, the embodiment of the present application obtains test constraints and generates global configuration information and interrupt configuration information of the interrupt signal to be tested according to the test constraints; based on the global configuration information and the interrupt configuration information, a configuration file is generated, the configuration file including a global configuration code for configuring the simulation processor and the global registers of the interrupt controller according to the global configuration information, an interrupt configuration code for configuring the interrupt register corresponding to the interrupt signal to be tested according to the interrupt configuration information, and a program configuration code for the interrupt verification program; the configuration file is sent to the simulation processor so that the simulation processor executes the configuration file to configure the global registers of the simulation processor, the global registers of the interrupt controller, the interrupt register corresponding to the interrupt signal to be tested in the interrupt controller, and the interrupt verification program; when the simulation processor When the configuration is completed, the interrupt signal to be tested that meets the interrupt configuration information is sent to the interrupt controller, so that the interrupt controller processes the interrupt signal to be tested according to the interrupt register, and sends the processed interrupt request to the simulation processor; when it is detected that the simulation processor enters the interrupt verification program in the process of responding to the interrupt request, the interrupt signal identifier and the interrupt level are obtained; when the interrupt signal identifier and the interrupt level meet the interrupt configuration information, it is determined that the verification is passed. Compared with the related art, each test requires manual software writing and repeating the entire test process, the embodiment of the present application generates a configuration file through global configuration information and interrupt configuration information generated by constraint conditions for the simulation processor to configure, and automatically verifies the interrupt signal to be tested after the configuration is completed, avoiding manual software writing and improving test efficiency.

[0114] The specific implementation of the above steps can be found in the previous embodiments and will not be repeated here.

[0115] To facilitate better implementation of the C2F interruption verification method provided in the embodiments of the present application, the embodiments of the present application also provide a device based on the above-mentioned C2F interruption verification method. The meanings of the terms herein are the same as those in the above-mentioned interruption verification method, and the specific implementation details can be referred to the description in the method embodiment.

[0116] See also Figure 7 , Figure 7 This is a schematic diagram of the structure of an interruption verification device provided in an embodiment of the present application. The interruption verification device for C2F is applied to a computer device. The interruption verification device for C2F may include a first acquisition unit 601, a generation unit 602, a first sending unit 603, a second sending unit 604, a second acquisition unit 605, and a verification unit 606.

[0117] A first acquiring unit 601 is configured to acquire test constraints and generate global configuration information and interrupt configuration information of an interrupt signal to be tested according to the test constraints;

[0118] A generating unit 602 is configured to generate a configuration file based on the global configuration information and the interrupt configuration information, the configuration file including a global configuration code for configuring the global registers of the simulation processor and the interrupt controller according to the global configuration information, an interrupt configuration code for configuring the interrupt register corresponding to the interrupt signal to be tested according to the interrupt configuration information, and a program configuration code for an interrupt verification program;

[0119] A first sending unit 603 is configured to send the configuration file to the simulation processor, so that the simulation processor executes the configuration file to configure the global register of the simulation processor, the global register of the interrupt controller, the interrupt register corresponding to the interrupt signal to be tested in the interrupt controller, and the interrupt verification program;

[0120] A second sending unit 604 is configured to send a test interrupt signal that matches the interrupt configuration information to the interrupt controller when the simulation processor is configured, so that the interrupt controller processes the test interrupt signal according to the interrupt register and sends the processed interrupt request to the simulation processor;

[0121] The second acquiring unit 605 is configured to acquire an interrupt signal identifier and an interrupt level when detecting that the simulation processor enters an interrupt verification program in the process of responding to the interrupt request;

[0122] The verification unit 606 is configured to determine that the verification is successful when the interrupt signal identifier and the interrupt level match the interrupt configuration information.

[0123] In some embodiments, the generating unit 602 includes:

[0124] A first acquisition subunit is configured to acquire a first interrupt privilege mode, a parent interrupt control mode, and a child interrupt control mode required for the current test from the global configuration information and the interrupt configuration information;

[0125] A second obtaining subunit is used to obtain a second interrupt privilege mode currently run by the simulation processor;

[0126] a first determining subunit, configured to determine a target interrupt verification mode of the interrupt signal to be tested based on the first interrupt privilege mode, the parent interrupt control mode, the child interrupt control mode, and the second interrupt privilege mode;

[0127] A second determining subunit is configured to determine a target code template corresponding to the interruption verification program based on a mapping relationship between the interruption verification mode and the code template of the interruption verification program;

[0128] a third acquiring subunit, configured to acquire the to-be-replaced content included in the target code template, and a content type corresponding to each of the to-be-replaced content;

[0129] a replacement subunit, configured to obtain replacement content corresponding to each content type from the interruption configuration information, and replace the replacement content with the corresponding content type in the target code template to obtain a program configuration code for the interruption verification program;

[0130] a fourth acquiring subunit, configured to acquire a first register configuration content of the emulation processor and a second register configuration content of the interrupt controller from the global configuration information;

[0131] a first generating subunit, configured to generate a global configuration code according to the first register configuration content and the second register configuration content;

[0132] a fifth acquiring subunit, configured to acquire, from the interrupt configuration information, a third register configuration content of the interrupt register corresponding to the interrupt signal to be measured in the interrupt controller;

[0133] A second generating subunit, configured to generate an interrupt configuration code according to the configuration content of the third register;

[0134] The combining subunit is used to combine the program configuration code, the global configuration code and the interrupt configuration code to obtain a configuration file.

[0135] In some embodiments, the first determining subunit is configured to:

[0136] comparing the first interrupt privilege mode with the second interrupt privilege mode to obtain a comparison result;

[0137] When the comparison result indicates that the first interrupt privilege mode is greater than the second interrupt privilege mode, determining that the interrupt signal to be tested is processed as a vertical interrupt;

[0138] When the parent interrupt control mode is the CLINT mode and the child interrupt control mode is the Direct mode, determining the interrupt verification mode of the Direct mode as the target interrupt verification mode of the interrupt signal to be tested;

[0139] When the parent interrupt control mode is the CLINT mode and the child interrupt control mode is not the Direct mode, the interrupt verification mode of the vector mode is determined as the target interrupt verification mode of the interrupt signal to be tested.

[0140] In some embodiments, the first determining subunit is further configured to:

[0141] When the parent interrupt control mode is the CLIC mode and the child interrupt control mode is the hardware vector mode, determining the interrupt verification mode of the vector mode as the target interrupt verification mode of the interrupt signal to be tested;

[0142] When the parent interrupt control mode is the CLIC mode and the child interrupt control mode is not the hardware vector mode, the interrupt verification mode of the non-vector mode is determined as the target interrupt verification mode of the interrupt signal to be tested.

[0143] In some embodiments, the first determining subunit is further configured to:

[0144] When the comparison result indicates that the first interrupt privilege mode is equal to the second interrupt privilege mode, determining that the interrupt signal to be tested is processed as a horizontal interrupt;

[0145] When the parent interrupt control mode is the CLINT mode and the child interrupt control mode is the Direct mode, determining the interrupt verification mode of the Direct mode as the target interrupt verification mode of the interrupt signal to be tested;

[0146] When the parent interrupt control mode is the CLINT mode and the child interrupt control mode is not the Direct mode, the interrupt verification mode of the vector mode is determined as the target interrupt verification mode of the interrupt signal to be tested.

[0147] In some embodiments, the first determining subunit is further configured to:

[0148] When the parent interrupt control mode is the CLIC mode, obtaining a global enable state from the global configuration information, and obtaining an interrupt enable state of the interrupt signal to be tested from the interrupt configuration information;

[0149] When the global enable state and the interrupt enable state are enabled, obtaining a priority threshold from the global configuration information, and obtaining an interrupt priority of the interrupt signal to be tested from the interrupt configuration information;

[0150] determining a target priority that is the highest of the priority threshold and the current priority of the emulated processor;

[0151] When the interrupt priority is higher than the target priority and the sub-interrupt control mode is a hardware vector mode, the interrupt verification mode of the vector mode is determined as the target interrupt verification mode of the interrupt signal to be tested.

[0152] In some embodiments, the first determining subunit is further configured to:

[0153] When the interrupt priority is higher than the target priority and the sub-interrupt control mode is not the hardware vector mode, the interrupt verification mode of the non-vector mode is determined as the target interrupt verification mode of the interrupt signal to be tested.

[0154] The specific implementation of each of the above units can be found in the previous embodiments and will not be described again here.

[0155] As can be seen from the above, the embodiment of the present application obtains the test constraint conditions through the first acquisition unit 601, and generates global configuration information and interrupt configuration information of the interrupt signal to be tested according to the test constraint conditions; the generation unit 602 generates a configuration file based on the global configuration information and the interrupt configuration information, and the configuration file includes a global configuration code for configuring the simulation processor and the global registers of the interrupt controller according to the global configuration information, an interrupt configuration code for configuring the interrupt register corresponding to the interrupt signal to be tested according to the interrupt configuration information, and a program configuration code for the interrupt verification program; the first sending unit 603 sends the configuration file to the simulation processor so that the simulation processor executes the configuration file to configure the global registers of the simulation processor, the interrupt configuration code The global register of the interrupt controller, the interrupt register corresponding to the interrupt signal to be tested in the interrupt controller, and the interrupt verification program are configured; the second sending unit 604 sends the interrupt signal to be tested that meets the interrupt configuration information to the interrupt controller when the simulation processor is configured, so that the interrupt controller processes the interrupt signal to be tested according to the interrupt register, and sends the processed interrupt request to the simulation processor; the second acquisition unit 605 acquires the interrupt signal identifier and the interrupt level when it detects that the simulation processor enters the interrupt verification program in the process of responding to the interrupt request; the verification unit 606 determines that the verification is passed when the interrupt signal identifier and the interrupt level meet the interrupt configuration information. Compared with the related art, each test requires manual software writing and repeating the entire test process, the embodiment of the present application generates a configuration file through global configuration information and interrupt configuration information generated by constraint conditions for the simulation processor to configure, and automatically verifies the interrupt signal to be tested after the configuration is completed, avoiding manual software writing and improving test efficiency.

[0156] The specific implementation of each of the above units can be found in the previous embodiments and will not be described again here.

[0157] Reference Figure 8 , Figure 8This is a block diagram of the structure of a portion of a computer device 1000 for implementing an embodiment of the present disclosure. The computer device 1000 may vary greatly due to different configurations or performance, and may include one or more central processing units (CPUs) 622 (for example, one or more processors) and memories 632, and one or more storage media 630 (for example, one or more mass storage devices) for storing application programs 642 or data 644. The memories 632 and storage media 630 may be temporary storage or permanent storage. The program stored in the storage medium 630 may include one or more modules (not shown in the figure), each module may include a series of instruction operations on the server 600. Furthermore, the central processing unit 622 may be configured to communicate with the storage medium 630 to execute a series of instruction operations in the storage medium 630 on the server 600.

[0158] The computer device 1000 may also include one or more power supplies 626, one or more wired or wireless network interfaces 650, one or more input and output interfaces 658, and / or one or more operating systems 641, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0159] The central processing unit 622 in the computer device 1000 may be used to execute the interrupt verification method of the embodiment of the present disclosure, for example:

[0160] Acquire test constraints, and generate global configuration information and interrupt configuration information of the interrupt signal to be tested according to the test constraints;

[0161] Generate a configuration file based on the global configuration information and the interrupt configuration information, the configuration file including a global configuration code for configuring the simulation processor and the global registers of the interrupt controller according to the global configuration information, an interrupt configuration code for configuring the interrupt register corresponding to the interrupt signal to be tested according to the interrupt configuration information, and a program configuration code for an interrupt verification program;

[0162] Sending the configuration file to the simulation processor so that the simulation processor executes the configuration file to configure a global register of the simulation processor, a global register of the interrupt controller, an interrupt register corresponding to the interrupt signal to be tested in the interrupt controller, and an interrupt verification program;

[0163] When the simulation processor is configured, the interrupt signal to be tested that conforms to the interrupt configuration information is sent to the interrupt controller, so that the interrupt controller processes the interrupt signal to be tested according to the interrupt register and sends the interrupt request obtained by the processing to the simulation processor;

[0164] When detecting that the simulation processor enters an interrupt verification program in the process of responding to the interrupt request, obtaining an interrupt signal identifier and an interrupt level;

[0165] When the interrupt signal identifier and the interrupt level conform to the interrupt configuration information, it is determined that the verification is passed.

[0166] The embodiments of the present disclosure further provide a computer-readable storage medium, which is used to store program codes, and the program codes are used to execute the interruption verification methods of the aforementioned embodiments.

[0167] The present disclosure also provides a computer program product, which includes a computer program. The processor of a computer device reads and executes the computer program, so that the computer device executes the above-mentioned interrupt verification method. For example:

[0168] Acquire test constraints, and generate global configuration information and interrupt configuration information of the interrupt signal to be tested according to the test constraints;

[0169] Generate a configuration file based on the global configuration information and the interrupt configuration information, the configuration file including a global configuration code for configuring the simulation processor and the global registers of the interrupt controller according to the global configuration information, an interrupt configuration code for configuring the interrupt register corresponding to the interrupt signal to be tested according to the interrupt configuration information, and a program configuration code for an interrupt verification program;

[0170] Sending the configuration file to the simulation processor so that the simulation processor executes the configuration file to configure a global register of the simulation processor, a global register of the interrupt controller, an interrupt register corresponding to the interrupt signal to be tested in the interrupt controller, and an interrupt verification program;

[0171] When the simulation processor is configured, the interrupt signal to be tested that conforms to the interrupt configuration information is sent to the interrupt controller, so that the interrupt controller processes the interrupt signal to be tested according to the interrupt register and sends the interrupt request obtained by the processing to the simulation processor;

[0172] When detecting that the simulation processor enters an interrupt verification program in the process of responding to the interrupt request, obtaining an interrupt signal identifier and an interrupt level;

[0173] When the interrupt signal identifier and the interrupt level conform to the interrupt configuration information, it is determined that the verification is passed.

[0174] In addition, the terms "comprises" and "comprising" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or apparatus that comprises a series of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, product or apparatus.

[0175] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0176] It should be understood that in the description of the embodiments of the present application, the meaning of multiple (or multiple items) is more than two, greater than, less than, exceed, etc. are understood to exclude the number itself, and above, below, within, etc. are understood to include the number itself.

[0177] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0178] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0179] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0180] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0181] It should also be understood that the various implementation methods provided in the embodiments of the present application can be combined arbitrarily to achieve different technical effects.

[0182] In the embodiments of the present application, the term "module" or "unit" refers to a computer program or portion of a computer program that has a predetermined function and works together with other related parts to achieve a predetermined goal. It can be implemented in whole or in part using software, hardware (such as processing circuits or memory), or a combination thereof. Similarly, a processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be part of an overall module or unit that includes the functionality of the module or unit.

[0183] The above is a specific description of the implementation methods of the present application, but the present application is not limited to the above implementation methods. Technical personnel familiar with the art can also make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A method for verifying an interruption of C2F, characterized in that: include: Acquire test constraints, and generate global configuration information and interrupt configuration information of the interrupt signal to be tested according to the test constraints; Acquire a first interrupt privilege mode, a parent interrupt control mode, and a child interrupt control mode required for the current test from the global configuration information and the interrupt configuration information; Get the second interrupt privilege mode currently run by the simulation processor; Determining a target interrupt verification mode for the interrupt signal to be tested based on the first interrupt privilege mode, the parent interrupt control mode, the child interrupt control mode, and the second interrupt privilege mode; Determining a target code template corresponding to the interruption verification program based on a mapping relationship between the interruption verification mode and the code template of the interruption verification program; Acquire the to-be-replaced content included in the target code template, and the content type corresponding to each to-be-replaced content; Acquire replacement content corresponding to each content type from the interruption configuration information, and replace the replacement content with the corresponding content type in the target code template to obtain a program configuration code for the interruption verification program; Acquire a first register configuration content of the emulation processor and a second register configuration content of the interrupt controller from the global configuration information; Generate a global configuration code according to the first register configuration content and the second register configuration content; Acquire a third register configuration content of an interrupt register corresponding to the interrupt signal to be measured in the interrupt controller from the interrupt configuration information; generating an interrupt configuration code according to the configuration content of the third register; Combining the program configuration code, the global configuration code, and the interrupt configuration code to obtain a configuration file, the configuration file including a global configuration code for configuring the simulation processor and the global registers of the interrupt controller according to the global configuration information, an interrupt configuration code for configuring the interrupt register corresponding to the interrupt signal to be tested according to the interrupt configuration information, and a program configuration code for an interrupt verification program; Sending the configuration file to the simulation processor so that the simulation processor executes the configuration file to configure a global register of the simulation processor, a global register of the interrupt controller, an interrupt register corresponding to the interrupt signal to be tested in the interrupt controller, and an interrupt verification program; When the simulation processor is configured, the interrupt signal to be tested that matches the interrupt configuration information is sent to the interrupt controller, so that the interrupt controller processes the interrupt signal to be tested according to the interrupt register and sends the interrupt request obtained by the processing to the simulation processor; When detecting that the simulation processor enters an interrupt verification program in the process of responding to the interrupt request, obtaining an interrupt signal identifier and an interrupt level; When the interrupt signal identifier and the interrupt level conform to the interrupt configuration information, it is determined that the verification is passed.

2. The C2F interrupt verification method according to claim 1, characterized in that: The determining, based on the first interrupt privilege mode, the parent interrupt control mode, the child interrupt control mode, and the second interrupt privilege mode, of a target interrupt verification mode for the interrupt signal to be tested includes: comparing the first interrupt privilege mode with the second interrupt privilege mode to obtain a comparison result; When the comparison result indicates that the first interrupt privilege mode is greater than the second interrupt privilege mode, determining that the interrupt signal to be tested is processed as a vertical interrupt; When the parent interrupt control mode is the CLINT mode and the child interrupt control mode is the Direct mode, determining the interrupt verification mode of the Direct mode as the target interrupt verification mode of the interrupt signal to be tested; When the parent interrupt control mode is the CLINT mode and the child interrupt control mode is not the Direct mode, the interrupt verification mode of the vector mode is determined as the target interrupt verification mode of the interrupt signal to be tested.

3. The C2F interrupt verification method according to claim 2, characterized in that: The method further comprises: When the parent interrupt control mode is the CLIC mode and the child interrupt control mode is the hardware vector mode, determining the interrupt verification mode of the vector mode as the target interrupt verification mode of the interrupt signal to be tested; When the parent interrupt control mode is the CLIC mode and the child interrupt control mode is not the hardware vector mode, the interrupt verification mode of the non-vector mode is determined as the target interrupt verification mode of the interrupt signal to be tested.

4. The C2F interrupt verification method according to claim 2, wherein: The method further comprises: When the comparison result indicates that the first interrupt privilege mode is equal to the second interrupt privilege mode, determining that the interrupt signal to be tested is processed as a horizontal interrupt; When the parent interrupt control mode is the CLINT mode and the child interrupt control mode is the Direct mode, determining the interrupt verification mode of the Direct mode as the target interrupt verification mode of the interrupt signal to be tested; When the parent interrupt control mode is the CLINT mode and the child interrupt control mode is not the Direct mode, the interrupt verification mode of the vector mode is determined as the target interrupt verification mode of the interrupt signal to be tested.

5. The C2F interrupt verification method according to claim 4, characterized in that: The method further comprises: When the parent interrupt control mode is the CLIC mode, obtaining a global enable state from the global configuration information, and obtaining an interrupt enable state of the interrupt signal to be tested from the interrupt configuration information; When the global enable state and the interrupt enable state are enabled, obtaining a priority threshold from the global configuration information, and obtaining an interrupt priority of the interrupt signal to be tested from the interrupt configuration information; determining a target priority that is the highest of the priority threshold and the current priority of the emulated processor; When the interrupt priority is higher than the target priority and the sub-interrupt control mode is a hardware vector mode, the interrupt verification mode of the vector mode is determined as the target interrupt verification mode of the interrupt signal to be tested.

6. The C2F interrupt verification method according to claim 5, characterized in that: The method further comprises: When the interrupt priority is higher than the target priority and the sub-interrupt control mode is not the hardware vector mode, the interrupt verification mode of the non-vector mode is determined as the target interrupt verification mode of the interrupt signal to be tested.

7. A C2F interrupt verification device, characterized in that: include: a first acquiring unit, configured to acquire test constraints, and generate global configuration information and interrupt configuration information of the interrupt signal to be tested according to the test constraints; Generate unit, including: A first acquisition subunit is configured to acquire a first interrupt privilege mode, a parent interrupt control mode, and a child interrupt control mode required for the current test from the global configuration information and the interrupt configuration information; A second obtaining subunit is used to obtain a second interrupt privilege mode currently run by the simulation processor; a first determining subunit, configured to determine a target interrupt verification mode of the interrupt signal to be tested based on the first interrupt privilege mode, the parent interrupt control mode, the child interrupt control mode, and the second interrupt privilege mode; A second determining subunit is configured to determine a target code template corresponding to the interruption verification program based on a mapping relationship between the interruption verification mode and the code template of the interruption verification program; a third acquiring subunit, configured to acquire the to-be-replaced content included in the target code template, and a content type corresponding to each of the to-be-replaced content; a replacement subunit, configured to obtain replacement content corresponding to each content type from the interruption configuration information, and replace the replacement content with the corresponding content type in the target code template to obtain a program configuration code for the interruption verification program; a fourth acquiring subunit, configured to acquire a first register configuration content of the emulation processor and a second register configuration content of the interrupt controller from the global configuration information; a first generating subunit, configured to generate a global configuration code according to the first register configuration content and the second register configuration content; a fifth acquiring subunit, configured to acquire, from the interrupt configuration information, a third register configuration content of the interrupt register corresponding to the interrupt signal to be measured in the interrupt controller; A second generating subunit, configured to generate an interrupt configuration code according to the configuration content of the third register; a combining subunit, configured to combine the program configuration code, the global configuration code, and the interrupt configuration code to obtain a configuration file, the configuration file including a global configuration code for configuring the simulation processor and the global registers of the interrupt controller according to the global configuration information, an interrupt configuration code for configuring the interrupt register corresponding to the interrupt signal to be tested according to the interrupt configuration information, and a program configuration code for an interrupt verification program; a first sending unit, configured to send the configuration file to the simulation processor, so that the simulation processor executes the configuration file to configure a global register of the simulation processor, a global register of the interrupt controller, an interrupt register corresponding to the interrupt signal to be tested in the interrupt controller, and an interrupt verification program; a second sending unit, configured to send a test interrupt signal that conforms to the interrupt configuration information to the interrupt controller when the simulation processor is configured, so that the interrupt controller processes the test interrupt signal according to the interrupt register and sends an interrupt request obtained by the processing to the simulation processor; A second acquiring unit is configured to acquire an interrupt signal identifier and an interrupt level when detecting that the simulation processor enters an interrupt verification program in the process of responding to the interrupt request; The verification unit is configured to determine that the verification is passed when the interrupt signal identifier and the interrupt level conform to the interrupt configuration information.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a plurality of instructions, and the instructions are suitable for being loaded by a processor to execute the interruption verification method for C2F according to any one of claims 1 to 6.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the interruption verification method for C2F according to any one of claims 1 to 6 is implemented.

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