Multi-target comprehensive layout and wiring quality prediction method
Through the multi-objective comprehensive layout and routing quality prediction method, using the WCPNet model combined with feature extraction, the problems of line length, congestion and power consumption optimization in FPGA design are solved, and more efficient layout and routing quality is achieved.
Patent Information
- Application Number
- CN202311781866.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-22
- Publication Date
- 2025-06-24
AI Technical Summary
The prior art is difficult to optimize line length, congestion and power consumption at the same time during the layout stage of FPGA design, resulting in poor layout results and affecting subsequent wiring processes.
A multi-objective comprehensive layout and routing quality prediction method is adopted, and the deep neural network model WCPNet is combined with Place&Connections and PinUtilization features to jointly predict line length, congestion and power consumption.
It improves the layout and wiring quality during FPGA chip design, reduces the number of iterations between layout and wiring, and improves the design speed and quality.
Smart Images
Figure CN120197583A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of digital integrated circuit electronic design automation (EDA), and particularly to a method for predicting the layout and routing quality of multi-objective synthesis. Background Art
[0002] Field Programmable Gate Arrays (FPGAs) with reprogrammable and reconfigurable capabilities have attracted increasing attention in the industrial and academic communities and are widely adopted in various application fields in the era of Moore's Law, such as communication, image processing, digital signal processing, and control systems. With the continuous increase in the size of FPGA chips and the complexity of designs on the chip, the design process of FPGA circuits has become increasingly standardized and complex. The general design process usually includes system design, physical design, and customization, and the physical design can be further divided into technology mapping, placement, and routing. Given a netlist with logic elements (gates or flip-flops), the placer assigns all placeable components to legal positions on the FPGA chip to optimize specific design goals. Subsequently, the router determines the interconnections between different logic elements to achieve certain optimal design goals. Among the optimization goals, the bus length is the most fundamental quantity considered first because a smaller bus length can bring better signal integrity, lower power consumption, and lower latency. In addition, due to the limited routing resources of FPGAs and the increasing design complexity, reducing congestion is another necessary goal. Finally, power consumption is also one of the important design metrics that need to be considered.
[0003] Placement and routing are widely regarded as one of the most time-consuming stages because of the iterative relationship between them. In the placement stage, components are usually placed randomly or based on simple heuristic algorithms, which often result in congestion, sub-optimal routing wire lengths, and higher power consumption. Subsequently, routing is performed to determine the connections between components, identify areas prone to congestion and power consumption for further optimization. With the feedback of routing and power consumption information, the placement step is continuously improved by considering the estimated wire length, congestion, and power consumption information. Then, based on the updated placement results, the routing step is also optimized. The iterative improvement process between placement and routing will continue until a good trade-off is achieved among wire length, congestion, and power consumption in the placement result. Since the routing resources of FPGAs are predetermined and have limited capacity, placement results that require a large amount of routing resources will significantly affect the subsequent routing process, usually resulting in failure or a longer time to achieve a viable routing solution. Therefore, a good placement result is crucial for the FPGA design process.
[0004] To achieve better layout results, most existing works have introduced supervised machine learning (ML) techniques for predicting the quality of results (QoR) during the layout phase, where the prediction model aims to provide information about potential challenges and constraints that may arise during the subsequent routing phase. With the prediction results, anticipatory solutions can be effectively provided to reduce the iterations between layout and routing, further accelerating the design loop and improving QoR. Martin and his colleagues have explored linear regression and gradient boosting regression to establish the correlation between layout solutions and the final routed wire length. Congestion prediction is usually formulated as a computer vision task and uses generative models to learn the correlation, as layout information can be naturally represented by image-like data, where components, routing channels, and other structural elements are visually arranged on a grid. In addition to the research on wire length and congestion prediction, there are also studies focusing on predicting power consumption during the layout phase, such as the work of Vorwerk and his colleagues. Although prediction models have shown excellent performance in accelerating design speed and improving design quality, there are still two major challenges:
[0005] 1) The objectives to be optimized during the layout phase are usually a combination of multiple factors such as minimizing wire length, reducing congestion, and optimizing power consumption. An optimal layout result should strike a balance among these objectives. For example, reducing wire length may require clustering related components together, but this may lead to increased congestion. Similarly, merging high-power components may contribute to power consumption optimization but may result in longer wire lengths. All three factors need to be considered simultaneously, so various layout strategies need to be explored to find the best compromise. Therefore, compared with models that predict these metrics individually, machine learning models that can jointly predict wire length, congestion, and power consumption are more realistic, accurate, and effective. 2) Most existing methods adopt single-task learning (STL) models, which can only predict a specific design objective, such as wire length, congestion, or power consumption. These STL methods allow for simpler modeling and training because each metric can be processed independently. Although STL models are simpler, they cannot capture the complex trade-offs and interdependencies between different design objectives. Therefore, the results predicted by STL models may deviate from the actual results, which may further lead to suboptimal or non-optimal decision-making.
[0006] FPGA design is a multi-objective optimization process that involves finding the best design results for various resources under multiple conflicting objectives to achieve the best performance. Therefore, the drawback of using STL models is that they do not explicitly capture the potential correlations or dependencies between different metrics. By processing each metric independently, these models may overlook important interactions or trade-offs between metrics during the layout phase. Summary of the Invention
[0007] The object of the present invention is to provide a method for predicting the layout and routing quality with multi-objective integration, which is used to jointly predict wire length, congestion and power consumption during the layout stage, and further improve the layout and routing quality in the design of FPGA chips.
[0008] To achieve the above task, the present invention adopts the following technical solutions:
[0009] A method for predicting the layout and routing quality with multi-objective integration, comprising:
[0010] Perform layout on different designs, and extract and generate input features of each layout scheme after the layout is completed, including Place&Connections features and PinUtilization features. Among them, the Place&Connections features are obtained by adding the corresponding pixel values of the layout graph and the connection graph. The layout graph is used to describe the layout of logic resource blocks in the layout scheme, and the connection graph is used to describe the interconnection relationship of logic resource blocks after the layout is completed; the PinUtilization feature is used to describe the pin utilization rate of logic resource blocks.
[0011] Perform routing on different designs, and extract the corresponding label information after routing, where the label information includes the wire length, congestion, and power consumption of each design.
[0012] Use the input features of the layout scheme and the corresponding label information as samples to construct a training set.
[0013] Train the quality prediction model with the samples in the training set, and save the trained quality prediction model for predicting congestion, wire length, and power consumption of the design after layout is completed.
[0014] Furthermore, the PinUtilization feature is an image pin utilization rate graph.
[0015] For each logic resource block after the layout stage, its pin utilization rate is represented by r utilization , and can be calculated as follows:
[0016]
[0017] Among them, P utilized and P total respectively represent the number of used pins and the total number of pins. Subsequently, each logic resource block will be mapped to a corresponding color according to the pin utilization rate, so as to obtain the image pin utilization rate graph.
[0018] Furthermore, the quality prediction model is a deep neural network, including an encoder and a decoder, where:
[0019] The encoder includes three convolutional units and two max - pooling layers. The input of the first convolutional unit is the input features of the samples in the dataset. The first convolutional unit includes two convolutional layers, and after each convolutional layer, there is an InstanceNorm2d normalization layer and a LeakyReLU activation function connected; the structure of the second convolutional layer is the same as that of the first convolutional layer; the two max - pooling layers are located after the first convolutional unit and the second convolutional unit respectively; the third convolutional unit includes a convolutional layer, and after the convolutional layer, there are a batch normalization layer and a hyperbolic tangent activation function.
[0020] Furthermore, the decoder has three parallel network structures;
[0021] The first network structure is used to process the congestion prediction task, and includes a first convolutional unit, a first transposed convolutional unit, a second convolutional unit, a second transposed convolutional unit, and a third convolutional unit arranged in sequence; the first convolutional unit and the second convolutional unit have the same structure, including two convolutional layers, and after each convolutional layer, there is an InstanceNorm2d normalization layer and a LeakyReLU activation function connected; the third convolutional unit includes a convolutional layer; the first transposed convolutional unit and the second transposed convolutional unit have the same structure, including a deconvolution layer, and after the deconvolution layer, there are a LeakyReLU activation function and an InstanceNorm2d normalization layer connected;
[0022] The second network structure and the third network structure are the same, and are respectively used for the wire length or power consumption prediction tasks;
[0023] The second network structure is first a convolutional unit, which includes two convolutional layers, and after each convolutional layer, there is an InstanceNorm2d normalization layer and a LeakyReLU activation function connected; after the convolutional unit, there is an adaptive average pooling function layer, and after the adaptive average pooling function layer, there is a flattening layer connected; finally, there are 4 fully - connected layers connected, and the output of the last neuron of the fully - connected layer is used as the output of the second network structure.
[0024] Furthermore, the input of the second transposed convolutional unit of the decoder is the result of adding the feature map output by the first convolutional unit of the encoder and the feature map output by the second convolutional unit of the decoder, so as to fuse features of different scales together.
[0025] Furthermore, the total loss function \(L\) total (\(\theta\) total ) is expressed as:
[0026]
[0027] where \(\theta\) total represents the total parameters to be trained of the quality prediction model, and \(L\)w (θ w )、L p (θ p )、L c (θ c ) are the loss functions of wire length, power consumption, and congestion respectively. At the same time, θ w , θ p , θ c are parameters that can be trained.
[0028] Further, the loss function L w (θ w ) of wire length is expressed as:
[0029]
[0030] Among them, n1 represents the wire length label in the dataset, represents the true label value, j is the j-th sample, represents the predicted wire length value;
[0031] The loss function L p (θ p ) of power consumption is expressed as:
[0032]
[0033] Among them, n2 represents the power consumption label in the dataset, represents the actual power consumption value, j is the j-th sample, represents the predicted power consumption value;
[0034] The loss function L c (θ c ) of congestion is expressed as:
[0035]
[0036] Among them, n pixel represents the number of pixels in the congestion hot spot map for the congestion prediction task, n3 represents the congestion label in the dataset, represents the actual congestion value of the k-th pixel in the j-th sample, represents the predicted congestion value of the k-th pixel in the j-th sample.
[0037] A terminal device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the method for predicting the layout and routing quality of multi-objective integration.
[0038] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps of the method for predicting the layout and routing quality of multi-objective synthesis.
[0039] Compared with the prior art, the present invention has the following technical features:
[0040] 1. The present invention formulates a multi-task learning problem, which can simultaneously predict multiple design metrics, such as pixel-level congestion, image-level wire length, and image-level power consumption.
[0041] 2. The present invention proposes a supervised multi-task learning model called WCPNet to solve the above multi-task learning problem. Experimental results show that WCPNet can not only jointly predict these three metrics, but also outperform the STL model in terms of prediction accuracy and training speed.
[0042] 3. The present invention introduces a novel feature called PinUtilization to characterize the pin utilization information of the logic resource blocks in the layout solution. This feature captures the relationship between pin utilization and power consumption estimation, and can improve prediction accuracy. Experimental results show that this feature improves the prediction performance of the WCPNet of the present solution. Description of the Drawings
[0043] Figure 1 It is a construction flow chart of WCPNet;
[0044] Figure 2 It is a schematic diagram of features extracted based on the layout result, where (a) is the PinUtilization feature and (b) is the Place&Connections feature;
[0045] Figure 3 It is a network architecture diagram of WCPNet;
[0046] Figure 4 It is a training loss diagram of the WCPNet network and the single-task network;
[0047] Figure 5 It is an inference result diagram of the WCPNet congestion prediction task. Detailed Embodiments
[0048] Multi-Task Learning (MTL) is a machine learning technique in which a model is trained to simultaneously perform multiple related tasks and uses shared representations and parameters in some parts. MTL models can utilize the relationships between tasks to improve the generalization and performance of all tasks. Therefore, using an MTL model is an effective way to solve the limitations of the STL model.
[0049] This solution proposes an MTL model for jointly predicting wirelength, congestion, and power consumption during the layout phase; the model of this solution is designed to have strong generalization ability, enabling it to make accurate predictions on designs that do not exist in the training dataset. To the best knowledge of this solution, this is the first work to use a supervised MTL model to simultaneously predict multiple design metrics of FPGAs.
[0050] The supervised multi-task learning model proposed in this invention is called the Wirelength-Congestion-Power-Network (WCPNet), and its overall system process is as Figure 1 shown, including the feature extraction and ground truth label generation phases in dataset construction and the model construction phase.
[0051] 1. Feature Extraction
[0052] This solution will define the inputs for training and inference, mainly including two parts:
[0053] Images of Place&Connections and images of PinUtilization. The former is an improved version of the features proposed in existing literature, while the latter is a novel feature proposed in this solution.
[0054] 1.1 Place&Connections
[0055] Yu and Zhang proposed two feature images called the layout graph (image_place) and the connection graph (image_connect) respectively, which are used to describe the layout of logic resource blocks and their interconnection relationships after the layout phase. Based on their work, this solution defines a post-layout feature image called Place&Connections, which is obtained by adding the corresponding pixel values of image_place and image_connect. As Figure 2 (a) shows, the utilized logic resource blocks are represented by dark pixels, and their interconnections are represented by black flying wires, so as to capture the number of utilized logic resource blocks, layout positions, and their topological connection information. This feature plays a key role in the prediction accuracy of the MTL model of this solution.
[0056] Among them, image_place and image_connect are recorded in the literature Cunxi Yu and Zhiru Zhang. 2019. Painting on Placement: Forecasting Routing Congestion Using Conditional Generative Adversarial Nets. In Proceedings of the 56th Annual Design Automation Conference 2019 (DAC’19). Association for Computing Machinery.
[0057] In the dataset construction stage, this feature can be extracted and generated through the graph module of the FPGA open-source software VTR 8.0. The specific steps are to first layout a certain design, and by controlling the graph module of VTR, overlay the layout graph and the connection graph to form a layout connection graph and save the picture, which is used as one of the layout features of this design. In the subsequent process, this feature is one of the input features when training the model.
[0058] 1.2 Pin Utilization
[0059] In FPGA designs, higher resource utilization within a logic resource block usually leads to higher power consumption. In addition, the resource utilization within a logic resource block is closely related to its pin utilization. Pin utilization provides valuable information about the actual routing requirements in the area around the block. In short, the pin utilization of a logic resource block can play an important role in predicting power consumption and wire length.
[0060] Therefore, after the placement stage, a novel feature image, the Pin Utilization map, which is used to describe the pin utilization of logic resource blocks, is proposed. Its image is as shown in Figure 2 (b). For each logic resource block after the placement stage, its pin utilization is represented by r utilization , and can be calculated as follows:
[0061]
[0062] Among them, P utilized and P total represent the number of used pins and the total number of pins respectively. Subsequently, each logic block will be mapped to a corresponding color according to the pin utilization according to the color scheme Plasma.
[0063] In the dataset construction stage, this feature can also be extracted and generated through the graph module of the FPGA open-source software VTR8.0. The specific steps are to first perform placement and routing on a certain design, and by controlling the graph module of VTR, a graph of the utilization rate of logic resource blocks is formed, which is used as one of the placement features of this design. In the subsequent process, this feature is one of the input features when training the model.
[0064] 2. True label generation
[0065] In the dataset construction stage, the true labels in the dataset can also use the VTR software to obtain the true values of wire length and congestion after routing, while the true value of power consumption can be obtained in the analysis stage after routing. For each placement, the true value of wire length or power consumption is a scalar, while the true value of congestion is a hot spot map.
[0066] 3. Construction of the quality prediction model WCPNet
[0067] The fully convolutional network (FCN) has advantages in pixel-level prediction tasks such as congestion prediction, while the convolutional neural network (CNN) performs well in image-level prediction tasks such as wire length or power consumption prediction. By integrating their advantages, this solution proposes a new multi-task learning (MTL) model called WCPNet, which can perform pixel-level and image-level predictions simultaneously.
[0068] As Figure 3 shown, WCPNet is a deep neural network with one input and three outputs, and each output is related to congestion, wire length, and power consumption respectively. The model has three main components: an encoder, a decoder, and a parameter optimization strategy.
[0069] 3.1 Encoder
[0070] In WCPNet, the encoder includes three convolutional units and two max pooling layers, where:
[0071] The input of the first convolutional unit is the input feature of the samples in the dataset. The first convolutional unit includes two 3*3 convolutional layers, and each convolutional layer is connected with an InstanceNorm2d normalization layer and a LeakyReLU activation function; the structure of the second convolutional layer is the same as that of the first convolutional layer.
[0072] The two max pooling layers are located after the first convolutional unit and the second convolutional unit respectively. The convolutional layers in the convolutional unit extract local features from the image, while the max pooling layer enhances the abstraction of the features by downsampling the feature map.
[0073] The third convolutional unit includes a 3×3 convolutional layer, followed by a batch normalization layer and a hyperbolic tangent activation function to accelerate network convergence, improve gradient flow, and reduce sensitivity to weight and bias initialization. The encoder parameters are shared among the three tasks.
[0074] 3.2 Decoder
[0075] In WCPNet, the decoder has three parallel network structures, each for processing one task.
[0076] The first network structure is for processing the congestion prediction task and includes a first convolutional unit, a first transposed convolutional unit, a second convolutional unit, a second transposed convolutional unit, and a third convolutional unit arranged in sequence. Among them, the first convolutional unit and the second convolutional unit have the same structure, including two 3×3 convolutional layers, and each convolutional layer is connected to an InstanceNorm2d normalization layer and a LeakyReLU activation function; the third convolutional unit includes a 3×3 convolutional layer; the first transposed convolutional unit and the second transposed convolutional unit have the same structure, including a 4×4 deconvolutional layer, and a LeakyReLU activation function and an InstanceNorm2d normalization layer are connected after the deconvolutional layer; among them, the first convolutional unit of the encoder is skip-connected to the second transposed convolutional unit of the decoder, that is, the input of the second transposed convolutional unit is the result of adding the feature map output by the first convolutional unit of the encoder and the feature map output by the second convolutional unit of the decoder, so as to fuse features of different scales, and the output of this network part is the congestion hotspot map.
[0077] The second network structure and the third network structure are the same and are respectively used for the wire length or power consumption prediction tasks. This network structure first has a convolutional unit, which includes two 3×3 convolutional layers, and each convolutional layer is connected to an InstanceNorm2d normalization layer and a LeakyReLU activation function; after the convolutional unit is an AdaptiveAvgPool2d adaptive average pooling function layer, and after the AdaptiveAvgPool2d layer is connected to a flattening layer Flatten; finally, 4 fully connected layers are connected, including 800, 256, 32, and 1 neurons respectively; the output of the last neuron is used as the output of the entire network.
[0078] 3.3 Parameter Optimization
[0079] WPCNet trains a single model to perform multiple tasks simultaneously, and the loss function plays a key role in the training process. To capture the objectives and requirements of each individual task while considering joint optimization, a geometric loss strategy (GLS) is adopted. The total parameters of the WCPNet to be trained are represented as θ total, the equation of the total loss function is detailed as follows:
[0080]
[0081] Among them, L w (θ w ), L p (θ p ), L c (θ c ) are the loss functions of wire length, power consumption, and congestion respectively. At the same time, θ w , θ p , θ c are parameters that can be trained.
[0082] For wire length prediction, in formula (2), the real data is represented as a single continuous value, denoted as where j represents a certain data sample in the dataset, and n1 represents the wire length label in the dataset, represents the real label value. The loss function is defined as the mean squared error (MSE) between the predicted wire length value (denoted as ) and the actual wire length value on the ground:
[0083]
[0084] Similarly, the loss function for power consumption prediction is defined as the mean squared error (MSE) between the predicted power consumption value and the actual power consumption value on the ground :
[0085]
[0086] For congestion prediction, in formula 2, the real value is a heatmap of continuous values, denoted as which contains the congestion value of each pixel. The loss function is defined as the mean squared error (MSE) between the predicted value and the actual value on the ground of the k-th pixel in the j-th map :
[0087]
[0088] where n pixel represents the number of pixels in the congestion hotspot map for the congestion prediction task.
[0089] The relationship between different trainable parameters is described as follows:
[0090] θ total = θ w ∪ θ p ∪ θ c (6)
[0091] To minimize L total , techniques such as gradient descent or its variants can be used to optimize the trainable parameters.
[0092] The above are the output prediction values of the network respectively, while is the true label value.
[0093] Based on the above constructed model, the specific method of the present invention is as follows:
[0094] Step 1, feature extraction. Use the FPGA open-source tool VTR to perform placement on different designs, and after the placement is completed, extract and generate Place&Connections and PinUtilization features;
[0095] Step 2, generate labels. Use the FPGA open-source tool VTR to perform placement and routing on the design, and extract the corresponding label information of the design after routing, where the label information includes the wire length, congestion, and power consumption of each design.
[0096] Step 3, construct a training set. Combine the above extracted features and labels into a training set, and divide the training set and the test set according to a ratio of 8:2.
[0097] Step 4, network training. Successively use the input features (Place&Connections and PinUtilization) of each sample in the training set as the input of the encoder of the network model to train the network model. During the training process, the three parallel network structures of the decoder will respectively output the predicted congestion map, wire length, and power consumption. Subsequently, according to the gap between the predicted value and the true value, calculate the loss function, and use the Adam optimizer to update the model parameters;
[0098] Step 5, stop training when the loss function converges, and save the trained model.
[0099] Step 6, in actual application, for the design with completed placement, extract the input features according to the above steps, then input them into the trained model, and obtain the congestion map, wire length, and power consumption through model prediction.
[0100] To verify WPCNet, 85 different designs were selected from the benchmark suite provided by VTR in this solution. The resource utilization ranges of these designs are shown in Table 1. With the help of the VTR tool, 30 placement results are generated for each design using various different placement parameters (including default settings), and then each placement result is routed using the default routing parameters. Finally, the generated dataset includes 1800 samples, excluding those samples that failed to be routed successfully. At the same time, in order to evaluate the generalization ability of the method of this solution, a cross-design scheme was adopted for data splitting.
[0101] Table 1 Benchmark resource utilization range.
[0102] #LUTs #Nets #Adders #Multiply 0.1k - 5.2k 0.3k - 9k 0.1k - 1k 5-26
[0103] Specifically, the training data includes samples generated from 68 designs randomly selected from the above 85 designs, while the samples of the remaining designs are reserved for testing. This ensures that no design in the test data is seen during the training process. This scheme uses a computer equipped with an Intel Core i7-11800H CPU, 32GB of memory, and an Nvidia GTX3060 graphics card. The feature extractor and the ground truth generator are implemented in C++ based on VTR. The WCPNet and the benchmark STL model are implemented in Python based on PyTorch. The learning rate is set to 0.001, the batch size is set to 32, the training epoch is set to 500, and the Adam optimizer is adopted.
[0104] To evaluate the prediction accuracy and training speed of WCPNet, this scheme uses the prediction results of three STL models as the comparison baseline. For congestion prediction, this scheme implements the model proposed by Maarouff et al. [1] . For wire length or power consumption prediction, this scheme adopts the model consisting of a shared encoder and a task-specific decoder structure shown in Figure 3 . The WCPNet and the three STL models are trained on the training data, and then their performance is evaluated on the test data that only contains designs not seen in the training set. In Figure 4 , the training loss curve shows that the loss curve converges well at around the 400th epoch. The prediction accuracies of the WCPNet and the three STL models are listed in Table 2, and their training speeds are listed in Table 3.
[0105] Table 2 Prediction accuracy of WCPNet
[0106]
[0107] Table 3 Prediction accuracy of WCPNet
[0108]
[0109] As can be seen from Table 1, the prediction accuracy of WCPNet has increased by 23.44%, 10.56%, and 1.26% in terms of wire length, power consumption, and congestion respectively compared to the STL model. As can be seen from Table 2, the training time of WCPNet is only one-third of the time required to train the three STL models. In summary, the WCPNet of this scheme shows superior performance in terms of prediction accuracy and training speed compared to the STL model.
[0110] Figure 4 The training losses of WCPNet (including the total loss and the losses of each task) and three STL models were compared. When the training process converged, the total loss of WCPNet was lower than that of the three STL models. In addition, the loss specific to each task of WCPNet was lower than that of the corresponding STL model. Figure 5 The predicted congestion maps of WCPNet were compared with three randomly selected real maps from the test data. The high similarity between the predicted maps and the corresponding real maps further demonstrated the excellent performance of WCPNet in the congestion prediction task.
[0111] In addition, to evaluate the function and impact of the new feature PinUtilization introduced in the previous section, this scheme compared the prediction accuracy of WCPNet with and without PinUtilization maps as inputs while keeping all other experimental settings unchanged. The results are listed in Table 3.
[0112] From Table 4, this scheme can see that PinUtilization helps improve the accuracy of WCPNet in wire length, power consumption, and congestion prediction by 18.3%, 68.1%, and 2.9% respectively. In summary, PinUtilization improves the prediction accuracy of WCPNet, but the degree of influence on different metrics varies. Since PinUtilization is highly correlated with power consumption, it significantly improves the accuracy of power consumption prediction. However, its correlation with wire length and congestion is relatively low, so the improvement in the accuracy of these two metrics is relatively small.
[0113] Table 4 Prediction Accuracy of WCPNet
[0114]
[0115] The above embodiments are only used to illustrate the technical solutions of the present application, not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.
Claims
1. A method for predicting the quality of multi-objective integrated placement and routing, characterized in that, Including: Layout different designs, and after the layout is completed, extract and generate the input features of each layout scheme, including Place&Connections features and PinUtilization features. Among them, the Place&Connections features are obtained by adding the corresponding pixel values of the layout graph and the connection graph. The layout graph is used to describe the layout of logic resource blocks in the layout scheme, and the connection graph is used to describe the interconnection relationship of logic resource blocks after the layout is completed; the PinUtilization features are used to describe the pin utilization rate of logic resource blocks; Route different designs, and after routing, extract the corresponding label information of the design, where the label information includes the wire length, congestion, and power consumption of each design; Use the input features of the layout scheme and the corresponding label information as samples to construct a training set; Train the quality prediction model with the samples in the training set, and save the trained quality prediction model for predicting the congestion, wire length, and power consumption of the layout-completed design.
2. The method for predicting the layout and routing quality of multi-objective integration according to claim 1, characterized in that The PinUtilization feature is an image pin utilization rate graph; For each logical resource block after the placement phase, its pin utilization rate is represented by r utilization , and can be calculated as follows: where P utilized and P total represent the number of pins used and the total number of pins respectively. Subsequently, each logical resource block will be mapped to a corresponding color according to the pin utilization rate, so as to obtain the image pin utilization rate map.
3. The method for predicting the layout and routing quality of multi-objective integration according to claim 1, characterized in that The quality prediction model is a deep neural network, including an encoder and a decoder, where: The encoder includes three convolutional units and two max pooling layers. The input of the first convolutional unit is the input features of the samples in the dataset. The first convolutional unit includes two convolutional layers, and each convolutional layer is followed by an InstanceNorm2d normalization layer and a LeakyReLU activation function; the structure of the second convolutional layer is the same as that of the first convolutional layer; the two max pooling layers are located after the first convolutional unit and the second convolutional unit respectively; the third convolutional unit includes one convolutional layer, and a batch normalization layer and a hyperbolic tangent activation function are provided after the convolutional layer.
4. The method for predicting the layout and routing quality of multi-objective integration according to claim 3, characterized in that The decoder has three parallel network structures; The first network structure is used to process the congestion prediction task, including a first convolutional unit, a first transposed convolutional unit, a second convolutional unit, a second transposed convolutional unit, and a third convolutional unit arranged in sequence; the first convolutional unit and the second convolutional unit have the same structure, including two convolutional layers, and each convolutional layer is followed by an InstanceNorm2d normalization layer and a LeakyReLU activation function; the third convolutional unit includes one convolutional layer; the first transposed convolutional unit and the second transposed convolutional unit have the same structure, including one transposed convolutional layer, and a LeakyReLU activation function and an InstanceNorm2d normalization layer are connected after the transposed convolutional layer; The second network structure and the third network structure are the same, and are respectively used for the wire length or power consumption prediction task; The second network structure is first a convolutional unit, which includes two convolutional layers, and after each convolutional layer, an InstanceNorm2d normalization layer and a LeakyReLU activation function are connected; after the convolutional unit is an adaptive average pooling function layer, and after the adaptive average pooling function layer is a flattening layer; finally, 4 fully connected layers are connected, and the output of the last neuron in the fully connected layer is used as the output of the second network structure.
5. The method for predicting the layout and routing quality of multi-objective integration according to claim 4, wherein The input of the second transposed convolutional unit of the decoder is the result of adding the feature map output by the first convolutional unit of the encoder and the feature map output by the second convolutional unit of the decoder, so as to fuse features of different scales together.
6. The method for predicting the layout and routing quality of multi-objective integration according to claim 1, characterized in that The total loss function L of the quality prediction model total (θ total ) is expressed as: where θ total represents the total parameters to be trained by the quality prediction model, and L w (θ w ), L p (θ p ), L c (θ c ) are the loss functions of wire length, power consumption, and congestion respectively. At the same time, θ w , θ p , θ c are parameters that can be trained.
7. The method for predicting the layout and routing quality of multi-objective integration according to claim 6, wherein The loss function L of the wire length w (θ w ) is expressed as: Among them, n1 represents the line length label in the dataset, representing the true label value, and j is the j-th sample, indicating the predicted line length value; Power consumption loss function L p (θ p ) is expressed as: Among them, n2 represents the power consumption label in the dataset, representing the actual power consumption value, and j is the j-th sample, indicating the predicted power consumption value; Congestion loss function L c (θ c ) is expressed as: where n pixel represents the number of pixels in the congestion hotspot map for the congestion prediction task, and n3 represents the congestion label in the dataset. represents the actual congestion value of the k-th pixel in the j-th sample. represents the predicted congestion value of the k-th pixel in the j-th sample.
8. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method for predicting the layout and routing quality of multi-objective synthesis according to any one of claims 1-7.
9. A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps of the method for predicting the layout and routing quality of multi-objective synthesis according to any one of claims 1-7.