ONO structure and preparation method and application thereof
By densifying the tunnel oxide layer and improving the density of its atoms, the problem of reduced reliability of the tunnel layer during repeated writing and erasing is solved, and higher charge storage reliability and data retention capabilities are achieved.
Patent Information
- Application Number
- CN202311725600.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-14
- Publication Date
- 2025-06-24
AI Technical Summary
During repeated write and erase, the reliability of the tunneling layer is reduced, resulting in an increase in the possibility of direct tunneling of carriers, affecting the ability to voltage difference between the write and erase thresholds.
By densifying the tunneled oxide layer formed by deposition, including annealing, the density of atoms in the tunneled oxide layer is increased, thereby reducing charge loss in the storage layer.
Improves the reliability of tunneling oxide layer, reduces charge loss in the storage layer, and improves the work efficiency of writing and erasing and data retention capabilities.
Smart Images
Figure CN120199684A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductors, and specifically, relates to an ONO structure, a preparation method thereof, and an application thereof. Background Art
[0002] A Flash Cell, also known as a Flash memory cell, is a semiconductor memory cell composed of floating gate transistors. In the e-Flash Cell structure, the ONO structure is the core layer for controlling writing and erasing. Among them, the tunneling layer controls the tunneling of carriers, and the silicon nitride layer controls the storage of carriers. In such charge trapping memories, when the gate voltage is positive, electrons in the channel enter the charge storage layer through excitation or tunneling through the tunneling layer to achieve the programming process; when the direction of the electric field changes, the charges return from the storage layer to the channel to achieve the erasing process.
[0003] In the process of repeated writing and erasing, high-energy electrons or holes continuously impact the Si / SiO2 interface, SiO2 / Si3N4 interface, and silicon dioxide blocking layer in the ONO structure. Therefore, in order to ensure the normal operation of the ONO structure during repeated writing and erasing, it is very important to control the operation window of the interface tunneling layer, and its ability to maintain the voltage difference between the writing and erasing thresholds can only be maintained if it is not easily damaged. However, as the process line width continues to shrink and the tunneling layer becomes thinner, it means that the chance of carriers transitioning back from the storage layer to the channel increases, and the possibility of direct tunneling of carriers greatly increases, reducing the reliability of the tunneling layer. Summary of the Invention
[0004] The purpose of the present invention is to provide a preparation method for preparing an ONO structure to enhance the reliability of the tunneling layer.
[0005] To achieve the above object, a first aspect of the present invention provides a preparation method for an ONO structure, the method comprising the following steps: depositing a tunneling oxide layer on the surface of a substrate, and then densifying the tunneling oxide layer to obtain a densified tunneling oxide layer; the density of atoms in the densified tunneling oxide layer is higher than the density of atoms in the tunneling oxide layer; depositing a charge trapping layer on the tunneling oxide layer; and forming a blocking layer on the silicon nitride layer.
[0006] Optionally, the method for depositing the tunneling oxide layer includes atomic layer deposition and plasma-enhanced atomic layer deposition; the conditions for the atomic layer deposition include: the deposition temperature is 80 - 600 °C; the silicon precursor gas is selected from one or more of SiCl4, SiH2Cl2, and bis(diethylamino)silane; and / or the oxygen source is selected from one or more of H2O, NO, N2O, and O2.
[0007] Optionally, the number of film deposition times of the tunneling oxide layer is 0 - 700 times; and / or the thickness of the tunneling oxide layer is 0 - 200 angstroms.
[0008] Optionally, the densification treatment includes annealing the tunneling oxide layer; the conditions of the annealing treatment include: the annealing temperature is 800 - 1100 °C, and the time is 5 - 20 min.
[0009] Preferably, the time of the annealing treatment is 5 - 10 min.
[0010] Optionally, the charge trapping layer is a silicon nitride layer or a high-k material layer; the method for depositing the silicon nitride layer includes low-pressure chemical vapor deposition and atomic layer deposition; preferably, the conditions for forming the silicon nitride layer by atomic layer deposition include: the precursor gases are SiH2Cl2 and NH3.
[0011] Optionally, the method for forming the barrier layer includes atomic layer deposition: the deposition temperature is 0 - 600 °C; the precursor gases include SiH2Cl2 and N2O, and the flow rate ratio of SiH2Cl2 to N2O is 1:(5 - 10).
[0012] Optionally, the thickness of the charge trapping layer is 0 - 200 angstroms; and / or the thickness of the barrier layer is 0 - 200 angstroms.
[0013] The second aspect of the present invention provides an ONO structure prepared by the method provided in the first aspect of the present invention.
[0014] The third aspect of the present invention provides a Flash memory, and the Flash memory includes the aforementioned ONO structure.
[0015] Through the above technical solutions, by densifying the deposited tunneling oxide layer, the present invention makes the density of atoms in the tunneling oxide layer higher, reduces the charge loss in the storage layer, and improves the reliability of the tunneling oxide layer.
[0016] Other features and advantages of the present invention will be described in detail in the subsequent specific implementation section. Brief Description of the Drawings
[0017] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. Together with the following specific implementation, they are used to explain the present invention, but do not constitute a limitation to the present invention. In the drawings:
[0018] Figure 1 is a schematic structural diagram of an ONO structure prepared by the method provided by the present invention. Specific Implementation
[0019] The following provides a detailed description of the specific embodiments of the present invention. It should be understood that the specific embodiments described herein are only for explaining and illustrating the present invention, and are not used to limit the present invention.
[0020] In a charge trapping memory, the nitride layer is used to store charges and serves as a charge storage layer; the oxide layer between the nitride layer and the substrate is relatively thin and acts as a charge tunneling layer. When the device operates, electrons in the channel pass through the charge tunneling layer and enter the charge storage layer, causing a change in the threshold voltage of the memory. As the tunneling oxide layer becomes thinner, the reliability of the tunneling oxide layer prepared by conventional methods such as LPCVD decreases. After repeated write / erase operations, there may be defects in the tunneling oxide layer, resulting in charge loss in the charge storage layer.
[0021] The reliability of a charge trapping memory includes the anti-fatigue ability (Endurance) and data retention ability (Retention) of the device. The anti-fatigue ability refers to the data retention ability of the device without an external power supply after the device performs multiple write / erase operations. The main reason is that after several write / erase operations, the tunneling oxide layer of the device degrades, resulting in charge loss in the charge storage layer.
[0022] The data retention ability refers to the ability of data to be retained in the device after cutting off the external power supply. Usually, the industrial standard is that the data can be retained for 10 years at the maximum operating temperature.
[0023] Taking the traditional SONOS charge trapping memory as an example, charge loss mainly includes trap-to-band tunneling of electrons, trap-to-trap tunneling of electrons, band-to-trap tunneling of holes, and thermal excitation caused by temperature. Among them, trap-to-band tunneling and thermal excitation are the main charge loss mechanisms. Therefore, the present invention proposes a method for improving the tunneling oxide layer.
[0024] As Figure 1 shown, the present invention provides an ONO structure 200, which is formed on a substrate 100 and includes a tunneling oxide layer 210, a charge trapping layer 220, and a blocking layer 230 that are sequentially stacked on the surface of the substrate 100.
[0025] Among them, the semiconductor substrate 100 can specifically be single crystal silicon, polycrystalline silicon, or amorphous silicon, and can also be silicon germanium, silicon on insulator (SOI), or other materials.
[0026] The following will be specifically described in combination with the specific preparation method of the ONO structure.
[0027] The first aspect of the present invention provides a method for preparing an ONO structure, which includes the following steps:
[0028] S1. Deposit and form a tunneling oxide layer on the substrate surface, and then densify the tunneling oxide layer to obtain a densified tunneling oxide layer; the density of atoms in the densified tunneling oxide layer is higher than that of atoms in the tunneling oxide layer;
[0029] S2. Deposit and form a charge trapping layer on the tunneling oxide layer; and
[0030] S3. Form a barrier layer on the silicon nitride layer.
[0031] In the present invention, by densifying the deposited tunneling oxide layer, the density of atoms in the tunneling oxide layer is higher, reducing the charge loss in the storage layer and improving the reliability of the tunneling oxide layer.
[0032] In some embodiments of the present invention, the tunneling oxide layer is a silicon oxide layer, and the method for depositing and forming the tunneling oxide layer includes atomic layer deposition (ALD) and plasma enhanced atomic layer deposition (PEALD).
[0033] Atomic layer deposition (ALD) can deposit very thin films through multiple deposition cycles, can be used to deposit compound semiconductors, and can also be used to deposit high-k dielectrics. In the ALD process, the first step is that the gas enters the reaction chamber and is adsorbed on the substrate surface, then the reaction chamber is cleaned, and the unreacted gas fed in the first step is pumped out, leaving only a small amount of gas adsorbed on the substrate surface; the second step is to feed the reaction gas into the reaction chamber to react with the gas adsorbed on the substrate surface in the first step to form a compound molecular layer. When the gas molecules in the first step are consumed, the chemical reaction automatically terminates, the reaction chamber is cleaned and the gas fed in the second step is pumped out, and then the next deposition reaction is started again. After multiple deposition reactions, a film with the required thickness is formed.
[0034] When forming a silicon oxide film by atomic layer deposition, the conditions for the atomic layer deposition include: the deposition temperature is 80 - 600 °C. The silicon precursor gas is selected from one or more of SiCl4, SiH2Cl2, and bis(diethylamino)silane (BDEAS).
[0035] The oxygen source is selected from one or more of H2O, NO, N2O, and O2. That is, when forming the tunneling oxide layer by atomic layer deposition, the silicon precursor gas and the oxygen source are used as reaction gases respectively to deposit and form a silicon oxide film layer with the required thickness on the substrate surface.
[0036] Since the tunneling oxide layer is generally thin, an overly thick tunneling oxide layer is not conducive to improving the efficiency of SONOS memory cells. However, an overly thin tunneling oxide layer will affect the reliability of SONOS devices, such as durability and data retention ability. The silicon oxide layer formed by the above method has a high density. Especially compared with the tunneling oxide layer formed by the low-pressure chemical vapor deposition process (usually high-temperature thermal oxidation), the tunneling oxide layer formed by atomic layer deposition has a higher density, and the stacking of oxygen atoms and silicon atoms is denser, making the quality and uniformity of the film layer better.
[0037] In step S1, in a specific embodiment of the present invention, the conditions for atomic layer deposition include: the reactants include SiH2Cl2 and N2O, and the deposition temperature is 80 - 600 °C.
[0038] Specifically, the silicon wafer is processed to make the surface of the silicon wafer reach a suitable hydrophobicity, and then the silicon wafer is placed in an ALD device, and the reaction chamber is evacuated. The first reaction gas and the second reaction gas are alternately introduced to form a silicon dioxide film layer on the surface of the silicon wafer. It is judged whether the thickness of the silicon dioxide film layer formed in each pulse cycle is within the preset thickness range, so as to adjust the thickness of the tunneling oxide layer by combining the reaction time and the number of film layer depositions.
[0039] In some embodiments of the present invention, the number of film layer depositions of the tunneling oxide layer is 0 - 700 times; specifically, the thickness of the tunneling oxide layer is 0 - 200 angstroms. Through the atomic layer deposition method, a tunneling oxide layer with better density and uniformity can be obtained. Although the tunneling oxide layer is thin, it has good reliability, which can enable the majority carriers to tunnel into the nitride layer, while blocking the recombination of minority carriers, so that the majority carriers can laterally transport in the nitride layer, improving the write and erase working efficiency of the Flash memory cell.
[0040] When forming a silicon oxide film by plasma-enhanced atomic layer deposition (PEALD), first, the silicon wafer is cleaned and pretreated, and then a silicon precursor is introduced to adsorb silicon atoms on the surface of the silicon wafer and argon is used to purge the unreacted silicon atoms, so as to adsorb a layer of silicon atoms on the surface of the silicon wafer. An oxygen source is introduced to deposit and form a silicon dioxide film on the surface of the silicon wafer under the action of a radio frequency power supply electric field. The unreacted oxygen source is purged out. The introduction of the silicon precursor and the oxygen source are repeated respectively to deposit and form a tunneling oxide layer with the required thickness on the surface of the silicon wafer. Specifically, the deposition temperature is 80 - 600 °C, the radio frequency power supply is a square wave or sine wave power supply, the silicon precursor is silane, and the oxygen source is oxygen or N2O.
[0041] In some embodiments of the present invention, the densification treatment includes annealing the tunneling oxide layer; the conditions of the annealing treatment include: the annealing temperature is 800 - 1100 °C. In the densified tunneling oxide layer obtained by annealing, the molecules are more dense, and the density of silicon and oxygen is greater than that in the unannealed tunneling oxide layer, increasing the density and shrinkage stress of the tunneling oxide layer film. After annealing, the tunneling oxide layer has better densification and a better film layer structure. The dense tunneling oxide layer can produce a better oxidation passivation effect on the silicon wafer surface, but the densification of the tunneling oxide layer needs to be within a certain range to facilitate the selective movement of majority carriers and at the same time prevent electrons from directly tunneling due to the too thin tunneling oxide layer.
[0042] In the present invention, the densification treatment can be carried out in a vertical diffusion furnace tube or a Single RTP heat treatment device. Specifically, the annealing temperature can be 800 °C, 900 °C, 920 °C, 940 °C, 960 °C, 980 °C, 1000 °C, 1020 °C, 1040 °C, 1060 °C, 1080 °C, 1100 °C or any value within the foregoing range.
[0043] In some embodiments, the annealing treatment time can be 5 - 20 min. In some embodiments of the present invention, the annealing treatment time is 5 - 10 min. It should be noted that when the RTP heat treatment device is used for annealing, the time is shorter, being several seconds or even shorter.
[0044] In step S2, in some embodiments of the present invention, the charge trapping layer is a silicon nitride layer or a high - k material layer. There are defects in the charge trapping layer, and these defects trap electrons and holes. Silicon nitride (Si3N4) as the charge trapping layer has a low trap density. In order to increase the trap density, high - k materials such as Al2O3, La2O3, ZrO3, and HfO2 with high dielectric constants and large bandgaps are gradually used to form the charge trapping layer, which can reduce the leakage current and have good data retention ability.
[0045] The methods for depositing the silicon nitride layer include low - pressure chemical vapor deposition and atomic layer deposition. Compared with the silicon nitride layer formed by chemical vapor deposition, the silicon nitride layer formed by atomic layer deposition has a higher densification and a higher charge storage density. Therefore, it is preferably to use atomic layer deposition to form the silicon nitride layer.
[0046] Specifically, atomic layer deposition can also be used to form the above - mentioned high - k material layer as the charge trapping layer.
[0047] Preferably, the conditions for forming the silicon nitride layer by atomic layer deposition include: the precursor gases are SiH2Cl2 and NH3.
[0048] In step S3, specifically, the blocking layer is a silicon dioxide layer. In some embodiments of the present invention, the method for forming the blocking layer includes atomic layer deposition: the deposition temperature is 0 - 600 °C; the precursor gases include SiH2Cl2 and N2O. Further, the flow rate ratio of SiH2Cl2 to N2O is 1:(5 - 10).
[0049] In some embodiments of the present invention, the thickness of the charge trapping layer is 0 - 200 angstroms.
[0050] In some embodiments of the present invention, the thickness of the blocking layer is 0 - 200 angstroms.
[0051] The present invention also provides a Flash memory, which includes the aforementioned ONO structure. The Flash memory can be a SONOS memory.
[0052] The present invention will be further described in detail below through examples.
[0053] Example
[0054] As Figure 1 shown, the ONO structure 200 provided in this embodiment includes a tunneling oxide layer 210, a charge trapping layer 220, and a blocking layer 230 sequentially disposed on a substrate 100. Among them, the substrate 100 is a silicon substrate; the tunneling oxide layer is a silicon dioxide layer with a thickness of 100 angstroms; the charge trapping layer is a silicon nitride layer with a thickness of 100 angstroms; the blocking layer is a silicon dioxide layer with a thickness of 100 angstroms.
[0055] The preparation method of the ONO structure having the above structure includes the following steps:
[0056] (1) Atomic layer deposition is used to deposit a tunneling oxide layer on the surface of the substrate. The specific process parameters are: the silicon precursor gas is SiH2Cl2, the oxygen source is N2O, and the deposition temperature is room temperature.
[0057] (2) The sample obtained in step (2) is placed in a vertical diffusion furnace tube for annealing treatment. The annealing temperature is 1000 °C, the annealing time is 10 - 12 min, and the annealing atmosphere is air.
[0058] (3) Atomic layer deposition is used to deposit a charge trapping layer on the surface of the substrate. The specific process parameters are: the precursor gases are SiH2Cl2 and NH3, and the deposition temperature is room temperature.
[0059] (4) Atomic layer deposition is used to deposit a blocking layer on the surface of the substrate. The specific process parameters are: the deposition temperature is room temperature; the precursor gases include SiH2Cl2 and N2O.
[0060] Comparative Example
[0061] The thicknesses of the respective film layers of the ONO structure provided in this comparative example are the same as those in the embodiment, and the differences are as follows:
[0062] (1) A tunneling oxide layer was deposited on the substrate surface by LPCVD (high-temperature thermal oxidation method). The specific process parameters were as follows: the silicon source was SiH4, and the oxygen source was O2.
[0063] The methods for preparing the ONO structure in the above-mentioned embodiment and comparative example were used in the preparation process of the SONOS memory. If the channel current of the SONOS device based on the above ONO structure was read with the same gate voltage, the channel current of the SONOS device prepared by the method provided in the embodiment of the present invention was much smaller than that of the SONOS device prepared by the comparative example method.
[0064] In addition, the data retention performance of the ONO structure of SONOS can also be evaluated by conventional evaluation methods. For example, after obtaining the parameters of the operating voltage window and tunneling electric field window of SONOS, the tunneling electric field window and the SONOS operating voltage window are calculated, and then the data retention of the SONOS memory based on this is evaluated. The SONOS memory prepared with the ONO structure provided in the embodiment of the present invention has stronger data retention ability and higher reliability.
[0065] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solutions of the present invention, and these simple modifications all fall within the protection scope of the present invention.
[0066] In addition, it should be noted that, in the case of no contradiction, the various specific technical features described in the above specific embodiments can be combined in any suitable way. To avoid unnecessary repetition, the present invention will not separately describe various possible combination methods.
[0067] In addition, any combination can be made between various different embodiments of the present invention, as long as it does not violate the idea of the present invention, and it should also be regarded as the content disclosed by the present invention.
Claims
1. A method for preparing an ONO structure, characterized in that, The method comprises the following steps: Deposit and form a tunneling oxide layer on the substrate surface, and then densify the tunneling oxide layer to obtain a densified tunneling oxide layer; the density of atoms in the densified tunneling oxide layer is higher than that of atoms in the tunneling oxide layer; Deposit and form a charge trapping layer on the tunneling oxide layer; and Form a blocking layer on the silicon nitride layer.
2. The method according to claim 1, wherein, The method for depositing and forming the tunneling oxide layer includes atomic layer deposition and plasma enhanced atomic layer deposition; The conditions for the atomic layer deposition include: the deposition temperature is 80 - 600 °C; the silicon precursor gas is selected from one or more of SiCl4, SiH2Cl2, and bis(diethylamino)silane; and / or the oxygen source is selected from one or more of H2O, NO, N2O, and O2.
3. The method according to claim 1, wherein The number of film deposition times of the tunneling oxide layer is 0 - 700 times; and / or the thickness of the tunneling oxide layer is 0 - 200 angstroms.
4. The method according to claim 1, wherein, The densification treatment includes annealing the tunneling oxide layer; the conditions for the annealing treatment include: the annealing temperature is 800 - 1100 °C, and the time is 5 - 20 min.
5. The method according to claim 4, wherein The time for the annealing treatment is 5 - 10 min.
6. The method according to claim 1, wherein The charge trapping layer is a silicon nitride layer or a high-k material layer; The method for depositing and forming the silicon nitride layer includes low-pressure chemical vapor deposition and atomic layer deposition; Preferably, the conditions for forming the silicon nitride layer by atomic layer deposition include: the precursor gases are SiH2Cl2 and NH3.
7. The method according to claim 1, wherein The method for forming the blocking layer includes atomic layer deposition: the deposition temperature is 0 - 600 °C; the precursor gases include SiH2Cl2 and N2O, and the flow rate ratio of SiH2Cl2 to N2O is 1:(5 - 10).
8. The method according to claim 1, wherein The thickness of the charge trapping layer is 0 - 200 angstroms; and / or the thickness of the blocking layer is 0 - 200 angstroms.
9. The ONO structure prepared by the method according to any one of claims 1 - 8.
10. A Flash memory, characterized in that, The Flash memory includes the ONO structure according to claim 9.