Semiconductor structure and forming method thereof

Abstract

In one embodiment, a method includes forming a die including: forming a first metal pillar on a first side of a first semiconductor substrate of the die; polishing the first semiconductor substrate of the die to expose a first via in the first semiconductor substrate; and forming a second metal pillar on the second side of the die. The first side and the second side are on opposite sides of the first semiconductor substrate. The method further includes sealing the die in an encapsulant; forming a first conductive feature electrically connected to the first metal pillar on the first side of the first semiconductor substrate; and forming a second conductive feature electrically connected to the second metal pillar on the second side of the first semiconductor substrate. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] With the development of integrated circuits, more and more functions are built into integrated circuit packages. Therefore, the requirements for local communication and interconnection between adjacent device dies and packages have become more stringent. Thus, local interconnect dies are used as part of the package. Summary of the Invention

[0003] Some embodiments of the present application provide a method of forming a semiconductor structure, including: forming a first die, including: forming a first metal pillar on a first side of a first semiconductor substrate of the first die; polishing the first semiconductor substrate of the first die to expose a first through hole in the first semiconductor substrate; and forming a second metal pillar on a second side of the first die, wherein the first side and the second side are located on opposite sides of the first semiconductor substrate; sealing the first die in a sealant; forming a first conductive component electrically connected to the first metal pillar on the first side of the first semiconductor substrate; and forming a second conductive component electrically connected to the second metal pillar on the second side of the first semiconductor substrate.

[0004] Some other embodiments of the present application provide a semiconductor structure, including: a first interconnect die, including: a first semiconductor substrate; a first through hole located in the first semiconductor substrate; and a first metal pillar and a second metal pillar located at opposite surfaces of the first interconnect die, wherein at least one of the first metal pillar and the second metal pillar is electrically connected to the first through hole; a sealant, wherein the first interconnect die is located in the sealant; and a metal pillar surrounded by the sealant.

[0005] Some further embodiments of the present application provide a semiconductor structure, including: a first die, including: a first metal pillar located at a first surface of the first die; and a second metal pillar located at a second surface of the first die, wherein the second surface is opposite to the first surface, and the second metal pillar is electrically connected to the first metal pillar, and wherein the first metal pillar and the second metal pillar have a first total thickness; and a second die, including: a third metal pillar located at a third surface of the second die; and a fourth metal pillar located at a fourth surface of the second die, wherein the fourth surface is opposite to the third surface, and the fourth metal pillar is electrically connected to the third metal pillar, and wherein the third metal pillar and the fourth metal pillar have a second total thickness different from the first total thickness. Brief Description of the Drawings

[0006] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings, it should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, for the sake of clear discussion, the dimensions of the various components can be increased or decreased arbitrarily.

[0007] Figures 1 to 13 and Figure 14A FIG. shows a cross-sectional view of an intermediate stage in the formation of a package according to some embodiments.

[0008] Figure 14B and Figure 14C FIG. shows some packages according to some embodiments.

[0009] Figure 15 FIG. shows a top view of a package according to some embodiments.

[0010] Figure 16A and Figure 16B FIG. shows a partially interconnected die according to some embodiments.

[0011] Figure 17 FIG. shows a process flow for forming a package according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing the different features of the embodiments of the present disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are formed in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. In addition, the embodiments of the present disclosure may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity, and in itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0013] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation depicted in the figures, the spatially relative terms are intended to include different orientations of the device during use or operation. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0014] A package including local silicon interconnect (LSI) dies (also referred to as bridge dies) and a method of forming the same are provided. According to some embodiments of the present disclosure, a plurality of LSI dies having different thicknesses are formed. The LSI dies include vias, and metal pillars (sometimes referred to as metal vias) are formed on opposite sides of the LSI dies. As the metal pillars are formed on both sides of the LSI dies, the difference in thicknesses of the LSI dies can be compensated. Cracks caused by TSVs on the back side of the LSI dies can be reduced. The process risk of trapping air bubbles during the thermal process is also reduced.

[0015] The embodiments discussed herein are provided to give examples of the subject matter that can make or use embodiments of the present disclosure, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the scope of different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being implemented in a particular order, other method embodiments may be implemented in any logical order.

[0016] Figures 1 to 13 and Figure 14A A cross-sectional view showing an intermediate stage in the formation of a package according to some embodiments of the present disclosure is shown. The corresponding process is also schematically reflected in the process flow shown in Figure 17 the process flow.

[0017] Figures 1 to 5 A view showing the formation of an LSI die having bilateral metal pillars according to some embodiments is shown. Figure 1 A cross-sectional view showing the formation of a wafer 20 including a plurality of identical dies 20' is shown, and one of the dies 20' is shown. The corresponding process is shown as the process 202 in the process flow 200 shown in Figure 17 According to some embodiments, the die 20' is an LSI die formed based on a silicon substrate and includes a plurality of circuit paths for electrically interconnecting two package components. Some details of the die 20' are discussed with reference to Figure 16A and Figure 16A an enlarged view of an exemplary die 20' is shown.

[0018] As Figure 1 shown, according to some embodiments, the die 20' includes a semiconductor substrate 24 and components formed at the top surface of the semiconductor substrate 24. The semiconductor substrate 24 may be formed of or include crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, etc. The semiconductor substrate 24 may also be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate.

[0019] According to some embodiments, die 20' does not include active and passive devices. According to alternative embodiments, die 20' includes integrated circuit devices 25 (also refer to Figure 16A ), and integrated circuit devices 25 are formed at the surface of semiconductor substrate 24. Thus, integrated circuit devices 25 are shown as dashed lines to indicate that they may or may not be formed. According to some embodiments, integrated circuit devices 25 (if formed) may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc.

[0020] Returning to the reference Figure 1 (and also refer to Figure 16A ), die 20' may include vias 26 (also known as through-silicon vias (TSVs) or semiconductor vias (also known as TSVs)) that extend to an intermediate level of semiconductor substrate 24, where the intermediate level is between the top and bottom surfaces of semiconductor substrate 24. According to some embodiments, via 26 has a top width WT and a bottom width TB that is less than the top width WT.

[0021] An interconnect structure 28 is formed above semiconductor substrate 24. According to some embodiments, interconnect structure 28 includes a plurality of dielectric layers 30 and a plurality of conductive components 34 in dielectric layers 30. Dielectric layer 30 may include an interlayer dielectric (ILD) (not shown separately) that fills the spaces between the gate stacks of the transistors in integrated circuit devices 25 (if formed). According to some embodiments, the ILD is formed of silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. The ILD may be formed using spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), etc.

[0022] Conductive components 34 may include metal lines and vias, and the metal lines and vias may form a conductive path that serves as a bridge to interconnect two package components and is connected to via 26. Although the vias are not shown in Figure 1 , the vias are also formed and are shown in the details shown in Figure 16A . If integrated circuit devices 25 are formed, conductive components 34 may also be connected to integrated circuit devices 25 (if formed). Metal lines at the same level are collectively referred to as metal layers hereinafter. According to some embodiments, interconnect structure 28 includes a plurality of metal layers interconnected by vias. The metal lines and vias may be formed of copper, copper alloy, and / or another metal.

[0023] According to some embodiments, an electrical connector 38 is formed at the top surface of the wafer 20. The electrical connector 38 may include metal pillars, which may be formed by plating and have vertical and straight sidewalls. Thus, throughout the description, the electrical connector 38 is referred to as the metal pillar 38. A solder layer may or may not be present on top of the metal pillar 38.

[0024] According to some embodiments, the height H1 of the metal pillar 38 is determined based on the structure of the package into which the corresponding die 20’ will be incorporated and may be based on the width W1 of the metal pillar 38. The determination of the height H1 will be discussed in subsequent paragraphs.

[0025] According to some embodiments, a dielectric layer 40 is formed to cover the metal pillar 38 and embed the metal pillar 38 therein. The dielectric layer 40 may be formed of or include a polymer, and the polymer may include polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), etc. According to alternative embodiments, the dielectric layer 40 is not formed.

[0026] Figure 2 The placement of the wafer 20 onto the release film 44-1 is shown, and the release film 44-1 is also located on the carrier 42-1. The corresponding process is shown as process 204 in process flow 200 as shown in Figure 17 The carrier 42-1 may be a glass carrier, a silicon wafer, an organic carrier, etc. The release film 44-1 may be formed of a polymer-based material and / or a heat-release material based on epoxy resin (such as a light-to-heat conversion (LTHC) material). The release film 44-1 is capable of decomposing under radiation such as a laser beam, such that the carrier 42-1 can be peeled off from the overlying structure that will be formed in subsequent processes. According to some embodiments of the present disclosure, the release film 44-1 is applied onto the carrier 42-1 by coating.

[0027] Then, a backside grinding process is performed on the thin wafer 20. The corresponding process is shown as process 206 in process flow 200 as shown in Figure 17 According to some embodiments, the backside grinding process is performed until the TSV 26 is exposed. The backside grinding process may be performed by a chemical mechanical polishing (CMP) process or a mechanical grinding process.

[0028] Next, referring to Figure 3 , the semiconductor substrate 24 in the device die 20’ may be recessed in an etching process such that the top portion of the TSV 26 protrudes above the semiconductor substrate 24. The corresponding process is shown as process 208 in process flow 200 as shown in Figure 17 Then, a dielectric isolation layer 46 may be formed to surround the top portion of the TSV 26. The corresponding process is shown as process 208 in process flow 200 as shown in Figure 17Process 210 in process flow 200 as shown. The formation of the dielectric isolation layer 46 may include a deposition process to deposit a dielectric layer onto the semiconductor substrate 24 such that the protruding portion of the TSV 26 is located within the dielectric layer, followed by a planarization process. The portion of the dielectric layer located above the TSV 26 is removed, and the remaining portion of the dielectric layer forms the dielectric isolation layer 46, which becomes part of the die 20' and the wafer 20.

[0029] Reference Figure 4 , an electrical connector 48 is formed. The electrical connector 48 includes a metal pillar having vertical and straight sidewalls. The corresponding process is shown as process 212 in process flow 200 as Figure 17 shown. The electrical connector 48 may include copper and may or may not include titanium, nickel, palladium, etc. The electrical connector 48 is hereinafter referred to as the metal pillar 48. According to some embodiments, the metal pillar 48 is formed by: forming a metal seed layer (such as a titanium layer and a copper layer above the titanium layer); forming a plating mask (such as a patterned photoresist); plating the metal pillar 48 in the plating mask; removing the plating mask; and etching the portion of the metal seed layer previously covered by the plating mask.

[0030] According to some embodiments, the height H2 of the metal pillar 48 is selected based on the structure of the package into which the corresponding die 20' will be incorporated and may be selected based on the width W2 of the metal pillar 48. The determination of the height H2 will be discussed in subsequent paragraphs.

[0031] Further reference Figure 4 , a dielectric layer 50 is formed on the metal pillar 48. According to some embodiments, the dielectric layer 50 includes a molding compound, a molded underfill, etc. The molding compound or the molded underfill may include a base dielectric material (such as a polymer, a resin, an epoxy resin, etc.) and filler particles in the base material. The filler particles may be dielectric particles such as SiO2, Al2O3, silica, etc. and may have a spherical shape. In addition, the spherical filler particles may have a variety of different diameters.

[0032] Optionally, the dielectric layer 50 may be formed of a silicon-containing dielectric material, which may be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc. or a combination thereof. The formation process may include a deposition process followed by a planarization process. According to still other alternative embodiments, the dielectric layer 50 may be formed of or include a homogeneous polymer, such as polyimide, PBO, BCB, etc. The dielectric layer 50 may have a top surface that is coplanar with or higher than the top surface of the metal pillar 48.

[0033] In a subsequent process, a support substrate 52 ( Figure 5)It can be attached to the wafer 20, for example, by an adhesive film 54. The corresponding process is shown as process 214 in process flow 200 as shown in Figure 17 As shown in. According to some embodiments, the support substrate 52 can be a silicon substrate. The layer 54 (which can be an adhesive film or a bonding layer) can be used to attach the support substrate 52 to the wafer 20. When it is a bonding layer, the layer 54 can include a silicon-containing dielectric material such as SiO, SiN, SiCN, SiOCN, etc.

[0034] Next, as also shown in Figure 5 As shown in, the wafer 20 is sawed in a dicing process, and the dicing process can be implemented using a saw blade. The corresponding process is shown as process 216 in process flow 200 as shown in Figure 17 As shown in. Thus, the wafer 20 is divided into packages 56, each including a discrete device die 20' and a piece of support substrate 52.

[0035] Figures 6 to 13 and Figure 14A shows a cross-sectional view in the formation of a package according to some embodiments, in which two or more dies 20' including bilateral metal pillars are employed.

[0036] Referring to Figure 6 , a carrier 42-2 is provided, on which a release film 44-2 is coated. The carrier 42-2 can be a glass carrier, a silicon wafer, an organic carrier, etc. The release film 44-2 can be formed of a polymer-based material and / or a heat-release material based on epoxy resin, such as LTHC coating. There can be a buffer dielectric layer (not shown) formed on the release film 44-2, such as a PBO layer.

[0037] Then a metal rod 60 is formed. The corresponding process is shown as process 218 in process flow 200 as shown in Figure 17 As shown in. According to some embodiments, the forming process includes: depositing a metal seed layer; forming and patterning a plating mask such as photoresist; plating a metal material in the plating mask; removing the plating mask; and removing the previously plated-mask-covered portion of the metal seed layer. The plated metal material and the remaining portion of the metal seed layer are collectively referred to as the metal rod 60.

[0038] Next, as shown in Figure 7 As shown in, packages 56 (including packages 56A and 56B) including dies 20' (including die 20'A and 20'B respectively) are placed above the carrier 42-2. The corresponding process is shown as process 220 in process flow 200 as shown in Figure 17 As shown in. The forming process of each of the packages 56A and 56B can refer to Figures 1 to 5Found. According to some embodiments, the attachment can be implemented by a die attachment film (not shown), which can be bonded to the wafer 20 before the wafer 20 is sawed into packages 56 ( Figure 5 ). According to some embodiments, packages 56A and 56B have different structures and different thicknesses, and the difference in thickness is compensated by metal posts 38 and 48, as will be discussed in the subsequent paragraphs.

[0039] According to some embodiments, after placement, the top surfaces of the metal posts 48 in die 20’A are coplanar or substantially coplanar with the top surfaces of the metal posts 48 in die 20’B (e.g., having a variation less than 10% of the height of the metal posts 38). This can be achieved by selecting the heights of the metal posts 38 and 48 to compensate for the thickness differences of the interconnect structures 28 and the semiconductor substrates 24 in dies 20’A and 20’B, as will be discussed with reference to Figure 14A discussion.

[0040] According to some embodiments, a thinning process can be implemented to remove or thin the support substrate 52. The thinning process can be implemented by a CMP process or a mechanical polishing process. Thinning can reduce the aspect ratio of the gap between packages 56A and 56B and the metal rods 60, making the subsequent gap filling process easier.

[0041] Refer to Figure 8 , packages 56A and 56B and metal rods 60 are sealed in a sealant 64. The corresponding process is shown as process 222 in process flow 200 as shown in Figure 17 . The sealant 64 can include a molding compound, a molded underfill, an epoxy resin, and / or a resin. The top surface of the sealant 64 can be higher than the top surfaces of packages 56A and 56B. When formed by a molding compound or a molded underfill, the sealant 64 can include a base material and filler particles in the base material, and the base material can be a polymer, a resin, an epoxy resin, etc. The filler particles can be dielectric particles such as SiO2, Al2O3, silica, etc., and can have a spherical shape. In addition, the spherical filler particles can have a variety of different diameters.

[0042] In a subsequent process, as shown in Figure 9 , a planarization process such as a CMP process or a mechanical grinding process is implemented to thin the sealant 64 and packages 56A and 56B. The corresponding process is shown as process 224 in process flow 200 as shown in Figure 17 . The metal rods 60 are optionally referred to as vias 60 hereinafter because they penetrate the thinned sealant 64. Since the top surfaces of the metal posts 38 in die 20’A are coplanar or substantially coplanar with the top surfaces of the metal posts 38 in die 20’B, after the planarization process, the metal posts 38 in both dies 20’A and 20’B are exposed. The vias 60 are also exposed.

[0043] Figure 10 illustrates the formation of a redistribution structure 68, which includes a dielectric layer 70 and redistribution lines (RDLs) 72 in the dielectric layer 70. The corresponding process is shown as process 226 in process flow 200 as shown in Figure 17 . The redistribution structure 68 can be formed layer by layer. For example, the formation of one layer of the RDLs 72 can include: forming the dielectric layer 70; and forming openings in the dielectric layer 70 through a patterning process. Then a metal seed layer (not shown) is deposited, and the metal seed layer includes some portions located above the dielectric layer 70 and some other portions extending into the dielectric layer 70. The dielectric layer 70 can be formed of an organic material such as PBO, polyimide, BCB, etc. or an inorganic material such as silicon oxide, silicon nitride, etc. or includes an organic material such as PBO, polyimide, BCB, etc. or an inorganic material such as silicon oxide, silicon nitride, etc. Then a patterning mask such as a photoresist is formed above the metal seed layer, followed by a metal plating process to deposit a metal material on the exposed metal seed layer. Then the patterning mask and the portions of the metal seed layer covered by the patterning mask are removed, leaving a layer of the RDLs 72.

[0044] According to some embodiments, the metal seed layer includes a titanium layer and a copper layer above the titanium layer. The metal seed layer can be formed using, for example, physical vapor deposition (PVD) or a similar process. The plating material can include copper, aluminum, cobalt, nickel, gold, silver, tungsten, or their alloys. The plating can be implemented through, for example, an electroless plating process. The dielectric layer 70 and the RDLs 72 are formed layer by layer to jointly form the redistribution structure 68.

[0045] Figure 11 illustrates the bonding of a package assembly 74 (e.g., including package assemblies 74A, 74B, and 74C) to the redistribution structure 68 according to some embodiments. The corresponding process is shown as process 228 in process flow 200 as shown in Figure 17 . The package assembly 74 can include device dies, multi-die stacks, packages, etc. According to some embodiments, the package assembly 74A is a system die including multiple device dies packaged as a system. For example, the device dies in the package assembly 74A can include logic dies and memory dies. The package assemblies 74B and 74C can be discrete device dies, or can be packages including a system, a memory stack (with memory dies bonded to form a stack), or a combination thereof. The memory stack can include a high bandwidth memory (HBM) stack.

[0046] According to some embodiments, die 20’A and 20’B are LSI dies. For example, die 20’A can electrically interconnect package components 74A and 74B through circuit path 80, and die 20’B can electrically interconnect package components 74A and 74C through circuit path 80.

[0047] Figure 16A Details of die 20’ according to some embodiments are shown, and die 20’ can be die 20’A and / or 20’B. The shown die 20’ is an LSI die. According to some embodiments of the present disclosure, die 20’ includes substrate 24. Interconnect structure 28 is formed above substrate 24 and includes dielectric layer 30 (which can include a low-k dielectric layer and an etch stop layer) and metal lines and vias 34 in dielectric layer 30.

[0048] Dielectric layer 30 can include an IMD layer. According to some embodiments of the present disclosure, some lower dielectric layers 30 are formed of a low-k dielectric material having a dielectric constant (k value) below 3.8, and the k value can be below about 3.0. Dielectric layer 30 can be formed of a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. Metal lines and vias 34 can be formed using a single damascene and / or dual damascene process.

[0049] Dielectric layer 30 can also include a passivation layer having a low k value above dielectric layer 30. The passivation layer has the function of isolating the underlying low-k dielectric layer (if any) from the adverse effects of harmful chemicals and moisture. The passivation layer can be formed of or include a non-low-k dielectric material, such as silicon oxide, silicon nitride, USG, etc. or a composite layer thereof. Metal pillars 38 and dielectric layer 40 are formed at the surface of die 20’.

[0050] According to some embodiments, die 20’ can be a bridge die for electrically and signal-interconnecting package components 74( Figure 14A 、 Figure 14B 、 Figure 14C and Figure 15 ). Metal lines and vias 34 and metal pillars 38 can jointly form a plurality of conductive paths (bridges) 80 or 80’, each including a metal pillar 38 and two of the corresponding metal lines / pads and vias 34.

[0051] According to some embodiments of the present disclosure, die 20’ further includes TSV 26 and metal pillar 48. TSV 26 can be formed of or include Cu, Al, W, etc. or their alloys. Thus, die 20’ is a bilateral device having conductive components on both the top side and the bottom side. Conductive components 38 and 48 are electrically interconnected through via 26. According to some embodiments, circuit paths 80 / 80’ can also be electrically connected to via 26 and metal pillars 38 and 48.

[0052] Further referring to Figure 11 , the sealant 78 is dispensed, cured, and planarized. The corresponding process is shown as process 230 in process flow 200 as shown in Figure 17 . The structure above the release film 44-2 is hereinafter referred to as the reconstructed wafer 82. Next, a carrier conversion process is performed, and the reconstructed wafer 82 is attached to the carrier 42-3, for example, through the release film 44-3( Figure 12 ). After the carrier conversion process, the reconstructed wafer 82 is peeled off from the carrier 42-2. Accordingly, the sealant 64 and the vias 60 can be exposed. The support substrate 52 (if remaining) can be exposed. The resulting structure is shown in Figure 12 .

[0053] Figure 13 Further shown is the formation of RDL and electrical connectors on the reconstructed wafer 82 according to some embodiments. The corresponding process is shown as process 232 in process flow 200 as shown in Figure 17 . According to some embodiments, a planarization process can be performed to remove the support substrate 52 and the layer 54, and to flush the top surface of the metal pillars 48 with the top surface of the vias 60. Next, a dielectric layer 84 is formed. According to some embodiments, the dielectric layer 84 includes polyimide, PBO, BCB, etc. Optionally, the dielectric layer 84 can be formed of an inorganic dielectric material, such as silicon oxide, silicon nitride, etc. Then, more dielectric layers 84 and RDL 83 are formed.

[0054] Then, electrical connectors 86 are formed on the surface of the reconstructed wafer 82. According to some embodiments, the electrical connectors 86 include metal pillars, solder layers, etc. The formation process can include: patterning the dielectric layer 84 to expose the metal pillars 48 and the vias 60; forming a plating mask such as a patterned photoresist; plating the electrical connectors 86 in the plating mask; removing the plating mask; and etching the previously plated mask-covered portion of the metal seed layer. When plating the solder layer, a reflow process can be performed.

[0055] In a subsequent process, the reconstructed wafer 82 can be peeled off from the carrier 42-3 and placed on a dicing tape (not shown). Then, the reconstructed wafer 82 is diced to form a plurality of packages 82'. The corresponding process is shown as process 234 in process flow 200 as shown in Figure 17 .

[0056] In a subsequent process, as shown in Figure 14A , the packages 82' can be bonded to a package assembly 94, and the package assembly 94 can be a package substrate, a printed circuit board, an interposer, another package, etc. The corresponding process is shown as process 236 in process flow 200 as shown in Figure 17 . Accordingly, the package 85 is formed.

[0057] As Figure 14A shown, the portions of the dies 20’A and 20’B that do not include the metal posts 38 and 48 may have different thicknesses from each other. For example, if die 20’B is an LSI die for interconnecting two system-in-packages that include logic dies, and die 20’A is an LSI die for interconnecting a system-in-package and a memory package, then die 20’A may have fewer wiring layers than die 20’B and may be thinner than die 20’B. Accordingly, thickness T1 is less than thickness T2, where thicknesses T1 and T2 are the thicknesses of dies 20’A and 20B’, respectively, excluding the thicknesses of the metal posts 38 and 48. According to some embodiments, the thicknesses of the semiconductor substrates 24 in dies 20’A and 20’B may have the same thickness, and thus the thickness difference (T2 - T1) may be equal to the difference in the thicknesses of the interconnect structures 28 of dies 20’A and 20’B.

[0058] In the following discussion, the metal post 38 in die 20’A is referred to as metal post 38A, and the metal post 38 in die 20’B is referred to as metal post 38B. The metal post 48 in die 20’A is referred to as metal post 48A, and the metal post 48 in die 20’B is referred to as metal post 48B. The thicknesses of metal posts 38A and 38B are denoted as H1A and H1B, respectively. The thicknesses of metal posts 48A and 48B are denoted as H2A and H2B, respectively.

[0059] As Figure 14A shown, the thickness T20’A of die 20’A is equal to the thickness T20’B of die 20’B. On the other hand, the thickness T1 of die 20’A is less than the thickness T2 of die 20’B, where thicknesses T1 and T2 are the thicknesses of dies 20’A and 20’B, respectively, excluding the thicknesses of the metal posts 38 and 48. According to some embodiments, the thicknesses of the metal posts 38 of dies 20’A and 20’B are designed according to the relation (H1A + H2A) - (H1B + H2B) = (T2 - T1). Due to process variations, e.g., variations caused by non-flatness in the CMP process, in the structure shown in Figure 14A (and Figure 14B and Figure 14C ), the value of ((H1A + H2A) - (H1B + H2B)) may be designed to be α*(T2 - T1), where the process variation factor α may be between 0.9 and 1.1.

[0060] Accordingly, the design of die 20A’ and 20B’ involves determining thicknesses T1 and T2 and then calculating thicknesses H1A, H2A, H1B, and H2B. Thicknesses T1 and T2 can be determined by estimating the thicknesses of the interconnect structure 28 and semiconductor substrate 24 of die 20’A and 20’B. Optionally, thicknesses T1 and T2 can be determined by fabricating sample die 20’A and 20’B and then measuring thicknesses T1 and T2 from the sample die 20’A and 20’B.

[0061] It should be understood that the reliability in the formation of metal pillars 38 and 48 is related to the aspect ratios of metal pillars 38 and 48. High aspect ratios may cause problems in the fabrication of metal pillars 38 and 48, especially for die 20’A, where the metal pillar heights H1A and H2A of die 20’A are greater than the heights H1B and H2B of die 20’B.

[0062] Furthermore, reducing the aspect ratio of metal pillar 38 will cause the aspect ratio of metal pillar 48 to increase, and vice versa. According to some embodiments, metal pillars 38 and 48 of both die 20’A and 20’B are designed such that for die 20’A, the aspect ratio H1A / W1A is equal to H2A / W2A. Additionally, for die 20’B, the aspect ratio H1B / W1B is equal to H2B / W2B. Using these relationships, no aspect ratio will be too high, and the reliability in the fabrication of metal pillars 38 and 48 is improved.

[0063] According to an embodiment, metal pillars are formed on both sides of each of die 20’A and 20’B. Thus, the ability to adjust the thicknesses of die 20’A and 20’B using the thickness of the metal pillars is improved. As a comparison, if metal pillar 48 is not formed and electrical connector 86 (or backside RDL) is formed to directly contact TSV 26, then metal pillar 38 must bear the full responsibility for compensating the thickness difference (T2 - T1). The height H1A and aspect ratio H1A / W1A of die 20’A may be too high and may cause reliability issues. Additionally, without the cushioning of metal pillar 48, the direct connection of electrical connector 86 to TSV 26 may cause TSV cracking problems.

[0064] According to some embodiments, in the case where the thickness difference (T2 - T1) is too large and difficult to be compensated by metal pads 38 and 48, die 20’A can adopt the structure shown in Figure 16B On the other hand, die 20’B can adopt the structure shown in Figure 16A As shown in Figure 16BAs shown, an interconnect structure 92 can be formed between the vias 26 and the metal pads 48. Thus, the thickness of die 20’A can be increased without the metal pads 38A and 38B being too tall. The formation of the interconnect structure 92 can be substantially the same as that for forming the redistribution structure 68. The interconnect structure 92 in die 20’A may not have any lateral routing metal lines and is only used for vertical connection. Thus, the vias and the metal pads in the interconnect structure are vertically aligned, with the metal pads being slightly wider than the corresponding upper and lower vias.

[0065] In the embodiment as Figure 14A shown, a dielectric layer 40 is formed to seal the metal posts 38. Thus, on one side of one of dies 20’A and 20’B, the polymer dielectric layer 40 (formed of polyimide, PBO, BCB, etc.) contacts and surrounds the metal posts 38. On the other side, the dielectric layer 50 contacts and surrounds the metal posts 48. The dielectric layer 50 can be formed of a polymer such as polyimide, PBO, BCB, etc. Optionally, the dielectric layer 50 can be formed of a molding compound, a molded underfill, an inorganic dielectric material such as SiO, SiN, etc.

[0066] Figure 14B An encapsulation 85 formed according to an alternative embodiment is shown. These embodiments are similar to Figure 14A the embodiments in

[0067] Figure 14C except that the dielectric layer 40 in one or both of dies 20’A and 20’B is not formed. Thus, the sealant 64 fills the spaces between the metal posts 38 and surrounds the metal posts 38. Figure 14A An encapsulation 85 formed according to an alternative embodiment is shown. These embodiments are similar to

[0068] Figure 15 the embodiments in Figure 14A except that instead of directly forming the dielectric layer 40 and the RDL starting from the metal posts 38 and the vias 60, a solder joint is employed. Thus, the metal posts 38 and the vias 60 are joined to the upper RDL 72 through a solder region 88. An underfill 90 can be dispensed to seal the metal posts 38 and the solder region 88 therein.

[0068] Figure 15 A top view of an encapsulation 85 according to some embodiments is shown, the encapsulation 85 including a plurality of encapsulation components 74. A die 20’ including an LSI die is located below the encapsulation components 74 ( Figure 14A 、 Figure 14B and Figure 14C ). Each of the LSI dies 20’ can electrically interconnect two (or more) adjacent encapsulation components 74. Due to the differences between the encapsulation components, the die 20’ can have different structures, and the metal posts 38 and 48 are formed to compensate for the differences in their thicknesses.

[0069] In the embodiments shown above, according to some embodiments of the present disclosure, some processes and components are discussed to form a three-dimensional (3D) package. Other components and processes may also be included. For example, test structures may be included to assist in the verification testing of 3D packages or 3DIC devices. The test structures may include, for example, test pads formed in the redistribution layer or on the substrate, which allow testing of the 3D package or 3DIC, using probes and / or probe cards, etc. The verification testing may be implemented on the intermediate structure as well as the final structure. In addition, the structures and methods disclosed herein may be used in combination with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0070] Embodiments of the present disclosure have some advantageous features. By forming metal pillars on both sides of a die having TSVs, it is easy to compensate for some high thickness differences between the dies. The TSV crack problem is reduced.

[0071] According to some embodiments of the present disclosure, a method includes forming a first die, including: forming a first metal pillar on a first side of a first semiconductor substrate of the first die; polishing the first semiconductor substrate of the first die to expose a first through hole in the first semiconductor substrate; and forming a second metal pillar on a second side of the first die, wherein the first side and the second side are on opposite sides of the first semiconductor substrate; sealing the first die in a sealant; forming a first conductive component electrically connected to the first metal pillar on the first side of the first semiconductor substrate; and forming a second conductive component electrically connected to the second metal pillar on the second side of the first semiconductor substrate.

[0072] In an embodiment, the method further includes forming a second die, including: forming a third metal pillar on a first side of a second semiconductor substrate of the second die, wherein the third metal pillar and the first metal pillar have different heights; forming a fourth metal pillar on a second side of the second die; and sealing the second die in a sealant.

[0073] In an embodiment, the method further includes: determining a first thickness of a first portion of the first die, wherein the first portion includes a first interconnect structure of the first die; determining a second thickness of a second portion of the second die, wherein the second portion includes a second interconnect structure of the second die; determining a first height of the first metal pillar and the second metal pillar; and determining a second height of the third metal pillar and the fourth metal pillar, such that a first sum of the first thickness and the first height is equal to a second sum of the second thickness and the second height.

[0074] In an embodiment, the method further includes: bonding a first encapsulation component and a second encapsulation component above a first die, wherein the first die electrically connects the first encapsulation component to the second encapsulation component. In an embodiment, forming the second metal pillar includes a plating process. In an embodiment, the first metal pillar and the second metal pillar have the same aspect ratio. In an embodiment, when the first die is sealed in a sealant, the first metal pillar is located in a polymer layer, and wherein the polymer layer is formed of a homogeneous dielectric material.

[0075] In an embodiment, the second metal pillar is located in a molding compound including a base material and filler particles in the base material. In an embodiment, the sealant is filled into the gap between the first metal pillar and an additional first metal pillar of the first die. In an embodiment, the method further includes: attaching a support substrate to the first die before the first die is sealed in the sealant.

[0076] In an embodiment, the method further includes: thinning the support substrate before the first die is sealed in the sealant. In an embodiment, the method further includes: performing a planarization process to remove the support substrate after the first die is sealed in the sealant.

[0077] According to some embodiments of the present disclosure, a structure includes: a first local interconnect die including a first semiconductor substrate; a first through hole penetrating the first semiconductor substrate; and first and second metal pillars located at opposite surfaces of the first local interconnect die, wherein at least one of the first metal pillar and the second metal pillar is electrically connected to the first through hole; a sealant, wherein the first local interconnect die is located in the sealant; a first dielectric layer contacting a first surface of the first local interconnect die; a first conductive component located in the first dielectric layer and contacting the first metal pillar; a second dielectric layer contacting a second surface of the first local interconnect die, wherein the second surface is opposite to the first surface; and a second conductive component located in the second dielectric layer and contacting the second metal pillar.

[0078] In an embodiment, the structure further includes: a second local interconnect die including a second semiconductor substrate; a second through hole penetrating the second semiconductor substrate; and third and fourth metal pillars located at opposite surfaces of the second local interconnect die, wherein the first metal pillar and the second metal pillar have a first total thickness, and the third metal pillar and the fourth metal pillar have a second total thickness different from the first total thickness.

[0079] In an embodiment, the first metal pillar and the second metal pillar have the same aspect ratio. In an embodiment, there are no active devices in the first local interconnect die. In an embodiment, the first metal pillar and the second metal pillar are copper pillars with vertical sidewalls.

[0080] According to some embodiments of the present disclosure, a structure includes: a first die, including: a first metal pillar located at a first surface of the first die; and a second metal pillar located at a second surface of the first die, wherein the second surface is opposite to the first surface, and the second metal pillar is electrically connected to the first metal pillar, and wherein the first metal pillar and the second metal pillar have a first total thickness; and a second die, including: a third metal pillar located at a third surface of the second die; and a fourth metal pillar located at a fourth surface of the second die, wherein the fourth surface is opposite to the third surface, and the fourth metal pillar is electrically connected to the third metal pillar, and wherein the third metal pillar and the fourth metal pillar have a second total thickness different from the first total thickness; and a sealant, including: a first additional surface coplanar with the first surface of the first die and the third surface of the second die; and a second additional surface coplanar with the second surface of the first die and the fourth surface of the second die.

[0081] In an embodiment, the structure further includes: a first packaging component and a second packaging component located on the same side of the sealant and electrically interconnected through the first die; and a third packaging component and a fourth packaging component located on the same side of the sealant and electrically interconnected through the second die.

[0082] In an embodiment, the first die includes a first semiconductor substrate and a first through hole, and the first through hole includes at least a part in the first semiconductor substrate, wherein the first through hole electrically connects the first metal pillar to the second metal pillar; and the second die includes a second semiconductor substrate and a second through hole, and the second through hole includes at least a part in the second semiconductor substrate, wherein the second through hole electrically connects the third metal pillar to the fourth metal pillar.

[0083] Some embodiments of the present application provide a method for forming a semiconductor structure, including: forming a first die, including: forming a first metal pillar on a first side of a first semiconductor substrate of the first die; polishing the first semiconductor substrate of the first die to expose a first through hole in the first semiconductor substrate; and forming a second metal pillar on a second side of the first die, wherein the first side and the second side are located on opposite sides of the first semiconductor substrate; sealing the first die in a sealant; forming a first conductive component electrically connected to the first metal pillar on the first side of the first semiconductor substrate; and forming a second conductive component electrically connected to the second metal pillar on the second side of the first semiconductor substrate.

[0084] In some embodiments, the method further includes forming a second die, including: forming a third metal pillar on a first side of a second semiconductor substrate of the second die, wherein the third metal pillar and the first metal pillar have different heights; forming a fourth metal pillar on a second side of the second die; and sealing the second die in the sealant.

[0085] In some embodiments, the method further includes: determining a first thickness of a first portion of the first die, wherein the first portion includes a first interconnect structure of the first die; determining a second thickness of a second portion of the second die, wherein the second portion includes a second interconnect structure of the second die; determining a first height of the first metal pillar and the second metal pillar; and determining a second height of the third metal pillar and the fourth metal pillar, such that a first sum of the first thickness and the first height is equal to a second sum of the second thickness and the second height. In some embodiments, the method further includes: bonding a first package component and a second package component over the first die, wherein the first die electrically connects the first package component to the second package component. In some embodiments, forming the second metal pillar includes a plating process. In some embodiments, the first metal pillar and the second metal pillar have the same aspect ratio. In some embodiments, when the first die is sealed in the sealant, the first metal pillar is located in a polymer layer, and wherein the polymer layer is formed of a homogeneous dielectric material. In some embodiments, the second metal pillar is located in a molding compound including a base material and filler particles in the base material. In some embodiments, the sealant is filled into a gap between the first metal pillar and an additional first metal pillar of the first die. In some embodiments, the method further includes: attaching a support substrate to the first die before the first die is sealed in the sealant. In some embodiments, the method further includes: thinning the support substrate before the first die is sealed in the sealant. In some embodiments, the method further includes: performing a planarization process to remove the support substrate after the first die is sealed in the sealant.

[0086] Some other embodiments of the present application provide a semiconductor structure, including: a first interconnect die, including: a first semiconductor substrate; a first via hole located in the first semiconductor substrate; and a first metal pillar and a second metal pillar located at opposite surfaces of the first interconnect die, wherein at least one of the first metal pillar and the second metal pillar is electrically connected to the first via hole; a sealant, wherein the first interconnect die is located in the sealant; and a metal pillar surrounded by the sealant.

[0087] In some embodiments, the semiconductor structure further includes a second interconnect die, comprising: a second semiconductor substrate; second vias penetrating the second semiconductor substrate; and third and fourth metal pillars located at opposite surfaces of the second interconnect die, wherein the first and second metal pillars have a first total thickness, and the third and fourth metal pillars have a second total thickness different from the first total thickness. In some embodiments, the first and second metal pillars have the same aspect ratio. In some embodiments, the semiconductor structure further includes: a first dielectric layer contacting a first surface of the first interconnect die; a first conductive component located in the first dielectric layer and contacting the first metal pillar; a second dielectric layer contacting a second surface of the first interconnect die, wherein the second surface is opposite to the first surface; and a second conductive component located in the second dielectric layer and contacting the second metal pillar.

[0088] Some other embodiments of the present application provide a semiconductor structure, comprising: a first die, including: a first metal pillar located at a first surface of the first die; and a second metal pillar located at a second surface of the first die, wherein the second surface is opposite to the first surface, and the second metal pillar is electrically connected to the first metal pillar, and wherein the first and second metal pillars have a first total thickness; and a second die, including: a third metal pillar located at a third surface of the second die; and a fourth metal pillar located at a fourth surface of the second die, wherein the fourth surface is opposite to the third surface, and the fourth metal pillar is electrically connected to the third metal pillar, and wherein the third and fourth metal pillars have a second total thickness different from the first total thickness.

[0089] In some embodiments, the semiconductor structure further includes a sealant, comprising: a first additional surface coplanar with the first surface of the first die and the third surface of the second die; and a second additional surface coplanar with the second surface of the first die and the fourth surface of the second die. In some embodiments, the semiconductor structure further includes: a first packaging component and a second packaging component, located on the same side of the sealant and electrically interconnected through the first die; and a third packaging component and a fourth packaging component, located on the same side of the sealant and electrically interconnected through the second die. In some embodiments, the first die includes a first semiconductor substrate and a first through-hole, the first through-hole including at least a portion in the first semiconductor substrate, wherein the first through-hole electrically connects the first metal pillar to the second metal pillar; and the second die includes a second semiconductor substrate and a second through-hole, the second through-hole including at least a portion in the second semiconductor substrate, wherein the second through-hole electrically connects the third metal pillar to the fourth metal pillar.

[0090] The features of several embodiments are outlined above so that those skilled in the art can better understand various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the embodiments of the present disclosure, and they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: Forming a first die, comprising: forming a first metal pillar on a first side of a first semiconductor substrate of the first die; polishing the first semiconductor substrate of the first die to expose a first through hole in the first semiconductor substrate; and forming a second metal pillar on a second side of the first die, wherein the first side and the second side are located on opposite sides of the first semiconductor substrate; sealing the first die in an encapsulant; forming a first conductive feature electrically connected to the first metal pillar on the first side of the first semiconductor substrate; and A second conductive feature electrically connected to the second metal pillar is formed on the second side of the first semiconductor substrate.

2. The method of claim 1 , further comprising forming a second die, comprising: forming a third metal pillar on the first side of the second semiconductor substrate of the second die, wherein the third metal pillar and the first metal pillar have different heights; forming a fourth metal pillar on a second side of the second die; and The second die is encapsulated in the encapsulant.

3. The method according to claim 2, further comprising: determining a first thickness of a first portion of the first die, wherein the first portion includes a first interconnect structure of the first die; determining a second thickness of a second portion of the second die, wherein the second portion includes a second interconnect structure of the second die; determining first heights of the first metal pillar and the second metal pillar; and Second heights of the third metal pillar and the fourth metal pillar are determined such that a first sum of the first thickness and the first height is equal to a second sum of the second thickness and the second height.

4. The method according to claim 1, further comprising: A first package component and a second package component are bonded over the first die, wherein the first die electrically connects the first package component to the second package component.

5. The method according to claim 1, wherein: Forming the second metal pillar includes a plating process.

6. The method according to claim 1, wherein: The first metal pillar and the second metal pillar have the same aspect ratio.

7. The method according to claim 1, wherein: The first metal post is located in a polymer layer when the first die is encapsulated in the encapsulant, and wherein the polymer layer is formed of a homogenous dielectric material.

8. The method according to claim 7, wherein: The second metal pillar is located in a molding compound including a base material and filler particles in the base material.

9. A semiconductor structure comprising: A first interconnect die comprising: a first semiconductor substrate; a first through hole located in the first semiconductor substrate; and a first metal pillar and a second metal pillar located at opposite surfaces of the first interconnect die, wherein at least one of the first metal pillar and the second metal pillar is electrically connected to the first via; an encapsulant, wherein the first interconnect die is located in the encapsulant; and A metal post is surrounded by the sealant.

10. A semiconductor structure comprising: The first die comprises: a first metal pillar located at a first surface of the first die; and a second metal pillar located at a second surface of the first die, wherein the second surface is opposite to the first surface and the second metal pillar is electrically connected to the first metal pillar, and wherein the first metal pillar and the second metal pillar have a first total thickness; and The second die comprises: a third metal pillar located at a third surface of the second die; and A fourth metal pillar is located at a fourth surface of the second die, wherein the fourth surface is opposite to the third surface, and the fourth metal pillar is electrically connected to the third metal pillar, and wherein the third metal pillar and the fourth metal pillar have a second total thickness different from the first total thickness.

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