High-reliability large-size chip packaging structure and electronic equipment

Abstract

The invention relates to the field of chip packaging, in particular to a high-reliability large-size chip packaging structure and electronic equipment. At least one capacitor is fixedly arranged between the substrate and the PCB, the capacitor is located in a first installation area, and the first installation area is an area corresponding to the orthographic projection of the chip on the PCB or the substrate; the height of the capacitor is larger than the height of the solder ball when the connecting solder ball is fractured, and the melting temperature of the capacitor is higher than the maximum temperature of reflow soldering. According to the invention, at least one capacitor is fixedly arranged between the substrate and the PCB, so that the downward pressure generated by downward deformation of the substrate and the downward pressure generated by gravity of the chip are supported and counteracted. Meanwhile, due to the fact that the gravity of the chip in the first installation area is maximum and the downward deformation amount of the substrate is maximum, the situation that the connecting solder balls are fractured easily occurs in the first installation area. Correspondingly, the capacitor is arranged in the first mounting area, so that the condition that the connecting solder balls are fractured can be better improved.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging, and in particular, to a large-size chip packaging structure with high reliability and an electronic device. Background Art

[0002] In emerging requirements such as the Internet of Things, artificial intelligence, high-performance computing (HPC), big data, and Industry 4.0, a large amount of data transmission and processing are required, and thus the requirements for processor performance are getting higher and higher. To meet this demand, the chips in the processor are also developing towards large size (>70mm*70mm), multi-joints, multi-chips, modularization, and three-dimensionalization. As a result, the capacity of the chips increases by 2-3 times every 2-3 years, the packaging size is constantly increasing, and the pitch of the packaging pins is constantly decreasing. The corresponding 2.5D / 3D system-level packaging form will become the standard for such large-size chips.

[0003] At the same time, since the system-level packaging involves a variety of heterogeneous materials, and the deformation characteristics of each material are different. Therefore, during the packaging thermal process, as the reflow soldering temperature changes, each material will deform according to its own expansion characteristics, resulting in a situation where large internal stresses are generated due to mutual extrusion and pulling between the materials, and thus causing the substrate to warp into a smile or a frown. At the same time, during the reflow soldering process, the connection solder balls used to connect the substrate and the PCB (Printed Circuit Board) will become in a molten state (liquid state) at high temperature. At this time, the pressure that the molten connection solder balls can withstand is limited.

[0004] However, since the substrate is in a smile warping state at high temperature, the substrate part corresponding to the center area of the chip will bulge downward, thereby forming a downward extrusion force on the molten connection solder balls. In addition, since the number of chips included in the system-level packaging is large and the size is large, the gravity of the chips will also be greatly increased, forming a greater downward extrusion force on the molten connection solder balls.

[0005] Under the action of this double extrusion force, the liquid connection solder balls are more likely to break through the surface tension and appear the failure phenomenon of cracking. And after the solder balls are broken, the overflowing liquid solder can connect adjacent solder balls, resulting in the problem of short circuit between the connection solder balls, reducing the yield of the packaging product and the reliability of the large-size chip packaging structure. Summary of the Invention

[0006] In view of this, the present invention provides a large-size chip packaging structure with high reliability and an electronic device, which at least partially solves the problem of low reliability of the large-size chip packaging structure in the prior art.

[0007] According to one aspect of the present invention, a large-sized chip packaging structure with high reliability is provided. At least one capacitor is fixedly arranged between the substrate and the PCB board. The capacitor is located in the first installation area, and the first installation area is the area corresponding to the orthographic projection of the chip on the PCB board or the substrate; the height of the capacitor is greater than the height of the solder ball when the connection solder ball fractures, and the melting temperature of the capacitor is higher than the maximum temperature of the reflow soldering.

[0008] Further, when there is one capacitor, the capacitor is arranged at the center of the first installation area.

[0009] Further, when the number of capacitors is greater than two, one of the capacitors is the central capacitor, and the capacitors other than the central capacitor are peripheral capacitors;

[0010] The central capacitor is arranged at the center of the first installation area, the peripheral capacitors are evenly arranged around the center of the first installation area, and the distance from each peripheral capacitor to the central capacitor is the same.

[0011] Further, the minimum side length of the first installation area is greater than or equal to 70 mm.

[0012] Further, the capacitor is arranged at the installation position corresponding to the connection solder ball to replace the connection solder ball.

[0013] Further, at least one compensation capacitor is included in the capacitor;

[0014] The positive electrode of the compensation capacitor is connected to the power supply pin of the target load in the chip, and the negative electrode of the compensation capacitor is connected to the ground pin of the target load to form a compensation circuit for the target load;

[0015] The compensation circuit of the target load is arranged in parallel with the power supply circuit of the target load, and the circuit length between the compensation capacitor and the connection of the power supply pin is less than the circuit length between the power supply in the power supply circuit and the connection of the power supply pin.

[0016] Further, the compensation capacitor is arranged directly below the power supply pin of the target load.

[0017] Further, the target load is connected with multiple compensation circuits, and the multiple compensation circuits are arranged in parallel.

[0018] Further, the target load includes multiple power supply pins and ground pins, and the multiple power supply pins and ground pins are arranged to form a power supply area;

[0019] The positive electrode of the compensation capacitor is connected to each power supply pin in the power supply area, and the negative electrode of the compensation capacitor is connected to each ground pin in the power supply area to form a compensation circuit for the target load;

[0020] The compensation capacitor is located at the center of the second installation area, and the second installation area is the area corresponding to the orthographic projection of the power supply area on the PCB board or the substrate.

[0021] As the second aspect of the present invention, an electronic device is further provided, including the above-mentioned high-reliability large-size chip packaging structure.

[0022] The technical solution of the present invention has at least the following beneficial effects:

[0023] In the present invention, at least one capacitor is fixedly arranged between the substrate and the PCB board to support and offset the downward pressure generated by the downward deformation of the substrate and the downward pressure generated by the gravity of the chip. At the same time, since the gravity of the chip in the first installation area is the largest and the downward deformation amount of the substrate is the largest, the connection solder balls in the first installation area are more likely to be cracked. Correspondingly, the present invention arranges the capacitor in the first installation area to better improve the situation of the connection solder balls being cracked.

[0024] And the height of the capacitor is greater than the height of the solder ball when the connection solder ball is cracked. Thus, under the support of the capacitor, it is possible to prevent the connection solder balls between the substrate and the PCB board from being over-extruded and then cracked and failing. Furthermore, it is possible to prevent the problem of short circuit between the connection solder balls, improve the yield rate of the packaging product, and improve the reliability of the large-size chip packaging structure. Description of the Drawings

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0026] Figure 1 It is a schematic cross-sectional structure diagram of a high-reliability large-size chip packaging structure in an embodiment of the present application;

[0027] Figure 2 It is a schematic layout structure diagram of capacitors in the first installation area when the number of capacitors is 5 in another embodiment of the present application;

[0028] Figure 3 It is a schematic layout structure diagram of capacitors in the first installation area when the number of capacitors is 9 in another embodiment of the present application;

[0029] Figure 4 It is a schematic circuit connection structure diagram of the compensation circuit and the power supply circuit in another embodiment of the present application;

[0030] Figure 5Schematic diagram of the pin layout of the power supply area corresponding to the target load in another embodiment of the present application, where no compensation capacitor is connected and set;

[0031] Figure 6 Schematic diagram of the pin layout of the power supply area corresponding to the target load in another embodiment of the present application, where a compensation capacitor is connected and set at the center of the power supply area;

[0032] Figure 7 Schematic diagram of the pin layout of the power supply area corresponding to the target load in another embodiment of the present application, where a compensation capacitor is connected and set in a corner area of the power supply area;

[0033] Figure 8 From right to left in sequence are Figure 5 、 Figure 7 and Figure 6 The average value fluctuation change diagram of the voltages of all power supply pins in the power supply area shown; wherein, the abscissa is time, and the ordinate is the average value of the voltages of all power supply pins.

[0034] Reference numerals

[0035] 1. Chip; 10. First installation area; 11. Power supply area; 12. Power supply pin; 13. Ground pin; 2. Substrate; 3. PCB board; 4. Capacitor; 41. Central capacitor; 42. Peripheral capacitor; 43. Compensation capacitor; 5. Connection solder ball; 6. Power supply. Detailed implementation manners

[0036] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other; and, based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present disclosure.

[0038] It should be noted that the following describes various aspects of the embodiments within the scope of the appended claims. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. Additionally, this device and / or this method can be implemented using other structures and / or functions in addition to one or more of the aspects described herein.

[0039] As an embodiment of the present invention, as Figures 1 to 3As shown, a large-size chip packaging structure with high reliability is provided. At least one capacitor 4 is fixedly arranged between a substrate 2 and a PCB board 3. The capacitor 4 is located in a first installation area 10, and the first installation area 10 is the area corresponding to the orthographic projection of the chip 1 on the PCB board 3 or the substrate 2. The height of the capacitor 4 is greater than the height of the solder ball when the connecting solder ball 5 undergoes fracturing. And the melting temperature of the capacitor 4 is higher than the maximum temperature of the reflow soldering. The capacitor 4 in this embodiment is the capacitor 4 that meets the applicable requirements of the present invention in the prior art. The capacitor 4 can be clamped between the PCB board 3 and the substrate 2 by existing fixed connection methods such as bonding or soldering.

[0040] Specifically, when there is one capacitor 4, the capacitor 4 is arranged at the center of the first installation area 10. Since the substrate 2 at the center position in the first installation area 10 warps downward the most, and the weight distribution of the chip 1 in the central area is also relatively large, when the capacitor 4 is arranged at the center position, the situation where the connecting solder ball 5 is fractured can be better prevented.

[0041] When the number of capacitors 4 is greater than two, one of the capacitors 4 is a central capacitor 41, and the capacitors 4 other than the central capacitor 41 are peripheral capacitors 42.

[0042] The central capacitor 41 is arranged at the center of the first installation area 10, the peripheral capacitors 42 are evenly arranged around the center of the first installation area 10, and the distance from each peripheral capacitor 42 to the central capacitor 41 is the same.

[0043] Generally, since the warping deformation of the substrate 2 spreads from the middle to the periphery gradually, the warping conditions at various positions on the circle with the center of the first installation area 10 as the center are basically the same. So when the number of capacitors 4 is greater than two, one of them will be arranged at the center of the circle, and the remaining ones will be arranged on the circle. Specifically, when the number of capacitors 4 is 5 and 9, they can be arranged in the ways as Figure 2 and Figure 3 shown.

[0044] For a single-chip 1 packaging structure, the first installation area 10 is the orthographic projection area of a single chip 1; for a multi-chip 1 packaging structure, the first installation area 10 is the orthographic projection area of the chip 1 installation area after multiple chips 1 are arranged and installed. And the first installation area 10 in these two cases is usually a square area. The large-size chip packaging structure described in the present invention refers to a packaging structure in which the minimum side length of the first installation area 10 is greater than or equal to 70 mm.

[0045] In the present invention, at least one capacitor 4 is fixedly arranged between the substrate 2 and the PCB board 3 to support and offset the downward pressure generated by the downward deformation of the substrate 2 and the downward pressure generated by the gravity of the chip 1. At the same time, since the gravity of the chip 1 in the first mounting area 10 is the largest and the downward deformation amount of the substrate 2 is the largest, the connection solder balls 5 in the first mounting area 10 are more likely to be cracked. Correspondingly, the capacitor 4 is arranged in the first mounting area 10 in the present invention, which can better improve the situation of the connection solder balls 5 being cracked.

[0046] And the height of the capacitor 4 is greater than the solder ball height when the connection solder balls 5 are cracked. Thus, under the support of the capacitor 4, it can prevent the connection solder balls 5 between the substrate 2 and the PCB board 3 from being over-extruded and then cracked and failing. Furthermore, it can prevent the problem of short circuit between the connection solder balls 5, improve the yield of the packaged product, and improve the reliability of the large-size chip packaging structure.

[0047] As another embodiment of the present invention, the capacitor 4 is arranged at the mounting position corresponding to the connection solder balls 5 to replace the connection solder balls 5.

[0048] Generally, when the connection solder balls 5 are connected to the substrate 2 and the PCB board 3, windows need to be opened at the corresponding positions on the substrate 2 and the PCB board 3 to expose the metal electrical connection layers in the substrate 2 and the PCB board 3, which is convenient for later welding and connecting the connection solder balls 5 and ensuring the smoothness of the circuit between the PCB board 3 and the substrate 2.

[0049] Based on the characteristics of this connection structure, now the capacitor 4 in the present invention is used to replace the connection solder balls 5 in the target area. Thus, the connection pins of the capacitor 4 can be respectively welded to the metal electrical connection layers of the PCB board 3 and the substrate 2. To realize that the capacitor 4 is fixedly clamped and connected between the PCB board 3 and the substrate 2.

[0050] At the same time, the connection method of the capacitor 4 in this embodiment can use the existing reflow soldering for connection. That is, in the process of welding and fixing the PCB board 3 and the substrate 2 through the connection solder balls 5 by reflow soldering, the fixed connection of the capacitor 4 can be completed simultaneously. Without adding a special connection process for the capacitor 4, the fixed connection of the capacitor 4 can be completed, reducing the processing difficulty of this packaging structure and facilitating manufacturing and implementation.

[0051] As another embodiment of the present invention, the capacitor 4 includes at least one compensating capacitor 43.

[0052] The positive electrode of the compensating capacitor 43 is connected to the power supply pin 12 of the target load in the chip 1, and the negative electrode of the compensating capacitor 43 is connected to the ground pin 13 of the target load to form a compensation circuit for the target load.

[0053] The compensation circuit of the target load is arranged in parallel with the power supply circuit of the target load, and the circuit length between the compensation capacitor 43 and the power supply pin 12 is less than the circuit length between the power supply 6 and the power supply pin 12 in the power supply circuit.

[0054] During the power supply process of the chip 1, due to the objective existence of power supply noise, the voltage or current reaching the power supply pin 12 of the target load is a fluctuating value. Usually, the power supply pin 12 can accept a certain range of voltage changes, but the fluctuating voltage is very likely to exceed the acceptance range of the power supply pin 12 at the peak and trough values.

[0055] Due to the influence of this power supply noise, it will cause the working voltage of the chip 1 to be unstable, and even cause problems such as the peak voltage exceeding the rated voltage and burning out the circuit devices, or the trough voltage being lower than the minimum working voltage and the circuit being unable to work normally. Thus, it affects the reliability of the normal operation of the chip 1. For the high-performance chip 1 involved in the present invention, a large voltage fluctuation may cause distortion in the high-frequency signal processing of the chip 1, thereby affecting the overall performance and normal operation of the chip 1.

[0056] Therefore, in order to further reduce the fluctuation amplitude of the power supply noise, as Figure 4 shown, in this embodiment, a compensation circuit (the circuit in the dotted line in the figure) for the target load is formed by the compensation capacitor 43. And this compensation circuit is arranged in parallel with the original power supply circuit. Since the current and voltage in the original power supply circuit are constantly changing, the compensation capacitor 43 in the compensation circuit will always be in a state of charging and discharging with the change of the current. For example, when the current in the power supply circuit decreases, the compensation capacitor 43 will discharge, thereby compensating for the decreased current. When the current in the power supply circuit increases, the compensation capacitor 43 will store electricity, thereby absorbing and reducing the increased current. Thus, the compensation circuit is equivalent to a reservoir on a river, storing water when the water level rises and discharging water when the water level drops to ensure the stability of the river water level.

[0057] At the same time, in order to more effectively compensate the voltage at the power supply pin 12 of the target load. It is required that the circuit length between the compensation capacitor 43 and the power supply pin 12 is less than the circuit length between the power supply 6 and the power supply pin 12 in the power supply circuit. This structural setting is also similar to the structural setting of a reservoir, a river, and the target water level adjustment position. Usually, the reservoir closer to the downstream target water level adjustment position can more effectively and timely adjust the water level at the downstream target position.

[0058] Respectively detect the voltages of the target loads with and without the compensation capacitor 43 as Figure 5 and Figure 6 shown, and generate a mean fluctuation change diagram of the voltages at all the power supply pins 12 in the power supply area 11, asFigure 8 as shown in the detection result diagrams at the far right and far left in the figure.

[0059] As can be seen from the detection results in the figure, for the power supply area 11 where the compensation capacitor 43 is set, the maximum voltage average value of 748.2 mv appears at 24.02 ns, and the minimum voltage average value of 716.5 mv appears at 2.539 us. For the power supply area 11 where the compensation capacitor 43 is not set, the maximum voltage average value of 748.5 mv appears at 26.75 ns, and the minimum voltage average value of 708 mv appears at 2.541 us. Thus, it can be known that setting the compensation capacitor 43 has a better effect on suppressing power supply noise.

[0060] Preferably, the compensation capacitor 43 is set directly below the power supply pin 12 of the target load. Generally, for a target load with only 1 - 3 power supply pins 12, the compensation capacitor 43 will be directly set directly below the power supply pin 12 of the target load. This can further shorten the circuit length between the compensation capacitor 43 and the power supply pin 12, and improve the ability to suppress power supply noise.

[0061] Preferably, the target load is connected with multiple compensation circuits, and the multiple compensation circuits are set in parallel. This setting is equivalent to setting multiple reservoirs on a river to improve the compensation ability of the compensation circuits for the noise in the original power supply circuit, so as to narrow the fluctuation range of the current reaching the power supply pin 12, and further suppress the power supply noise.

[0062] Generally, since the center position of the first installation area 10 is also the layout position of important functional modules in the chip 1, thus, setting the compensation capacitor 43 at the center position of the first installation area 10 can not only better prevent the occurrence of the connection solder ball 5 being fractured, but also better suppress the power supply noise of the important functional modules, so as to improve the stability and reliability of the chip 1.

[0063] As another embodiment of the present invention, the target load includes multiple power supply pins 12 and ground pins 13, and the multiple power supply pins 12 and ground pins 13 are arranged to form a power supply area 11.

[0064] For a relatively large target load, multiple different functional modules will be integrated therein, and each module needs to be powered, thus the number of power supply pins 12 of this target load will increase. After their arrangement, a square power supply area 11 will be formed, as Figure 5 shown.

[0065] The positive electrode of the compensation capacitor 43 is connected to each power supply pin 12 in the power supply area 11, and the negative electrode of the compensation capacitor 43 is connected to each ground pin 13 in the power supply area 11 to form a compensation circuit for the target load.

[0066] The compensation capacitor 43 is located at the center of the second installation area, and the second installation area is the area corresponding to the orthographic projection of the power supply area 11 on the PCB board 3 or the substrate 2.

[0067] In order to better reduce the power supply noise of the target load in this embodiment, as Figure 6 shown, it is necessary to set the compensation capacitor 43 at the center of the second installation area. This setting can ensure that the length range of the power transmission paths from the compensation capacitor 43 to each power supply pin 12 is relatively small and more balanced as much as possible. If the compensation capacitor 43 is set at a non - central position in the second installation area, such as at a corner position in the second installation area, as Figure 7 shown. At this time, the length of the power transmission path from the compensation capacitor 43 to the power supply pin 12 close to its setting position is relatively small, but the length of the power transmission path from the compensation capacitor 43 to the power supply pin 12 at the diagonal position of its setting position will increase significantly. As a result, the length range of the power transmission paths from the compensation capacitor 43 to each power supply pin 12 increases, that is, there will be longer conductive traces.

[0068] For longer conductive traces, on the one hand, since parasitic inductance is also an inherent property of conductive traces, and its qualitative relationship is that the longer the conductive trace, the greater the parasitic inductance of the conductive trace. In addition, parasitic inductance hinders the change of current in the circuit. Therefore, it will increase the inductance in the compensation circuit, and then reduce the compensation ability of the compensation capacitor 43 for the current in the power supply circuit. On the other hand, it will increase the resistance value on the conductive trace, reduce the current in the compensation circuit, and then reduce the compensation ability of the compensation circuit for the current. Under the influence of the above two factors, the ultimate intuitive manifestation is the increase in the voltage fluctuation at the target load.

[0069] Separate detections are carried out on the Figure 6 and Figure 7 shown layout methods of the compensation capacitor 43, and a mean voltage fluctuation change diagram of all power supply pins 12 in the power supply area 11 during the working process is generated, as shown in the left - most and middle detection results in Figure 8 .

[0070] Among them, in the mean voltage fluctuation change diagram corresponding to the layout form of the compensation capacitor 43 at the central position, the maximum voltage mean value of 748.2 mv appears at 24.02 ns, and the minimum voltage mean value of 716.5 mv appears at 2.539 us.

[0071] In the mean voltage fluctuation change diagram corresponding to the layout form of the compensation capacitor 43 at the corner position, the maximum voltage mean value of 748.5 mv appears at 26.75 ns, and the minimum voltage mean value of 712.2 mv appears at 2.541 us. Thus, it can be seen that the layout form of the compensation capacitor 43 at the central position always has a better effect on power supply noise.

[0072] As a second aspect of the present invention, there is also provided an electronic device, including the above-mentioned large-size chip packaging structure with high reliability.

[0073] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A large-size chip packaging structure with high reliability, characterized in that, At least one capacitor is fixedly arranged between the substrate and the PCB board, and the capacitor is located in the first installation area, and the first installation area is the area corresponding to the orthographic projection of the chip on the PCB board or the substrate; the height of the capacitor is greater than the height of the solder ball when the connecting solder ball is fractured, and the melting temperature of the capacitor is higher than the maximum temperature of the reflow soldering.

2. A high-reliability large-size chip packaging structure according to claim 1, characterized in that When there is one capacitor, the capacitor is arranged at the center of the first installation area.

3. A large-size chip packaging structure with high reliability according to claim 1, characterized in that When the number of capacitors is more than two, one of the capacitors is the central capacitor, and the capacitors other than the central capacitor are peripheral capacitors; The central capacitor is arranged at the center of the first installation area, the peripheral capacitors are evenly arranged around the center of the first installation area, and the distance from each peripheral capacitor to the central capacitor is the same.

4. A large-size chip packaging structure with high reliability according to claim 1, characterized in that The minimum side length of the first installation area is greater than or equal to 70 mm.

5. A high-reliability large-size chip packaging structure according to claim 1, characterized in that, The capacitor is arranged at the installation position corresponding to the connecting solder ball to replace the connecting solder ball.

6. A high-reliability large-size chip packaging structure according to claim 1, characterized in that, At least one compensation capacitor is included in the capacitor; The positive electrode of the compensation capacitor is connected to the power supply pin of the target load in the chip, and the negative electrode of the compensation capacitor is connected to the ground pin of the target load to form a compensation circuit for the target load; The compensation circuit of the target load is arranged in parallel with the power supply circuit of the target load, and the circuit length between the compensation capacitor and the connection of the power supply pin is less than the circuit length between the power supply in the power supply circuit and the connection of the power supply pin.

7. A large-size chip packaging structure with high reliability according to claim 6, characterized in that The compensation capacitor is arranged directly below the power supply pin of the target load.

8. A high-reliability large-size chip packaging structure according to claim 6, characterized in that, The target load is connected with a plurality of compensation circuits, and the plurality of compensation circuits are arranged in parallel.

9. A high-reliability large-size chip packaging structure according to claim 6, characterized in that, The target load includes a plurality of power supply pins and ground pins, and the plurality of power supply pins and ground pins are arranged to form a power supply area; The positive electrode of the compensation capacitor is connected to each power supply pin in the power supply area, and the negative electrode of the compensation capacitor is connected to each ground pin in the power supply area to form a compensation circuit for the target load; The compensation capacitor is located at the center of the second installation area, and the second installation area is the area corresponding to the orthographic projection of the power supply area on the PCB board or the substrate.

10. An electronic device, comprising a high-reliability large-size chip packaging structure according to any one of claims 1-9.

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