Inverter I-type three-level driving logic protection circuit and inverter

Abstract

The invention discloses an inverter I-type three-level driving logic protection circuit and an inverter, and the circuit comprises a triode push-pull assembly of which the input end is connected with an inner tube input signal; the first input end of the logic gate assembly is connected with an outer tube input signal, and the second input end is connected with the output end of the triode push-pull assembly; the delay protection module comprises a resistor, a first diode and a capacitor, one end of the resistor is connected with the output end of the triode push-pull assembly, the other end is connected with one end of the capacitor, the other end of the capacitor is grounded, and two ends of the first diode are respectively connected with two ends of the resistor; wherein the output end of the logic gate assembly is used for outputting an outer tube output signal, the output end of the delay protection module is used for outputting an inner tube output signal, the power device can be effectively protected on the hardware level through cooperative work of the logic gate assembly and the delay protection module, and then it is ensured that the system can operate stably.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly to an inverter type-I three-level drive logic protection circuit and an inverter. Background Art

[0002] Currently, power devices in an inverter type-I three-level circuit operate in series, and each device only needs to bear half of the system voltage. Therefore, the on-off logic for driving the switching tubes becomes particularly important, and it is necessary to ensure the correct switching timing of the inner and outer tubes. Once the drive logic is incorrect, it is very likely to cause overvoltage damage to the power devices, and then lead to serious consequences such as faults and equipment damage.

[0003] Traditional drive logic protection for the type-I three-level topology mainly relies on software implementation, and there is a lack of effective protection measures for power devices at the hardware level. Summary of the Invention

[0004] An object of the present invention is to at least solve one of the technical problems existing in the prior art, and provide an inverter type-I three-level drive logic protection circuit and an inverter, which can, at the hardware level, through the collaborative work of a logic gate component and a delay protection module, achieve effective protection for power devices, and thus ensure the stable operation of the system.

[0005] In a first aspect, an embodiment of the present invention provides an inverter type-I three-level drive logic protection circuit, including: a triode push-pull component, whose input end is connected to an inner tube input signal; a logic gate component, whose first input end is connected to an outer tube input signal, and whose second input end is connected to the output end of the triode push-pull component; a delay protection module, including a resistor, a first diode, and a capacitor, one end of the resistor is connected to the output end of the triode push-pull component, the other end is connected to one end of the capacitor, the other end of the capacitor is grounded, and both ends of the first diode are respectively connected to both ends of the resistor; wherein, the output end of the logic gate component is used to output an outer tube output signal, and the output end of the delay protection module is used to output an inner tube output signal.

[0006] In some embodiments, the logic gate component is an AND gate component, the end of the resistor close to the capacitor is connected to the output end of the delay protection module, the first diode is arranged in the forward direction, with the positive electrode connected to the output end of the triode push-pull component and the negative electrode connected to the output end of the delay protection module.

[0007] In some embodiments, the delay protection module further includes a second diode, which is arranged between the output end of the triode push-pull component and the resistor, the second diode is arranged in the reverse direction, with the positive electrode connected to the resistor and the negative electrode connected to the output end of the triode push-pull component.

[0008] In some embodiments, the delay protection module further includes a second diode. The second diode is disposed between the resistor and the output terminal of the delay protection module. The second diode is reversely arranged, with the positive terminal connected to the output terminal of the delay protection module and the negative terminal connected to the resistor.

[0009] In some embodiments, a high-level signal is used to turn on the corresponding switching transistor, and a low-level signal is used to turn off the corresponding switching transistor; when the input signal of the outer transistor is a high-level signal and the input signal of the inner transistor is a low-level signal, both the output signal of the outer transistor and the output signal of the inner transistor are low-level signals; when both the input signal of the outer transistor and the input signal of the inner transistor change from a high-level signal to a low-level signal, the output signal of the outer transistor changes from a high-level signal to a low-level signal, and the output signal of the inner transistor changes from a high-level signal to a low-level signal after the capacitor discharges completely.

[0010] In some embodiments, the logic gate component is an OR gate component. One end of the resistor close to the capacitor is connected to the output terminal of the delay protection module; the first diode is reversely arranged, with the positive terminal connected to the output terminal of the delay protection module and the negative terminal connected to the output terminal of the triode push-pull component.

[0011] In some embodiments, the delay protection module further includes a second diode. The second diode is disposed between the resistor and the output terminal of the delay protection module. The second diode is forwardly arranged, with the positive terminal connected to the resistor and the negative terminal connected to the output terminal of the delay protection module.

[0012] In some embodiments, the delay protection module further includes a second diode. The second diode is disposed between the output terminal of the triode push-pull component and the resistor. The second diode is forwardly arranged, with the positive terminal connected to the output terminal of the triode push-pull component and the negative terminal connected to the resistor.

[0013] In some embodiments, a low-level signal is used to turn on the corresponding switching transistor, and a high-level signal is used to turn off the corresponding switching transistor; when the input signal of the outer transistor is a low-level signal and the input signal of the inner transistor is a high-level signal, both the output signal of the outer transistor and the output signal of the inner transistor are high-level signals; when both the input signal of the outer transistor and the input signal of the inner transistor change from a low-level signal to a high-level signal, the output signal of the outer transistor changes from a low-level signal to a high-level signal, and the output signal of the inner transistor changes from a low-level signal to a high-level signal after the capacitor charges completely.

[0014] In a second aspect, an embodiment of the present invention provides an inverter, including the inverter type-I three-level drive logic protection circuit according to any one of the embodiments in the first aspect.

[0015] According to an embodiment of the present invention, an inverter type-I three-level drive logic protection circuit and an inverter are provided, which have at least the following beneficial effects: The present invention provides an inverter type-I three-level drive logic protection circuit. By introducing a triode push-pull component and a delay protection module, the stability and reliability of the system are improved. Specifically, the inverter type-I three-level drive logic protection circuit includes a triode push-pull component, a logic gate component, and a delay protection module. The first input terminal of the logic gate component is connected to the external transistor input signal, and the second input terminal is connected to the output terminal of the triode push-pull component. This means that only when both input signals are high-level, the logic gate component will output a high-level signal to control the conduction of the external transistor. At the same time, the triode push-pull component enhances the driving ability of the internal transistor input signal and transmits it to the delay protection module. Due to the existence of the delay protection module, the output signal of the internal transistor will change after an appropriate time delay. It can be understood that the resistor, the first diode, and the capacitor in the delay protection module together constitute an RC delay circuit. When the signal at the output terminal of the triode push-pull component changes, the capacitor charges or discharges through the resistor, generating a delay effect. This enables the present invention to ensure the correct switching timing and avoid overvoltage damage caused by timing problems. In summary, the inverter type-I three-level drive logic protection circuit and the inverter provided in the present invention can, at the hardware level, through the coordinated work of the logic gate component and the delay protection module, effectively protect the power devices, and thus ensure the stable operation of the system.

[0016] Other features and advantages of the present invention will be described in the following specification, and, in part, will be obvious from the specification, or will be understood by implementing the present invention. The objectives and other advantages of the present invention can be achieved and obtained by the structures specifically pointed out in the specification, the claims, and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings are used to provide a further understanding of the technical solutions of the present invention, and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the technical solutions of the present invention, and do not constitute a limitation to the technical solutions of the present invention.

[0018] The following further illustrates the present invention in conjunction with the drawings and embodiments;

[0019] Figure 1 is a schematic diagram of the inverter type-I three-level circuit provided by the embodiment of the present invention;

[0020] Figure 2 is a schematic diagram of the inverter type-I three-level drive logic protection circuit provided by the embodiment of the present invention, where the logic gate component is an AND gate component;

[0021] Figure 3It is a schematic diagram of the inverter type-I three-level drive logic protection circuit provided by the embodiment of the present invention, in which the logic gate component is an AND gate component and the second diode is reversely arranged;

[0022] Figure 4 It is another schematic diagram of the inverter type-I three-level drive logic protection circuit provided by the embodiment of the present invention, in which the logic gate component is an AND gate component and the second diode is reversely arranged;

[0023] Figure 5 It is a schematic diagram of the inverter type-I three-level drive logic protection circuit provided by the embodiment of the present invention, in which the logic gate component is an OR gate component;

[0024] Figure 6 It is a schematic diagram of the inverter type-I three-level drive logic protection circuit provided by the embodiment of the present invention, in which the logic gate component is an OR gate component and the second diode is forwardly arranged;

[0025] Figure 7 It is another schematic diagram of the inverter type-I three-level drive logic protection circuit provided by the embodiment of the present invention, in which the logic gate component is an OR gate component and the second diode is forwardly arranged. Detailed implementation manners

[0026] This part will describe in detail the specific embodiments of the present invention. The preferred embodiments of the present invention are shown in the drawings. The function of the drawings is to supplement the description in the text part of the specification, enabling people to intuitively and vividly understand each technical feature and the overall technical solution of the present invention, but it cannot be understood as a limitation on the protection scope of the present invention.

[0027] In the description of the present invention, the meaning of several is one or more, the meaning of multiple is more than two, understand greater than, less than, exceeding, etc. as not including the present number, understand above, below, within, etc. as including the present number, "any one" means one or more, "at least one of the following" and its similar expressions mean any combination of these items, including any combination of single items or plural items. If it is described as first and second, it is only for the purpose of distinguishing technical features and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence of the indicated technical features.

[0028] It should be noted that words such as setting, installing, and connecting in the embodiments of the present invention should be understood in a broad sense. Those skilled in the art can reasonably determine the specific meanings of the above words in the embodiments of the present invention in combination with the specific content of the technical solution. For example, the term "connection" can be a mechanical connection, an electrical connection, or a connection that can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium.

[0029] It should be noted that the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0030] Currently, the power devices in the inverter type-I three-level circuit operate in series, and each device only needs to bear half of the system voltage. Therefore, the on-off logic for driving the switching tubes becomes particularly important. It is necessary to ensure the correct switching timing of the inner and outer tubes. Once the driving logic is incorrect, it is very likely to cause overvoltage damage to the power devices, which may further lead to serious consequences such as faults and equipment damage. The traditional driving logic protection for the type-I three-level topology mainly relies on software implementation, and there is a lack of effective protection measures for power devices at the hardware level.

[0031] Reference Figure 1 , Figure 1 is a schematic diagram of the inverter type-I three-level circuit provided by an embodiment of the present invention. Q1, Q2, Q3, and Q4 are power switching tubes (usually IGBTs or MOSFETs), which are used to control the on-off of the current; D1 and D2 are diodes, which are used to provide a freewheeling path to prevent voltage spikes. By controlling the switching states of Q1, Q2, Q3, and Q4, three different output levels can be generated: the positive bus voltage, the zero voltage, and the negative bus voltage.

[0032] It can be understood that in the above topology, the switching tubes Q1 and Q2 are grouped together, where the switching tube Q1 is the outer tube and the switching tube Q2 is the inner tube; the switching tubes Q3 and Q4 form another group, where the switching tube Q4 is the outer tube and the switching tube Q3 is the inner tube. Of course, those skilled in the art can flexibly select other types of type-I three-level circuit forms according to actual needs. In other words, the type-I three-level driving logic protection circuit disclosed in this embodiment has wide applicability and can be adapted to any form of type-I three-level circuit structure, providing a solid and reliable guarantee and support for the stable operation of related circuit systems.

[0033] Based on this, the purpose of the present invention is to solve at least one of the technical problems existing in the prior art, and provide an inverter type-I three-level driving logic protection circuit and an inverter, which can, at the hardware level, through the collaborative work of logic gate components and delay protection modules, effectively protect power devices, and thus ensure the stable operation of the system.

[0034] Reference Figure 2 , Figure 2It is a schematic diagram of the inverter type-I three-level drive logic protection circuit provided by the embodiments of the present invention, where the logic gate component is an AND gate component; First, the embodiments of the present invention provide an inverter type-I three-level drive logic protection circuit, including: a triode push-pull component, whose input end is connected to the inner tube input signal; a logic gate component, whose first input end is connected to the outer tube input signal, and the second input end is connected to the output end of the triode push-pull component; a delay protection module, including a resistor, a first diode, and a capacitor, one end of the resistor is connected to the output end of the triode push-pull component, the other end is connected to one end of the capacitor, the other end of the capacitor is grounded, and both ends of the first diode are respectively connected to both ends of the resistor; wherein, the output end of the logic gate component is used to output the outer tube output signal, and the output end of the delay protection module is used to output the inner tube output signal.

[0035] Among them, the present invention provides an inverter type-I three-level drive logic protection circuit. By introducing a triode push-pull component and a delay protection module, the stability and reliability of the system are improved; specifically, the logic gate component is an AND gate component. The inverter type-I three-level drive logic protection circuit includes a triode push-pull component, an AND gate component, and a delay protection module. The first input end of the AND gate component is connected to the outer tube input signal, and the second input end is connected to the output end of the triode push-pull component. This means that only when both input signals are high-level, the AND gate component will output a high-level signal to control the conduction of the outer tube. At the same time, the triode push-pull component enhances the driving ability of the inner tube input signal and transmits it to the delay protection module. Due to the existence of the delay protection module, the inner tube output signal will change after an appropriate time delay.

[0036] It can be understood that the resistor, the first diode, and the capacitor in the delay protection module together constitute an RC delay circuit. When the signal at the output end of the triode push-pull component changes, the capacitor charges or discharges through the resistor, generating a delay effect, so that the present invention can ensure the correct switching timing and avoid overvoltage damage caused by delay mismatch. In summary, the inverter type-I three-level drive logic protection circuit and the inverter provided in the present invention can, at the hardware level, through the coordinated work of the AND gate component and the delay protection module, effectively protect the power devices, and thus ensure the stable operation of the system.

[0037] Such as Figure 2As shown, the input end of the triode push-pull component is connected to the inner tube input signal IN2, the output end is connected to the second input end of the AND gate component, and is also connected to the delay protection module; for the AND gate component, the first input end is connected to the outer tube input signal IN1, the second input end is connected to the output end of the triode push-pull component, and the output end is used to output the outer tube output signal OUT1; the delay protection module includes a resistor R1, a first diode D1 and a capacitor C1. One end of the resistor R1 is connected to the output end of the triode push-pull component, the other end is connected to one end of the capacitor C1, the other end of the capacitor C1 is grounded, the first diode D1 is arranged in the forward direction, the positive electrode end is connected to the output end of the triode push-pull component, and the negative electrode end is connected to the output end OUT2 of the delay protection module.

[0038] In some embodiments, the end of the resistor close to the capacitor is connected to the output end of the delay protection module, the first diode is arranged in the forward direction, the positive electrode end is connected to the output end of the triode push-pull component, and the negative electrode end is connected to the output end of the delay protection module. Among them, the outer tube input signal IN1 passes through the first input end of the AND gate component, the triode push-pull component enhances the inner tube input signal IN2, and is connected to the second input end of the AND gate component through its output end. When both input signals are at high level, the output end OUT1 of the AND gate component outputs a high level to control the conduction of the outer tube; it can be understood that after the inner tube input signal IN2 is enhanced by the triode push-pull component, it is connected to the delay protection module. The resistor R1, capacitor C1 and first diode D1 in the delay protection module work together to produce a delay effect. When the signal at the output end of the triode push-pull component changes, the capacitor C1 discharges through the resistor R1 to produce a delay effect.

[0039] It should be noted that the output end of the AND gate component is connected to the control end of the outer tube switch tube in the inverter type I three-level circuit, the output end of the delay protection module is connected to the control end of the inner tube switch tube in the inverter type I three-level circuit. The outer tube input signal is a signal used to control the switching state of the outer tube, such as Q1 or Q4, the inner tube input signal is a signal used to control the switching state of the inner tube, such as Q2 or Q3, the outer tube output signal is the outer tube control signal processed by the logic protection circuit and is used to actually drive the outer tube, and the inner tube output signal is the inner tube control signal processed by the delay protection circuit and is used to actually drive the inner tube.

[0040] In some embodiments, OUT1 is connected to the drive circuit of the outer tube to control its on or off, OUT2 is connected to the drive circuit of the inner tube to control its on or off, and a delay protection circuit is used to ensure the correct timing and prevent overvoltage damage caused by drive logic errors.

[0041] In some embodiments, the triode push-pull component is used to amplify signals or drive a load. It consists of a pair of complementary triodes. The push-pull circuit can include two triodes, one is an NPN type and the other is a PNP type. These two triodes operate in different half-cycles of the input signal. When the input signal is in the positive half-cycle, the NPN-type triode conducts, while the PNP-type triode is cut off, and the current flows from the power supply through the NPN triode to the load; when the input signal is in the negative half-cycle, the situation is reversed, the PNP-type triode conducts, and the NPN-type triode is cut off, and the current flows from the load through the PNP triode back to the power supply; this alternating working mechanism enables the entire circuit to provide continuous current throughout the signal cycle, thereby achieving effective driving of the load; in the inverter type-I three-level drive logic protection circuit, the triode push-pull component is mainly used to enhance the driving ability of the input signal IN2 of the inner tube, ensuring that even if the driving ability of the original signal is limited, the signal amplified by the push-pull component can have sufficient strength to correctly drive the subsequent logic gate circuits and other components, thereby improving the stability and reliability of the system.

[0042] Reference Figure 3 , Figure 3 FIG. is a schematic diagram of the inverter type-I three-level drive logic protection circuit provided by an embodiment of the present invention, in which the logic gate component is an AND gate component and the second diode is reversely arranged; in some embodiments, the delay protection module further includes a second diode, and the second diode is arranged between the output end of the triode push-pull component and the resistor, and the second diode is reversely arranged, with the positive end connected to the resistor and the negative end connected to the output end of the triode push-pull component.

[0043] Among them, one end of the resistor R1 is connected to the output end of the triode push-pull component, and the other end is connected to one end of the capacitor C1. The other end of the capacitor C1 is grounded. The positive end of the first diode D1 is connected to the output end of the triode push-pull component, and the negative end is connected to the end of the resistor R1 close to the capacitor. The second diode D2 is reversely arranged, with the positive end connected to the resistor R1 and the negative end connected to the output end of the triode push-pull component.

[0044] Reference Figure 4 , Figure 4 FIG. is another schematic diagram of the inverter type-I three-level drive logic protection circuit provided by an embodiment of the present invention, in which the logic gate component is an AND gate component and the second diode is reversely arranged; in some embodiments, the delay protection module further includes a second diode, and the second diode is arranged between the resistor and the output end of the delay protection module, and the second diode is reversely arranged, with the positive end connected to the output end of the delay protection module and the negative end connected to the resistor.

[0045] Among them, one end of the resistor R1 is connected to the output end of the triode push-pull component, and the other end is connected to one end of the capacitor C1; the other end of the capacitor C1 is grounded; the positive terminal of the first diode D1 is connected to the output end of the triode push-pull component, and the negative terminal is connected to the end of the resistor R1 close to the capacitor; the second diode D2 is arranged in reverse, the positive terminal is connected to the output end of the delay protection module, and the negative terminal is connected to the resistor R1.

[0046] In some embodiments, a high-level signal is used to turn on the corresponding switching tube, and a low-level signal is used to turn off the corresponding switching tube; when the outer tube input signal is a high-level signal and the inner tube input signal is a low-level signal, both the outer tube output signal and the inner tube output signal are low-level signals; when both the outer tube input signal and the inner tube input signal change from a high-level signal to a low-level signal, the outer tube output signal changes from a high-level signal to a low-level signal, and after the capacitor discharges completely, the inner tube output signal changes from a high-level signal to a low-level signal.

[0047] Among them, it can be understood that the delay protection module forms an RC delay circuit through the resistor R1, the capacitor C1 and the first diode D1. When the input signal changes, the capacitor C1 discharges through the resistor R1, generating a certain time delay, ensuring that the inner and outer tubes perform switching operations in the correct order.

[0048] A high-level signal is used to turn on the corresponding switching tube. For example, when the outer tube output signal OUT1 is a high level, the outer tube will be turned on, and a low-level signal is used to turn off the corresponding switching tube. For example, when the outer tube output signal OUT1 is a low level, the outer tube will be turned off.

[0049] Specifically, in some embodiments, a high level is defined as on, represented by "1"; a low level is defined as off, represented by "0". Considering the time difference and uncertainty between the driving signal and the turn-on and turn-off delays of the power device, it is necessary to increase the turn-off delay of the inner tube. As Figures 2 to 4 shown, the turn-off delay protection circuit is connected between the output signal OUT2 and the second input terminal of the AND gate to control the turn-off delay of the inner tube. When the input signals IN1 and IN2 are 0, 0; 0, 1; 1, 1 respectively, the output signals OUT1 and OUT2 are still 0, 0; 0, 1; 1, 1. When the input signals IN1 and IN2 are 1, 0 respectively, the output signals OUT1 and OUT2 become 0, 0, thus realizing the logic that the inner tube must also be turned on when the outer tube is turned on.

[0050] The dynamic analysis of the drive logic protection timing of the type-I three-level topology is as follows: when the input signals IN1 and IN2 change from 1, 1 to 0, 0, the output signal OUT1 immediately becomes 0; due to the action of R1 and C1, the capacitor discharges first, and after a delay time, the output signal 0UT2 changes from 1 to 0, realizing the turn-off delay of the inner tube.

[0051] Reference Figure 5 , Figure 5 is a schematic diagram of an inverter type-I three-level drive logic protection circuit provided by an embodiment of the present invention, where the logic gate component is an OR gate component; in some embodiments, the logic gate component is an OR gate component, and one end of the resistor close to the capacitor is connected to the output end of the delay protection module; the first diode is reversely arranged, with the positive terminal connected to the output end of the delay protection module and the negative terminal connected to the output end of the triode push-pull component.

[0052] Reference Figure 6 , Figure 6 is a schematic diagram of an inverter type-I three-level drive logic protection circuit provided by an embodiment of the present invention, where the logic gate component is an OR gate component and the second diode is forwardly arranged; in some embodiments, the delay protection module further includes a second diode, which is arranged between the resistor and the output end of the delay protection module, the second diode is forwardly arranged, with the positive terminal connected to the resistor and the negative terminal connected to the output end of the delay protection module.

[0053] Reference Figure 7 , Figure 7 is another schematic diagram of an inverter type-I three-level drive logic protection circuit provided by an embodiment of the present invention, where the logic gate component is an OR gate component and the second diode is forwardly arranged; in some embodiments, the delay protection module further includes a second diode, which is arranged between the output end of the triode push-pull component and the resistor, the second diode is forwardly arranged, with the positive terminal connected to the output end of the triode push-pull component and the negative terminal connected to the resistor.

[0054] It can be understood that Figures 5 to 7 is an anti-logic alternative for the above Figures 2 to 4 , which can improve the design flexibility. In this anti-logic alternative, one end of the resistor R1 is connected to the output end of the delay protection module, and the other end is connected to one end of the capacitor C1. The other end of the capacitor C1 is grounded. The first diode D1 is reversely arranged, with the positive terminal connected to the output end of the delay protection module and the negative terminal connected to the output end of the triode push-pull component. In Figure 6 , the second diode D2 is forwardly arranged, with the positive terminal connected to the resistor R1 and the negative terminal connected to the output end of the delay protection module. In Figure 7 , the second diode D2 is forwardly arranged, with the positive terminal connected to the output end of the triode push-pull component and the negative terminal connected to the resistor R1.

[0055] In some embodiments, when the logic gate component is an OR gate component, a low-level signal is used to turn on the corresponding switching transistor, and a high-level signal is used to turn off the corresponding switching transistor. When the outer tube input signal is a low-level signal and the inner tube input signal is a high-level signal, both the outer tube output signal and the inner tube output signal are high-level signals; when both the outer tube input signal and the inner tube input signal change from a low-level signal to a high-level signal, the outer tube output signal changes from a low-level signal to a high-level signal, and after the capacitor is charged, the inner tube output signal changes from a low-level signal to a high-level signal.

[0056] Specifically, in some embodiments, it is defined that a low level is for turning on, represented by "0"; a high level is for turning off, represented by "1". When the input signals IN1 and IN2 are 1, 1; 1, 0; 0, 0 respectively, the output signals OUT1 and OUT2 are still 1, 1; 1, 0; 0, 0. When the input signals IN1 and IN2 are 0, 1 respectively, the output signals OUT1 and OUT2 become 1, 1, thus realizing the logic that the inner tube must also be turned on when the outer tube is turned on.

[0057] The dynamic analysis of the driving logic protection timing of the type-I three-level topology is as follows: when the input signals IN1 and IN2 change from 0, 0 to 1, 1, the output signal OUT1 immediately becomes 1, but due to the action of R1 and C1, the capacitor is first charged, and after a delay time, the output signal OUT2 changes from 0 to 1, realizing the turn-off delay of the inner tube.

[0058] In some embodiments, the resistance value range of the resistor can be 1 to 10 Ω, which can minimize the energy loss while providing an appropriate delay, and thus reduce the impact on the current of the subsequent circuit; in addition, when selecting the package, it can be based on the Irms evaluation of the resistor in a single cycle, and 50% power margin should be reserved. For example, if a 1206 package (power is 0.25 W) is used, the actual power consumption of the resistor should not exceed 0.125 W.

[0059] In some embodiments, the capacitor can be determined in combination with the resistance value of the resistor and the required turn-off delay of the inner tube. For example, if R1 = 1 Ω and C1 = 100 nF, the theoretical turn-off delay is about 100 ns (calculation formula: R×C = 1 Ω×100 nF = 100 ns); in addition, in practical applications, the capacity attenuation of the capacitor due to changes in temperature, frequency, voltage, etc. also needs to be considered. Therefore, the final parameter size needs to be verified by experiments to determine the optimal value.

[0060] In some embodiments, diodes D1 and D2 are used to drive a logic protection circuit, whose operating frequency is the same as the driving PWM frequency. Therefore, fast recovery diodes or Schottky diodes can be used for diodes D1 and D2 to reduce the reverse recovery time and improve the efficiency. The specific current magnitudes of diodes D1 and D2 can be determined according to the operating frequency of the circuit and the capacitance value of capacitor C1. For example, the maximum forward current of the diodes should be greater than or equal to the peak current in the circuit.

[0061] In some embodiments, the main purpose of the triode push-pull component is to prevent the current of the IN2 signal source chip pin from being too large, which may cause overheating or damage. This component is mainly responsible for handling the charging and discharging current of capacitor C1. Among them, the selection of the triode can be based on the capacitance value of capacitor C1 and the peak current during its charging and discharging process to ensure that the peak current does not exceed the maximum allowable value of the triode. In addition, in addition to the traditional NPN / PNP triode combination, switching elements such as MOSFET or IGBT can also be considered as alternative solutions to provide better performance in high-frequency or high-power application scenarios.

[0062] In a second aspect, an embodiment of the present invention provides an inverter, including the inverter type-I three-level drive logic protection circuit according to any one of the embodiments in the first aspect.

[0063] The embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the scope of knowledge possessed by those of ordinary skill in the art.

Claims

1. An inverter type I three-level drive logic protection circuit, characterized in that: include: The triode push-pull component, the input end of which is connected to the internal tube input signal; A logic gate component, wherein the first input end is connected to the external tube input signal, and the second input end is connected to the output end of the triode push-pull component; The delay protection module comprises a resistor, a first diode and a capacitor, one end of the resistor is connected to the output end of the transistor push-pull component, the other end is connected to one end of the capacitor, the other end of the capacitor is grounded, and the two ends of the first diode are respectively connected to the two ends of the resistor; The output end of the logic gate component is used to output the external tube output signal, and the output end of the delay protection module is used to output the internal tube output signal.

2. The inverter I-type three-level driving logic protection circuit according to claim 1, characterized in that: The logic gate component is an AND gate component, the end of the resistor close to the capacitor is connected to the output end of the delay protection module, the first diode is set in the forward direction, the positive end is connected to the output end of the transistor push-pull component, and the negative end is connected to the output end of the delay protection module.

3. The inverter type I three-level driving logic protection circuit according to claim 2, characterized in that: The delay protection module also includes a second diode, which is arranged between the output end of the transistor push-pull component and the resistor. The second diode is reversely arranged, with a positive end connected to the resistor and a negative end connected to the output end of the transistor push-pull component.

4. The inverter type I three-level driving logic protection circuit according to claim 2, characterized in that: The delay protection module also includes a second diode, which is arranged between the resistor and the output end of the delay protection module. The second diode is reversely arranged, with a positive end connected to the output end of the delay protection module and a negative end connected to the resistor.

5. The inverter type I three-level driving logic protection circuit according to claim 2, characterized in that: A high-level signal is used to turn on the corresponding switch tube, and a low-level signal is used to turn off the corresponding switch tube; When the outer tube input signal is a high level signal and the inner tube input signal is a low level signal, the outer tube output signal and the inner tube output signal are both low level signals; when both the outer tube input signal and the inner tube input signal change from a high level signal to a low level signal, the outer tube output signal changes from a high level signal to a low level signal, and the inner tube output signal changes from a high level signal to a low level signal after the capacitor is discharged.

6. The inverter type I three-level driving logic protection circuit according to claim 1, characterized in that: The logic gate component is an OR gate component, and the end of the resistor close to the capacitor is connected to the output end of the delay protection module; the first diode is set in reverse, with the positive end connected to the output end of the delay protection module and the negative end connected to the output end of the transistor push-pull component.

7. The inverter type I three-level driving logic protection circuit according to claim 6, characterized in that: The delay protection module also includes a second diode, which is arranged between the resistor and the output end of the delay protection module. The second diode is arranged in a forward direction, with a positive end connected to the resistor and a negative end connected to the output end of the delay protection module.

8. The inverter type I three-level driving logic protection circuit according to claim 6, characterized in that: The delay protection module also includes a second diode, which is arranged between the output end of the transistor push-pull component and the resistor. The second diode is arranged in a forward direction, with a positive end connected to the output end of the transistor push-pull component and a reverse end connected to the resistor.

9. The inverter type I three-level driving logic protection circuit according to claim 6, characterized in that: A low-level signal is used to turn on the corresponding switch tube, and a high-level signal is used to turn off the corresponding switch tube; When the outer tube input signal is a low level signal and the inner tube input signal is a high level signal, the outer tube output signal and the inner tube output signal are both high level signals; when both the outer tube input signal and the inner tube input signal change from low level signals to high level signals, the outer tube output signal changes from a low level signal to a high level signal, and the inner tube output signal changes from a low level signal to a high level signal after the capacitor is fully charged.

10. An inverter, characterized in that: It comprises the inverter I-type three-level drive logic protection circuit as described in any one of claims 1 to 9.

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