Power rail power generation system

Abstract

A power rail power generation system is provided. The system includes a first power rail generator. The first power rail generator is configured to generate a first power rail voltage for the first gate driver. The first gate driver is configured to drive a switching operation of the first power switch of the first switching converter. The first power rail generator is further configured to regulate the first power rail voltage to have a substantially constant first voltage difference from the first local voltage during operation of the first switching converter.

Description

[0001] The present disclosure relates to a power rail generation system. In particular, the present disclosure relates to a power rail generation system for generating a power rail voltage for a gate driver of a switching converter.

[0002] Background

[0003] Figure 1 is a schematic diagram of a known output stage of a buck converter 100. The power stage 100 includes a high-side driver 102 for driving a high-side PMOS switch 104 and a low-side driver 106 for driving a low-side NMOS switch 108.

[0004] The high-side driver 102 includes a comparator 110 that compares the gate voltage GATEP of the PMOS switch 104 with the driver rail voltage. The low-side driver 104 includes a comparator 112 that compares the gate voltage GATEN of the NMOS switch 108 with the driver rail voltage.

[0005] The outputs of the comparators 110, 112 are used to turn off the direct drive of their respective switches 104, 108 after the gate voltage crosses a 2.5V threshold. Until the gate voltage is below the 2.5V threshold, the gate is directly driven (direct drive) by a current source from the voltage VSYS_Bi.

[0006] In Figure 1 the power rail 114 is generated by a low-dropout regulator LDO 116, and the power rail 118 is generated by an analog buffer 120.

[0007] Figure 1 The features shown are as follows:

[0008] οHS: High-side power device - PMOS

[0009] οLS: Low-side power device - NMOS

[0010] οGATEP: Gate of the high-side pass device

[0011] οGATEN: Gate of the low-side pass device

[0012] οPCHARGED: Output of the comparator of the high-side driver, which goes high only when GATEP > 2.5V threshold (i.e., VGS of HS is close to / greater than 2.5V and HS is on)

[0013] o NCHAEGED: Output of the comparator of the low-side driver, which goes high only when GATEN > 2.5V threshold (i.e., VGS of LS is close to / greater than 2.5V and LS is on)

[0014] o BBMAKE: First open then close circuit (combinational logic)

[0015] o MAG: Command signal for the magnetization coil, which changes from low to high to turn on HS

[0016] o DEMAG: Command signal to demagnetize the coil, which changes from low to high to turn on LS

[0017] o Switching frequency of BUCK, e.g., 2 MHz: This is the frequency of the power stage.

[0018] o VSYS_Bi: The switched power supply (VIN) is the same as VDD_SW

[0019] o VSS_Bi: The switched ground is the same as VSS_SW

[0020] o VDD: Clean analog power supply

[0021] o VSS: Clean analog ground

[0022] o VDD_DIG: Digital power supply

[0023] o VSS_DIG: Digital ground

[0024] o gP_cmd: HS gate command signal. If it is high, it means MAG is high and HS is turned on

[0025] o gN_cmd: LS gate command signal. If it is low, it means DEMAG is high and LS is turned on

[0026] Current imbalance between switching converters means that the gate driver circuit may not work consistently between different switching converters. Additionally, the requirement to keep LDO 116 always on consumes more than 2 μA of DC current and has low power efficiency.

[0027] Overview

[0028] It is desirable to provide a system for ensuring proper operation of a gate driver between multiple switching converters, regardless of current imbalance between the converters.

[0029] It is desirable to provide a system for a switching converter that reduces power requirements compared to known systems.

[0030] According to a first aspect of the present disclosure, there is provided a power rail power generation system, including: a first power rail generator configured to generate a first power rail voltage for a first gate driver, the first gate driver being configured to drive the switching operation of a first power switch of a first switching converter and to adjust the first power rail voltage during the operation of the first switching converter to have a substantially constant first voltage difference from a first local voltage.

[0031] Optionally, the first power switch includes a first transistor.

[0032] Optionally, the first gate driver is configured to receive a first switching signal, receive the first local voltage, receive the first power rail voltage, and output a first gate drive signal to the first power switch to drive the switching operation of the first switch.

[0033] Optionally, the first gate driver is a first high-side driver, the first power switch is a first high-side switch and the first local voltage is a first local ground voltage, or the first gate driver is a first low-side driver, the first power switch is a first low-side switch and the first local voltage is a first local power supply voltage.

[0034] Optionally, the first switching converter is a buck converter, a boost converter or a buck-boost converter.

[0035] Optionally, the first voltage difference is equal to the first local voltage minus the first power rail voltage.

[0036] Optionally, the power rail power generation system includes a code generator configured to generate a digital code and provide the digital code to the first power rail generator, wherein the first power rail generator is configured to generate the first power rail voltage using the digital code.

[0037] Optionally, the code generator includes a bit counter configured to generate the digital code.

[0038] Optionally, the bit counter is a 5-bit counter.

[0039] Optionally, the bit counter is configured to receive a first clock signal and a digital power supply voltage.

[0040] Optionally, the power rail power generation system includes a decision circuit configured to provide an up signal and a down signal to the bit counter, wherein the bit counter is configured to generate the digital code based on the up signal and the down signal.

[0041] Optionally, the determination circuit includes a first comparator configured to compare the adaptive voltage with a first reference voltage and generate a comparator output signal based on the comparison, where the up signal and the down signal depend on the comparator output signal.

[0042] Optionally, the code generator includes a first adaptive diode configured to receive a digital code and generate an adaptive voltage based on the digital code.

[0043] Optionally, the power rail generation system includes a first level shifter configured to shift the digital code into a first voltage domain before providing the digital code to the first adaptive diode.

[0044] Optionally, the first adaptive diode includes a first resistor divider, a first transistor, and a second transistor, where the first resistor divider, the first transistor, and the second transistor are arranged to generate an adaptive voltage.

[0045] Optionally, the power rail generation system includes a first current source and a first switch, where a first clean supply voltage is coupled to the determination circuit and the adaptive diode via the first switch.

[0046] Optionally, the first power rail generator includes a second adaptive diode configured to receive a digital code and generate a first power rail voltage using the digital code.

[0047] Optionally, the first power rail generator includes a second level shifter configured to shift the digital code into a second voltage domain before providing the digital code to the second adaptive diode.

[0048] Optionally, the second adaptive diode includes a second resistor divider, a third transistor, and a fourth transistor, where the second resistor divider, the third transistor, and the fourth transistor are arranged to generate the first power rail voltage.

[0049] Optionally, the first local voltage is coupled to the second adaptive diode via a first capacitor.

[0050] Optionally, the first power rail generator is configured to generate a second power rail voltage for a second gate driver, where the second gate driver is configured to drive the switching operation of a second power switch of a first switching converter and regulate the second power rail voltage during the operation of the first switching converter to have a substantially constant second voltage difference with a second local voltage.

[0051] Optionally, the first power switch includes a first transistor and / or the second power switch includes a second transistor.

[0052] Optionally, the first gate driver is configured to receive a first switching signal, receive a first local voltage, receive a first power rail voltage, and output a first gate drive signal to a first power switch to drive the switching operation of the first switch, and the second gate driver is configured to receive a second switching signal, receive a second local voltage, receive a second power rail voltage, and output a second gate drive signal to a second power switch to drive the switching operation of the second switch.

[0053] Optionally, the first gate driver is a first high-side driver, the first power switch is a first high-side switch, the first local voltage is a first local ground voltage, or the second gate driver is a second low-side driver, the second power switch is a second low-side switch, and the second local voltage is a second local power voltage.

[0054] Optionally, the first switching converter is a buck converter, a boost converter, or a buck-boost converter.

[0055] Optionally, the first voltage difference is equal to the first local voltage minus the first power rail voltage, and the second voltage difference is equal to the second local voltage minus the second power rail voltage.

[0056] Optionally, the power rail power generation system includes a code generator configured to generate a digital code and provide the digital code to a first power rail generator, where the first power rail generator is configured to generate a first power rail voltage and a second power rail voltage using the digital code.

[0057] Optionally, the code generator includes a bit counter configured to generate a digital code.

[0058] Optionally, the bit counter is a 5-bit counter.

[0059] Optionally, the bit counter is configured to receive a first clock signal and a digital power voltage.

[0060] Optionally, the power rail power generation system includes a determination circuit configured to provide an up signal and a down signal to the bit counter, where the bit counter is configured to generate a digital code based on the up signal and the down signal.

[0061] Optionally, the determination circuit includes a first comparator configured to compare an adaptive voltage with a first reference voltage and generate a comparator output signal based on the comparison, and the up signal and the down signal depend on the comparator output signal.

[0062] Optionally, the code generator includes a first adaptive diode configured to receive a digital code and generate an adaptive voltage based on the digital code.

[0063] Optionally, the power rail generation system includes a first level shifter configured to shift a digital code into a first voltage domain before providing the digital code to the first adaptive diode.

[0064] Optionally, the first adaptive diode includes a first resistor divider, a first transistor, and a second transistor, wherein the first resistor divider, the first transistor, and the second transistor are arranged to generate an adaptive voltage.

[0065] Optionally, the power rail generation system includes a first current source and a first switch, wherein a first clean power supply voltage is coupled to the decision circuit and the adaptive diode via the first switch.

[0066] Optionally, the first power rail generator includes a second adaptive diode and a third adaptive diode, the second adaptive diode being configured to receive a digital code and generate a first power rail voltage using the digital code, the third adaptive diode being configured to receive a digital code and generate a second power rail voltage using the digital code.

[0067] Optionally, the first power rail generator includes a second level shifter and a third level shifter, the second level shifter being configured to shift a digital code into a second voltage domain before providing the digital code to the second adaptive diode, the third level shifter being configured to shift a digital code into a third voltage domain before providing the digital code to the third adaptive diode.

[0068] Optionally, the second adaptive diode includes a second resistor divider, a third transistor, and a fourth transistor, wherein the second resistor divider, the third transistor, and the fourth transistor are arranged to generate the first power rail voltage, and the third adaptive diode includes a third resistor divider, a fifth transistor, and a sixth transistor, wherein the third resistor divider, the fifth transistor, and the sixth transistor are arranged to generate the second power rail voltage.

[0069] Optionally, the first local voltage is coupled to the second adaptive diode via a first capacitor, and the second local voltage is coupled to the third adaptive diode via a second capacitor.

[0070] Optionally, the power generation system includes a second power rail generator configured to generate a third power rail voltage for a third gate driver, the third gate driver being configured to drive the switching operation of a third power switch of a second switching converter and regulate the third power rail voltage during operation of the second switching converter to have a substantially constant third voltage difference from a third local voltage.

[0071] According to a second aspect of the present disclosure, there is provided an apparatus including a plurality of switching converters and a power rail power generation system. The power rail power generation system includes a plurality of power rail generators, where each switching converter includes one of the plurality of power rail generators, and each power rail generator is configured to generate a power rail voltage for a gate driver of the switching converter. The power rail generator is part of the switching converter. The gate driver is configured to drive the switching operation of a power switch of the switching converter and to adjust the power rail voltage during the operation of the switching converter to have a substantially constant voltage difference from a local voltage.

[0072] Optionally, the power rail power generation system includes a code generator configured to generate a digital code and provide the digital code to each power rail generator, where each power rail generator is configured to generate a power rail voltage using the digital code.

[0073] It will be understood that the apparatus of the second aspect may include the features set forth in the first aspect and may be combined with other features described herein.

[0074] According to a third aspect of the present disclosure, there is provided a power rail power generation method including: generating a first power rail voltage for a first gate driver configured to drive the switching operation of a first power switch of a first switching converter and, during the operation of the first switching converter, adjusting the first power rail voltage to have a substantially constant first voltage difference from a first local voltage.

[0075] It will be understood that the method of the third aspect may include the features set forth in the first aspect and / or the second aspect and may be combined with other features described herein. Brief Description of the Drawings

[0077] The present disclosure will be described in more detail below by way of example and with reference to the drawings, in which:

[0078] Figure 1 is a schematic diagram of a known output stage of a buck converter;

[0079] Figure 2 is a schematic diagram of a buck converter;

[0080] Figure 3A is a schematic diagram of a specific implementation of a first gate driver, Figure 3B is a schematic diagram of a specific implementation of a second gate driver;

[0081] Figure 4A is a schematic diagram of a power rail power generation system according to a first embodiment of the present disclosure;

[0082] Figure 4BSchematic diagram of a power rail power generation system according to a second embodiment of the present disclosure;

[0083] Figure 4C Schematic diagram of a power rail power generation system according to a third embodiment of the present disclosure;

[0084] Figure 5 Is Figure 2 Alternative schematic diagram of a buck converter;

[0085] Figure 6A Schematic diagram of a power rail power generation system according to a fourth embodiment of the present disclosure;

[0086] Figure 6B Schematic diagram of a power rail power generation system according to a fifth embodiment of the present disclosure;

[0087] Figure 7A Schematic diagram of a power rail power generation system;

[0088] Figure 7B Schematic diagram of a specific implementation of a code generator;

[0089] Figure 7C Schematic diagram of a specific implementation of an adaptive diode;

[0090] Figure 7D Schematic diagram of a specific implementation of a decision circuit;

[0091] Figure 7E Schematic diagram of a specific implementation of a power rail generator;

[0092] Figure 8A Is a graph showing the simulation results of the actual implementation of the specific implementation of the code generator as shown in Figure 7B ;

[0093] Figure 8B Is a graph showing the simulation results of the actual implementation of the specific implementation of the code generator as shown in Figure 7B ;

[0094] Figure 8C Is a graph showing the simulation results of the actual implementation of the specific implementation of the code generator as shown in Figure 7B ;

[0095] Figure 8D Is a graph showing the simulation results of the actual implementation of the specific implementation of the system as shown in Figure 7A - Figure 7E ;

[0096] Figure 8E Is a graph showing the simulation results of the actual implementation of the specific implementation of the system as shown in Figure 7A - Figure 7E ;

[0097] Figure 8F is a graph showing the simulation results of an actual implementation that shows a specific implementation of the system as Figure 7A - Figure 7E shown; and

[0098] Figure 8G is a graph showing the simulation results of an actual implementation that shows a specific implementation of the system as Figure 7A - Figure 7E shown.

[0099] Detailed description

[0100] Figure 2 is a schematic diagram of a buck converter 200 including an inductor 202, a capacitor 204, switches 206, 208, and gate drivers 210, 212. It should be understood that this schematic diagram represents a general implementation of the output stage 100, where switches 206 and 208 correspond to switches 104 and 108 respectively, and gate drivers 210 and 212 correspond to gate drivers 102 and 106 respectively.

[0101] The gate driver 210 is a high-side driver circuit. During operation, the gate driver 210 receives a command signal gP_cmd as an input and drives the switch 206 to magnetize the inductor 202.

[0102] The power rail voltage VSS_FG is used as the ground for the gate driver 210. In this example, the power rail voltage VSS_FG is 2.5V lower than the local voltage VDD_SW. Therefore, when the command signal gP_cmd goes high, the switch 206 can obtain 2.5V (gate-source voltage) VGS to fully turn on.

[0103] The gate driver 212 is a low-side driver circuit. The gate driver 212 receives a command signal gN_cmd as an input and drives the switch 208 to demagnetize the inductor 202.

[0104] In this example, the 2.5V rail of the power rail voltage is the rail required to be used as the supply rail for the gate driver 212. The 2.5V rail of the power rail voltage is 2.5V higher than the local voltage VSS_SW, such that when the command signal gN_cmd goes high, the switch 208 can obtain 2.5V VGS to fully turn on.

[0105] Figure 3A is a schematic diagram of a specific implementation of the gate driver 210. The gate driver 210 includes a comparator 300, switches S1, S2, S3, S4, S5, a resistor R1, a logic gate 304, and a level shifter 306.

[0106] During operation, the comparator compares the gate voltage GATEP and the power supply rail voltage VSS_FG (a floating rail that is 2.5V lower than VDD_SW). At the start of the magnetization cycle, GATEP discharges from VDD_SW through switch S5 and approaches VSS_FG. When GATEP crosses a threshold (which is equal to VSS_FG minus the system comparator offset threshold), the output of comparator 300 goes high, and thereby switch S3 is turned on. Switch S3 shorts VSS_FG to GATEP to turn on switch 206. During the demagnetization cycle, the command signal gP_cmd is low, thereby turning on switch S4 to pull down the voltage at the gates of switch S2 and switch S5. The discharge path of GATEP (which is switch S5) is cut off, and GATEP is pulled up to VDD_SW to ensure the turn-off of switch 206.

[0107] Figure 3B is a schematic diagram of a specific implementation of the gate driver 212. The gate driver 212 includes a comparator 308, switches S6, S7, S8, S9, S10, S11, a resistor R2, and a logic gate 310.

[0108] During operation, comparator 308 compares the gate voltage GATEN and the power supply rail voltage of the 2.5V rail. At the start of the demagnetization cycle, the gate voltage GATEN is charged through switch S9 and approaches the power supply rail voltage of the 2.5V rail. When the gate voltage GATEN crosses a threshold (which is equal to the 2.5V rail minus the system COMP offset), the output ncharged_n of comparator 308 goes low, and thereby switch S8 (PMOS) is turned on. Switch S8 (PMOS) shorts the power supply rail voltage of the 2.5V rail to the gate voltage GATEN to turn on switch 208. During demagnetization, the command signal gN_cmd is low, and thereby switch S11 is turned on to pull down the gate voltage GATEN to the local voltage VSS_SW, while the charging current source is also pulled up to the local voltage VDD_SW.

[0109] In this example, a 2.5V VGS needs to be generated for switches 206 and 208, and preferably, when switches 206 and 208 are not switching, the entire design should not consume more than 2μA of DC current.

[0110] In addition, the voltages of the power supply rails (VSS_FG and the 2.5V rail) should be well-defined relative to the local voltages (VDD_SW and VSS_SW) respectively, such that the digital logic and the comparator can operate reliably to send the correct on / off signals and ensure the proper switching sequence of the two power devices 206 and 208.

[0111] As described above, VDD is a clean analog power supply voltage. VDD_SW represents the local power supply voltage of the switching converter 200 and experiences variations due to current imbalance (e.g., due to changes in the load current).

[0112] Thus, for a system including multiple switching converters, each converter can receive the same clean power supply voltage VDD. The power supply voltage used by the switching converter will experience variations due to the operation of the switching converter. This distinction is achieved by referring to the local power supply voltage VDD_SW of a given switching converter. Due to the current imbalance between the switching converters, multiple switching converters can have different local power supply voltages VDD_SW.

[0113] Similarly, VSS represents a clean analog power supply voltage that serves as a ground voltage, where VSS_SW is the local power supply voltage of a specific switching converter and experiences variations due to current imbalance (e.g., due to changes in the load current).

[0114] As Figure 2 、 Figure 3A and Figure 3B shown, the direct drive scheme uses two power rails, one power rail for each of the drivers 210, 212. If these two power rails are generated from an LDO (VSS_FG, e.g., as Figure 1 shown - LDO 116) and an analog buffer (2.5V rail, e.g., as Figure 1 shown - buffer 120), the requirements are not met. This direct drive scheme has the following disadvantages:

[0115] · Power rail generation requires at least one LDO that is always on, consuming a DC current far exceeding 2 μA, resulting in low power efficiency.

[0116] · The problem of generating 2.5V through any LDO is determining what the ground of the LDO should be. Due to the high load current flowing through the power distribution network, the local voltage VSS_SW will have a peak - to - peak voltage variation of more than 2V, i.e., >2V of bounce. If the LDO output refers to the clean ground voltage VSS, then due to the bounce of the local voltage VSS_SW, sometimes the VGS of switch 208 will be only 1.5V (+1V bounce on VSS_SW) or 3.5V (-1V bounce on VSS_SW). Similar problems occur for switch 206 due to the bounce on the local voltage VDD_SW.

[0117] · A 1.5V VGS on a power device (e.g., one of switches 206, 208) results in an increased on - resistance R_ON, which is harmful to the efficiency of the switching converter.

[0118] · A 3.5V VGS on a power device (e.g., one of switches 206, 208) may damage the device because it violates the SOA (Safe Operating Area).

[0119] · One input of the comparator (the 2.5V rail, from the 2.5V LDO, or VSS_FG, from the buffer) is referenced to a clean ground, and the other input is from the gate of the power device, referenced to the switch ground (VSS_SW) or the switched power supply (VDD_SW). Thus, the comparator sensing the gate nodes of switches 206, 208 is always switching.

[0120] Embodiments of the present disclosure are directed to solving one or more of the above disadvantages by providing a new system for power rail generation.

[0121] Figure 4A is a schematic diagram of a power rail generation system 400 according to a first embodiment of the present disclosure. The power rail generation system 400 includes a power rail generator 402 configured to generate a power rail voltage VR1 for a gate driver 404.

[0122] During operation, the gate driver 404 drives the switching operation of a power switch 406 of a switch converter 408. The switch 406 may include a transistor. The switch converter 408 may be, for example, a buck converter, a boost converter, or a buck - boost converter.

[0123] The power rail generator 402 is further configured to regulate the power rail voltage VR1 during the operation of the switch converter 408 to have a substantially constant voltage difference ΔV1 with a local voltage VL1. The voltage difference may be provided, for example, by the following equation:

[0124] ΔV1 = VL1 - VR1 (1)

[0125] The gate driver 404 may be configured to receive a switch signal 410, receive the local voltage VL1, and output a gate drive signal 412 to the power switch 406 to drive the switching operation of the switch 406. The power switch may be referred to as a "power device".

[0126] It should be understood that the power rail generation system 400 may be used, for example, to generate the power rail voltage required for the systems described in Figure 2 , Figure 3A and Figure 3B as described.

[0127] For example, the power rail voltage VR1 can correspond to VSS_FG, and the local voltage VL1 corresponds to VDD_SW, the gate driver 404 corresponds to the gate driver 210, and the switch 406 corresponds to the switch 206. In another embodiment, the power rail voltage VR1 can correspond to the 2.5V rail, and the local voltage VL1 corresponds to VSS_SW, the gate driver 404 corresponds to the gate driver 212, and the switch 406 corresponds to the switch 208. Additionally, two implementations of the system 400 can be used to generate two power rail voltages.

[0128] Figure 4B FIG. 4 is a schematic diagram of a power rail generation system 414 according to a second embodiment of the present disclosure. Compared with the power rail generation system 400, the power rail generator 402 is further configured to generate a power rail voltage VR2 for the gate driver 416. The gate driver 416 is configured to drive the switching operation of the switch 418 of the switched-mode converter 408. The switch 418 can include a transistor.

[0129] The power rail generator 402 is further configured to regulate the power rail voltage VR2 during the operation of the switched-mode converter 408 to have a substantially constant voltage difference ΔV2 with the local voltage VL2. This voltage difference can be provided, for example, by the following equation:

[0130] ΔV2 = VL2 - VR2 (2)

[0131] The gate driver 416 can operate as described for the gate driver 404, where the gate driver receives the switching signal 420, the local voltage VL2, the power rail voltage VR2, and outputs a gate drive signal 422 for controlling the switching of the switch 418.

[0132] It should be understood that the power rail generation system 414 can be used, for example, to generate two of the power rail voltages required for the systems described in Figure 2 , Figure 3A and Figure 3B . For example, VR1 can correspond to VSS_FG, while VR2 can correspond to the 2.5V rail.

[0133] Figure 4C FIG. 5 is a schematic diagram of a power rail generation system 422 according to a third embodiment of the present disclosure. In this embodiment, there are two power rail generators 424, 426, which can each be used as any power rail generator described herein according to the understanding of those skilled in the art.

[0134] The power rail generator 424 is configured to generate a rail voltage VR3 for a switched-mode converter 428 including a gate driver 430 and a switch 432. During operation, the rail voltage VR3 is regulated by the power rail generator 424 to have a substantially constant voltage difference with the local voltage VL3.

[0135] The power rail generator 426 is configured to generate a rail voltage VR4 for use in a switching converter 434 that includes a gate driver 436 and a switch 438. During operation, the rail voltage VR4 is regulated by the power rail generator 426 to have a substantially constant voltage difference from the local voltage VL4.

[0136] Although shown for two switching converters, it should be understood that in additional embodiments, more than two power rail generators may be provided to generate power rail voltages for more than two switching converters. Additionally, as understood by one skilled in the art, in additional embodiments having multiple power rail generators, each of the power rail generators associated with a single switching converter may be configured to generate more than one power rail voltage, such as Figure 4B shown, and may be used to generate power rail voltages for high-side and low-side gate drivers.

[0137] Figure 5 is Figure 2 an alternative schematic of the buck converter 200, showing that the buck converter 200 has received a rail voltage that may be provided by the power rail generation system of the present disclosure (e.g., the power rail generation system 414 as Figure 4B shown). In this example, the power rail voltage VSS_FG_BUCK corresponds to the previously discussed power rail voltage VSS_FG and may be provided by the power rail voltage VR1. In this example, the power rail voltage VDD_2V5_BUCK corresponds to the previously discussed 2.5V rail power rail voltage and may be provided by the power rail voltage VR2.

[0138] Graph 500 shows a comparison between the local voltage VDD_SW and the power rail voltage VSS_FG_BUCK. Graph 502 shows a comparison between the local voltage VSS_SW and the power rail voltage VDD_2V5_BUCK. It can be observed that using the power generation system 414 ensures that the voltage differences ΔV1, ΔV2 provided by equations (1) and (2) respectively remain constant during operation and are independent of changes in the local voltages VDD_SW, VSS_SW.

[0139] VDD_2V5_BUCK and VSS_FG_BUCK are two local rails to each phase, which are coupled to VSS_SW and VDD_SW respectively. VDD_2V5_BUCK and VSS_FG_BUCK each maintain a 2.5V difference (VGS of the power device) from VSS_SW and VDD_SW respectively.

[0140] In summary, the power rail generator system of the present disclosure ensures that the power rail for the gate driver is well-referenced (coupled) to VDD_SW for the high-side gate driver and VSS_SW for the low-side gate driver, so that the comparator can make a correct determination of the gate voltage of the associated power switch.

[0141] As previously discussed, mismatched current flow in two different phases can cause ground imbalance or power supply bounce. If a central LDO or buffer provides the rails to all drivers (phases), each driver will be unbalanced and may get an incorrect determination during switching (e.g., it may occur when using Figure 1 the system).

[0142] The use of an LDO also means that the power rails may be severely disturbed (overshoot / undershoot) due to the rapid charging / discharging of the power device gate nodes. For example, if these two rails are from any LDO or similar design, it will suffer a large overshoot / undershoot (>1V) to support the transient current for rapid charging / discharging of the gate (<10 ns). Embodiments of the present disclosure prevent this from happening.

[0143] If we want to use an LDO / buffer to design the rails for each phase (e.g., as Figure 1 shown), then we need to design the LDO to have a very small quiescent current so that we do not exceed the current consumption specification of the target 2 μA. However, an LDO with a current consumption specification <250 nA (considering 8 output stages for driving) will not meet the ultra-fast load transient specification, which will cause the driver operation to fail. For a current consumption less than 2 μA, embodiments of the present disclosure do not cause the driver operation to fail.

[0144] In summary, embodiments of the present disclosure avoid the coupling problem of VSS_FG_BUCK to VDD_SW because there is no dependence on any central power supply for power rail generation. Specifically, embodiments of the present disclosure can locally generate the floating rail VSS_FG_BUCK inside each phase. Now, this floating rail VSS_FG_BUCK is locally coupled to VDD_SW. Similarly, for the low side, there is no longer a dependence on any central block or LDO output required by known systems. Instead, embodiments of the present disclosure can locally generate the 2.5V rail VDD_2V5_BUCK inside each phase.

[0145] Figure 6ASchematic diagram of a power rail power generation system 600 according to a fourth embodiment of the present disclosure. In this embodiment, the power rail power generation system 600 further includes a code generator 602 configured to generate a digital code D1 and provide the digital code D1 to the power rail generator 402. The power rail generator 402 is configured to use the digital code D1 to generate a power rail voltage VR1. The code generator 602 may include a bit counter 604 configured to generate the digital code D1. The bit counter 604 may be, for example, a 5-bit counter. The bit counter 604 may be configured to receive a clock signal CLK1 and a digital power supply voltage VDD_DIG.

[0146] Figure 6B Schematic diagram of a power rail power generation system 606 according to a fifth embodiment of the present disclosure. The power rail power generation system 606 includes a determination circuit 608 configured to provide an up signal UP and a down signal DOWN to the bit counter 604. The bit counter 604 is configured to generate a digital code D1 based on the signals UP and DOWN.

[0147] The determination circuit 608 may include a comparator 610 that compares an adaptive voltage VA with a reference voltage VREF and generates an output signal COUT. The signals UP and DOWN depend on the output signal COUT.

[0148] The code generator 602 may include an adaptive diode 612 configured to receive the digital code D1 and generate an adaptive voltage VA based on the digital code D1.

[0149] The power rail power generation system includes a level shifter 614 configured to shift the digital code D1 to a first voltage domain before providing the digital code D1 to the adaptive diode 612.

[0150] The main advantage of transmitting the digital code D1 and level shifting the digital code D1 to the vdd_2v5_buck domain (which may be provided by the level shifter 614, for example) is that the code D1 is not affected by power supply bounce.

[0151] Figure 7A Schematic diagram of a power rail power generation system 700 including power rail generators 702, 704, 706, where the power rail generators 702, 704, 706 are each coupled to drivers 708, 710, 712. As understood by those skilled in the art, any of the embodiments described herein may be used to implement the power rail generators 702, 704, 706.

[0152] In this example, driver rails (such as vdd_2v5_buck_1 and vss_fg_buck_1) are generated within each phase, and the driver rails are coupled to phase-specific local VDD_SW and VSS_SW. As previously discussed, locally generated power rails have the great advantage of not being corrupted or disturbed by the bounce on the VDD_SW / VSS_SW of other buck converters (BUCK) / phases of the entire chip.

[0153] In this example, a central reference code generator 602 is provided, and the central reference code generator 602 can stay in the clean power voltage VDD domain and the clean ground voltage VSS domain inside the analog core of the chip.

[0154] This code generator 602 generates a digital code D1, and the digital code D1 is sent to all buck converters (different phases) of the entire chip. In this example, three buck converters are shown.

[0155] The buck output stage receives the code D1 and uses a local power rail generator to generate local power rails within each phase using the code D1. In this example, there are 3 phases, and each phase respectively generates its own local rails vdd_2v5_buck_1 / 2 / 3 and vss_fg_buck_1 / 2 / 3.

[0156] The power rail generation system 700 can maintain the quality of the rails (vdd_2v5_buck and vss_fg_buck) by quickly delivering transient current to the output stage driver.

[0157] Additionally, zero always-on current is required inside the power rail generation system 700. The power rail generation system 700 only needs power when the buck converter output stage starts to switch.

[0158] Furthermore, the central reference code generator 602 can be enabled using a 10KHz clock, and it does not require any DC current to generate the digital code D1. This is a great advantage compared to any traditional LDO / analog buffer-based rail design method.

[0159] Figure 7B It is a schematic diagram of a specific implementation of the code generator 602. In this example, the adaptive diode 612 is labeled as ADAPTIVE N_DIODE, and the decision circuit 608 is labeled as VCOMP DECISION MAKER. The input of the adaptive diode 612 is the digital code D1 in the 2.5V domain provided by the level shifter 614. The current source 714 is coupled to the adaptive diode 612 via the switch 716. The 60μA current source 714 is the source of the diode 612, and the operation of the current source 714 is synchronized with the 10kHz clock CLK2.

[0160] The decision circuit 608 receives the adaptive voltage VA (also labeled vtap_2v5) as an input and generates two flip-flops UP (also labeled up_dig) and DOWN (also labeled down_dig).

[0161] The decision circuit 608 operates in the VDD_DIG domain and its output is sent to the 5-bit counter 604. Depending on the UP trigger or DOWN trigger, the counter 604 generates the central code D1. This central code D1 in the digital domain is the output of the central code reference generator 602. The clock signal CLK1 (also labeled clk_10k_dig) is the clock provided to the 5-bit counter 604.

[0162] Figure 7C is a schematic diagram of a specific implementation of the adaptive diode 612. The adaptive diode 612 includes a resistor divider 718 and transistors N1, N2. The resistor divider 718 and transistors N1, N2 are arranged to generate the adaptive voltage VA.

[0163] The resistor divider 718 is a programmable resistor divider and the adaptive diode 612 is an NMOS device. This resistor divider 718 is programmed by the voltage shift code (output of the counter 604) and generates the adaptive voltage VA (also labeled vtap_2v5(2.5V)), and vtap_2v5 refers to VSS.

[0164] In Figure 7B the adaptive voltage VA (also labeled vtap_2v5) is generated by the adaptive diode 612. In this embodiment, the adaptive diode 612 includes a 2.5V NMOS diode (N1, N2) and a resistor divider 718.

[0165] Digital codes are used to turn on / off the switches (2.5V domain devices) inside the programmable resistor divider 718. If the switches inside the resistor divider 718 are not turned on / off correctly, the adaptive voltage VA may be damaged.

[0166] In this example, the digital codes come from the digital domain and these digital bits are shifted up in voltage to turn on / off the switches inside the resistor divider 718 and are shifted to the 2.5V domain signal to ensure correct and reliable turn on / off of the 2.5V domain switches. The voltage shifter 614 provides this function.

[0167] The voltage shifter 614 shifts the voltage between the digital domain (e.g., VDD_DIG, VSS_DIG) to another suitable domain (e.g., VDD domain, VSS domain).

[0168] Figure 7D It is a schematic diagram of the specific implementation of the determination circuit 608. The determination circuit includes resistors RA, RB, and digital gates 720, 722.

[0169] Comparator 610 operates in the VDD_DIG domain and compares a voltage-divided version (the output of the programmed resistor divider) of the adaptive voltage VA (at the vtap_2v5 node) with a reference voltage VREF, where the reference voltage VREF is equal to 1V in this example and is provided by a bandgap reference voltage. When the voltage-divided version of vtap_2v5 is greater than the reference voltage VREF, the comparator output COUT (also labeled trigger_dig) goes high.

[0170] Figure 7E It is a schematic diagram of the specific implementation of the power rail generator 702. It should be understood that, according to the understanding of those skilled in the art, Figure 7E the implementation shown can be used to implement generator 704, generator 706, or any other generator described herein. This block is local to each phase inside the buck converter.

[0171] Power rail generator 702 includes an adaptive diode 724 that is configured to receive digital code D1 and generate a power rail voltage VR1. Power rail generator 702 includes a level shifter 726 that is configured to shift digital code D1 into a second voltage domain before providing it to the adaptive diode 724.

[0172] The adaptive diode 724 can be implemented using a resistor divider and transistors arranged as Figure 7C shown. In this example for the adaptive diode 724, the resistor divider 718 will receive digital code D1 in an appropriate voltage domain, the output will be the power rail voltage VR1 instead of the adaptive voltage VA, and the power supply voltage will be the local power supply voltage instead of the clean power supply voltage VSS as Figure 7C shown. The local voltage VL1 is coupled to the adaptive diode 724 via a capacitor 728.

[0173] Power rail generator 702 includes an adaptive diode 730 that is configured to receive digital code D1 and generate a power rail voltage VR2. Power rail generator 702 includes a level shifter 732 that is configured to shift digital code D1 into a third voltage domain before providing it to the adaptive diode 730.

[0174] The adaptive diode 730 can be used as Figure 7Cimplemented by a resistor divider and a transistor in the arrangement shown. In this example for the adaptive diode 730, the resistor divider 718 will receive the digital code D1 in the appropriate voltage domain, the output will be the power rail voltage VR2 instead of the adaptive voltage VA, and the power supply voltage will be the local power supply voltage instead of the clean power supply voltage VSS as Figure 7C shown. The local voltage VL2 is coupled to the adaptive diode 730 via a capacitor 734.

[0175] The power rail generator 702 generates VR2 (vdd_2v5_buck, the 2.5V rail for the output stage) and VR1 (vss_fg_buck, the floating rail / VSS_FG). These are two power rail voltages which, as described previously, are local for each phase.

[0176] It should be understood that in another embodiment, as would be understood by a person skilled in the art, the power rail generator may include only a single adaptive diode to provide a single power rail voltage.

[0177] This block includes two matched ADAPTIVE N_DIODEs 724, 730 which can be implemented using the same circuitry provided within the central reference code generator 602 as Figure 7B shown.

[0178] In addition, 60pF capacitors 728, 734 are connected between the generated rails and the corresponding reference rails to help meet sudden transient current demands.

[0179] The input to this block comes from the central reference code generator 602 in the VDD_DIG domain, so the level shifter 732 is used to level shift the digital code D1 up from the VDD_DIG domain to the vdd_2v5_buck domain.

[0180] The level shifted code is sent to the adaptive diode 730 which regulates a 2.5V differential (δ) from VSS_SW, so vdd_2v5_buck is always 2.5V higher than the local VSS_SW and becomes immune to any perturbations / imbalances from other buck converters on the chip.

[0181] The above description relates to low side operation and a similar operation is provided for the high side where the output of the level shifter 732 is provided to the level shifter 726 which level shifts the input code up from the vdd_2v5_buck, VSS_SW domain to the VDD_SW, vss_fg_buck domain.

[0182] The code for level shifting code_2v5_vddsw<4:0> is sent to the adaptive N_DIODE 724 coupled between VDD_SW and vss_fg_buck. This N_DIODE 724 maintains a 2.5V difference from VDD_SW, so vss_fg_buck is always lower than the local VDD_SW and becomes immune to any perturbations / imbalances from other buck converters on the chip.

[0183] The adaptive N_DIODE 730 that generates vdd_2v5_buck is given a 60μA current source that is turned on only when the buck converter is switching, i.e., when the vdd_2v5_buck rail is needed to drive the low-side switch. The adaptive diode N_DIODE 724 used to generate vss_fg_buck is given a 60μA sink current that is turned on only when the buck converter is switching, i.e., when the vss_fg_buck rail is needed to drive the high-side switch.

[0184] Even if the rise / fall times of GATEP and GATEN are less than 10ns, the local power rails are good enough to reliably drive the output stage and ensure the correct turn-on / turn-off sequence.

[0185] Figure 8A is a graph 800 showing the simulation results of the actual implementation that shows the specific implementation of the code generator 602 as Figure 7B shown.

[0186] It shows the trace en_code_gen_vdd (the enable of the code generator, which is synchronized with a 10KHz clock and has a 10μs pulse width) and the trace clk_10k_dig (the clock to a 5-bit counter, which has a 5μs pulse width). In addition, the trace of the 60μA source current to the ADAPTIVE N_DIODE and the trace of the vtap_2v5 node are also shown. It can be observed that when en_code_gen_vdd goes low, there is no current to the N_DIODE.

[0187] Figure 8B is another graph 802 showing the simulation results of the actual implementation that shows the specific implementation of the code generator 602 as Figure 7B shown.

[0188] It can be observed that the vtap_2v5 node increases in each cycle. The vtap_2v5 node voltage increases in each cycle by an increment of 1 LSB in the output (code) of the 5-bit counter. At the very beginning, the 5-bit counter is reset, so the digital code starts from 00000.

[0189] Figure 8C is another graph 804 showing the simulation results of the actual implementation that shows the specific implementation of the code generator 602 as Figure 7B shown.

[0190] Figure 8C Shows that when vtap_2v5 is greater than 2.5V, the same counter switches down 1 LSB through ADAPTIVE_N_DIODE to make the vtap_2v5 node voltage close to 2.5V. Therefore, during steady-state operation, vtap_2v5 will switch around 2.5V through the 1 LSB output of the counter because the 5-bit output will also switch 1 SLB in the steady state.

[0191] Figure 8D is a graph 806 showing the simulation results of the actual implementation that shows the specific implementation of the system as Figure 7A - Figure 7E shown.

[0192] Figure 8D Shows the simulation results from the buck converter output stage, where all control bits are shifted up in voltage to the vdd_2v5_buck level (local for each phase). In addition, the 2.5V rail of the LS, i.e., "vdd_2v5_buck", is shown together with the switch ground VSS_SW. Finally, at the bottom, we show the differential signal going to the LS gate, which is locally referenced to VSS_SW, i.e., (vdd_2v5_buck - VSS_SW).

[0193] Figure 8E is a graph 808 showing the simulation results of the actual implementation that shows the specific implementation of the system as Figure 7A - Figure 7E shown.

[0194] Figure 8E Shows the simulation results from the buck converter output stage, where all control bits are shifted up in voltage between VDD_SW and the vss_fg_buck domain (local for each phase). In addition, the 2.5V rail of the HS, i.e., "vss_fg_buck", is shown together with the switched power supply VDD_SW. Finally, at the bottom, we show the differential signal going to the HS gate, which is locally referenced to VDD_SW, i.e., (VDD_SW - vss_fg_buck).

[0195] Figure 8F is a graph 810 showing the simulation results of the actual implementation that shows the specific implementation of the system as Figure 7A - Figure 7E shown.

[0196] Figure 8F Shows that for the HS and LS, both gates switch reliably and maintain the correct on / off sequence without going sharply low or high.

[0197] Figure 8G is a graph 812 showing the simulation results of an actual implementation that shows a specific implementation of the system as Figure 7A - Figure 7E shown.

[0198] Figure 8G shows that even if the system simulates a 2.5V rail (LS) and a floating ground (HS) with an ideal voltage source and also does not consider the switching of the driver comparator (the bounce on VDD_SW and VSS_SW due to a large load current), embodiments of the present disclosure still provide superior performance.

[0199] In summary, embodiments of the present disclosure do not use / depend on any central power source, such as any central LDO. Embodiments of the present disclosure locally generate local power rails inside each phase for each buck converter in the entire chip.

[0200] Embodiments of the present disclosure do not require area-inefficient (off-chip) capacitors like known systems (any traditional LDO), which must support ultra-high-speed (<6ns) charging and the discharging of a large amount of gate capacitance of HS and LS power devices.

[0201] Embodiments of the present disclosure solve the problem of ground / power imbalance because rail generation is local for each phase. The advantage of embodiments of the present disclosure is that it can work seamlessly with the help of a central digital code. Using digital codes and level shifting is beneficial because digital codes are not affected by power / ground bounce.

[0202] Embodiments of the present disclosure do not require any always-on blocks that consume DC current. For example, a central reference code generator is turned on with a 10KHz clock that is on for 10us in time. In addition, inside the output stage, the power rail generator only uses a current source (LS rail) and a current sink (HS rail) when we start to switch the output stage (when de-asserting the tri-state).

[0203] Various improvements and modifications can be made to the above without departing from the scope of the present disclosure.

[0204] The present disclosure provides the following:

[0205] Clause 1. A power rail generation system, comprising:

[0206] A first power rail generator configured to:

[0207] generate a first power rail voltage for a first gate driver, the first gate driver being configured to drive the switching operation of a first power switch of a first switch converter; and

[0208] During operation of the first switching converter, the first power rail voltage is adjusted to have a substantially constant first voltage difference from a first local voltage.

[0209] Clause 2. The power rail power generation system according to Clause 1, further comprising:

[0210] A code generator configured to:

[0211] Generate a digital code; and

[0212] Provide the digital code to the first power rail generator;

[0213] Wherein, the first power rail generator is configured to generate the first power rail voltage using the digital code.

[0214] Clause 3. The power rail power generation system according to Clause 2, wherein the code generator includes a bit counter configured to generate the digital code.

[0215] Clause 4. The power rail power generation system according to Clause 3, wherein the bit counter is configured to receive a first clock signal and a digital power supply voltage.

[0216] Clause 5. The power rail power generation system according to Clause 4, further comprising: a determination circuit configured to provide an up signal and a down signal to the bit counter, wherein the bit counter is configured to generate the digital code based on the up signal and the down signal.

[0217] Clause 6. The power rail power generation system according to Clause 5, wherein the determination circuit includes a first comparator configured to compare an adaptive voltage with a first reference voltage and generate a comparator output signal based on the comparison, and the up signal and the down signal depend on the comparator output signal.

[0218] Clause 7. The power rail power generation system according to Clause 6, wherein the code generator includes a first adaptive diode configured to receive the digital code and generate the adaptive voltage based on the digital code.

[0219] Clause 8. The power rail power generation system according to Clause 7, further comprising a first level shifter configured to shift the digital code to a first voltage domain before providing the digital code to the first adaptive diode.

[0220] Clause 9. The power rail power generation system according to Clause 2, wherein the first power rail generator includes a second adaptive diode configured to receive the digital code and generate the first power rail voltage using the digital code.

[0221] Clause 10. The power rail power generation system according to Clause 9, wherein the first power rail generator includes a second level shifter configured to shift the digital code to a second voltage domain before providing the digital code to the second adaptive diode.

[0222] Clause 11. The power rail power generation system according to Clause 1, wherein the first power rail generator is configured to:

[0223] generate a second power rail voltage for a second gate driver configured to drive the switching operation of a second power switch of the first switching converter; and

[0224] regulate the second power rail voltage during the operation of the first switching converter to have a substantially constant second voltage difference from a second local voltage.

[0225] Clause 12. The power rail power generation system according to Clause 11, further comprising:

[0226] a code generator configured to:

[0227] generate a digital code; and

[0228] provide the digital code to the first power rail generator;

[0229] wherein the first power rail generator is configured to generate the first power rail voltage and the second power rail voltage using the digital code.

[0230] Clause 13. The power rail power generation system according to Clause 12, wherein the code generator includes a bit counter configured to generate the digital code.

[0231] Clause 14. The power rail power generation system according to Clause 13, wherein the bit counter is configured to receive a first clock signal and a digital supply voltage.

[0232] Clause 15. The power rail power generation system according to Clause 14, further comprising: a decision circuit configured to provide an up signal and a down signal to the bit counter, wherein the bit counter is configured to generate the digital code based on the up signal and the down signal.

[0233] Clause 16. The power rail power generation system according to Clause 15, wherein the determination circuit includes a first comparator configured to compare an adaptive voltage with a first reference voltage and generate a comparator output signal based on the comparison, and the up signal and the down signal depend on the comparator output signal.

[0234] Clause 17. The power rail power generation system according to Clause 12, wherein the first power rail generator includes:

[0235] A second adaptive diode configured to receive the digital code and generate the first power rail voltage using the digital code; and

[0236] A third adaptive diode configured to receive the digital code and generate the second power rail voltage using the digital code.

[0237] Clause 18. The power rail power generation system according to Clause 1, further comprising:

[0238] A second power rail generator configured to:

[0239] Generate a third power rail voltage for a third gate driver configured to drive the switching operation of a third power switch of a second switching converter; and

[0240] During the operation of the second switching converter, adjust the third power rail voltage to have a substantially constant third voltage difference from a third local voltage.

[0241] Clause 19. An apparatus comprising:

[0242] A plurality of switching converters; and

[0243] A power rail power generation system including a plurality of power rail generators; wherein:

[0244] Each of the switching converters includes one of the plurality of power rail generators; and

[0245] Each of the power rail generators is configured to:

[0246] Generate a power rail voltage for a gate driver of the switching converter, the power rail generator being part of the switching converter, the gate driver being configured to drive the switching operation of a power switch of the switching converter; and

[0247] During the operation of the switching converter, adjust the power rail voltage to have a substantially constant voltage difference from a local voltage.

[0248] Clause 20. A power rail power generation method, the method comprising:

[0249] Generating a first power rail voltage for a first gate driver configured to drive a switching operation of a first power switch of a first switched converter; and

[0250] During operation of the first switched converter, adjusting the first power rail voltage to have a substantially constant first voltage difference from a first local voltage.

Claims

1. A power rail power generation system, comprising: The first power rail generator is configured to: generating a first power rail voltage for a first gate driver configured to drive a switching operation of a first power switch of a first switching converter; as well as The first power rail voltage is regulated during operation of the first switching converter to have a substantially constant first voltage difference from a first local voltage.

2. The power rail power generation system according to claim 1, further comprising: A code generator, the code generator being configured to: Generate a digital code; as well as providing the digital code to the first power rail generator; Wherein, the first power rail generator is configured to generate the first power rail voltage using the digital code.

3. The power rail power generation system according to claim 2, wherein: The code generator includes a bit counter configured to generate the digital code.

4. The power rail power generation system according to claim 3, wherein: The bit counter is configured to receive a first clock signal and a digital supply voltage.

5. The power rail power generation system according to claim 4, further comprising: A decision circuit is configured to provide an up signal and a down signal to the bit counter, wherein the bit counter is configured to generate the digital code based on the up signal and the down signal.

6. The power rail power generation system according to claim 5, wherein: The decision circuit includes a first comparator configured to compare the adaptive voltage with a first reference voltage and generate a comparator output signal based on the comparison, the up signal and the down signal depending on the comparator output signal.

7. The power rail power generation system according to claim 6, wherein: The code generator includes a first adaptive diode configured to receive the digital code and generate the adaptive voltage based on the digital code. 8 . The power rail power generation system of claim 7 , further comprising a first level shifter configured to shift the digital code to a first voltage domain before providing the digital code to the first adaptive diode.

9. A power rail power generation system according to any preceding claim, wherein: The first power rail generator is configured to: generating a second power rail voltage for a second gate driver configured to drive a switching operation of a second power switch of the first switching converter; as well as The second power rail voltage is regulated during operation of the first switching converter to have a substantially constant second voltage difference from a second local voltage.

10. An apparatus comprising: Multiple switching converters; as well as A power rail power generation system, the power rail power generation system comprising a plurality of power rail generators; wherein: Each of the switching converters includes one of the plurality of power rail generators; and Each of the power rail generators is configured to: generating a power rail voltage for a gate driver of the switching converter, the power rail generator being part of the switching converter, the gate driver being configured to drive a switching operation of a power switch of the switching converter; as well as During operation of the switching converter, the power rail voltage is regulated to have a substantially constant voltage difference from a local voltage.

11. A power rail power generation method, the method comprising: generating a first power rail voltage for a first gate driver configured to drive a switching operation of a first power switch of a first switching converter; as well as During operation of the first switching converter, the first power rail voltage is regulated to have a substantially constant first voltage difference from a first local voltage.

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