Conversion control circuit for controlling resonant power converter and control method thereof

Abstract

A switching control circuit for controlling a resonant power converter and a control method thereof are provided. The conversion control circuit is used for controlling a resonant power converter, and the resonant power converter comprises an upper bridge transistor and a lower bridge transistor which are coupled between an input voltage and a ground potential so as to convert the input voltage into an output voltage; the resonant circuit comprises at least one resonant inductor and a resonant capacitor. The conversion control circuit includes: a sensing circuit configured to sense a resonance-related parameter related to a resonance of the resonance circuit to generate a sensing signal; and the pulse width modulation control circuit is used for generating an upper bridge driving signal and a lower bridge driving signal according to the sensing signal and a feedback signal related to the output voltage. When the feedback signal is lower than the low power threshold value, the resonant power converter enters a burst turn-off period, and the upper bridge transistor and the lower bridge transistor are turned off at the moment. The lower limit of the burst turn-off period is equal to the switching period of the upper bridge driving signal and the lower bridge driving signal.

Description

Technical Field

[0001] The present invention relates to a conversion control circuit, and particularly to a conversion control circuit for controlling a resonant power converter. The present invention also relates to a control method for controlling the above-mentioned resonant power converter. Background Art

[0002] Due to the high power conversion efficiency of resonant power converters (such as LLC resonant power converters), they are widely favored. In addition, in the information technology industry, the light-load efficiency and transient response of LLC resonant converters have also received increasing attention. The prior art "Resonant Mode Power Supply with High-Efficiency Low-Power Standby Mode" (US 6,018,467) discloses a burst mode to reduce power losses in light-load and standby operations by periodically blocking the switching signal. However, due to the high switching frequency in the light-load state, the light-load power consumption is still significant in the above prior art.

[0003] Since capacitor voltage control has a wider bandwidth, fast dynamic response, and higher efficiency under light load, it is usually a better solution. In this method, the voltage on the resonant capacitor determines the switching point for controlling the resonant tank voltage, and has a low switching frequency under light load. The prior art "Control Device for Resonant Converter" (US 9,019,725) adopts resonant capacitor voltage control. However, since the converter operates the switch according to the duty cycle and input voltage to generate a square-wave voltage for the resonant tank, the disadvantages of this prior art include: the DC component of the voltage on the resonant capacitor is directly related to the duty cycle and input voltage of the converter. In an operation with a duty cycle of 50%, the DC value of the voltage on the resonant capacitor is equal to half of the supply voltage, which means that any deviation in sensing the DC component will affect the duty cycle and thus cause the malfunction of the resonant power converter.

[0004] Figure 1A Shows a waveform diagram of a prior art resonant power converter operating at a duty cycle of 50%. Figure 1B Shows a waveform diagram of a prior art resonant power converter operating at a non-50% duty cycle. Figure 1A And Figure 1B Shows the waveforms of the secondary-side current Isecondary, the voltage across the resonant capacitor Vcr, the primary-side switching signal Vsw, the primary-side current Iprimary, and the magnetizing inductor current ILM. As Figure 1B shown, if the resonant power converter operates at a non-50% duty cycle, the operation result will cause unbalanced current to be delivered to the secondary side, which will result in poor power efficiency.

[0005] Another prior art, "Resonant Converter Control Based on Voltage Difference" (US 9,065,350), discloses a method of sampling the voltage difference of a resonant capacitor. This method does not require canceling the DC component of the resonant capacitor voltage. However, due to the small voltage difference in the light load state, it may face challenges in operation in the light load state.

[0006] In view of the above situation, in order to overcome the disadvantages of the prior art, the present invention proposes a control method and a conversion control circuit to solve the above problems. The present invention provides precise capacitor voltage control, including burst mode operation of an LLC resonant power converter. Summary of the Invention

[0007] In one aspect, the present invention provides a conversion control circuit for controlling a resonant power converter, where the resonant power converter includes: an upper bridge transistor and a lower bridge transistor, sequentially connected in series between an input voltage and a ground potential to form a half-bridge circuit; and a resonant circuit including at least one resonant inductor and a resonant capacitor, where the upper bridge transistor and the lower bridge transistor are used to switch the resonant circuit to convert the input voltage into an output voltage; where the conversion control circuit includes: a sensing circuit for sensing a resonant-related parameter having a resonant state to generate a sensing signal, where the resonant-related parameter is related to the resonance generated by the resonant circuit; and a pulse width modulation (PWM) control circuit for generating an upper bridge drive signal and a lower bridge drive signal according to the sensing signal and a feedback signal to respectively control the upper bridge transistor and the lower bridge transistor, thereby switching the resonant circuit to generate the output voltage; where the feedback signal is related to an output power of the output voltage; where when the feedback signal is lower than a low power threshold, the resonant power converter enters a burst OFF period, during which both the upper bridge transistor and the lower bridge transistor are turned off; where the burst OFF period is equal to or greater than a conduction period of the upper bridge drive signal plus a conduction period of the lower bridge drive signal.

[0008] In a preferred embodiment, the resonant power converter also enters the burst OFF period when a current sensing signal exceeds an over-current threshold, where the current sensing signal is related to the sensing signal.

[0009] In a preferred embodiment, the resonant-related parameter includes one of the following: (1) a resonant voltage on the resonant capacitor; or (2) a resonant current flowing through the resonant capacitor or the at least one resonant inductor.

[0010] In a preferred embodiment, the sensing circuit includes one of the following: (1) a differentiator circuit coupled to the resonant capacitor for generating the sensing signal related to the resonant current; or (2) a direct current resistance (DCR) sensing circuit coupled in parallel to one of the at least one resonant inductor and for generating the sensing signal related to the resonant current.

[0011] In a preferred embodiment, the starting point of the burst-off period is synchronized with the time point when the upper bridge transistor turns off, and its ending point is synchronized with the time point when the lower bridge transistor turns on.

[0012] In a preferred embodiment, the ending point of the burst-off period is further synchronized with a zero-current point of a current sensing signal, thereby reducing the conduction loss when the lower bridge transistor conducts; wherein the current sensing signal is related to the sensing signal; wherein when the ending point of the burst-off period is synchronized with the zero-current point of the current sensing signal, the burst-off period is equal to or greater than a quasi-resonant period, wherein the quasi-resonant period is related to the synchronization of the zero-current point of the current sensing signal.

[0013] In a preferred embodiment, when the burst-off period exceeds an overtime period threshold, the ending point of the burst-off period is not synchronized with the zero-current point of the current sensing signal.

[0014] In a preferred embodiment, the duration of the burst-off period increases as the output power of the output voltage decreases.

[0015] In a preferred embodiment, the PWM control circuit includes: a soft-start circuit for enabling a soft-start power supply startup sequence during which the feedback signal gradually increases; wherein the PWM control circuit is used to generate the upper bridge drive signal and the lower bridge drive signal according to the sensing signal and a compensation signal, wherein the compensation signal is generated by subtracting a ramp signal from the feedback signal.

[0016] In a preferred embodiment, the conversion control circuit further includes a full-wave rectifier circuit for canceling a DC component of the sensing signal according to an offset signal and for full-wave rectifying the sensing signal to generate a rectified sensing signal; wherein the PWM control circuit is used to generate the upper bridge drive signal and the lower bridge drive signal according to a comparison between the rectified sensing signal and a compensation signal, wherein the compensation signal is related to the feedback signal.

[0017] In a preferred embodiment, the full-wave rectifier circuit is further used to adjust a DC bias of the rectified sensing signal according to the offset signal.

[0018] In a preferred embodiment, the offset signal is adjusted based on the difference between a duty cycle of the upper-bridge driving signal and a duty cycle of the lower-bridge driving signal, thereby adjusting and matching the duty cycle of the upper-bridge driving signal and the duty cycle of the lower-bridge driving signal.

[0019] In a preferred embodiment, the offset signal includes a bias voltage, wherein the bias voltage is generated by a resistor divider connected to the input voltage.

[0020] In a preferred embodiment, the conversion control circuit further includes a calibration circuit for adjusting the duty cycle of the upper-bridge driving signal to match the duty cycle of the lower-bridge driving signal, or for adjusting the duty cycle of the lower-bridge driving signal to match the duty cycle of the upper-bridge driving signal.

[0021] In a preferred embodiment, the PWM control circuit is further configured to generate a phase signal, wherein the phase signal is set and enabled according to a cross signal, and the cross signal is generated when the integrated sensing signal is lower than a low voltage threshold; wherein when the integrated sensing signal exceeds the compensation signal, the phase signal is reset and disabled.

[0022] In a preferred embodiment, when the upper-bridge driving signal is turned on and the phase signal is enabled, if the integrated sensing signal intersects with the compensation signal, the upper-bridge driving signal is turned off, and after a first dead time, the lower-bridge driving signal is turned on; wherein when the lower-bridge driving signal is turned on and the phase signal is enabled, if the integrated sensing signal intersects with the compensation signal, the lower-bridge driving signal is turned off, and after a second dead time, the upper-bridge driving signal is turned on.

[0023] In a preferred embodiment, the pulse widths of the upper-bridge driving signal and the lower-bridge driving signal are limited to a maximum conduction time to limit a switching cycle time to be shorter than a resonance period of the resonant circuit, wherein the switching cycle time includes the conduction period and the non-conduction period of the upper-bridge driving signal or the lower-bridge driving signal.

[0024] In a preferred embodiment, when the input voltage is lower than a low voltage threshold and the output power is higher than an overload threshold, the maximum conduction time is extended such that the switching cycle time can be optionally longer than a resonance period of the resonant circuit, wherein the switching cycle time includes the conduction period and the non-conduction period of the upper-bridge driving signal or the lower-bridge driving signal.

[0025] In another aspect, the present invention provides a conversion control circuit for controlling a resonant power converter, where the resonant power converter includes: an upper bridge transistor and a lower bridge transistor, serially connected in sequence between an input voltage and a ground potential to form a half-bridge circuit; and a resonant circuit including at least one resonant inductor and a resonant capacitor, where the upper bridge transistor and the lower bridge transistor are used to switch the resonant circuit to convert the input voltage into an output voltage; where the conversion control circuit includes: a sensing circuit for sensing a resonant-related parameter having a resonant state to generate a sensing signal, where the resonant-related parameter is related to the resonance generated by the resonant circuit; a pulse width modulation (PWM) control circuit for generating an upper bridge drive signal and a lower bridge drive signal according to the sensing signal and a feedback signal to respectively control the upper bridge transistor and the lower bridge transistor, thereby switching the resonant circuit to generate the output voltage; where the feedback signal is related to an output power of the output voltage; and a full-wave rectifier circuit for canceling a DC component of the sensing signal according to an offset signal and for performing full-wave rectification on the sensing signal to generate a rectified sensing signal; where the PWM control circuit is further used to generate the upper bridge drive signal and the lower bridge drive signal according to a comparison between the rectified sensing signal and a compensation signal, where the compensation signal is related to the feedback signal.

[0026] In another aspect, the present invention provides a control method for controlling a resonant power converter, where the resonant power converter includes: an upper bridge transistor and a lower bridge transistor, serially connected in sequence between an input voltage and a ground potential to form a half-bridge circuit; and a resonant circuit including at least one resonant inductor and a resonant capacitor, where the upper bridge transistor and the lower bridge transistor are used to switch the resonant circuit to convert the input voltage into an output voltage; where the control method includes: sensing a resonant-related parameter having a resonant state to generate a sensing signal, where the resonant-related parameter is related to the resonance generated by the resonant circuit; generating an upper bridge drive signal and a lower bridge drive signal according to the sensing signal and a feedback signal to respectively control the upper bridge transistor and the lower bridge transistor, thereby switching the resonant circuit to generate the output voltage; where the feedback signal is related to an output power of the output voltage; and when the feedback signal is lower than a low power threshold, causing the resonant power converter to enter a burst OFF period, during which both the upper bridge transistor and the lower bridge transistor are turned off; where the burst OFF period is equal to or greater than a conduction time of the upper bridge drive signal plus a conduction time of the lower bridge drive signal.

[0027] In another aspect, the present invention provides a control method for controlling a resonant power converter, wherein the resonant power converter includes: an upper bridge transistor and a lower bridge transistor, sequentially connected in series between an input voltage and a ground potential to form a half-bridge circuit; and a resonant circuit including at least one resonant inductor and a resonant capacitor, wherein the upper bridge transistor and the lower bridge transistor are used to switch the resonant circuit to convert the input voltage into an output voltage; wherein the control method includes: sensing a resonant-related parameter having a resonant state to generate a sensing signal, wherein the resonant-related parameter is related to the resonance generated by the resonant circuit; generating an upper bridge driving signal and a lower bridge driving signal according to the sensing signal and a feedback signal to respectively control the upper bridge transistor and the lower bridge transistor, thereby switching the resonant circuit to generate the output voltage; wherein the feedback signal is related to an output power of the output voltage; generating a rectified sensing signal, the steps of which include: canceling a DC component of the sensing signal according to an offset signal; and performing full-wave rectification on the sensing signal to generate the rectified sensing signal; wherein the steps of generating the upper bridge driving signal and the lower bridge driving signal are also performed according to a comparison between the rectified sensing signal and a compensation signal, wherein the compensation signal is related to the feedback signal.

[0028] The following will be described in detail through specific embodiments to more easily understand the purpose, technical content, features and achieved effects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1A A waveform diagram showing a prior art resonant power converter operating at a duty cycle of 50%.

[0030] Figure 1B A waveform diagram showing a prior art resonant power converter operating at a non-50% duty cycle.

[0031] Figure 2 A block diagram showing a resonant power converter in an embodiment of the present invention.

[0032] Figure 3 A schematic diagram showing a resonant power converter in an embodiment of the present invention.

[0033] Figure 4 A schematic diagram showing a resonant power converter in an embodiment of the present invention.

[0034] Figure 5 A schematic diagram showing a resonant power converter in an embodiment of the present invention.

[0035] Figure 6 A schematic diagram showing a resonant power converter in an embodiment of the present invention.

[0036] Figure 7A And Figure 7B Respectively show the waveform diagrams of the resonant power converter operating in the light load and deep light load (such as standby mode) states in an embodiment of the present invention.

[0037] Figure 8 Show the waveform diagrams of the current sensing signal and the zero current signal generated, for example, by quasi-resonance during the burst-off period in an embodiment of the present invention.

[0038] Figure 9A Show a schematic diagram of the current detection circuit corresponding to Figure 4 in an embodiment of the present invention.

[0039] Figure 9B Show a schematic diagram of the current detection circuit corresponding to Figure 5 Or Figure 6 in an embodiment of the present invention.

[0040] Figure 10 Show a schematic diagram of the full-wave rectifier circuit in an embodiment of the present invention.

[0041] Figure 11 Show the operation waveform diagram of the full-wave rectifier circuit in an embodiment of the present invention.

[0042] Figure 12 Show a partial schematic diagram of the control circuit for generating the upper bridge drive signal and the lower bridge drive signal in an embodiment of the present invention.

[0043] Figure 13A Show the operation waveform diagram of the PWM control circuit operating in the light load state in an embodiment of the present invention.

[0044] Figure 13B Show the operation waveform diagram of the PWM control circuit operating in the heavy load state in an embodiment of the present invention.

[0045] Figure 13C Show the operation waveform diagram of the PWM control circuit operating in the full load state in an embodiment of the present invention.

[0046] Figure 14 Show a partial schematic diagram of the PWM control circuit for generating a compensation signal based on a feedback signal in an embodiment of the present invention.

[0047] Figure 15 Show a schematic diagram of the single-shot circuit corresponding to Figure 12 in a preferred embodiment of the present invention.

[0048] Figure 16 Show a partial schematic diagram of the PWM control circuit for generating a burst period signal in an embodiment of the present invention.

[0049] Figure 17 Showing the schematic diagram of the delay circuit corresponding to Figure 16 in an embodiment of the present invention.

[0050] Figure 18A And Figure 18B Showing the schematic diagrams of the automatic tuning circuit corresponding to Figure 10 in two embodiments of the present invention.

[0051] Symbol Explanation in the Figures

[0052] 10: Upper-bridge transistor

[0053] 100: Pulse-width modulation control circuit

[0054] 1002, 1004, 1005, 1006: Resonant power converter

[0055] 117: Digital-to-analog converter

[0056] 118: Counter

[0057] 120: Resistor

[0058] 122, 141: Transistor

[0059] 123: Summing circuit

[0060] 130, 150: Comparator

[0061] 131, 134: Inverter

[0062] 132, 133, 135, 153, 160, 180: Flip-flop

[0063] 137, 151, 161, 167, 181, 187: AND gate

[0064] 139, 162, 182: OR gate

[0065] 140: Current source

[0066] 145: Capacitor

[0067] 147: NOR gate

[0068] 163, 183: Maximum conduction time circuit

[0069] 170, 190: Monostable circuit

[0070] 20: Lower-bridge transistor

[0071] 200: Delay circuit

[0072] 2002, 2004, 2005, 2006: Conversion control circuit

[0073] 210, 215: Current source

[0074] 211, 212: Transistor

[0075] 250: Capacitor

[0076] 255: Comparator

[0077] 30, 31: Resonant inductor

[0078] 300: Resonant circuit

[0079] 312, 335: Transistor

[0080] 315: Current source

[0081] 350: Capacitor

[0082] 355: Comparator

[0083] 40: Transformer

[0084] 400, 401, 402, 403, 404: Sensing circuit

[0085] 41: Current sensing resistor

[0086] 410, 411, 412, 415, 416, 435: Resistor

[0087] 42: Blocking capacitor

[0088] 420, 425: Operational amplifier

[0089] 43: Current sensing capacitor

[0090] 430: Buffer amplifier

[0091] 450: Current source

[0092] 50: Resonant capacitor

[0093] 500: Automatic tuning circuit

[0094] 51, 52, 515, 523, 524, 545: Capacitor

[0095] 510, 540: Current source

[0096] 511, 512, 521, 522: Switch

[0097] 53, 54, 57, 58: Resistor

[0098] 531, 532: Comparator

[0099] 533, 534: Inverter

[0100] 535, 536, 541, 548: AND gate

[0101] 537, 538: Flip-flop

[0102] 542: Transistor

[0103] 55: Feedback resistor

[0104] 56: Input resistor

[0105] 570: Up-down counter

[0106] 580: Digital-to-analog converter

[0107] 59: Feedback capacitor

[0108] 610, 630: Current source

[0109] 613: Comparator

[0110] 620: Monostable circuit

[0111] 631: Transistor

[0112] 635: Capacitor

[0113] 640: NOR gate

[0114] 67: Current sensing capacitor

[0115] 68: Current sensing resistor

[0116] 69: Resistor

[0117] 70, 71, 72: Current detection circuit

[0118] 75: Buffer amplifier

[0119] 76: Operational amplifier

[0120] 81, 82: Gate driver

[0121] 83: Voltage level shifter

[0122] 90, 91: Full-wave rectifier circuit

[0123] CK_H: Second dead time signal

[0124] CK_L: First dead time signal

[0125] Inverted clock signal

[0126] CLK1, CLK2: Clock signals

[0127] Comp: Compensation signal

[0128] CS: Current sensing signal

[0129] Cx: Current sensing capacitor

[0130] D1, D2: Diodes

[0131] DWN: Down signal

[0132] FW_VCR: Full-wave sensing signal

[0133] HS: High-side drive signal

[0134] I122, I212, I312, I315, IB, IB1, IB2, Imin, IREF, Ix, Iy: Currents

[0135] IA: Current

[0136] ID: Tuning current

[0137] ILM: Magnetizing inductance current

[0138] IN: Input of the one-shot circuit

[0139] Iprimary: Primary-side current

[0140] Isecondary: Secondary-side current

[0141] k*VIN: Bias voltage

[0142] LS: Low-side drive signal

[0143] LTH: Latch signal

[0144] LX: Switching node

[0145] mVCR: Sensing signal

[0146] n: Current mirror ratio

[0147] nVCR: Capacitor signal

[0148] OCP: Over-current signal

[0149] OUT: Output of the comparator

[0150] Pwrest: Power reset signal

[0151] R120: Resistance value

[0152] Ramp: Ramp signal

[0153] Rx: Current sensing resistor

[0154] SB: Burst signal

[0155] SBur: Signal during burst

[0156] SCZ: Signal

[0157] SE: Phase signal

[0158] ST: Output signal

[0159] Sz: Cross signal

[0160] t1~t3: Time points

[0161] TBur, TBur2: Burst off period

[0162] TBur_en, TBur_en2: Burst enable period

[0163] Td1: First dead time

[0164] Td2: Second dead time

[0165] TonH, TonH2: Upper bridge conduction time

[0166] TonL, TonL2: Lower bridge conduction time

[0167] UP: Upward signal

[0168] V1, V2: Voltage

[0169] VADJ: Adjustment signal

[0170] Vcomp: Adjustment feedback signal

[0171] Vcr: Voltage across resonant capacitor

[0172] VCS: Current sensing signal

[0173] VFB: Feedback signal

[0174] VIN: Input voltage

[0175] VLX: Voltage at switching node

[0176] VOS: Offset signal

[0177] VOUT: Output voltage

[0178] VREF: DC bias voltage

[0179] Vsw: Primary side switch signal

[0180] VT_B: Low power threshold

[0181] VT1: Threshold value

[0182] VT2: Threshold voltage

[0183] VTC: Reference voltage

[0184] VTH, VTL, VTZ: Threshold values

[0185] VVFB, VVTC: Voltages

[0186] ZCD: Zero current signal

[0187] ZCD_T: Signal Detailed implementation manners

[0188] The drawings in the present invention are all schematic, mainly intended to show the coupling relationship between each circuit and the relationship between each signal waveform. As for the circuit, signal waveform and frequency, they are not drawn according to the proportion. For the sake of clear description, many practical details will be described together in the following narration, but this is not intended to limit the scope of the patent application of the present invention.

[0189] Figure 2 Show the block diagram of the resonant power converter in an embodiment of the present invention. In an embodiment, the conversion control circuit 2002 is used to control the resonant power converter 1002. The conversion control circuit 2002 includes: a sensing circuit 400 and a pulse width modulation (PWM) control circuit 100. In an embodiment, the resonant power converter 1002 is, for example, an LLC resonant power converter. The resonant power converter 1002 includes an upper bridge transistor 10, a lower bridge transistor 20 and a resonant circuit 300. The upper bridge transistor 10 and the lower bridge transistor 20 are sequentially connected in series between the input voltage VIN and the ground potential to form a half-bridge circuit. The resonant circuit 300 includes at least one resonant inductor and a resonant capacitor 50. In this embodiment, the at least one resonant inductor includes a resonant inductor 30 and a resonant inductor 31. The resonant inductor 30, the resonant inductor 31 and the resonant capacitor 50 are sequentially connected in series between the switching node LX (located between the upper bridge transistor 10 and the lower bridge transistor 20) and the ground potential. In an embodiment, the resonant inductor 31 is the excitation inductor of the transformer 40. The upper bridge transistor 10 and the lower bridge transistor 20 are used to switch the resonant circuit 300 to convert the input voltage VIN into the output voltage VOUT.

[0190] In one embodiment, the sensing circuit 400 is used to sense resonance-related parameters having a resonance state to generate a sensing signal mVCR. The resonance-related parameters are related to the resonance generated by the resonance circuit 300. The PWM control circuit 100 is used to generate an upper-bridge driving signal HS and a lower-bridge driving signal LS according to the sensing signal mVCR and the feedback signal VFB to respectively control the upper-bridge transistor 10 and the lower-bridge transistor 20, thereby switching the resonance circuit 300 to generate an output voltage VOUT. In this embodiment, the feedback signal VFB is related to the output power of the output voltage VOUT. In one embodiment, when the feedback signal VFB is lower than a low-power threshold, the resonant power converter 1002 enters a burst OFF period, during which both the upper-bridge transistor 10 and the lower-bridge transistor 20 are turned off. The details of the burst OFF period will be described in detail in subsequent embodiments.

[0191] In one embodiment, the aforementioned resonance-related parameters include a resonance current flowing through the resonance capacitor 50 or at least one resonance inductor, as described in the following Figures 3 to 5 description.

[0192] Figure 3 Schematic diagram showing a resonant power converter in an embodiment of the present invention. Different from the Figure 2 embodiment, in the Figure 3 embodiment, the resonance capacitor 50, the resonance inductor 31, and the resonance inductor 30 are sequentially connected in series between the switching node LX and the ground potential. In one embodiment, Figure 3 the sensing circuit 401 in

[0193] Figure 4 includes a current sensing resistor Rx and a current sensing capacitor Cx. In this embodiment, after the current sensing resistor Rx and the current sensing capacitor Cx are connected in series with each other, they are connected in parallel to the resonance inductor 30 for direct current resistance (DCR) sensing. This configuration is used to sense the current flowing through the resonance circuit 300. Specifically, the current flowing through the resonance inductor 30 is sensed by DCR to generate a current sensing signal VCS at the common node of the current sensing resistor Rx and the current sensing capacitor Cx. Figure 4 The resonant power converter 1004 of Figure 2 is a specific embodiment of the resonant power converter 1002 of Figure 4The conversion control circuit 2004 also includes a current detection circuit 70 and a full-wave rectification circuit 90. In one embodiment, the upper bridge drive signal HS drives the upper bridge transistor 10 via the gate driver 81 and the voltage level shifter 83. The lower bridge drive signal LS drives the lower bridge transistor 20 via the gate driver 82. In one embodiment, the sensing circuit 402 is used for current sensing and includes capacitors 51 and 52, resistors 53 and 54, a current sensing capacitor 67 and a current sensing resistor 68, and a buffer amplifier 75. The current sensing capacitor 67 is serially connected with the current sensing resistor 68 and coupled to the sensing circuit 402, and is used to sense the current flowing through the resonant capacitor 50 to generate a current sensing signal CS.

[0194] Please continue to refer to Figure 4 , in one embodiment, the sensing circuit 402 is also used to generate a current sensing signal VCS. Specifically, the resistor 69 connected to the current detection circuit 70 provides a bias voltage to the current sensing signal CS to generate a current sensing signal VCS. In one embodiment, the capacitors 51 and 52 are configured as a capacitive voltage divider to sense the voltage on the resonant capacitor 50 to generate a capacitance signal nVCR. The buffer amplifier 75 is used to generate a sensing signal mVCR according to the capacitance signal nVCR. Then, the full-wave rectification circuit 90 is used to perform full-wave rectification on the sensing signal mVCR to generate a rectified sensing signal FW_VCR.

[0195] In one embodiment, the PWM control circuit 100 generates the upper bridge drive signal HS and the lower bridge drive signal LS by comparing the rectified sensing signal FW_VCR with the feedback signal VFB, thereby adjusting the output voltage VOUT. The resistors 57 and 58 are configured as a resistive voltage divider, which is connected to the input voltage VIN to generate a bias voltage k*VIN.

[0196] Figure 5 Show a schematic diagram of a resonant power converter in an embodiment of the present invention. Similar to Figure 4 , Figure 5 The resonant power converter 1005 is Figure 2 Another specific embodiment of the resonant power converter 1002. In one embodiment, the sensing circuit 403 in the conversion control circuit 2005 includes a current sensing resistor 41, a blocking capacitor 42, an input resistor 56, a feedback resistor 55, a feedback capacitor 59, and an operational amplifier 76. In one embodiment, the current sensing resistor 41 is serially coupled with the resonant capacitor 50 to generate a current sensing signal CS.

[0197] As Figure 5As shown, an integrator generates a sensed signal mVCR based on a current sensing signal CS. The integrator includes an operational amplifier 76, a feedback capacitor 59 coupled in parallel with a feedback resistor 55, and an input resistor 56. The operational amplifier 76 includes a DC bias voltage VREF such that the circuit can operate with a single power supply instead of a dual power supply. A blocking capacitor 42 is coupled between the current sensing signal CS and the input of the integrator (input resistor 56). The blocking capacitor 42 provides a high impedance to the gain of the DC signal (the DC bias voltage VREF of the integrator), so the DC signal at the positive input terminal of the operational amplifier 76 is not affected by the feedback resistor connected to the negative input terminal. In addition, the blocking capacitor 42 is also used to remove the DC component of the current sensing signal CS. For the remaining operation details not mentioned, please refer to the above Figure 2 and Figure 4 description.

[0198] Figure 6 Schematic diagram showing a resonant power converter in an embodiment of the present invention. Similar to Figure 5 , Figure 6 the resonant power converter 1006 is Figure 2 another specific embodiment of the resonant power converter 1002. Different from Figure 5 , Figure 6 the sensing circuit 404 in the conversion control circuit 2006 of Figure 2 includes: a current sensing capacitor 43 and a current sensing resistor 41 coupled in series with each other, used to sense the current flowing through the resonant capacitor 50 to generate a current sensing signal CS. In this embodiment, the current sensing signal CS represents the derivative of the voltage across the resonant capacitor 50, that is, the current flowing through the resonant capacitor 50. For the remaining operation details not mentioned, please refer to the above Figure 4 , Figure 5 description.

[0199] Figure 7A and Figure 7B respectively show waveform diagrams of the resonant power converter operating in a light load and a deep light load (such as standby mode) state in an embodiment of the present invention. In one embodiment, a period of the burst period signal SBur (for example, from time point t1 to t3) includes a burst enable period TBur_en and a burst off period TBur. In one embodiment, the start point of the burst off period TBur of the burst period signal SBur is synchronized with the turn-off time point of the upper bridge drive signal HS (for example, time point t2), and the turn-on time point of the lower bridge drive signal LS is synchronized with the end time point of the burst off period TBur (for example, time point t3). In another embodiment, when the current sensing signal CS exceeds an overcurrent threshold, the burst off period is also triggered. In one embodiment, the duration of the burst off period TBur increases as the output power of the output voltage VOUT decreases.

[0200] In one embodiment, during the burst-off period TBur, both the upper-bridge transistor 10 and the lower-bridge transistor 20 are turned off, causing the junction capacitances of the upper-bridge transistor 10 and the lower-bridge transistor 20 to resonate with the resonant inductor 30 and the magnetizing inductor of the transformer 40. This is also known as quasi-resonance, and the resonant energy decays due to the parasitic resistance in the circuit. If the load is not very light, the burst-off period will be short, and the resonant current flowing through the resonant capacitor 50 has not completely decayed before the end of the burst-off period.

[0201] As Figure 7A shown in Figure 7B , in one embodiment, after the start of the burst enable period TBur_en (e.g., time point t1), the lower-bridge drive signal LS turns on first, and before the end of the burst enable period TBur_en (e.g., time point t2), the upper-bridge drive signal HS turns off last. In one embodiment, the burst enable period TBur_en includes at least one pair of the lower-bridge conduction time of the lower-bridge drive signal LS and the upper-bridge conduction time of the upper-bridge drive signal HS. For example Figure 7B shown in

[0202] Please continue to refer to Figure 7B , from one perspective, when the resonant power converter operates in burst mode, during a burst enable period TBur_en, the lower-bridge drive signal LS conducts for a time length of a lower-bridge conduction time TonL. Then, the upper-bridge drive signal HS and the lower-bridge drive signal LS turn off during a first dead time Td1. After the first dead time Td1, the upper-bridge drive signal HS conducts for a time length of an upper-bridge conduction time TonH. Then, during a burst-off period TBur, both the upper-bridge drive signal HS and the lower-bridge drive signal LS turn off. Then, during another burst enable period TBur_en2, the lower-bridge drive signal LS conducts for a time length of a lower-bridge conduction time TonL2. Then, the upper-bridge drive signal HS and the lower-bridge drive signal LS turn off during a second dead time Td2. After the second dead time Td2, the upper-bridge drive signal HS conducts for a time length of an upper-bridge conduction time TonH2. Then, during another burst-off period TBur2, both the upper-bridge drive signal HS and the lower-bridge drive signal LS turn off, and similar cycles can continue to repeat. The details of the subsequent waveforms can be inferred from the above description, so they will not be elaborated.

[0203] In one embodiment, the burst-off period TBur is much longer than the first dead time Td1 or the second dead time Td2. In one embodiment, the minimum value of the burst-off period TBur is equal to the switching period of the upper-bridge drive signal HS or the lower-bridge drive signal LS. For example, the switching period can be Figure 7B the sum of the upper-bridge conduction time TonH and the lower-bridge conduction time TonL in

[0204] Figure 8 Shows the waveforms of the current sensing signal and the zero current signal generated, for example, by quasi-resonance during burst-off in one embodiment of the present invention. In one embodiment, when the current sensing signal VCS changes from positive to negative, the voltage VLX of the switching node LX also reaches the lowest point simultaneously. At this time, the current detection circuit (such as Figures 4 to 6 70 therein) detects zero current at a specific time point and generates a zero current signal ZCD. In one embodiment, when the zero current signal ZCD is generated, it represents the instant (crossing point) when the resonant current changes from positive to negative. At this time, the lower bridge transistor 20 is turned on, thereby achieving soft switching. In other words, the lower bridge transistor 20 is turned on synchronously at the zero current time point marked by the zero current signal ZCD.

[0205] It should be noted that the above embodiment realizes valley-voltage switching, effectively reducing the switching loss at the end of the burst-off period. In one embodiment, the end time point of the burst-off period is synchronized with the zero current time point of the current sensing signal VCS. In this embodiment, the burst-off period TBur is equal to or greater than a quasi-resonant period, and this quasi-resonant period is synchronized with the zero current point of the current sensing signal VCS. In another embodiment, when the burst-off period exceeds an over-time period threshold, the end time point of the burst-off period and the zero current point of the current sensing signal VCS no longer need to be synchronized.

[0206] Please refer to Figure 4 、 Figure 8 and Figure 9A . Figure 9A Shows a schematic diagram of the current detection circuit corresponding to Figure 4 in one embodiment of the present invention, which is used to generate an over-current signal OCP and a zero current signal ZCD. In one embodiment, in the current detection circuit 71 in Figure 9A , when the current sensing signal VCS exceeds the threshold VTH or is lower than the threshold VTL, the over-current signal OCP is generated through the one-shot circuit 620. When the current sensing signal VCS exceeds the threshold VTZ, the comparator 613 generates a signal SCZ. In this embodiment, the current of the current source 610 flows through the resistor 69 (as shown in Figure 4 ) to generate a bias voltage for the current sensing signal CS, thereby generating the current sensing signal VCS, that is, the current sensing signal VCS has the DC voltage provided by this bias voltage. The above threshold VTZ is set slightly higher than the bias voltage determined by the current source 610 and the resistor 69. The pulse generator includes a current source 630, a transistor 631, a capacitor 635 and a NOR gate 640, which are used to generate a zero current signal ZCD according to the falling edge of the signal SCZ.

[0207] Figure 9B Schematic diagram of the current detection circuit corresponding to Figure 5 or Figure 6 in one embodiment of the present invention. Figure 9B The current detection circuit 72 corresponding to Figure 9A is similar to the current detection circuit 71 corresponding to Figure 9A . The difference from Figure 9B is that the current sensing signal VCS in Figure 5 or Figure 6 is generated through the blocking capacitor 42 (as shown in Figure 9A ), so the current detection circuit 72 does not need to include the current source 610. For the operation details not mentioned, please refer to the description of

[0208] Please refer to Figure 10 and Figure 11 . Figure 10 Schematic diagram of the full-wave rectifier circuit in one embodiment of the present invention. Figure 11 Operation waveform diagram of the full-wave rectifier circuit in one embodiment of the present invention. Figure 10 The full-wave rectifier circuit 91 corresponding to Figures 4 to 6 is a specific embodiment of the full-wave rectifier circuit 90 corresponding to Figure 11 . In one embodiment, the full-wave rectifier circuit 91 includes operational amplifiers 420 and 425, diodes D1 and D2, resistors 410, 411, 412, 415, 416 and 435, buffer amplifier 430, and current source 450. The full-wave rectifier circuit 91 is used to receive the sensing signal mVCR to generate the rectified sensing signal FW_VCR. In this embodiment, the full-wave rectifier circuit 91 includes an offset signal VOS, and the offset signal VOS is used to cancel the DC component of the sensing signal mVCR. As shown in

[0209] Please continue to refer to Figure 10 and Figure 11 . In one embodiment, when the rectified sensing signal FW_VCR is lower than the low voltage threshold VT, the comparator 440 generates a cross signal Sz. The low voltage threshold VT is slightly higher than the voltage of the offset signal VOS. The offset signal VOS is coupled to the operational amplifier 420 to adjust the DC bias voltage of the full-wave rectifier circuit 91. In one embodiment, the offset signal VOS includes a bias voltage k*VIN and an adjustment signal VADJ. The adjustment signal VADJ is used to adjust the offset voltage of the offset signal VOS to adjust the rectified sensing signal FW_VCR, and the adjustment signal VADJ can be represented by the following equation.

[0210] VADJ = (IA – ID) * R435

[0211] In the above equation, the current IA represents a constant current provided by the current source 450, and the calibration current ID is an adjustable current generated by the automatic calibration circuit 500 for adjusting the offset signal VOS. The details of the calibration current ID are described later. The automatic calibration circuit 500 generates the calibration current ID based on the conduction time of the upper bridge drive signal HS and the conduction time of the lower bridge drive signal LS. Both the calibration current ID and the offset signal VOS are generated based on the difference between the duty cycle of the upper bridge drive signal HS and the duty cycle of the lower bridge drive signal LS. The offset signal VOS is then used to adjust the DC bias of the full-wave rectifier circuit 91 and the duty cycles of the upper bridge drive signal HS and the lower bridge drive signal LS. Finally, the offset signal VOS is used to make the duty cycle of the upper bridge drive signal HS match the duty cycle of the lower bridge drive signal LS, or to make the duty cycle of the lower bridge drive signal LS match the duty cycle of the upper bridge drive signal HS.

[0212] Figure 12 FIG. shows a partial schematic diagram of a control circuit for generating an upper bridge drive signal and a lower bridge drive signal in an embodiment of the present invention. In one embodiment, the flip-flop 153 sets and enables the phase signal SE according to the rising edge of the cross signal Sz. When the integrated sense signal FW_VCR exceeds the compensation signal Comp (through the comparator 150), the phase signal SE is reset and disabled according to the first dead time signal CK_L or the second dead time signal CK_H.

[0213] In one embodiment, when the upper bridge drive signal HS is conducting and the phase signal SE is enabled, when the integrated sense signal FW_VCR exceeds the compensation signal Comp, the upper bridge drive signal HS is turned off via the AND gate 161, the OR gate 162, and the one-shot circuit 170 (generating the first dead time signal CK_L). Then, when the upper bridge drive signal HS is turned off, the lower bridge drive signal LS is turned on via the flip-flop 180 after the first dead time of the first dead time signal CK_L. In one embodiment, when the lower bridge drive signal LS is conducting and the phase signal SE is enabled, when the integrated sense signal FW_VCR exceeds the compensation signal Comp, the lower bridge drive signal LS is turned off via the AND gate 181, the OR gate 182, and the one-shot circuit 190 (generating the second dead time signal CK_H). When the lower bridge drive signal LS is turned off, the upper bridge drive signal HS is re-conducted via the flip-flop 160 after the second dead time of the second dead time signal CK_H.

[0214] Please continue to refer to Figure 12In one embodiment, when an overcurrent occurs in the resonant circuit, the two flip-flops 160 and 180 are reset by the overcurrent signal OCP via the AND gates 167 and 187 , respectively, thereby disabling the upper bridge driving signal HS and the lower bridge driving signal LS.

[0215] In one embodiment, when the burst period signal SBur is generated under a light load state, both the upper bridge driving signal HS and the lower bridge driving signal LS are turned off.

[0216] In one embodiment, when the power is turned on or when the switching starts after the burst off period, the lower bridge drive signal LS will first be triggered via the AND gate 151. The pulse widths of the upper bridge drive signal HS and the lower bridge drive signal LS are both limited to a maximum on time. When the upper bridge drive signal HS is generated, the maximum on time signal for controlling the upper bridge drive signal HS is generated by the maximum on time circuit 163. Similarly, when the lower bridge drive signal LS is generated, the maximum on time signal for controlling the lower bridge drive signal LS is generated by the maximum on time circuit 183.

[0217] In one embodiment, under light load and normal operation conditions, the maximum on-time signal is used to limit the switching cycle time to be no longer than the resonant cycle of the resonant circuit. The switching cycle time includes the on-time periods of the upper bridge driving signal HS and the lower bridge driving signal LS.

[0218] In another embodiment, when the input voltage VIN becomes low and the output is in a heavy load state, the maximum on-time signal can be extended so that the switching cycle time selectively exceeds the resonant cycle of the resonant circuit, for example, to meet the hold-up time requirement.

[0219] Figure 13A , Figure 13B and Figure 13C The operating waveforms of the PWM control circuit according to an embodiment of the present invention are shown. Figure 13A , Figure 13B and Figure 13C The operation waveform diagrams of the PWM control circuit operating under light load, heavy load and full load conditions in one embodiment of the present invention are respectively shown. It should be noted that, from one point of view, the phase of the phase signal SE represents the phase offset between the resonance of the resonant circuit 300 and the switching time point of the upper bridge drive signal HS or the lower bridge drive signal LS, which will actually cause the resonant output power level output by the resonant power converter to change with the phase offset. In other words, the power level of the resonant power converter is controlled by the phase offset of the phase signal SE, which is determined by comparing the compensation signal Comp with the rectifier sensing signal FW_VCR. Through feedback control, the output power can be adjusted to a preset level. About Figures 13A to 13CFor the waveform details in [the above], those skilled in the art can infer from the foregoing Figure 12 description and will not be elaborated here.

[0220] Figure 14 FIG. [X] shows a partial schematic diagram of a PWM control circuit for generating a compensation signal based on a feedback signal in an embodiment of the present invention. In one embodiment, a soft-start circuit includes a digital-to-analog converter (DAC) 117 and a counter 118 for enabling a gradual power-on sequence according to the feedback signal VFB, during which the feedback signal VFB gradually increases. The full-range input of the digital-to-analog converter 117 is connected to the feedback signal VFB. The output of the counter 118 is reset to zero (e.g., represented as 0000) by the power reset signal Pwrest when the resonant power converter is turned on, and the output of the digital-to-analog converter 117 is also set to zero voltage. Then, the counter 118 counts according to the clock signal CLK1, and its output will increase to the full range (represented as 1111), so that the output of the digital-to-analog converter 117 aligns with the level of the feedback signal VFB to achieve soft start of the output voltage. When the voltage of the feedback signal VFB drops below the reference voltage VTC, the adjusted feedback signal Vcomp is clamped to the reference voltage VTC to clamp the voltage of the feedback signal VFB not lower than the reference voltage VTC and generate a current I122 flowing through the transistor 122. The current I122 can be represented by the following equation.

[0221] I122 = (VVTC – VVFB) / R120

[0222] In the above equation, VVFB and VVTC are the voltages of the feedback signal VFB and the reference voltage VTC respectively, and R120 is the resistance value of the resistor 120. The currents IB, IB1, and IB2 are generated by mirroring the current I122. When the feedback signal VFB is lower than the reference voltage VTC, the currents IB, IB1, and IB2 are generated and increase according to the decrease of the feedback signal VFB. The sum circuit 123 subtracts the ramp signal Ramp from the adjusted feedback signal Vcomp to generate a compensation signal Comp, thereby performing slope compensation in the feedback loop.

[0223] Please refer to Figure 12 and Figure 15 . Figure 15 FIG. [Y] shows a preferred embodiment of the present invention corresponding to Figure 12 It should be noted that the specific figure numbers [X] and [Y] need to be filled in according to the actual figure numbers in the original patent text. Since they are not provided in the given content, they are left as placeholders here.Schematic diagram of the single-shot circuits (170 and 190). In one embodiment, when the input IN of the single-shot circuit 170 or 190 is a low logic signal, the capacitor 350 is charged to a high level. When the input IN transitions to a high logic signal, the capacitor 350 discharges via the transistor 335, causing the output OUT of the comparator 355 to have a low logic level. When the output OUT of the single-shot circuit 170 or 190 is at a low logic level, the flip-flop 160 or 180 is reset, and then the input IN of the single-shot circuit 170 or 190 transitions to a low logic level. Before the voltage of the capacitor 350 is charged to exceed the threshold voltage VT2, the output OUT of the single-shot circuit 170 or 190 will remain at a low logic level. The pulse widths of the single-shot circuits 170 and 190 (corresponding to the pulse widths of the first dead-time signal CK_L and the second dead-time signal CK_H) are determined according to the capacitance of the capacitor 350, the current I312 flowing through the transistor 312, and the current I315 of the current source 315. The pulse widths of the single-shot circuits 170 and 190 can be adjusted by the currents Ix and Iy respectively.

[0224] Figure 16 Schematic diagram showing a part of the PWM control circuit for generating the burst period signal in an embodiment of the present invention. In one embodiment, during the burst-off period, when the feedback signal VFB drops below the low-power threshold VT_B (this comparison is implemented by the comparator 130), both the high-side drive signal HS and the low-side drive signal LS are turned off. The start point of the burst-off period is synchronized with the disablement (off state, e.g., 0) of the high-side drive signal HS, and its end point is synchronized with the enabling (on state, e.g., 1) of the low-side drive signal LS. The disablement of the high-side drive signal HS is triggered by the enabling of the first dead-time signal CK_L coupled to the inverter 131. When the feedback signal VFB is lower than the low-power threshold VT_B, the flip-flop 132 is enabled to generate the burst signal SB. After the burst signal SB is generated, the delay circuit 200 is used to determine a delay period before disabling the flip-flop 132 and the burst signal SB, and the burst-off period includes this delay period. When the burst signal SB is generated, the delay circuit 200 is used to ensure the lower limit of the delay period.

[0225] In one embodiment, the duration of the burst-off period increases proportionally with the decrease in the output power level of the output voltage VOUT. In addition, the overcurrent signal OCP is used to set the preset state of the flip-flop 132 and generate the burst signal SB according to the overcurrent situation. Then, the burst signal SB passes through the inverter 135 to generate the burst period signal SBur.

[0226] As Figure 16As shown, in one embodiment, AND gate 137 is synchronized with the end point of the burst-off period according to the zero-current signal ZCD. Flip-flop 133, inverter 134, and OR gate 139 are used to generate signal ZCD_T to indicate synchronization with the zero-current signal ZCD during the timeout period. When the zero-current signal ZCD is generated, transistor 141 is used to discharge capacitor 145. In the case where the zero-current signal ZCD cannot be generated (for example, before the end of the burst-off period, the quasi-resonance has completely damped), the timeout period will prohibit the synchronization of the zero-current signal ZCD and the burst period signal SBur, where the timeout period is generated by charging capacitor 145 via current source 140. Specifically, after the lower-bridge drive signal LS is enabled, flip-flop 133 is reset via NAND gate 147 to prohibit the synchronization of the burst period signal SBur and the zero-current signal ZCD.

[0227] Please refer to Figure 16 and Figure 17 . Figure 17 shows a schematic diagram of the delay circuit corresponding to Figure 16 in an embodiment of the present invention. In one embodiment, the delay period is determined by the current I212 flowing through transistor 212 and the capacitance of capacitor 250. When capacitor 250 is charged beyond the threshold VT1, the output signal ST of comparator 255 will reset flip-flop 132. When the feedback signal VFB drops below the reference voltage VTC, the current IB will increase according to the decrease in output power ( Figure 14 ).

[0228] The current I212 can be expressed by the following equation:

[0229] I212 = n * (IREF – IB)

[0230] In the above equation, n is the current mirror ratio of transistors 211 and 212. From the above equation, it can be seen that as the current IB increases, the current I212 will decrease, resulting in an increase in the burst-off period of the burst period signal SBur when the output power decreases. The current IREF of current source 210 is used to determine the lower limit of the delay period of delay circuit 200, and the current Imin of current source 215 is used to determine the upper limit of the delay period of delay circuit 200. Therefore, the burst period signal SBur is restricted between the upper and lower limits of the delay period.

[0231] Figure 18A and Figure 18B show schematic diagrams of two embodiments of the present invention corresponding to Figure 10 in the automatic tuning circuit. Figure 18ADisplays a time - voltage converter. In one embodiment, during the conduction period of the upper - bridge drive signal HS, the current source 510 is used to charge the capacitors 515 and 523 via the switches 511 and 521. When the upper - bridge drive signal HS is turned off, the capacitor 523 will hold the voltage V1 until the upper - bridge drive signal HS is turned on again. Thus, the level of the voltage V1 is related to the pulse width of the upper - bridge drive signal HS. During the conduction period of the lower - bridge drive signal LS, the current source 510 is used to charge the capacitors 515 and 524 via the switches 511 and 522. When the lower - bridge drive signal LS is turned off, the capacitor 524 will hold the voltage V2 until the lower - bridge drive signal LS is turned on again. Thus, the level of the voltage V2 is related to the pulse width of the lower - bridge drive signal LS. When the first dead - time signal CK_L or the second dead - time signal CK_H is generated, the capacitor 515 discharges through the switch 512. In one embodiment, the capacitance value of the capacitor 515 is much higher than that of the capacitors 523 and 524.

[0232] As Figure 18B shown in the automatic calibration circuit (continuing Figure 18A with another part of the circuit), a calibration current ID is generated according to the level of the voltage V1 and the level of the voltage V2. In one embodiment, the comparators 531 and 532, the inverters 533 and 534, the AND gates 535 and 536, and the flip - flops 537 and 538 are configured as a comparison circuit to compare the voltages V1 and V2, thereby generating an up signal UP and a down signal DWN for the up - down counter 570. In one embodiment, the current source 540, the AND gates 541 and 548, the transistor 542, and the capacitor 545 are configured as a delay - time circuit to generate a latch signal LTH when the first dead - time signal CK_L or the second dead - time signal CK_H is generated. The latch signal LTH is used to latch the states of the flip - flops 537 and 538. In one embodiment, the flip - flop 537 is used to generate the up signal UP for up - counting, and the flip - flop 538 is used to generate the down signal DWN for down - counting. The up - down counter 570 counts according to the first dead - time signal CK_L and / or the second dead - time signal CK_H. In one embodiment, as Figure 18B shown, the up - down counter 570 counts according to the clock signal CLK2, where the clock signal CLK2 is the logical result generated by the AND gate of the first dead - time signal CK_L and the second dead - time signal CK_H. It should be noted that both the first dead - time signal CK_L and the second dead - time clock signal CK_H are low - active signals. Therefore, the clock signal CLK2 (more precisely, the inverted clock signal )To indicate the time point triggered by the first dead time signal CK_L or the second dead time signal CK_H. The digital output codes (B1 to BN) of the up / down counter 570 are coupled to the digital-to-analog converter (DAC) 580 to generate a calibration current ID, and the calibration current ID is used to adjust the offset signal VOS (please also refer to Figure 10 ). In one embodiment, the calibration current ID is preferably a current sink, that is, a calibration current ID flowing into the direction of the DAC is generated.

[0233] Please continue to refer to Figure 18A 、 18B And Figure 10 , more generally, the voltages V1 and V2 are respectively related to the duty cycles of the upper bridge driving signal HS and the lower bridge driving signal LS. In one embodiment, a calibration current ID is generated according to the comparison of the voltages V1 and V2, and the calibration current ID is related to the difference between the voltages V1 and V2. The calibration current ID is used to adjust the offset signal VOS ( Figure 10 ), thereby balancing the duty cycles of the upper bridge driving signal HS and the lower bridge driving signal LS.

[0234] The present invention has been described with respect to the preferred embodiments above. However, the above description is only for making those skilled in the art easily understand the content of the present invention, and is not used to limit the scope of the rights of the present invention. Each of the described embodiments is not limited to being applied alone, and can also be applied in combination. For example, two or more embodiments can be combined and used, and some components in one embodiment can also be used to replace the corresponding components in another embodiment. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the so-called "processing or calculating or generating a certain output result according to a certain signal" in the present invention is not limited to the signal itself, but also includes, when necessary, converting the signal between voltage and current, current and voltage, and / or ratio conversion, etc., and then processing or calculating according to the converted signal to generate a certain output result. It can be seen that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combination methods, which are not listed one by one here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A conversion control circuit for controlling a resonant power converter, wherein the resonant power converter comprises: An upper bridge transistor and a lower bridge transistor are sequentially coupled in series between an input voltage and a ground potential to form a half bridge circuit; and a resonant circuit, comprising at least one resonant inductor and a resonant capacitor, wherein the upper bridge transistor and the lower bridge transistor are used to switch the resonant circuit to convert the input voltage into an output voltage; wherein the conversion control circuit comprises: a sensing circuit for sensing a resonance-related parameter having a resonant state to generate a sensing signal, wherein the resonance-related parameter is related to the resonance generated by the resonant circuit; as well as a pulse width modulation control circuit for generating an upper bridge driving signal and a lower bridge driving signal according to the sensing signal and a feedback signal, so as to control the upper bridge transistor and the lower bridge transistor respectively, thereby switching the resonant circuit to generate the output voltage; wherein the feedback signal is related to an output power of the output voltage; When the feedback signal is lower than a low power threshold, the resonant power converter enters a burst off period, during which both the upper bridge transistor and the lower bridge transistor are turned off; The burst off period is equal to or greater than a conduction period of the upper bridge driving signal plus a conduction period of the lower bridge driving signal.

2. The conversion control circuit according to claim 1, wherein: The resonant power converter also enters the burst shutdown period when a current sensing signal exceeds an over-current threshold, wherein the current sensing signal is related to the sensing signal.

3. The conversion control circuit according to claim 1, wherein: The resonance-related parameter includes one of the following: (1) a resonant voltage on the resonant capacitor; or (2) A resonant current flowing through the resonant capacitor or the at least one resonant inductor.

4. The conversion control circuit according to claim 3, wherein: The sensing circuit includes one of the following: (1) a differentiator circuit coupled to the resonant capacitor to generate the sensing signal related to the resonant current; or (2) A DC resistance sensing circuit coupled in parallel to one of the at least one resonant inductor and used to generate the sensing signal related to the resonant current.

5. The conversion control circuit according to claim 1, wherein: The starting time point of the burst off period is synchronized with the time point when the upper bridge transistor turns into a non-conducting state, and the ending time point is synchronized with the time point when the lower bridge transistor turns into a conducting state.

6. The conversion control circuit according to claim 5, wherein: The end time point of the burst off period is also synchronized with a zero current time point of a current sensing signal, thereby reducing the conduction loss of the lower bridge transistor when it is turned on; wherein the current sensing signal is related to the sensing signal; When the end time of the burst off period is synchronized with the zero current time point of the current sensing signal, the burst off period is equal to or greater than a quasi-resonant period, wherein the quasi-resonant period is synchronized with the zero current time point of the current sensing signal.

7. The conversion control circuit according to claim 6, wherein: When the burst off period exceeds a timeout period threshold, the end time point of the burst off period is not synchronized with the zero current time point of the current sensing signal.

8. The conversion control circuit according to claim 1, wherein: The duration of the burst off period increases as an output power of the output voltage decreases.

9. The conversion control circuit according to claim 1, wherein: The pulse width modulation control circuit comprises: a soft start circuit for enabling a soft start power supply startup sequence during which the feedback signal gradually increases; The pulse width modulation control circuit is used for generating the upper bridge driving signal and the lower bridge driving signal according to the sensing signal and a compensation signal, wherein the compensation signal is generated by subtracting a ramp signal from the feedback signal.

10. The conversion control circuit according to claim 1, wherein: It also includes a full-wave rectification circuit for offsetting a DC component of the sensing signal according to an offset signal and for performing full-wave rectification on the sensing signal to generate a rectified sensing signal; The pulse width modulation control circuit is used for generating the upper bridge driving signal and the lower bridge driving signal according to the comparison between the rectified sensing signal and a compensation signal, wherein the compensation signal is related to the feedback signal.

11. The conversion control circuit according to claim 10, wherein: The full-wave rectifier circuit is further used for adjusting a DC bias voltage of the rectified sensing signal according to the offset signal.

12. The conversion control circuit according to claim 10, wherein: The offset signal is adjusted based on a difference between a duty cycle of the upper bridge driving signal and a duty cycle of the lower bridge driving signal, thereby adjusting and matching the duty cycle of the upper bridge driving signal and the duty cycle of the lower bridge driving signal.

13. The conversion control circuit according to claim 10, wherein: The offset signal includes a bias voltage, wherein the bias voltage is generated by a resistor divider connected to the input voltage.

14. The conversion control circuit according to claim 1, wherein: The invention also comprises a calibration circuit for adjusting a duty cycle of the upper bridge driving signal to match a duty cycle of the lower bridge driving signal, or adjusting the duty cycle of the lower bridge driving signal to match the duty cycle of the upper bridge driving signal.

15. The conversion control circuit according to claim 10, wherein: The pulse width modulation control circuit is further used to generate a phase signal, wherein the phase signal is set and enabled according to a cross signal, wherein the cross signal is generated when the rectified sensing signal is lower than a low voltage threshold; When the rectified sensing signal exceeds the compensation signal, the phase signal is reset and disabled.

16. The conversion control circuit according to claim 15, in, When the upper bridge driving signal is turned on and the phase signal is enabled, if the rectifier sensing signal intersects with the compensation signal, the upper bridge driving signal is turned off, and after a first dead time, the lower bridge driving signal is turned on; When the lower bridge driving signal is turned on and the phase signal is enabled, if the rectifier sensing signal intersects with the compensation signal, the lower bridge driving signal becomes non-conductive, and after a second dead time, the upper bridge driving signal is turned on.

17. The conversion control circuit according to claim 1, wherein: The pulse width of the upper bridge driving signal and the lower bridge driving signal is limited to a maximum conduction time to limit a switching cycle time to be shorter than a resonance cycle of the resonant circuit, wherein the switching cycle time includes a conduction period and a non-conduction period of the upper bridge driving signal or the lower bridge driving signal.

18. The conversion control circuit according to claim 17, wherein: When the input voltage is lower than a low voltage threshold and the output power is higher than a heavy load threshold, the maximum on-time is extended so that the switching cycle time is optionally longer than a resonant cycle of the resonant circuit, wherein the switching cycle time includes a conduction period and a non-conduction period of the upper bridge drive signal or the lower bridge drive signal.

19. A conversion control circuit for controlling a resonant power converter, wherein the resonant power converter comprises: An upper bridge transistor and a lower bridge transistor are sequentially coupled in series between an input voltage and a ground potential to form a half bridge circuit; and a resonant circuit, comprising at least one resonant inductor and a resonant capacitor, wherein the upper bridge transistor and the lower bridge transistor are used to switch the resonant circuit to convert the input voltage into an output voltage; wherein the conversion control circuit comprises: a sensing circuit for sensing a resonance-related parameter having a resonant state to generate a sensing signal, wherein the resonance-related parameter is related to the resonance generated by the resonant circuit; a pulse width modulation control circuit for generating an upper bridge driving signal and a lower bridge driving signal according to the sensing signal and a feedback signal, so as to control the upper bridge transistor and the lower bridge transistor respectively, thereby switching the resonant circuit to generate the output voltage; wherein the feedback signal is related to an output power of the output voltage; as well as a full-wave rectifier circuit, used for canceling a DC component of the sensing signal according to an offset signal, and for performing full-wave rectification on the sensing signal to generate a rectified sensing signal; The pulse width modulation control circuit is further used for generating the upper bridge driving signal and the lower bridge driving signal according to the comparison between the rectified sensing signal and a compensation signal, wherein the compensation signal is related to the feedback signal.

20. The conversion control circuit according to claim 19, wherein: The full-wave rectifier circuit is further used for adjusting a DC bias voltage of the rectified sensing signal according to the offset signal.

21. The conversion control circuit according to claim 19, wherein: The offset signal is adjusted based on a difference between a duty cycle of the upper bridge driving signal and a duty cycle of the lower bridge driving signal, thereby adjusting and matching the duty cycle of the upper bridge driving signal and the duty cycle of the lower bridge driving signal.

22. A control method for controlling a resonant power converter, wherein the resonant power converter comprises: An upper bridge transistor and a lower bridge transistor are sequentially coupled in series between an input voltage and a ground potential to form a half bridge circuit; and a resonant circuit, comprising at least one resonant inductor and a resonant capacitor, wherein the upper bridge transistor and the lower bridge transistor are used to switch the resonant circuit to convert the input voltage into an output voltage; wherein the control method comprises: sensing a resonance-related parameter having a resonant state to generate a sensing signal, wherein the resonance-related parameter is related to the resonance generated by the resonant circuit; Generate an upper bridge driving signal and a lower bridge driving signal according to the sensing signal and a feedback signal to control the upper bridge transistor and the lower bridge transistor respectively, thereby switching the resonant circuit to generate the output voltage; wherein the feedback signal is related to an output power of the output voltage; as well as When the feedback signal is lower than a low power threshold, the resonant power converter enters a burst off period, during which both the upper bridge transistor and the lower bridge transistor are turned off; The burst off period is equal to or greater than a conduction time of the upper bridge driving signal plus a conduction time of the lower bridge driving signal.

23. The control method according to claim 22, wherein: The resonance-related parameter includes one of the following: (1) a resonant voltage on the resonant capacitor; or (2) A resonant current flowing through the resonant capacitor or the at least one resonant inductor.

24. The control method according to claim 22, wherein: The steps of causing the resonant power converter to enter the burst shutdown period include: Controlling the starting time point of the burst off period to be synchronized with the time point when the upper bridge transistor turns into a non-conducting state; and The end time point of the burst off period is controlled to be synchronized with the time point when the lower bridge transistor turns into the on state.

25. The control method according to claim 22, wherein: The method also includes increasing the duration of the burst shutdown period as an output power of the output voltage decreases.

26. The control method according to claim 22, wherein: Also included is: generating a rectified sensing signal, the steps of which include: canceling a DC component of the sensing signal according to an offset signal; and Full-wave rectifying the sensing signal to generate the rectified sensing signal; The step of generating the upper bridge driving signal and the lower bridge driving signal is further performed according to a comparison between the rectified sensing signal and a compensation signal, wherein the compensation signal is related to the feedback signal.

27. The control method according to claim 26, wherein: The step of generating the rectified sensing signal further includes: adjusting a DC bias voltage of the rectified sensing signal according to the offset signal.

28. The control method according to claim 26, wherein: The step of generating the rectified sensing signal also includes: adjusting the offset signal based on the difference between a duty cycle of the upper bridge drive signal and a duty cycle of the lower bridge drive signal, thereby adjusting and matching the duty cycle of the upper bridge drive signal and the duty cycle of the lower bridge drive signal.

29. A control method for controlling a resonant power converter, wherein the resonant power converter comprises: An upper bridge transistor and a lower bridge transistor are sequentially coupled in series between an input voltage and a ground potential to form a half bridge circuit; and a resonant circuit, comprising at least one resonant inductor and a resonant capacitor, wherein the upper bridge transistor and the lower bridge transistor are used to switch the resonant circuit to convert the input voltage into an output voltage; wherein the control method comprises: sensing a resonance-related parameter having a resonant state to generate a sensing signal, wherein the resonance-related parameter is related to the resonance generated by the resonant circuit; Generate an upper bridge driving signal and a lower bridge driving signal according to the sensing signal and a feedback signal to control the upper bridge transistor and the lower bridge transistor respectively, thereby switching the resonant circuit to generate the output voltage; The feedback signal is related to an output power of the output voltage; Generating a rectified sensing signal comprises the following steps: canceling a DC component of the sensing signal according to an offset signal; and Full-wave rectifying the sensing signal to generate the rectified sensing signal; The step of generating the upper bridge driving signal and the lower bridge driving signal is further performed according to a comparison between the rectified sensing signal and a compensation signal, wherein the compensation signal is related to the feedback signal.

30. The control method according to claim 29, wherein: The step of generating the rectified sensing signal further includes: adjusting a DC bias voltage of the rectified sensing signal according to the offset signal.

31. The control method according to claim 29, wherein: The step of generating the rectified sensing signal also includes: adjusting the offset signal based on the difference between a duty cycle of the upper bridge drive signal and a duty cycle of the lower bridge drive signal, thereby adjusting and matching the duty cycle of the upper bridge drive signal and the duty cycle of the lower bridge drive signal.

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