Power converter with improved zero current detection function

Abstract

The invention discloses a circuit, and particularly relates to a zero-current detection circuit. The zero current detection circuit is provided with a calibration circuit used for calibrating the offset error of the zero current detection circuit. The offset calibration circuit detects a delay between an output time of the zero current detection circuit and a voltage fluctuation timing of the common node, and correspondingly outputs a calibration signal. The zero current detection circuit includes a pre-amplifier that calibrates the differential voltage according to the offset control signal, and a phase comparator that detects a zero current point from the differential voltage.

Description

Technical Field

[0001] The present invention discloses a zero - current detection circuit technology, and the zero - current detection circuit optimizes the charge - discharge control of energy - storage elements in a power converter, especially a DC - DC converter. Background Art

[0002] A DC - DC converter controls the charge and discharge of energy - storage elements such as inductors through switching elements. At this time, if the switching timing is incorrect, the energy charged in the inductor cannot be completely transferred to the load, or current backflow may occur, thereby reducing the power conversion efficiency. However, since the switching timing needs to change according to load fluctuations or changes in the operating environment, it is not simple to perform adaptive control on it.

[0003] In a DC - DC converter, a zero - current detecting circuit compares the voltage at the common node of a high - side transistor and a low - side transistor with a reference voltage to detect the zero - current point at which the energy - storage element completes discharge, thereby adaptively controlling the switching timing. However, due to the offset or delay occurring in the comparator of the zero - current detection circuit itself, as well as manufacturing errors or delays of internal components, the detected zero - current point may have an error from the actual zero - current point. These errors not reflected and unpredictable in these designs limit the efficiency of the DC - DC converter. Summary of the Invention

[0004] The object of the present invention is to calibrate the detection error of the zero - current detection circuit.

[0005] In addition, the object of the present invention is to provide a zero - current detection circuit that can detect the zero - current point with high precision while operating at low power consumption.

[0006] In addition, the object of the present invention is to provide a power conversion circuit with low self - power consumption and high conversion efficiency.

[0007] According to one aspect, a zero - current detection circuit is proposed. The zero - current detection circuit has a calibration circuit that can calibrate its own offset error. According to one aspect, the offset calibration circuit detects the delay between the output time of the zero - current detection circuit and the voltage fluctuation moment of the common node, and accordingly outputs a calibration signal.

[0008] According to another aspect, the zero - current detection circuit may include a pre - amplifier and a phase comparator. The pre - amplifier calibrates the differential voltage according to an offset control signal, and the phase comparator detects the zero - current point from the differential voltage.

[0009] According to another aspect, the zero-current detection circuit includes a plurality of dynamic comparators. The working clock of the dynamic comparators can be generated by a plurality of flip-flops, which latch the output of each dynamic comparator and feed it to the clock of the subsequent dynamic comparator.

[0010] According to the present invention, the error caused by the zero-current detection circuit itself can be calibrated, thereby further improving the efficiency of the power converter. In addition, a power conversion circuit is proposed. While adopting dynamic comparators, it realizes low power consumption and improves the conversion efficiency through its own clock generation. Due to its low power consumption characteristics and high conversion efficiency, it can also exhibit good characteristics in sensitive application fields such as energy harvesting. Description of the Drawings

[0011] Figure 1 is a block diagram of the structure of a power converter according to an embodiment of the present invention.

[0012] Figure 2 shows a waveform diagram of the early state where the output of the zero-current circuit is earlier than the output of the common node signal and the change of the inductor current.

[0013] Figure 3 shows a waveform diagram of the late state where the output of the zero-current circuit is later than the output of the common node signal and the change of the inductor current.

[0014] Figure 4 is a block diagram of the structure of an offset calibration unit according to an embodiment of the present invention.

[0015] Figure 5 shows an embodiment of the falling time detection unit.

[0016] Figure 6 shows an embodiment of the phase detector.

[0017] Figure 7 shows an embodiment of the section detection unit.

[0018] Figure 8 shows an embodiment of the zero-current detection circuit.

[0019] Figure 9 is a circuit diagram of the structure of a preamplifier according to an embodiment of the present invention.

[0020] Figure 10 is a block diagram of the structure of a zero-current detection circuit according to another embodiment of the present invention.

[0021] Figure 11 shows Figure 10 a more detailed structure of the comparison circuit unit, the clock generation unit, and the output generation unit in the embodiment of

[0022] Figure 12 shows Figure 11 the structure of an embodiment of a dynamic comparator in an embodiment of

[0023] Figure 13 is a timing diagram depicting the operation of the clock generation unit (170).

[0024] Figure 14 shows the structure of an operation controller according to an embodiment of the present invention.

[0025] Figure 15 shows a flowchart of the structure of a power conversion control method according to an embodiment of the present invention. Detailed Description of the Invention

[0026] The foregoing and other aspects are embodied by way of embodiments illustrated in the accompanying drawings. Unless otherwise stated or mutually contradictory, the components of each embodiment can be combined in various ways with the components of one embodiment or the components of other embodiments. In accordance with the principle that the inventors can appropriately define the term concepts to best describe their invention, the terms used in this specification and the claims should be construed to have meanings and concepts consistent with the described or proposed technical concept. The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] <Description of the Invention of Claim 1>

[0028] According to one aspect, there is provided a zero-current circuit having a calibration circuit for calibrating an offset error. Figure 1 Shows an embodiment of a power converter that applies a zero-current circuit according to an embodiment. In the figure, solid lines represent the power signal flow, and dashed lines represent the sensing input or control signal flow. The illustrated embodiment is a boost type power converter, but the present invention is not limited thereto and can also be applied to a buck type power converter. A boost type power converter, also known as a step-up converter, is a DC-to-DC converter that increases voltage while reducing current.

[0029] As shown in the figure, a power converter according to an embodiment of the present invention includes an energy storage element (510), a high-side power switch (530), a low-side power switch (550), a switch control unit (700), and a zero-current detection circuit (100). The low-side power switch (550) interrupts the charging of the energy storage element (510) (here, an inductor) from the input power supply. The high-side power switch (530) interrupts the discharging of the energy stored in the energy storage element (510) (the electricity charged in the inductor here) to the load. The switch control unit (700) generates and outputs a switch control signal (OFF_TIME signal) for controlling the ON / OFF of the high-side power switch (530) and a switch control signal (ON_TIME signal) for controlling the ON / OFF of the low-side power switch (550). The zero-current detection circuit (100) detects the zero-current moment by comparing the outputs of the common node (VX) and the reference node (VR), and outputs a detection signal (ZCD_OUT signal) to the switch control unit (700). Here, the common node (VX) is the node commonly connected by the high-side power switch (530) and the low-side power switch (550), and the reference node (VR) is the node where the input intersects with the signal of the common node voltage in the zero-current detection circuit (100), which is the output node in a boost converter.

[0030] During the charging period when the mutually exclusive ON_TIME signal is activated and the OFF_TIME signal is disabled, the low-side power switch (550) is turned on and the high-side power switch (530) is turned off, so that the input power supplied by the power supply (520) charges the energy storage element (510). During the discharging period when the ON_TIME signal is disabled and the OFF_TIME signal is activated, the low-side power switch (550) is turned off and the high-side power switch (530) is turned on, so that the electricity charged in the energy storage element (510) discharges to the load (570). In order to improve the power conversion efficiency, the charging period must be set to fully charge so as to make full use of the capacity of the energy storage element; the discharging period must also be set so as to completely discharge the charge stored in the energy storage element. The switch control unit (700) generates and outputs these switch signals by itself according to the maximum power point tracking control algorithm, etc., and the zero-current detection circuit (100) compares the actual common node voltage and the reference node voltage, and supplements the control algorithm of the switch control unit (700) accordingly. Therefore, a well-designed power converter can achieve a power conversion efficiency close to 90%. The structure of this boost converter is a well-known technology and will not be described in detail here.

[0031] The power converter further includes an offset calibration unit (300). Offset refers to the error, i.e., the time difference, between the zero current point detected by the zero current detection circuit and the actual zero current point. These offsets are generally caused by design deviations of the input transistors (MOSFETs) in the amplifier and comparator that make up the zero current detection circuit, offsets brought to the comparator by power fluctuations, or internal delays of components. According to one aspect, the offset calibration circuit detects the error between the output time of the zero current detection circuit and the falling time of the common node voltage, and accordingly outputs a calibration signal to the zero current detection circuit (100).

[0032] In one embodiment, the zero current detection circuit (100) includes a calibration circuit that calibrates the offset according to the input calibration signal. In one embodiment, the zero current detection circuit may include a preamplifier and a comparator. The comparator detects the intersection point of two input signals, and the preamplifier can improve the sensitivity of intersection point detection by amplifying the input signal. According to one aspect, the zero current detection circuit may include a calibration circuit. The calibration circuit may be a variable voltage generation circuit that adds, when differentially amplifying in the preamplifier, its delay amount, i.e., an offset voltage proportional to the calibration input value. As another example, the calibration circuit may be a variable voltage generation circuit that reflects the input calibration signal by adding an asymmetric offset to one side input signal of the comparator.

[0033] <Description of the invention of claim 2>

[0034] Figure 2 and Figure 3 is a waveform diagram showing the relationship between the offset between the common node voltage and the output of the zero current detection circuit and the inductor current in a booster converter. In Figure 1 the booster converter, the low-side power switch (550, NMOS transistor) conducts to charge the inductor current; the high-side power switch (530, PMOS transistor) conducts to discharge the inductor current to the load side. At the beginning, the common node voltage is higher than the output voltage shown by the dotted line. After the discharge is completed, a falling waveform is drawn after the common node voltage equals the output voltage, and it drops to near the ground voltage.

[0035] Figure 2 shows a waveform diagram of the early state where the zero current circuit output is earlier than the common node signal output and the change of the inductor current. As shown in the inductor current waveform, the inductor discharge ends prematurely, resulting in a loss of power conversion efficiency. Figure 3Shows a waveform diagram of the delay state (Late State) where the zero-current circuit output lags behind the common node signal output and the change in inductor current. As shown in the inductor current waveform, even after the inductor discharge has ended, the high-side power switch (530) remains in the ON state, causing reverse current to flow, resulting in a loss of power conversion efficiency.

[0036] The present invention calibrates the zero-current circuit by utilizing the characteristics of the common node voltage. To this end, according to one aspect, the offset calibration unit (300) may include a phase detector. The phase detector receives the output signal of the input zero-current detection circuit and the falling time signal output from the common node, and detects the error between the two signals.

[0037] <Description of the inventions of Claim 3 and Claim 5>

[0038] Figure 4 Is a block diagram of the structure of the offset calibration unit according to an embodiment of the present invention. As shown, according to an embodiment, the offset calibration unit (300) may include a falling time detection unit (310), a phase detector (330), and an offset signal generation unit (350).

[0039] The falling time detection unit (310) receives the voltage of the common node (VX) and detects its falling time. At this time, the falling time detection unit (310) may detect the fluctuation moment according to the signal output from the switch control unit (700), that is, the ON_TIME signal.

[0040] Figure 5 Shows an embodiment of the falling time detection unit (310). In the illustrated embodiment, the falling time detection unit (310) detects the moment when the voltage of the common node (VX) drops, that is, the moment when it slowly drops to the output node voltage and then suddenly drops sharply to near the ground voltage. In Figure 2 this, this time is represented as tF. As Figure 5As shown, the fall time detection unit (310) according to an embodiment includes a D-flip flop (311). A digital "1" value is input to the data input terminal of the D-flip flop (311), and the voltage of the common node (VX) is applied to the clock input terminal through an inverter. The output of the pulse generator (313) is applied to the reset input terminal (RN) of the D-flip flop (311) through an inverter. The pulse generator (313) receives the signal (i.e., the ON_TIME signal) output by the switch control unit (700) and generates and outputs a short pulse at the moment when the signal is activated. Here, the reset input terminal (RN) is the input terminal that is reset when a digital "0" is input. The pulse generator (313) outputs a short pulse when the ON_TIME signal is input to the clock, that is, at the moment when the ON_TIME signal is input. Therefore, when the voltage of the common node (VX) suddenly drops to near the ground voltage, the VX_GEN signal output by the fall time detection unit (310) is converted to a "1" value and reset to a "0" value at the moment when the ON_TIME signal output by the switch control unit (700) is activated. Finally, the fall time detection unit (310) outputs a short pulse at the moment when the voltage of the common node (VX) drops rapidly.

[0041] Referring again to Figure 4 , the phase detector (330) detects the error between the output of the zero current detection circuit (100) and the output of the fall time detection unit (310). Figure 6 An embodiment of the phase detector is shown. This kind of phase detector is also called a phase frequency detector (PFD: Phase Frequency Detector), which is a well-known circuit applied to a phase locked loop (PLL: Phase Locked Loop). As shown, the phase detector (330) includes a D-flip flop (331) that outputs a pulse when the VX_GEN signal output by the fall time detection unit (310) is input. The output COMPARE_A signal reflects the timing of the VX_GEN signal. In addition, the phase detector (330) further includes a delay unit (335) and a D-flip flop (333). The delay unit (335) delays the ZCD_OUT signal output by the zero current detection circuit (100), and the D-flip flop (333) outputs a pulse when the delayed ZCD_OUT signal is input. The VX_GEN signal is the output signal of the fall time detection unit (310). Compared with the output signal of the zero current detection circuit (100), since the VX_GEN signal is through Figure 5generated by the structure shown, so there will be a further delay. To compensate for this delay, a delay element (335) is added. The COMPARE_B signal output by the D-flip flop (333) reflects the timing of the ZCD_OUT signal. The two D-flip flops (331, 333) are reset when their outputs are both "1", or when the ON_TIME_RST signal output by the pulse generator (313) is activated. The pulse generator (313) generates and outputs a short pulse when the ON_TIME signal is activated in the Figure 5 circuit shown. Among them, the reset input terminals (RN, RN) are input terminals that are reset when a digital "0" value is input. Therefore, the COMPARE_A signal is activated when the common node voltage rapidly drops to ground, and the COMPARE_B signal is activated when the zero current detection circuit outputs, and is reset when both of these signals are activated or the ON_TIME_RST signal is activated.

[0042] Referring again to Figure 4 , the offset signal generation unit (350) outputs an offset control signal proportional to the detected phase difference. For example, the offset control signal can be an analog signal whose voltage is proportional to the detected phase difference. In another example, the offset control signal can be a pulse signal whose length is directly proportional to the detected phase difference. In another example, the offset control signal can be a binary signal whose value is proportional to the detected phase difference.

[0043] In the illustrated embodiment, the offset signal generation unit (350) may include a section detection unit (370) and a counter (390). The section detection unit (370) detects the duration of the phase difference signal output by the phase detector (330). The counter (390) outputs an offset control signal that increases during the duration detected by the section detection unit (370). Figure 7 An embodiment of the section detection unit is shown. As shown, the section detection unit (370) includes a D-flip flop that is converted to "1" when the COMPARE_A signal is input at the output terminal of the phase detector (330) and is reset when the COMPARE_B signal is disabled. Here, the reset input terminal (RN) is an input terminal that is reset when a digital "0" is input. When both the ZCD_OUT output by the zero current detection circuit and the falling time of the common node output arrive, the COMPARE_B signal is reset, and the COMPARE_A signal reflects the falling time of the common node output. Therefore, the "UP" signal output by the section detection unit (370) remains active between the falling time of the common node output and the time when both signals are activated.

[0044] When the section detection unit (370) outputs an UP signal, the counter (390) increments. In other words, whenever the output of the zero-current detection circuit (100) is in an early state, the counter (390) increments. When the output of the zero-current detection circuit (100) stabilizes and locks, the counter (390) maintains a constant value. Therefore, when the zero-current detection circuit restarts or when relocking is required due to sudden fluctuations, the counter (390) may be reset. In the illustrated embodiment, the output of the counter (390) starts from zero, gradually increases when the inductor current (IL) exhibits an offset in the form of an early delay, and is locked and maintains a constant value after the offset is eliminated. In one embodiment, the counter (390) may be reset by an MPPT_RST signal, which is Figure 1 a signal output when the maximum power point tracking algorithm of the switch control unit (700) is reset.

[0045] <Description of the inventions of Claim 4 and Claim 6>

[0046] According to one aspect, in the preamplifier of the zero-current detection circuit, the differential voltage can be adjusted according to an offset control signal. Figure 8 An embodiment of the zero-current detection circuit applying this aspect is shown. The zero-current detection circuit according to an embodiment may include a preamplifier (110) for differentially amplifying the voltages of a common node and a reference node, and a phase comparator (130) for detecting a zero-current point from the amplified differential voltage. The preamplifier differentially amplifies the voltages of the common node (VX) and the reference node (VR), but adjusts its differential voltage according to an offset control signal (CAL). The phase comparator (130) detects the zero-current point by receiving the differential voltage.

[0047] <Description of the inventions of Claim 7 and Claim 8>

[0048] Figure 9 is a circuit diagram of the preamplifier structure according to an embodiment of the present invention. As shown, the preamplifier according to an embodiment includes a first differential amplifier (113), a second differential amplifier (111), and a common current adjustment unit (117). The first differential amplifier (113) differentially amplifies the voltages of the common node (VX) and the reference node (VR), and outputs a positive differential voltage (OUT_P). The second differential amplifier (111) differentially amplifies the voltages of the common node (VX) and the reference node (VR), and outputs a negative differential voltage (OUT_N).

[0049] A current limiting circuit (115) is connected between the lower node of the first differential amplifier (113) and the ground terminal. The current limiting circuit (115) limits the common emitter current to a certain level and applies a clock signal that interrupts the circuit operation to this limiting circuit. Correspondingly, a common current regulating unit (117) is connected between the lower node of the second differential amplifier (111) and the ground terminal. The common current regulating unit (117) regulates the common emitter current according to the offset control signal (CAL) and applies a clock signal that interrupts the circuit operation to this common current regulating unit. However, the present invention is not limited thereto. The common current regulating unit (117) can be implemented in various forms, such as by a circuit that applies a bias to one of the input terminal or the output terminal on the preamplifier side, for example, by a voltage addition circuit or a current regulating circuit. Additionally, the common current regulating unit (117) can also be added to the first differential amplifier (111). In the illustrated embodiment, the common current regulating unit (117) is connected between the common terminal of the second differential amplifier (111) and the power supply terminal (here the ground terminal) and can be implemented by an array resistor whose connection of corresponding individual resistors is interrupted by each bit output by the counter. However, the common current regulating unit (117) can also be connected between the upper node of the differential amplifier and the power supply terminal (here the VDD terminal).

[0050] In Figure 8 and Figure 9 In the illustrated embodiment, the preamplifier and the phase comparator in the illustrated zero current detection circuit can be dynamic comparators. Due to positive feedback, compared with the static comparator, the dynamic comparator has the advantages of faster latching speed and lower static power consumption.

[0051] <Description of the inventions of Claim 10, Claim 11, and Claim 12>

[0052] According to another aspect of the present invention, the zero current detection circuit includes a plurality of dynamic comparators. The operating clocks of the dynamic comparators can be generated by a plurality of flip - flops. These flip - flops latch the output of each dynamic comparator and feed it to the clock of the subsequent dynamic comparator.

[0053] Figure 10It is a block diagram of a zero - current detection circuit structure according to another embodiment of the present invention. As shown in the figure, the zero - current detection circuit according to another embodiment includes a comparison circuit unit (150), a clock generation unit (170), and an output generation unit (190). The comparison circuit unit (150) receives the switch - node voltage and the output - node voltage of the boost - type power converter and detects the zero - current state. According to one embodiment, the comparison circuit unit (150) may include a plurality of dynamic comparators. Each dynamic comparator may have a structure similar to that of Figure 8 the embodiment shown. In one embodiment, each dynamic comparator includes a pre - amplifier and a phase comparator. The pre - amplifier is used to differentially amplify the voltages of the common node and the reference node, but adjusts the differential voltage according to an offset control signal. The phase comparator is used to receive the output differential voltage and detect the zero - current point.

[0054] The clock generation unit (170) is a circuit for generating the clock signal required for the operation of the comparison circuit unit (150). The output generation unit (190) generates and outputs a zero - current detection signal according to the output of the comparison circuit unit (150). The operation controller (120) receives Figure 1 the ON_TIME signal, the OFF_TIME signal output by the switch control unit (700) of the boost - type power converter shown, and the MPP_EN signal for activating the internal maximum - power - point - tracking algorithm of the switch control unit (700), and generates and outputs a control signal AMP_ON for activating the operation of the comparison circuit unit (150) and a SENS_START signal for activating the operation of the clock generation unit (170).

[0055] Figure 11 shows Figure 10 a more detailed structure of the comparison circuit unit, the clock generation unit, and the output generation unit in the embodiment of Figure 10 the embodiment shown. Similar structures corresponding to the embodiment shown are denoted by the same reference numerals. In the comparison circuit unit (150), the switch node and the output node of the boost - type power converter are used as a pair of detection nodes and are connected to the input terminals of each dynamic comparator. In the illustrated embodiment, one terminal of the low - voltage - side power switch of the boost - type power converter is connected to one input terminal of each dynamic comparator (151 - 1, …, 151 - 4) to apply the low - voltage - side voltage (VX), and one terminal of the high - voltage - side power switch of the boost - type power converter is connected to the other input terminal of each dynamic comparator (151 - 1, …, 151 - 4) to apply the high - voltage - side voltage (VR).

[0056] The clock generation unit (170) is a circuit for generating the clock signal required for the operation of the comparison circuit unit (150). The clock generation unit (170) includes a plurality of flip - flops (171 - 1, …, 171 - 4). Each flip - flop receives the output of the previous dynamic comparator as the clock signal and outputs it as the clock input of the subsequent dynamic comparator. For example, the flip - flop Q1 (171 - 1) receives the output of the previous dynamic comparator (151 - 1) as the clock signal and outputs it as the clock input of the subsequent dynamic comparator (151 - 2). The flip - flop Q2 (171 - 2) receives the output of the previous dynamic comparator (151 - 2) as the clock signal and outputs it as the clock input of the subsequent dynamic comparator (151 - 3). The flip - flop Q3 (171 - 3) receives the output of the previous dynamic comparator (151 - 3) as the clock signal and outputs it as the clock input of the subsequent dynamic comparator (151 - 4). The flip - flop Q4 (171 - 4) receives the output of the previous dynamic comparator (151 - 3) as the clock signal and outputs it as the clock input of the subsequent dynamic comparator (151 - 1).

[0057] From another perspective, the output pulse of the first dynamic comparator generates the clock input signal of the second dynamic comparator, the output pulse of the second dynamic comparator generates the clock input signal of the third dynamic comparator, the output pulse of the third dynamic comparator generates the clock input signal of the fourth dynamic comparator, and the output pulse of the fourth dynamic comparator generates the clock input signal of the first dynamic comparator. Therefore, the plurality of dynamic comparators (151 - 1, …, 151 - 4) and the plurality of flip - flops (171 - 1, …, 171 - 4) as a whole form a clock loop by themselves. Clock signals of different phases are sequentially input to each dynamic comparator, and each dynamic comparator detects zero current when the clock signal is activated and outputs a detection pulse. Since the clock required for the operation of the dynamic comparator can be generated without a separate oscillator, the chip area and power consumption can be reduced.

[0058] The output generation unit (190) performs a logical sum of the outputs of the plurality of dynamic comparators and outputs it. Therefore, when at least one of the plurality of dynamic comparators (151 - 1, …, 151 - 4) detects zero current and outputs a pulse, the output generation unit (190) can output it to the outside through an output terminal.

[0059] Figure 12 Shows Figure 11 the structure of an embodiment of the dynamic comparator in the embodiment of. As shown in the figure, according to an embodiment, the dynamic comparator includes a pre - amplifier (153) and a dynamic latch (155).

[0060] The front - end amplifier (153) receives the switch - node voltage (VX) and the output - node voltage (VR) of the power converter and outputs the difference voltage between the two ends. The dynamic latch (155) receives the output voltage of the front - end amplifier (153) and outputs a zero - current detection (OUTPB) pulse signal at the cross - time of the voltages at both ends of the switch node and the output node through comparison.

[0061] In the case of a boost - type power converter, the voltage is detected at the moment when the inductor is charged at the input end, that is, at the moment when the voltage is high. Therefore, a front - end amplifier is provided to ensure the stable operation of the comparator. The front - end amplifier differentially amplifies the switch - node voltage (VX) and the output - node voltage (VR), and by further reducing the gain, ensures the stable operation of the dynamic latch (155). In addition, the comparison circuit unit (150) includes a plurality of dynamic comparators (151 - 1, …, 151 - 4). Compared with a static comparator, the dynamic comparator has the advantage of less current consumption. These four dynamic comparators do not work simultaneously but work sequentially one by one.

[0062] In the illustrated embodiment, the front - end amplifier (153) works during the activation of the AMP_ON signal and differentially amplifies the input signal. When the AMP_ON signal is disabled, the internal current is interrupted, thereby minimizing the power consumption. The dynamic latch (155) is synchronized with the input clock and outputs a pulse when the output of the front - end amplifier (153) becomes "0". The front - end amplifier (153) determines the offset voltage, and the dynamic latch (155) determines the speed of the comparator. The structure of this kind of dynamic comparator is well - known, so the detailed description will be omitted.

[0063] Refer again to Figure 11 , at the reset terminal (RST) of each flip - flop (171 - 1, …, 171 - 4) of the clock generation unit (170), the output terminal of the previous flip - flop in the clock loop is connected. In the illustrated embodiment, the reset terminal of the flip - flop (171 - 1) is connected to the negative output terminal of the flip - flop (171 - 3), the reset terminal of the flip - flop (171 - 2) is connected to the negative output terminal of the flip - flop (171 - 4), the reset terminal of the flip - flop (171 - 3) is connected to the negative output terminal of the flip - flop (171 - 1), and the reset terminal of the flip - flop (171 - 4) is connected to the negative output terminal of the flip - flop (171 - 2). In the illustrated embodiment, the two previous output terminals are connected together, but this is a design choice and can be determined according to the pulse - width design of the output pulse.

[0064] According to another aspect of the present invention, each flip-flop of the clock generation unit is configured to be reset according to the output of the previous flip-flop in the loop during the discharge of the high-side power switch to the load. In Figure 11 the clock generation unit (170) includes a plurality of AND elements (173-1, …, 173-4). The output terminal of each AND element (173-1, …, 173-4) is connected to the reset terminal of a flip-flop, and the output terminal of the previous flip-flop in the loop and the output terminal of the turn-off time generator are connected to its input terminal. Therefore, when the turn-off time signal is in the active state, that is, when the high-side power switch is in the connected state and the inductor power supplies the load to discharge, it becomes a resetable state.

[0065] Figure 13 is a timing diagram describing the operation of the clock generation unit (170). As shown in the figure, the dynamic comparator (151-2) that starts the first operation receives the SENS_START signal as a clock and generates the output ENT2 of the flip-flop (Q1). If it is not the intersection point of the switch node voltage (VX) and the output node voltage (VR), a negative output OUTNB2 is generated in the output of the dynamic comparator (151-2) that receives the ENT2 signal. Then, the second flip-flop (Q2) starts and outputs the ENT3 signal. At the same time, the output ENTB3 signal is turned off, and the ENT2 signal is also turned off. It works in the order of ENT2->ENT3->ENT4->ENT1 and repeats until the moment when the switch node voltage (VX) and the output node voltage (VR) intersect. When any one of the outputs of the four dynamic comparators (151-1, …, 151-4) detects the intersection moment and generates a pulse, the output generation unit (190) generates the ZCD_OUT signal.

[0066] According to another aspect of the present invention, the boost power converter can be controlled such that the front-end amplifier of the dynamic comparator is turned on during the disconnection of the low-side power switch. Taking the boost power converter applying the present invention as an example, since the zero-current detection circuit (100) needs to work at the moment when the high-side power switch is turned on, the “SENS_START” signal and the “AMP_ON” signal need to be prepared to ensure that the zero-current detection circuit (100) can work when the OFF_TIME signal is turned on. Referring again to Figure 10 According to this aspect, the boost power converter of an embodiment of the present invention may further include an operation controller (120). Figure 14 shows the structure of the operation controller according to an embodiment of the present invention. As shown in the figure, the operation controller (120) includes a first operation controller (121). The first operation controller (121) is in Figure 1During the period when the ON_TIME output of the switch control unit (700) is disabled, a control signal for activating the comparison circuit unit (150) is output. Since the OFF_TIME signal is generated after the ON_TIME signal is turned off, the motion controller generates an AMP_ON signal to ensure that the front-end amplifier is activated at the moment when the ON_TIME signal is turned off.

[0067] As shown in the figure, the ON_TIME signal is Figure 1 a control signal output by the switch control unit (700) in the embodiment. This signal is input to the clock input terminal of the flip-flop (Q2) through an inverter (G2). Since the data input terminal of the flip-flop (Q2) is always fixed at the high level (H) state, when the ON_TIME signal changes from the high level state to the low level state, the output of the flip-flop (Q2) changes to the high level state. The ON_TIME signal is Figure 1 a control signal output by the switch control unit (700) in the embodiment. When this signal is disabled, the low-side power switch (550) is turned off, and the charging of the main inductor (510) by the input power supply is interrupted. At this time, the OFF_TIME signal output by the switch control unit (700) is almost simultaneously activated to turn on the high-side power switch (530), so that the main inductor (510) starts to supply power to the load.

[0068] As shown in the figure, the first motion controller (121) may include a first flip-flop (Q1) and a second flip-flop (Q2). The first flip-flop (Q1) Figure 1 turns on when the ON_TIME signal output by the switch control unit (700) is activated. The second flip-flop (Q2) turns on when the ON_TIME signal is disabled and is reset by the negative output of the first flip-flop (Q1). As Figure 11 and Figure 12 shown, the generated output, that is, the AMP_ON signal, is applied to the front-end amplifier (153) of the comparison circuit unit (150).

[0069] The logic circuit related to the triggers (Q1, Q3) of the motion controller (120) is a circuit that generates a signal for resetting the trigger (Q2) that generates the AMP_ON signal. When the MPP_EN signal and the ON_TIME signal are applied to the clock input terminals of the triggers (Q1, Q3) and both are activated, the zero-current detection circuit is disabled, and the logic circuit inside the zero-current detection circuit is reset to prevent improper operations. Specifically, the data input terminals of the trigger (Q2) and the trigger (Q1) are always fixed at the high level state (H). Therefore, when the ON_TIME signal transitions from the low level state to the high level state, the output of the trigger (Q2) will transition to the high level state. Thus, the front-end amplifier (153) of the comparison circuit unit (150) can start working when the conduction time signal ON_TIME is disabled and is reset when the conduction time signal ON_TIME is activated.

[0070] Furthermore, the motion controller (120) may further include a second motion controller (123). The second motion controller (123) outputs a SENS_START signal, which is a control signal that, when Figure 1 the OFF_TIME signal output by the switch control unit (700) of Figure 11 is activated, causes the clock generation unit (170) in

[0071] <Description of the method invention>

[0072] Figure 15 shows a flowchart of the structure of a power conversion control method according to an embodiment of the present invention. The power conversion method according to an embodiment is a power conversion method that can be applied to Figure 1 the power converter shown. The shown power converter is not limited to the boost type and can also be applied to the buck type or the combined type. Below, taking the Figure 1 shown power converter as the center, the power conversion control method of the present invention will be described.

[0073] As shown in the figure, the power conversion method according to an embodiment includes an offset calibration step (1100). In the offset calibration step (1100), the power converter detects the error between the output time of the zero-current detection circuit and the falling time of the output of the common node, and outputs a corresponding calibration signal to the zero-current detection circuit.

[0074] According to one aspect, the offset calibration step (1100) may include a fall time detection step (1110), a phase detection step (1130), and an offset signal generation step (1150). In the fall time detection step (1110), the offset calibration unit detects the fall time of the output of the common node. In the phase detection step (1130), the offset calibration unit detects the error between the output of the zero current detection circuit and the detected fall time. In the offset signal generation step (1150), the offset calibration unit generates an offset control signal proportional to the detected error and outputs it to the zero current detection circuit.

[0075] According to another aspect of the present invention, the offset signal generation step may further include a section detection step (1151) and an offset accumulation step (1155). In the section detection step (1151), the offset calibration unit detects the duration of the error detected in the phase detection step. In the offset accumulation step (1155), the offset calibration unit counts the duration detected in the section detection step and outputs the count value as the offset control signal.

[0076] According to another aspect of the present invention, the power conversion control method may include a zero current detection calibration step (1300) of adjusting the zero current detection timing according to the offset control signal. In one embodiment, the zero current detection calibration step (1300) includes a pre-amplification step (1310) and a phase comparison step (1330). In the pre-amplification step (1310), the zero current detection circuit differentially amplifies the voltages of the common node and the reference node and adjusts the differential voltage according to the offset control signal. In the phase comparison step (1330), the zero current detection circuit receives the differential voltage to detect the zero current point. The specific description of this power conversion method is similar to the description related to the previous device invention.

[0077] As described above, the present invention has been described with reference to the drawings and embodiments, but the present invention is not limited thereto, and the present invention should be construed as including various modifications obvious to those skilled in the art. The claims should include these modified embodiments.

[0078]

Symbol Explanation

[0079] 100: Zero current detection circuit 110: Preamplifier

[0080] 130: Phase comparator 120: Operation controller

[0081] 150: Comparison circuit unit 170: Clock generation unit

[0082] 190: Output generation unit 300: Offset calibration unit

[0083] 310: Fluctuation detector 330: Phase detector

[0084] 350: Offset signal generation unit 370: Section detection unit

[0085] 390: Counter 510: Energy storage element

[0086] 520: Power supply 530: High-voltage side power switch

[0087] 550: Low-voltage side power switch 570: Load

[0088] 700: Switch control unit

Claims

1. A power converter, comprising: Energy storage element; Low-voltage side power switch, one end of which is connected to a common node (VX) and is used to interrupt the charging of the energy storage element by the input power supply; High-voltage side power switch, one end of which is connected to the common node and is used to interrupt the discharge of the energy storage element to the load; Switch control unit, which is used to generate and output switch control signals for controlling the ON / OFF of the high-voltage side power switch and the low-voltage side power switch; And, Zero current detecting circuit, which is used to compare the outputs of the common node (VX) and the reference node (VR), detect the zero current moment, and output the detection signal to the switch control unit; Wherein, the power converter further comprises: Offset calibration unit, which is used to detect the error between the output time of the zero current detecting circuit and the falling time of the output of the common node, and output the corresponding calibration signal to the zero current detecting circuit.

2. The power converter according to claim 1, wherein, The offset calibration unit comprises: Phase Detector, which is used to receive the output signal of the zero current detecting circuit and the falling time signal of the output of the common node and detect the error.

3. The power converter according to claim 1, wherein, The offset calibration unit comprises: Falling time detection unit, which is used to detect the falling time of the output of the common node; Phase Detector, which is used to detect the error between the output of the zero current detecting circuit and the output of the falling time detection unit; and, Offset signal generating unit, which is used to output an offset control signal proportional to the detected error.

4. The power converter according to claim 3, wherein, The zero current detecting circuit comprises: Preamplifier, which is used to differentially amplify the voltages of the common node and the reference node and adjust the differential voltage according to the offset control signal; and, Phase comparator, which is used to receive the differential voltage and detect the zero current point.

5. The power converter according to claim 3, wherein, The offset signal generating unit comprises: Section detection unit, which is used to detect the duration of the phase difference signal output by the Phase Detector; and, Counter, which is used to output the increased offset control signal in the duration detected by the section detection unit.

6. The power converter according to claim 5, wherein, The zero current detecting circuit comprises: Preamplifier, which is used to differentially amplify the voltages of the common node and the reference node and adjust the differential voltage according to the offset control signal; and, Phase comparator, which is used to receive the differential voltage and detect the zero current point.

7. The power converter according to claim 6, wherein, The preamplifier comprises: First differential amplifier, which is used to differentially amplify the voltages of the common node and the reference node and output a positive differential voltage; Second differential amplifier, which is used to differentially amplify the voltages of the common node and the reference node and output a negative differential voltage; and, Common current regulating unit, which is used to adjust the common current of the first differential amplifier or the second differential amplifier according to the offset control signal.

8. The power converter according to claim 7, wherein, The common current regulating unit comprises: An array resistor, which is connected between any one of the common terminals of the first differential amplifier or the second differential amplifier and the power supply terminal, and the connection of each corresponding resistor is interrupted by each bit of the counter output.

9. The power converter according to claim 1, wherein The power converter is a boost type, and the reference node is the output node.

10. The power converter according to claim 3, wherein, The zero current detection circuit includes: A comparison circuit unit, which includes a plurality of dynamic comparators. Each dynamic comparator differentially amplifies the voltages of the common node and the reference node, and includes a preamplifier and a phase comparator. The preamplifier adjusts the differential voltage according to an offset control signal, and the phase comparator detects the zero current point by receiving the output differential voltage; A clock generation unit, which includes a plurality of flip-flops. Each flip-flop receives the clock signal output by the previous dynamic comparator and outputs it as the clock input for the subsequent dynamic comparator, thereby forming an overall clock loop; and An output generation unit, which is used to perform a logical sum on the outputs of the plurality of dynamic comparators and output.

11. The power converter according to claim 10, wherein, Each phase comparator includes: A dynamic latch, which is synchronized with the input clock and outputs a pulse at the moment when the output of the preamplifier becomes "0".

12. The power converter according to claim 11, wherein The reset input terminal of each flip-flop of the clock generation unit is connected to the output terminal of the previous flip-flop in the clock loop.

13. A power conversion control method for a power converter, wherein The power converter includes: An energy storage element; A low-voltage side power switch, one end of which is connected to the common node (VX), and is used to interrupt the charging of the energy storage element by the input power supply; A high-voltage side power switch, one end of which is connected to the common node, and is used to interrupt the discharge of the energy storage element to the load; A switch control unit, which is used to generate and output a switch control signal for controlling the ON / OFF of the high-voltage side power switch and the low-voltage side power switch; and A zero current detection circuit, which is used to compare the outputs of the common node (VX) and the reference node (VR), detect the zero current moment, and output the detection signal to the switch control unit; Wherein, the method includes: An offset calibration step, which detects the error between the output time of the zero current detection circuit and the falling time of the output of the common node, and outputs a corresponding calibration signal to the zero current detection circuit.

14. The power conversion control method according to claim 13, wherein, The offset calibration step includes: A falling time detection step, which detects the falling time of the output of the common node; A phase detection step, which detects the error between the output of the zero current detection circuit and the detected falling time; and An offset signal generation step, which generates an offset control signal proportional to the detected error and outputs it to the zero current detection circuit.

15. The power conversion control method according to claim 14, wherein, The offset signal generation step includes: A section detection step for detecting the duration of the error detected in the phase detection step; and, An offset accumulation step for counting the duration detected in the section detection step and outputting the count value as an offset control signal.

16. The power conversion control method according to claim 15, wherein, The power conversion control method includes: A pre-amplification step in which the zero-current detection circuit differentially amplifies the voltages of the common node and the reference node and adjusts the differential voltage according to the offset control signal; and, A phase comparison step in which the zero-current detection circuit receives the differential voltage and detects the zero-current point.

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