Power converter, primary controller, secondary controller and control method

Abstract

The embodiment of the invention provides a method for reducing power consumption of a power converter. The power converter is provided with an optical coupler. The method comprises the following steps: when a load corresponding to the power converter is separated, enabling the power converter to enter a standby mode; and, in the standby mode, in each default fixed period, switching on and off a photodiode current for a predetermined number of times, the photodiode current flowing through a photodiode in the optical coupler, the predetermined number of times being at least once.

Description

Technical Field

[0001] The present invention relates to a power converter that can operate in a standby mode, and more particularly to a power converter that can reduce power consumption in the standby mode, a related primary controller, and a control method. Background Art

[0002] Flyback converters are often used as the main architecture of battery chargers for mobile electronic products due to their simple architecture. A flyback converter has a feedback loop to regulate an output voltage to supply a load, such as a rechargeable battery of a mobile electronic product. When the rechargeable battery is connected to the flyback converter, the flyback converter operates in a normal operating mode; when the rechargeable battery is disconnected and no longer connected to the flyback converter, the flyback converter operates in a standby mode. In the normal operating mode, the feedback loop often has an error amplifier that generates an error signal based on the difference between an output voltage of the flyback converter and a desired target voltage. This error signal is low-pass filtered by a loop filter to generate a compensation signal that can be used to control a power switch in the flyback converter that determines energy conversion. In the standby mode, the feedback loop still needs to be active to stabilize the output voltage. Therefore, the flyback converter still consumes power in the standby mode, and this steady power consumption is often referred to as standby power or standby loss.

[0003] To reduce standby power, one method is to reduce the power consumption of the integrated circuit. When the compensation signal indicates a very light load or no load in the standby mode, many functional blocks in the integrated circuit are turned off to reduce the current consumption. However, with just this method alone, the feedback loop still needs to exist to monitor and control the output voltage. Especially when the feedback loop generates a compensation signal through an optocoupler, the power required to maintain the operation of the optocoupler in the standby mode often occupies the majority of the standby power.

[0004] U.S. Patent No. US11527962 describes an operating mode in a standby mode. In the standby mode, the optocoupler is generally turned off, but it is only turned on when the output voltage is low to call the primary controller for power conversion. Summary of the Invention

[0005] An embodiment of the present invention provides a secondary controller for a power converter. The secondary controller includes a feedback loop, a load detector, and a deep burst trigger. In a normal operation mode, the feedback loop is configured to generate a control signal based on a difference between an output voltage and a target voltage. Corresponding to detecting that a load is connected to the power converter, the load detector is configured to control the feedback loop in the normal operation mode. Corresponding to detecting that the load is not connected to the power converter, the load detector is configured to reduce the power consumption of the feedback loop in a standby mode. In the standby mode, the deep burst trigger is configured to switch a photodiode current a predetermined number of times at each default fixed period, the photodiode current flowing through a photodiode in an optocoupler, the predetermined number of times being at least one time.

[0006] An embodiment of the present invention provides a primary controller for a power converter. The primary controller includes a power modulator and a deep burst reactor. In a normal operation mode, the power modulator is configured to control a switching cycle of a power switch based on a compensation signal, and reduce the power consumption of the power modulator in a standby mode. In the standby mode, the deep burst reactor switches the power switch a predetermined number of times based on a change in the compensation signal, the predetermined number of times being at least one time. The compensation signal is controlled by an optocoupler.

[0007] An embodiment of the present invention provides a method for reducing the power consumption of a power converter. The power converter has an optocoupler. The method includes: corresponding to when a load of the power converter is disconnected, causing the power converter to enter a standby mode; and, in the standby mode, switching a photodiode current a predetermined number of times at each default fixed period, the photodiode current flowing through a photodiode in the optocoupler, the predetermined number of times being at least once.

[0008] An embodiment of the present invention provides a control method applicable to a secondary controller of a power converter. The power converter further includes an optocoupler having a photodiode. The method includes: in a normal operation mode, generating a control signal based on a difference between an output voltage and a reference voltage to control a photodiode current flowing through the photodiode; corresponding to when a load of the power converter is disconnected, regulating an output voltage of the power converter so that the output voltage has a default characteristic; and, after the output voltage loses the default characteristic, entering a standby mode and switching the photodiode current. Description of the Drawings

[0009] Figure 1 Displays a power converter 100 implemented according to the present invention.

[0010] Figure 2Displays the operating status diagrams of the primary controller 102 and the secondary controller 104.

[0011] Figure 3 Displays the primary controller 102.

[0012] Figure 4 Displays the secondary controller 104. Detailed implementation

[0013] To make the objectives, implementation methods, and advantages of the embodiments of the present invention clearer, the following will, in conjunction with the accompanying drawings of the embodiments, clearly and completely describe the implementation methods in the embodiments. The embodiments described in this specification are only a part of the embodiments of the present invention, not all of them. Those with ordinary knowledge in the relevant field of the present invention can make various modifications and variations to the embodiments described in this specification without departing from the spirit and scope of the present invention.

[0014] According to an embodiment of the present invention, a power converter has a primary controller and a secondary controller. When powering a load, the power converter can operate in a normal operation mode. When the secondary controller detects that the load is not connected to the power converter, the power converter can operate in a standby mode. When the load is not connected to the power converter, the secondary controller transmits a no-load message to the primary controller by regulating an output voltage of the power converter. Then, the secondary controller receives an acknowledgment message by detecting the output voltage before enabling the power converter to operate in the standby mode.

[0015] In one embodiment, in the standby mode, the primary controller and the secondary controller respectively operate in a deep burst detection state and a deep burst triggering state. In the deep burst triggering state, the secondary controller supplies the light-emitting diode current for a short time after turning off the light-emitting diode current for a long time. In the deep burst detection state, when the primary controller detects a change in the level of a compensation signal, it switches a power switch a predetermined number of times, and this predetermined number is at least one.

[0016] Figure 1 Displays the power converter 100 implemented according to the present invention. As an example, it has a flyback converter architecture. The present invention is not limited to flyback converters and can also be applied to power converters with other architectures. The input voltage V IN- Can be a DC voltage generated by full-wave rectification of the mains power supply, across the input power line VIN and the input ground wire GNDI on the input capacitor C1. The power converter 100 is used to convert the primary input voltage V IN, is converted to the output voltage V stored in the secondary by the output capacitor C4 OUT , across the output power line VOUT and the output ground line GNDO.

[0017] The primary controller 102 can be a pulse width modulation (PWM) integrated circuit (IC), providing a control signal S DRV , controlling the switching cycle of the power switch SW1. The input voltage V IN Supplies the electrical energy stored in the primary winding LP, which can be converted into a secondary current I through the secondary winding LS LS , charging the output capacitor C4 to establish the output voltage V OUT . The primary winding LP, the secondary winding LS, and the auxiliary winding LA can be three mutually inductively coupled windings in a transformer. The secondary controller 104 can control the synchronous rectifier switch SW4 to rectify the secondary current I LS Provide a rectification function. The voltage divider composed of resistors R3 and R4 provides a feedback voltage V FB , which can be regarded as a scaled-down version of the output voltage V OUT There is a differential amplifier OP1 in the secondary controller 104. According to the difference between the feedback voltage V FB and the reference voltage V REF , to generate a control signal S ERR . Since the feedback voltage V FB is a scaled-down version of the output voltage V OUT , so the differential amplifier OP1 is equivalent to generating a control signal S according to the difference between the output voltage V OUT and the target voltage V TAR (proportional to the reference voltage V REF ). To generate a control signal S ERR . The control signal S ERR can adjust the photocurrent I of the photodiode flowing through the optocoupler OPT through the switch SW2 OPTD . Corresponding to the photocurrent I OPTD , the current generated by the optocoupler OPT in the primary, after being low-pass filtered by the loop filter composed of the resistor R6 and the compensation capacitor C3, generates a compensation signal V COMP . The primary controller 102 can control the switching cycle of the power switch SW1 according to the compensation signal V COMP . For example, the higher the compensation signal V COMP , the higher the switching frequency of the power switch SW1 and the larger the duty cycle, so that the input voltage V INThe greater the electric power stored in the main winding LP. Thus, the resistors R3 and R4, the differential amplifier OP1, the optocoupler OPT, the compensation capacitor C3, the primary controller 102, the power switch SW1, the main winding LP, the secondary winding LS, and the output capacitor C4 can be regarded as a feedback loop, which can be used to regulate the output voltage V OUT to the target voltage V TAR .

[0018] When the secondary winding LS discharges the output capacitor C4, the winding voltage V of the auxiliary winding LA A can be regarded as a reflected signal, reflecting the output voltage V OUT . The reflected signal V S can be the product of proportional division of the winding voltage V by the voltage divider circuit formed by the resistors R1 and R2 A . Therefore, the reflected signal V S can represent the output voltage V OUT . The primary controller 102 can detect the output voltage V approximately by detecting the reflected signal V S . OUT

[0019] In one embodiment, the power converter 100 has a USB type-C interface. The power delivery (PD) controller 106 in the secondary controller 104 can be used as a load detector. By means of the data channels CC1 / CC2 (channel configuration) in the interface, it can determine whether a load 110 is connected to the USB type-C interface, generate a no-load signal NoLoad accordingly, and determine the reference voltage V REF , which is equivalent to setting the target voltage V TAR .

[0020] Figure 2 Shows the state diagram of the operation states of the primary controller 102 and the secondary controller 104. When the power delivery PD controller 106 detects that a load 110 is connected to the power converter 100, the power converter 100 can operate in the normal operation mode S02, using the feedback loop to regulate the output voltage V OUT . In the normal operation mode S02, the primary controller 102 and the secondary controller 104 can operate individually in the power modulation state S10 and the output voltage feedback state S20. In the output voltage feedback state S20, the PD controller 106 controls the feedback loop by determining the target voltage V TAR . The differential amplifier OP1 compares the output voltage V OUT and the target voltage V TAR , generating a control signal S​EER , controlling the optical diode current I OPTD , equivalently controlling the compensation signal V at the primary COMP . In the power modulation state S10, the primary controller 102 controls the switching cycle of the power switch SW1 according to the compensation signal V COMP , approximately determining the secondary current I for charging the output capacitor C4 LS . These two states S10 and S20 cooperate with each other to form a feedback loop, enabling the output voltage V OUT to be stabilized at the target voltage V TAR .

[0021] In the normal operation mode S02, the switch SW3 that can be used to control the optical diode current I OPTD is maintained in the off state.

[0022] When the PD controller 106 detects that the load 110 is disconnected and not connected to the power converter 100, the power converter 100 can operate in the standby mode S04, where the primary controller 102 and the secondary controller 104 operate in the deep burst detection state S12 and the deep burst trigger state S22 respectively. In the standby mode S04, the power consumption of the feedback loop is reduced. For example, the PD controller 106 can disable the differential amplifier OP1 to stop consuming power, maintain the switch SW2 in the off state, and the primary controller 102 turns off the compensation capacitor V COMP determines the turn-on time and switching frequency of the power switch SW1.

[0023] In the deep burst trigger state S22, the secondary controller 104 fixedly turns off the switch SW2, and every default fixed period, through the signal S OPT controls the switch SW3, and the optical diode current I flowing through the optocoupler OPT is switched OPTD a predetermined number of times, and this predetermined number is at least 1 time. For example, fixed at 20Hz (every 50ms), the secondary controller 104 only turns on the switch SW3 once, about 200us each time. Therefore, the compensation signal V at the primary COMP , will also be fixed at every 50ms and be pulled low briefly (lasting about 200us) by the optocoupler OPT once. Compared with the output voltage feedback state S20, in the deep burst trigger state S22, the power consumed by the optocoupler OPT is significantly reduced.

[0024] In the deep burst detection state S12, the primary controller 102 detects whether the compensation signal V COMP changes, and when detecting that the compensation signal V COMP has a high-low change, turns on the power switch SW1 a predetermined number of times, and this predetermined number is at least once. For example, in the compensation signal V COMPWhen rising across 1.4V, the primary controller 102 turns on the power switch SW1 once, and in this one time, the on-time of the power switch SW1 can be a fixed value, for example, a preset minimum on-time, or end when the current detection signal V at the current detection terminal VCS CS equals a default value (0.1V, for example).

[0025] In the deep burst detection state S12, the primary controller 102 can also start and continue the switching cycle of the power switch SW1 when the operating voltage V DD is low until the operating voltage V DD returns to the normal acceptable range. Thus, in the standby mode S04, the power converter 100 can approximately maintain the operating voltage V DD and the output voltage V OUT so that they do not become too low.

[0026] In Figure 2 , the primary controller 102 and the secondary controller 104 notify each other of about to break away from the normal operation mode S02 and enter the standby mode S04 by controlling the output voltage V OUT .

[0027] As Figure 2 shown, in the normal operation mode S02, when the secondary controller 104 finds that the load 110 is no longer connected to the power converter 100, the secondary controller 104 enters the no-load notification state S24, and the PD controller 106 sets the target voltage V TAR to a no-load default value, for example, 3.6V. Thereby, the secondary controller 104 transmits a no-load message to the primary controller 102. In one embodiment, in the output voltage feedback state S20, the target voltage V TAR is a normal value always greater than 5V. In the no-load notification state S24, the target voltage V TAR is the relatively low 3.6V, that is, it is desired to regulate the output voltage V OUT to 3.6V.

[0028] When the secondary controller 104 operates in the output voltage feedback state S20, the primary controller 102 can find that the output voltage V S is low from the reflected signal V OUT . In one embodiment, when the output voltage V OUT is 3.6V, the reflected signal V S will approximately fall within a predetermined range of 0.7V to 0.35V. Once the primary controller 102 finds that the reflected signal V S falls within such a predetermined range for a long time (more than 50ms), and the compensation signal V COMPalso keeps indicating that the current load 110 is a light load (V COMP <1.4V), then the primary controller 102 can confirm that it has received the no-load message, knows that the load 110 is no longer connected to the power converter 100, and enters the intermediate state S14.

[0029] In the intermediate state S14, the primary controller 102 continuously switches the power switch SW1 until the reflected signal V S is greater than 0.75V, and then enters the deep burst detection state S12. By forcibly raising the output voltage V OUT , the primary controller 102 sends a confirmation message to the secondary controller 104. For example, in the intermediate state S14, fixed at 33kHz (every 30us), the primary controller 102 turns on the power switch SW1 once. At this time, the on-time of the power switch SW1 is a preset minimum on-time, or the on-time of the power switch SW1 is determined by limiting the peak value of the current detection signal V CS . In this way, the output voltage V OUT and the reflected signal V S will gradually rise over time. After the reflected signal V S is greater than 0.75V, the primary controller 102 directly enters the deep burst detection state S12, which is equivalent to entering the standby mode S04.

[0030] In the no-load notification state S24, the target voltage V TAR is set to 3.6V (an example). However, the primary controller 102 in the intermediate state S14 forcibly raises the output voltage V OUT . Therefore, when the secondary controller 104 finds that the output voltage V OUT was originally dropping towards 3.6V, but after a period of time was forcibly raised by the primary controller 102 to exceed 4V (a response default value), it can be determined that it has received the confirmation message sent by the primary controller 102, so the secondary controller 104 exits the no-load notification state S24 and enters the deep burst trigger state S22, which is equivalent to entering the standby mode S04.

[0031] Figure 2 also shows how the primary controller 102 exits the standby mode S04. If the power switch SW1 has not been turned on for too long, or the compensation signal V COMP is too low for too long, the primary controller 102 exits the deep burst detection state S12 and returns to the normal operation mode S02. For example, if the compensation signal V COMP has been greater than 1.4V for 700ms (so the power switch SW1 has not been turned on for 700ms), or the compensation signal V COMP is below 0.5V and remains so for more than 10ms, the primary controller 102 exits the deep burst detection state S12.

[0032] Figure 2 also shows the timing at which the secondary controller 104 exits the standby mode S04: when the load 110 is connected to the power converter 100, or when the output voltage V OUT exceeds 5.5V. For example, after exiting the standby mode S04, the secondary controller 104 first turns on the switch SW3 for a preset notification time (step S26), such as 20 ms, and then sets the target voltage V TAR to 5V (step S28), and then returns to the output voltage feedback state S20 in the normal operation mode S02.

[0033] Please refer to Figure 2 and Figure 3 . Figure 3 As an example, it shows that the primary controller 102 can implement Figure 2 the state diagram of the primary controller 102 in

[0034] The power modulator 140 implements the power modulation state S10 and controls the switching cycle of the power switch SW1 according to the compensation signal V COMP . The standby detector 144 has three comparators and a debouncing apparatus 146. When it is found that the reflected signal V S falls between 0.7V and 0.35V, the compensation signal V COMP is always lower than 1.4V, and after both of these conditions have persisted for 50 ms, the standby detector 144 causes the power modulator 140 to reduce power consumption through the SR flip-flop 142, causing the primary controller 102 to exit the power modulation state S10, and also causing the primary controller 102 to enter the intermediate state S14 through the SR flip-flop 150. After exiting the power modulation state S10, the power modulator 140 no longer drives the power switch SW1 according to the compensation signal V COMP . For example, the circuit in the power modulator 140 used to detect the compensation signal V COMP- is turned off and no longer consumes power, the drive circuit in the power modulator 140 used to drive the power switch SW1 is also turned off, and the power modulator 140 no longer drives the power switch SW1.

[0035] In the intermediate state S14, the SR flip-flop 150 causes the periodic oscillator 148 to start controlling the power switch SW1 at a switching frequency of 33 kHz. In each switching cycle (for example, 33 us), the on-time of the power switch SW1 is a preset minimum on-time, or the on-time of the power switch SW1 is determined by limiting the peak value of the current detection signal V CS .

[0036] When the comparator 152 finds that the reflected signal VS When it exceeds 0.75V, the comparator 152, through the SR flip-flop 150, causes the primary controller 102 to exit the intermediate state S14 and stops the cycle oscillator 148; at the same time, the comparator 152 also, through the SR flip-flop 154, causes the primary controller 102 to enter the deep burst detection state S12, enabling the deep burst reactor 162 to start working.

[0037] In the deep burst detection state S12, Figure 3 the D flip-flop 156 in... enables the cycle oscillator 160 when the compensation signal V COMP climbs past 1.4V. The cycle oscillator 160 starts and sustains the switching cycle of the power switch SW1, generating many pulses. When the pulses reach a predetermined number (at least once), the counter and comparator 161 disable the cycle oscillator 160 by resetting the D flip-flop 156 until the next time the compensation signal V COMP climbs past 1.4V and the cycle oscillator 160 is enabled. When the predetermined number is only once, the counter and comparator 161 can be directly omitted.

[0038] In the deep burst detection state S12, the deep burst reactor 160 can prevent the operating voltage V DD from being too low. As Figure 3 shown, when the operating voltage V DD is lower than 10V, the cycle oscillator 160 starts and sustains the switching cycle of the power switch SW1 to raise the operating voltage V DD until there is no problem with the operating voltage V DD being too low.

[0039] In the deep burst detection state S12, when the time that the compensation signal V COMP is lower than 0.5V exceeds 10ms (judged by the output of the defibrillator 168), or when the time that the power switch SW1 remains off exceeds 700ms (judged by the output of the defibrillator 166), the standby release 164 causes the primary controller 102 to exit the deep burst detection state S12 by resetting the SR flip-flop 154 and stops the operation of the deep burst reactor 162. At the same time, the standby release 164 also causes the primary controller 102 to enter the power modulation state S10 by resetting the SR flip-flop 142, and the power modulator 140 operates normally.

[0040] Please refer to Figure 2 and Figure 4 . Figure 4 As an example, it shows the secondary controller 104, which can achieve Figure 2 the state transition of the secondary controller 104 in...

[0041] Figure 4In the embodiment, the target voltage V TAR is twice the reference voltage V REF . In the output voltage feedback state S20 of the normal operation mode S02, when the load 110 is connected to the USB type-C interface, the PD controller 106 makes the no-load signal NoLoad logically "0", and negotiates with the load 110 through the data channels CC1 / CC2 to determine that the reference voltage V REF is at least 2.5V, so the target voltage V TAR is greater than 5V. At this time, the standby signal DBM output by the SR flip-flop 180 is logically "0", enabling the differential amplifier OP1. The differential amplifier OP1 compares the feedback voltage V FB with the reference voltage V FB to control the photodiode current I OPTD .

[0042] Once it is found that the load 110 is not connected to the USB type-C interface, the PD controller 106 makes the no-load signal NoLoad become logically "1", and the reference voltage V REF becomes 1.8V. Since the differential amplifier OP1 still normally controls the photodiode current I OPTD through the switch SW2, the feedback voltage V FB will slowly approach 1.8V. At this time, the secondary controller 104 enters the no-load notification state S24.

[0043] After the feedback voltage V FB is lower than 2V and then returns to 2V, the comparator 182 will generate a rising edge, and this rising edge sets the SR flip-flop 180 to make the standby signal DBM logically "1". At this time, the secondary controller 104 exits the no-load notification state S24 and enters the deep burst trigger state S22 in the standby mode S04. The comparator 182 is equivalent to comparing the output voltage V OUT with 4V (response default value).

[0044] In the deep burst trigger state S22, the standby signal DBM disables the differential amplifier OP1 and fixedly closes the switch SW2; the frequency generator 184 (which can be regarded as a deep burst trigger) is enabled and fixedly generates a pulse with a frequency of 20 Hz and a pulse width of 200 us each time. Such a pulse will turn on the photodiode current I OPTD through the switch SW3. Therefore, the photodiode current I OPTDThe duty cycle is only 200 us / 50 ms, less than 0.5%, almost equal to 0. Therefore, in the deep burst trigger state S22, the secondary controller 104 consumes very little electrical energy. In another embodiment, when the frequency generator 184 is enabled, it is fixed at a frequency of 20 Hz, generating two pulses with a pulse width of 100 us each time, and the two pulses are spaced 1 us apart from each other.

[0045] When the feedback voltage V FB is greater than 2.75 V, that is, the output voltage V OUT is greater than 5.5 V, or when the PD controller 106 detects that the load 110 is connected to the USB type-C interface, making the no-load signal NoLoad logically "0", the standby release 186 resets the SR flip-flop 180, stops the frequency generator 184, and also enables the differential amplifier OP1, resuming to drive the switch SW2 with the difference between the feedback voltage V FB and the reference voltage V REF . At this time, the standby release 186 also causes the PD controller 106 to set the reference voltage V REF to 2.5 V, that is, the target voltage V TAR is 5 V. Briefly, the standby release 186 can cause the secondary controller 104 to exit the deep burst trigger state S22 and enter the output voltage feedback state S20. When the standby release 186 causes the secondary controller 104 to exit the deep burst trigger state S22, the single-pulse generator 188 causes the switch SW3 to remain open for 20 ms and then close.

[0046] In Figure 2 this embodiment, the secondary controller 104 transmits a no-load message to the primary controller 102 by regulating the output voltage V OUT , and the primary controller 102 also transmits an acknowledgment message to the secondary controller 104 by strongly pulling the output voltage V OUT . However, the present invention is not limited to this. In other embodiments, the secondary controller 104 can vary the level of the output voltage V OUT to transmit a message to the primary controller 102. For example, when the secondary controller 104 detects that the load 110 is not connected to the USB type-C interface, it can force the output voltage V OUT to fluctuate between 5 V and 7 V to form a digital code, allowing the primary controller 102 to detect such a code through the reflected signal V S and determine whether to enter a special operating state, such as a standby state. Similarly, before entering a standby state, the primary controller 102 can also form a digital code by controlling the output voltage V OUT to transmit a message to the secondary controller 104, informing it that it is about to enter the standby state.

[0047] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope covered by the present invention.

[0048]

Symbol Description

[0049] 100 Power converter

[0050] 102 Primary controller

[0051] 104 Secondary controller

[0052] 106 PD controller

[0053] 110 Load

[0054] 140 Power modulator

[0055] 142 SR flip-flop

[0056] 144 Standby detector

[0057] 146 Defibrillator

[0058] 148 Periodic oscillator

[0059] 150 SR flip-flop

[0060] 152 Comparator

[0061] 154 SR flip-flop

[0062] 156 D flip-flop

[0063] 160 Periodic oscillator

[0064] 161 Counter and comparator

[0065] 162 Deep burst reactor

[0066] 164 Standby release

[0067] 166, 168 Defibrillators

[0068] 180 SR flip-flop

[0069] 182 Comparator

[0070] 184 Frequency generator

[0071] 186 Standby release

[0072] 188 Single pulse generator

[0073] C1 Input capacitor

[0074] C3 Compensation capacitor

[0075] C4 Output Capacitor

[0076] CC1 / CC2 Data Channel

[0077] DBM Standby Signal

[0078] GNDI Input Ground Wire

[0079] GNDO Output Ground Wire

[0080] I LS Secondary Current

[0081] I OPTD Photodiode Current

[0082] LA Auxiliary Winding

[0083] LP Primary Winding

[0084] LS Secondary Winding

[0085] NoLoad No-Load Signal

[0086] OP1 Differential Amplifier

[0087] OPT Optocoupler

[0088] R1~R6 Resistors

[0089] S02 Normal Operation Mode

[0090] S04 Standby Mode

[0091] S10 Power Modulation State

[0092] S12 Deep Burst Detection State

[0093] S14 Intermediate State

[0094] S20 Output Voltage Feedback State

[0095] S22 Deep Burst Trigger State

[0096] S24 No-Load Notification State

[0097] S26、S28 Steps

[0098] S ERR Control Signal

[0099] S DRV Control Signal

[0100] S OPT Signal

[0101] SW1 Power Switch

[0102] SW2 switch

[0103] SW3 switch

[0104] SW4 synchronous rectification switch

[0105] V A Winding voltage

[0106] V COMP Compensation signal

[0107] V CS Current detection signal

[0108] VCS current detection terminal

[0109] V DD Operating voltage

[0110] V FB Feedback voltage

[0111] V IN- Input voltage

[0112] VIN input power line

[0113] V OUT Output voltage

[0114] VOUT output power line

[0115] V REF Reference voltage

[0116] V S Reflection signal

[0117] V TAR Target voltage

Claims

1. A secondary controller for a power converter, the secondary controller comprising: a feedback loop, in a normal mode of operation, configured to generate a control signal according to a difference between an output voltage and a target voltage; a load detector, corresponding to detecting that a load is connected to the power converter, the load detector being configured to control the feedback loop in the normal operation mode, and corresponding to detecting that the load is not connected to the power converter, the load detector being configured to power down the feedback loop in a standby mode of operation; and A deep burst trigger is configured to switch a photodiode current a predetermined number of times in each default fixed period in the standby mode, wherein the photodiode current flows through a photodiode in an optical coupler, and the predetermined number of times is at least once.

2. The secondary controller of claim 1, wherein: In response to detecting that the load is not connected to the power converter, the load detector sets the target voltage to a no-load default value. In response to detecting that the load is connected to the power converter, the load detector sets the target voltage to a normal value that is higher than the no-load default value.

3. The secondary controller as described in claim 2 further includes a comparator to compare the output voltage and a response default value, which is higher than the no-load default value. When the output voltage is higher than the response default value, the comparator causes the secondary controller to enter the standby mode.

4. The secondary controller of claim 1, wherein: When the secondary controller operates in the standby mode, in response to detecting that the load is connected to the power converter, the connection line no-load detector turns on the photodiode current for a preset notification time.

5. The secondary controller as claimed in claim 1 further comprises a transistor connected in series with the photodiode current, wherein: The deep burst trigger is configured to switch the transistor at least once per the default fixed period to switch the photodiode current.

6. The secondary controller of claim 1, wherein: The load detector detects a data channel to determine that the load is not connected to the power converter.

7. A primary controller for a power converter, comprising: a power modulator configured to control a switching cycle of a power switch according to a compensation signal in a normal operation mode, and to reduce power consumption of the power modulator in a standby mode; and a deep burst reactor, which, in the standby mode, switches the power switch a predetermined number of times according to a change of the compensation signal, wherein the predetermined number of times is at least one; in, The compensation signal is controlled by an optical coupler.

8. The primary controller as claimed in claim 7, further comprising: A standby detector, based on a reflected signal, causes the primary controller to leave the normal operation mode and enter the standby mode, wherein: The reflected signal may represent an output voltage of the power converter.

9. The primary controller of claim 8, wherein: When the reflected signal meets a first condition, the intermediate system causes the primary controller to leave the normal operation mode first, and when the reflected signal meets a second condition, the primary system enters the standby mode.

10. The primary controller as claimed in claim 9, further comprising: A periodic oscillator is used to continuously switch the power switch to increase the output voltage after the primary controller leaves the normal operation mode and before entering the standby mode.

11. The primary controller of claim 7, wherein: The deep burst reactor continuously switches the power switch when an operating power source at the primary side is lower than a preset value.

12. A method for reducing power consumption of a power converter, wherein: The power converter has an optical coupler, and the method includes: When a load corresponding to the power converter is disconnected, the power converter enters a standby mode; and In the standby mode, in each default fixed period, a photodiode current is switched on and off for a predetermined number of times, and the photodiode current flows through a photodiode in the optical coupler, and the predetermined number of times is at least once.

13. The method of claim 12, further comprising: When the load is connected to the power converter, the power converter is operated in a normal operation mode; In the normal operation mode, a feedback loop is provided to control a photodiode current flowing through a photodiode of an optocoupler according to a difference between an output voltage of the power converter and a target voltage; and In the standby mode, the power consumption of the feedback loop is reduced.

14. The method of claim 13, wherein: The power converter includes a primary controller and a secondary controller, and the method further includes: When the load of the corresponding power converter is disconnected, the primary controller is notified that the load is disconnected by adjusting the output voltage; as well as After detecting the output voltage and determining that the primary controller is about to enter the standby mode, the secondary controller is caused to enter the standby mode.

15. The method of claim 13, wherein: The power converter includes a primary controller and a secondary controller, and the method further includes: By detecting a reflected signal, it is known that the load has been disconnected, and the primary controller is disconnected from the normal operation mode, wherein the reflected signal can represent the output voltage; After the primary controller leaves the normal operation mode, informing the secondary controller that the primary controller is about to enter the standby mode by controlling the output voltage; and After the reflected signal meets a default condition, the primary controller is enabled to enter the standby mode.

16. A control method, applicable to a secondary controller of a power converter, wherein: The power converter further includes an optical coupler having a photodiode. The method includes: In a normal operation mode, a control signal is generated according to a difference between an output voltage and a reference voltage to control a photodiode current flowing through the photodiode; When a load of the power converter is disconnected, regulating an output voltage of the power converter so that the output voltage has a default characteristic; as well as After the output voltage loses the default characteristic, it enters a standby mode to switch the photodiode current.

17. The control method according to claim 16, comprising: In response to the load being disconnected from the power converter, regulating the output voltage to be lower than a response default value; and After the output voltage is higher than the response default value, the standby mode is entered.

18. The control method according to claim 16, wherein: In the standby mode, in each default fixed period, the photodiode current is switched on and off a predetermined number of times, and the predetermined number of times is at least 1 time.

19. The control method according to claim 16, wherein: In the standby mode, the duty cycle of the photodiode current is less than 1%.

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