Crystal oscillator anti-interference shaping circuit

Abstract

The invention discloses a crystal oscillator anti-interference shaping circuit which comprises a reference current source, a fourth NMOS (N-channel Metal Oxide Semiconductor) tube, a fourth PMOS (P-channel Metal Oxide Semiconductor) tube, a fifth NMOS tube, a fifth PMOS tube, a second capacitor and a comparator, the grid end and the drain end of the fourth NMOS tube and the grid end of the fifth NMOS tube are in short circuit connection with the reference current source; the source end of the fourth NMOS tube, the source end of the fifth PMOS tube, the source end of the fourth PMOS tube and the negative input end of the comparator are in short circuit with a node A; the grid end and the drain end of the fourth PMOS tube and the grid end of the fifth PMOS tube are grounded; the drain end of the fifth PMOS tube and the source end of the fifth NMOS tube are both in short circuit connection with the node B; the drain end of the fifth NMOS tube, the positive input end of the comparator and one end of the second capacitor are connected with a node C; the other end of the second capacitor is connected with sine wave output signals of the crystal oscillator. According to the anti-interference shaping circuit of the crystal oscillator, interference on an output signal caused by direct-current level change of an input signal due to interference of an external environment can be effectively avoided without adopting a large resistor, and a stable and accurate clock signal is output.

Description

Technical Field

[0001] The present invention relates to circuit design technology, and particularly to a crystal oscillator anti-interference shaping circuit. Background Art

[0002] The function of a crystal oscillator circuit is to provide a stable and accurate clock signal for a chip. Due to its low cost and simple use, a microcontroller unit (MCU) usually uses a crystal oscillator as the main clock source. The usage scenarios of microcontroller units are relatively complex and are often subject to various external interferences. Therefore, the anti-interference ability of a crystal oscillator circuit is an important indicator for measuring the performance of the crystal oscillator circuit. Optimizing the shaping circuit of the crystal oscillator is the main means to improve the anti-interference ability of the crystal oscillator circuit.

[0003] In the prior art, the simplest crystal oscillator shaping circuit converts the sine oscillation signal output by the crystal oscillator into a square wave signal through an inverter. However, since this shaping method lacks hysteresis, external noise will interfere with the output waveform of the clock signal. In the case of simulating strong external electromagnetic interference, the output result of using a traditional comparator for shaping is as Figure 1 shown. When there is a DC offset in the crystal oscillator oscillation signal, signal non-overlap may occur at both ends of the comparator input. At this time, even if the crystal oscillator itself is still oscillating, the shaping module will no longer output a clock signal, causing the entire crystal oscillator module to fail.

[0004] To enhance the anti-interference ability, a Schmidt trigger or a comparator is usually used in the shaping circuit to introduce hysteresis. Compared with a Schmidt trigger, a comparator is a differential input circuit and can better eliminate common-mode noise. For example, in the Chinese invention application with the application number 202310314774.0, the first stage of its shaping module uses a comparator to eliminate the common-mode noise at both ends of the crystal oscillator, then the second stage uses a Schmidt trigger to introduce hysteresis, and the last-stage inverter is used to convert the sine wave into a square wave. However, when the crystal oscillator is subject to differential-mode noise interference at both ends, this shaping circuit will have the opposite effect, as Figure 2 shown. When there is a differential-mode deviation in the DC levels of the input signals at both ends, the comparator output may become a constant level instead of an oscillation signal.

[0005] To solve the problem of DC level offset, the Chinese utility model patent with the publication number CN213717956U uses a DC blocking technique to complete the shaping of the crystal oscillator output signal, as Figure 3 shown. The specific implementation is to connect a capacitor C1 before the input of the first-stage inverter and connect a very large resistor R1 in series between the input and output of the inverter to provide a DC bias point. This solution can provide a stable DC bias point, so it can effectively solve the interference to the output signal caused by the change in the DC level of the input signal due to external environmental interference, but the price is that a very large resistor (usually in the order of megohms) is required. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a crystal oscillator anti-interference shaping circuit, which can effectively avoid the interference to the output signal caused by the change of the DC level of the input signal due to external environmental interference without using a large resistor, and output a stable and accurate clock signal.

[0007] To solve the above technical problem, the crystal oscillator anti-interference shaping circuit provided by the present invention includes a reference current source I1, a fourth NMOS transistor NM4, a fourth PMOS transistor PM4, a fifth NMOS transistor NM5, a fifth PMOS transistor PM5, a second capacitor C2 and a comparator COMP1;

[0008] The gate and drain of the fourth NMOS transistor NM4 and the gate of the fifth NMOS transistor NM5 are short-circuited to the reference current source I1;

[0009] The source of the fourth NMOS transistor NM4, the source of the fifth PMOS transistor PM5, the source of the fourth PMOS transistor PM4 and the negative input terminal of the comparator COMP1 are short-circuited to node A;

[0010] The gate and drain of the fourth PMOS transistor PM4 and the gate of the fifth PMOS transistor PM5 are both connected to ground;

[0011] The drain of the fifth PMOS transistor PM5 and the source of the fifth NMOS transistor NM5 are both short-circuited to node B;

[0012] The drain of the fifth NMOS transistor NM5, the positive input terminal of the comparator COMP1 and one end of the second capacitor C2 are connected to node C;

[0013] The other end of the second capacitor C2 is connected to the sine wave output signal XI of the crystal oscillator.

[0014] Preferably, the size ratio of the fourth NMOS transistor NM4 to the fifth NMOS transistor NM5 is 1:M;

[0015] The size ratio of the fourth PMOS transistor PM4 to the fifth PMOS transistor PM5 is 1:M;

[0016] M is a positive number.

[0017] Preferably, M is greater than 2.

[0018] Preferably, M is 3, 4, 8, 17 or 20.

[0019] Preferably, the crystal oscillator anti-interference shaping circuit further includes a Schmitt trigger and an inverter;

[0020] The output of the comparator COMP1 is connected to the input of the Schmitt trigger;

[0021] The inverter is cascaded at the output end of the Schmitt trigger.

[0022] Preferably, the second capacitor C2 is a ceramic coupling capacitor, a metallized polyimide film coupling capacitor or a corrugated paper coupling capacitor.

[0023] Preferably, the second capacitor C2 is less than 10 pf.

[0024] In the crystal oscillator anti-interference shaping circuit of the present invention, the reference current source I1 provides current bias for the whole branch, so that the diode-connected fourth NMOS transistor NM4 and the fourth PMOS transistor PM4 operate in the saturation region, and the voltage of node A is almost independent of the power supply voltage VCC. The fifth NMOS transistor NM5 and the fifth PMOS transistor PM5 are used to replace the large resistor used in the conventional DC blocking technology. When the sine wave output signal XI of the crystal oscillator is in the positive half cycle of the sine wave, under the coupling of the second capacitor C2, the voltage of node C starts to rise and begins to exceed the voltage of node B. Since the fourth NMOS transistor NM4 is in the saturation region and the gate voltage of the fourth NMOS transistor NM4 is the same as the gate voltage of the fifth NMOS transistor NM5, as the voltage difference between node B and node C increases, the fifth NMOS transistor NM5 turns on and enters the saturation region. At this time, even if the voltage of node C continues to increase, most of the voltage difference is absorbed by the fifth NMOS transistor NM5, and a small part of the voltage difference will drop between node B and node A, making the fifth PMOS transistor PM5 turn on and enter the linear region. In this way, the voltage of node A will not be affected by the capacitive coupling effect of the second capacitor C2 under the isolation of the fifth PMOS transistor PM5 and the fifth NMOS transistor NM5, and will provide a stable DC level for the comparator COMP1 to shape. When the fifth NMOS transistor NM5 is in the saturation region and the fifth PMOS transistor PM5 is in the linear region, due to the source degeneration effect, the equivalent linear region resistance of the fifth PMOS transistor PM5 will be amplified by the intrinsic gain of the fifth NMOS transistor NM5, so it is easy to make its equivalent resistance reach the megohm level. When the sine wave output signal XI of the crystal oscillator is in the negative half cycle of the sine wave, similarly, it can be obtained that at this time the fifth PMOS transistor PM5 is in the saturation region and the fifth NMOS transistor NM5 is in the linear region, and its equivalent resistance can also reach the megohm level. The megohm-level equivalent resistance and the second capacitor C2 realize the isolation between the AC change signal of the sine wave output signal XI of the crystal oscillator and the DC bias point (node A), so that the two input ends of the comparator COMP1 have the same common-mode comparison voltage, eliminating the interference of the sine wave output signal XI of the crystal oscillator on the output waveform due to the DC level shift. The crystal oscillator anti-interference shaping circuit can effectively avoid the interference on the output signal caused by the change of the DC level of the input signal due to external environmental interference without using a large resistor, and outputs a stable and accurate clock signal. Description of the Drawings

[0025] To more clearly illustrate the technical solution of the present invention, the following briefly introduces the accompanying drawings required for the present invention. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0026] Figure 1 It is a schematic diagram of the output result of shaping using a traditional comparator under the condition of simulating external strong electromagnetic interference;

[0027] Figure 2 It is a schematic diagram of the output result of shaping when the crystal oscillator is subjected to differential-mode noise interference in Chinese Patent Application No. 202310314774.0;

[0028] Figure 3 It is the crystal oscillator buffer circuit of the crystal oscillator in Chinese Patent Document CN213717956U;

[0029] Figure 4 It is an embodiment of the crystal oscillator anti-interference shaping circuit of the present invention;

[0030] Figure 5 It is a schematic diagram of the output result of an embodiment of the crystal oscillator anti-interference shaping circuit of the present invention. Specific Embodiments

[0031] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0032] The "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Terms such as "including" or "comprising" mean that the elements or objects appearing before this term cover the elements or objects listed after this term and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", etc. are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.

[0033] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0034] Embodiment 1

[0035] A crystal oscillator anti-interference shaping circuit is as Figure 4 shown, which includes a reference current source I1, a fourth NMOS transistor NM4, a fourth PMOS transistor PM4, a fifth NMOS transistor NM5, a fifth PMOS transistor PM5, a second capacitor C2, and a comparator COMP1;

[0036] The gate and drain terminals of the fourth NMOS transistor NM4 and the gate terminal of the fifth NMOS transistor NM5 are short-circuited to the reference current source I1;

[0037] The source terminal of the fourth NMOS transistor NM4, the source terminal of the fifth PMOS transistor PM5, the source terminal of the fourth PMOS transistor PM4, and the negative input terminal of the comparator COMP1 are short-circuited to node A;

[0038] The gate and drain terminals of the fourth PMOS transistor PM4 and the gate terminal of the fifth PMOS transistor PM5 are both connected to ground;

[0039] The drain terminal of the fifth PMOS transistor PM5 and the source terminal of the fifth NMOS transistor NM5 are both short-circuited to node B;

[0040] The drain terminal of the fifth NMOS transistor NM5, the positive input terminal of the comparator COMP1, and one end of the second capacitor C2 are connected to node C together;

[0041] The other end of the second capacitor C2 is connected to the sine wave output signal XI of the crystal oscillator.

[0042] Preferably, the size ratio of the fourth NMOS transistor NM4 to the fifth NMOS transistor NM5 is 1:M, and the size (such as the channel length) ratio of the fourth PMOS transistor PM4 to the fifth PMOS transistor PM5 is 1:M; M is a positive number. The sizes of the fifth NMOS transistor NM5 and the fifth PMOS transistor PM5 are in a proportional relationship with the fourth NMOS transistor NM4 and the fourth PMOS transistor PM4 respectively.

[0043] Preferably, M is greater than 2.

[0044] Preferably, M is 3, 4, 8, 17, or 20, etc.

[0045] For the crystal oscillator anti-interference shaping circuit of Embodiment 1, the reference current source I1 provides current bias for the entire branch, so that the diode-connected fourth NMOS transistor NM4 and the fourth PMOS transistor PM4 operate in the saturation region, and the voltage of node A is almost independent of the power supply voltage VCC. The fifth NMOS transistor NM5 and the fifth PMOS transistor PM5 are used to replace the large resistor used in the conventional DC blocking technique. When the sine wave output signal XI of the crystal oscillator is in the positive half cycle of the sine wave, under the coupling of the second capacitor C2, the voltage of node C starts to rise and begins to exceed the voltage of node B. Since the fourth NMOS transistor NM4 is in the saturation region and the gate voltage of the fourth NMOS transistor NM4 is the same as the gate voltage of the fifth NMOS transistor NM5, as the voltage difference between node B and node C increases, the fifth NMOS transistor NM5 conducts and enters the saturation region. At this time, even if the voltage of node C continues to increase, most of the voltage difference is absorbed by the fifth NMOS transistor NM5, and a small part of the voltage difference will drop between node B and node A, causing the fifth PMOS transistor PM5 to conduct and enter the linear region. In this way, the voltage of node A will not be affected by the capacitive coupling of the second capacitor C2 under the isolation of the fifth PMOS transistor PM5 and the fifth NMOS transistor NM5, and will provide a stable DC level for the comparator COMP1 to shape. When the fifth NMOS transistor NM5 is in the saturation region and the fifth PMOS transistor PM5 is in the linear region, due to the source degeneration effect, the equivalent linear region resistance of the fifth PMOS transistor PM5 will be amplified by the intrinsic gain of the fifth NMOS transistor NM5, so it is easy to make its equivalent resistance reach the megohm level. When the sine wave output signal XI of the crystal oscillator is in the negative half cycle of the sine wave, it can be similarly obtained that at this time the fifth PMOS transistor PM5 is in the saturation region and the fifth NMOS transistor NM5 is in the linear region, and its equivalent resistance can also reach the megohm level. The megohm-level equivalent resistance and the second capacitor C2 achieve the isolation between the AC change signal of the sine wave output signal XI of the crystal oscillator and the DC bias point (node A), so that the two input terminals of the comparator COMP1 have the same common-mode comparison voltage, eliminating the interference of the sine wave output signal XI of the crystal oscillator on the output waveform due to the DC level offset.

[0046] The output result of the crystal oscillator anti-interference shaping circuit of Embodiment 1 is as Figure 5 shown. In the region where the signals at both ends of the crystal oscillator do not overlap, since the sine wave output signal XI of the crystal oscillator is still oscillating normally, a normal clock signal can be output. Without using a large resistor, it can effectively avoid the interference caused by the change of the DC level of the input signal due to external environmental interference, and output a stable and accurate clock signal.

[0047] Embodiment 2

[0048] Based on Embodiment 1, the crystal oscillator anti-interference shaping circuit further includes a Schmitt trigger and an inverter; the output of the comparator COMP1 is connected to the input of the Schmitt trigger, and the inverter is cascaded at the output end of the Schmitt trigger. The Schmitt trigger and the inverter process and shape based on the input conversion level signal, and output the converted square wave signal.

[0049] Preferably, the second capacitor C2 is a ceramic coupling capacitor, a metallized polyimide film coupling capacitor, a corrugated paper coupling capacitor, etc.

[0050] Preferably, the second capacitor C2 is less than 10 pf.

[0051] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A crystal oscillator anti-interference shaping circuit, characterized in that, It includes a reference current source (I1), a fourth NMOS transistor (NM4), a fourth PMOS transistor (PM4), a fifth NMOS transistor (NM5), a fifth PMOS transistor (PM5), a second capacitor (C2), and a comparator (COMP1); The gate and drain of the fourth NMOS transistor (NM4) and the gate of the fifth NMOS transistor (NM5) are short - connected to the reference current source (I1); The source of the fourth NMOS transistor (NM4), the source of the fifth PMOS transistor (PM5), the source of the fourth PMOS transistor (PM4), and the negative input terminal of the comparator (COMP1) are short - connected to node A; The gate, drain of the fourth PMOS transistor (PM4) and the gate of the fifth PMOS transistor (PM5) are all connected to ground; The drain of the fifth PMOS transistor (PM5) and the source of the fifth NMOS transistor (NM5) are both short - connected to node B; The drain of the fifth NMOS transistor (NM5), the positive input terminal of the comparator (COMP1), and one end of the second capacitor (C2) are commonly connected to node C; The other end of the second capacitor (C2) is connected to the sine - wave output signal (XI) of the crystal oscillator.

2. The crystal oscillator anti - interference shaping circuit according to claim 1, wherein The size ratio of the fourth NMOS transistor (NM4) to the fifth NMOS transistor (NM5) is 1:M; The size ratio of the fourth PMOS transistor (PM4) to the fifth PMOS transistor (PM5) is 1:M; M is a positive number.

3. The crystal oscillator anti - interference shaping circuit according to claim 1, wherein M is greater than 2.

4. The crystal oscillator anti - interference shaping circuit according to claim 1, wherein M is 3, 4, 8, 17, or 20.

5. The crystal oscillator anti - interference shaping circuit according to claim 1, wherein The crystal oscillator anti - interference shaping circuit further includes a Schmitt trigger and an inverter; The output of the comparator (COMP1) is connected to the input of the Schmitt trigger; The inverter is cascaded at the output of the Schmitt trigger.

6. The crystal oscillator anti - interference shaping circuit according to claim 1, wherein The second capacitor (C2) is a ceramic coupling capacitor, a metallized polyimide film coupling capacitor, or a corrugated paper coupling capacitor.

7. The crystal oscillator anti - interference shaping circuit according to claim 1, wherein The second capacitor (C2) is less than 10 pf.

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