Level shifter and chip

Abstract

The invention discloses a level shifter and a chip. The level shifter comprises a first transistor, a current unit, a bias unit and an adjusting unit, a first end of the first transistor is connected with a first voltage through the current unit, a second end of the first transistor forms an output end of the level shifter and is connected with a second voltage through the bias unit, a control end of the first transistor is used for receiving an input signal, and the adjusting unit is connected with the control end and the output end of the first transistor. The adjusting unit increases the rising or falling speed of the output voltage of the output end of the level shifter based on the change of the input signal. According to the level shifter and the chip provided by the invention, the signal establishment speed after the level shifter shifts can be improved through the adjusting unit, so that the problem of slow edge change during high-voltage level shifting is solved; level shifting can be completed only through the first transistor which is a high-voltage tube, the structure is simpler, the occupied area is smaller, and the cost is lower.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a level shifter and a chip. Background Art

[0002] In positive and negative high-voltage circuits, a level shifter is often required to transfer digital control signals. Traditional level-shifting circuits need to use multiple high-voltage transistors to complete the transfer of one signal, and the signal edge may slow down with the change of the power supply voltage, which will bring disadvantages to the control of subsequent circuits.

[0003] The information disclosed in this background art section is only intended to enhance the overall understanding of the present invention and should not be regarded as an admission or any form of suggestion that this information constitutes prior art already known to those of ordinary skill in the art. Summary of the Invention

[0004] The purpose of the present invention is to provide a level shifter and a chip, which can reduce the use of high-voltage transistors and improve the signal establishment speed.

[0005] To achieve the above purpose, a specific embodiment of the present invention provides a level shifter, including: a first transistor, a current unit, a bias unit, and an adjustment unit; the first end of the first transistor is connected to a first voltage through the current unit, the second end of the first transistor forms the output end of the level shifter and is connected to a second voltage through the bias unit, the control end of the first transistor is used to receive an input signal, the adjustment unit is connected to the control end and the output end of the first transistor, and the adjustment unit increases the rising or falling speed of the output voltage of the output end of the level shifter based on the change of the input signal.

[0006] In one or more embodiments of the present invention, the level shifter further includes an inverter, the input end of the inverter is used to receive the input signal, and the output end of the inverter is connected to the control end of the first transistor.

[0007] In one or more embodiments of the present invention, the adjustment unit includes a coupling control unit and a switching unit, the coupling control unit is connected to the control end of the first transistor and the control end of the switching unit, the coupling control unit generates a control signal based on the change of the input signal, the switching unit is simultaneously connected to the output end of the level shifter and the second voltage, and the switching unit is turned on based on the control of the control signal and the second voltage to increase the rising or falling speed of the output voltage of the output end of the level shifter.

[0008] In one or more embodiments of the present invention, the coupling control unit includes a capacitor and a first resistor. A first end of the capacitor is connected to a control end of a first transistor. A second end of the capacitor is connected to a control end of the switch unit and a first end of the first resistor. A second end of the first resistor is connected to a second voltage.

[0009] In one or more embodiments of the present invention, the switch unit includes a second transistor. A control end of the second transistor is connected to the coupling control unit to receive a control signal. A first end of the second transistor is connected to the second voltage. A second end of the second transistor is connected to an output end of a level shifter.

[0010] In one or more embodiments of the present invention, the current unit includes a current mirror or a third transistor.

[0011] In one or more embodiments of the present invention, the bias unit includes a second resistor.

[0012] In one or more embodiments of the present invention, the inverter operates in a low voltage domain.

[0013] In one or more embodiments of the present invention, the second voltage is a negative high voltage, or the second voltage is a positive high voltage.

[0014] The present invention also discloses a chip including the above-mentioned level shifter.

[0015] Compared with the prior art, the level shifter and the chip of the present invention can improve the signal establishment speed after shifting of the level shifter through an adjustment unit, thereby solving the problem of slow edge change during high-voltage level shifting. The present invention only needs one high-voltage transistor, namely the first transistor, to complete level shifting, with a simpler structure, smaller occupied area, and lower cost. The output voltage generated by the level shifter of the present invention has a relatively small delay error, realizing precise control of subsequent circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 FIG. is a circuit schematic diagram of the level shifter in Embodiment 1.

[0018] Figure 2 FIG. is a signal waveform diagram of the level shifter in Embodiment 1.

[0019] Figure 3 It is the circuit schematic diagram of the level shifter in Embodiment 2.

[0020] Figure 4 It is the signal waveform diagram of the level shifter in Embodiment 2. Detailed implementation manners

[0021] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0022] "Coupled" or "connected" or "linked" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include a connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as a connection through a circuit or component such as a switch, a follower circuit, etc. Additionally, in the invention, words such as "first", "second", etc. are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity, or order between these technical features.

[0023] In the detailed description of the specification, reference is made to the accompanying drawings that form a part of it, where the same reference numerals always represent the same components, and which are shown by way of exemplary embodiments that can be implemented. It should be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered limiting.

[0024] The various operations in the specification can be described as a plurality of discrete actions or operations in turn in a manner that is most helpful for understanding the claimed subject matter. However, the described order should not be construed as implying that these operations must be order-related. Specifically, these operations may not be performed in the order presented. The described operations can be performed in an order different from that of the described embodiments. Various additional operations can be performed in additional embodiments and / or the described operations can be omitted.

[0025] For the purposes of the present disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0026] Various components and devices may be referred to or shown herein in the singular (e.g., "transistor", "transistor", "switch", etc.), but this is merely for convenience of discussion, and any element referred to in the singular may include a plurality of such elements in accordance with the teachings herein.

[0027] The specification describes the use of the phrases "in one embodiment", "in other embodiments", or "in some embodiments", which may each refer to one or more of the same or different embodiments. Additionally, the terms "comprising", "including", "having", etc. used with respect to the embodiments of the present disclosure are synonymous.

[0028] Embodiment 1

[0029] As Figure 1 shown, a level shifter in an embodiment of the present invention includes: an inverter INV, a first transistor M1, a current unit 10, a bias unit 20, and an adjustment unit 30.

[0030] A first end of the first transistor M1 is connected to a first voltage through the current unit 10, a second end of the first transistor M1 forms an output end of the level shifter and is connected to a second voltage through the bias unit 20. An input end of the inverter INV is used to receive an input signal VIN, an output end of the inverter INV is connected to a control end of the first transistor M1 to form a node A, and the control end of the first transistor M1 is used to receive an inverted input signal VIN (VA). The adjustment unit 30 is connected to the control end of the first transistor M1, the output end of the level shifter, and the second voltage, and the adjustment unit 30 increases the rising or falling speed of the output voltage VOUT at the output end of the level shifter based on the change of the input signal VIN.

[0031] In one embodiment, the first voltage is a low positive voltage AVDD (such as 5V), and the second voltage is a negative high voltage AVSS (such as -30V).

[0032] The inverter INV operates in a low voltage domain, such as Figure 1 shown, the inverter INV is connected to the first voltage and a reference voltage, so as to be powered by the first voltage, and the reference voltage may be a ground voltage (which may be 0V). The inverter INV is used to invert and shape the input signal VIN. In other embodiments, the inverter INV may not be provided either.

[0033] In one embodiment, the current unit 10 includes a current mirror. The current mirror provides a bias current I0 to the first transistor M1. In other embodiments, the third transistor may be used instead of the current mirror to provide the bias current I0 to the first transistor M1.

[0034] In one embodiment, the bias unit 20 includes a second resistor R2. The first end of the second resistor R2 is connected to the second end of the first transistor M1, and the second end of the second resistor R2 is connected to the second voltage.

[0035] As Figure 1 shown, the adjustment unit 30 includes a coupling control unit 31 and a switching unit 32. The coupling control unit 31 is connected to the control end of the first transistor M1 and the control end of the switching unit 32. The coupling control unit 31 generates a control signal VB based on the change of the input signal VIN. The switching unit 32 is simultaneously connected to the output end of the level shifter and the second voltage. The switching unit 32 is turned on based on the control of the control signal VB and the second voltage to increase the rising or falling speed of the output voltage VOUT at the output end of the level shifter.

[0036] Among them, in one embodiment, the coupling control unit 31 includes a capacitor C1 and a first resistor R1. The first end of the capacitor C1 is connected to the control end of the first transistor M1 to form a node A. The second end of the capacitor C1 is connected to the control end of the switching unit 32 and the first end of the first resistor R1 to form a node B. The second end of the first resistor R1 is connected to the second voltage.

[0037] The switching unit 32 includes a second transistor M2. The control end of the second transistor M2 is connected to the coupling control unit 31 to receive the control signal VB. The first end of the second transistor M2 is connected to the second voltage. The second end of the second transistor M2 is connected to the output end of the level shifter.

[0038] In one embodiment, the first transistor M1 is a PMOS transistor, and the second transistor M2 is an NMOS transistor. The first ends of the first transistor M1 and the second transistor M2 are source electrodes. The second ends of the first transistor M1 and the second transistor M2 are drain electrodes. The control ends of the first transistor M1 and the second transistor M2 are gate electrodes.

[0039] The input signal VIN is a low-voltage signal. In one embodiment, it can be a signal that toggles between a first voltage and the ground voltage. The input signal VIN passes through an inverter INV to obtain an inverted signal VA in the same voltage domain. When the input signal VIN is high, the first transistor M1 conducts, and the bias current I0 flows through the channel of the first transistor M1 to the second resistor R2. At this time, the level signal of the shifted output voltage VOUT is AVSS + I0 * R2; when the input signal VIN is low, the first transistor M1 turns off, the bias current I0 flowing through the second resistor R2 disappears, and the charge on the output terminal of the level shifter is discharged through the second resistor R2, finally obtaining a second voltage or approaching the second voltage. Generally, in order to save power consumption, a relatively small bias current I0 is selected, and a relatively large second resistor R2 is selected. At this time, when the input signal VIN changes from high to low, the second resistor R2 discharges slowly, and the output voltage VOUT will obtain a very gentle falling edge, equivalently obtaining a relatively long delay, which will have a serious impact in some control scenarios.

[0040] Therefore, an adjustment unit 30 is adopted to solve the above problems. When the input signal VIN changes from high to low, the inverted signal VA output by the inverter INV changes from low to high. At this time, a signal in the same direction is coupled to the gate of the second transistor M2 through the capacitor C1, which will cause the second transistor M2 to turn on briefly and quickly discharge the charge on the output terminal of the level shifter, accelerating the establishment of the falling edge of the output voltage VOUT; when the input signal VIN changes from low to high, the signal coupled to the gate of the second transistor M2 will not cause the second transistor M2 to conduct, and will not have any impact on the output voltage VOUT. In this way, an output voltage VOUT with a very fast falling edge is obtained. Using a level shifter as Figure 1 shown can ensure that the output voltage VOUT is alignable under negative high voltage, accurately controlling other devices such as the high-voltage output transistor of the subsequent operational amplifier to obtain good performance.

[0041] Figure 2 The related signal timing diagram of the above level shifter is given. The ratio of the capacitor C1 to the parasitic capacitance between the node B and the ground will affect the slope and amplitude of the positive rising segment ph1 of the control signal VB at the node B. The larger the capacitor C1, the larger the amplitude of the positive rising segment ph1 and the faster the edge; the first resistor R1 affects the slope of the positive falling segment ph2. The larger the first resistor R1, the gentler the edge of the positive falling segment ph2. Therefore, in order to make the edge of the level shift faster (that is, the falling edge of the output voltage VOUT is steeper), it is necessary to increase the time constant R1 * C1. However, the larger the time constant, the more vulnerable it is to interference from other signals. Therefore, attention needs to be paid to the protection of nodes A and B on the layout (such as no other signal lines are routed around, or ground wires are arranged around nodes A and B) to avoid being coupled by other signals, otherwise it will cause jitter of the control signal VB.

[0042] In one embodiment, the first transistor M1 is a high-voltage transistor and the second transistor M2 is a low-voltage transistor. Therefore, the level-shifting circuit of this embodiment only requires one high-voltage transistor to complete the level shifting, with a simpler structure, smaller occupied area, and lower cost.

[0043] The present invention also discloses a chip including the above-mentioned level shifter.

[0044] Embodiment 2

[0045] As Figure 3 shown, in this embodiment, the first voltage is the ground voltage (such as 0V), and the second voltage is the positive high voltage HVDD (such as +30V). Therefore, the difference from Embodiment 1 is that the first transistor M1 is an NMOS transistor, the second transistor M2 is a PMOS transistor, the first ends of the first transistor M1 and the second transistor M2 are the source electrodes, the second ends of the first transistor M1 and the second transistor M2 are the drain electrodes, and the control ends of the first transistor M1 and the second transistor M2 are the gate electrodes. Correspondingly, the positions of the current unit 10, the bias unit 20, and the adjustment unit 30 connected to the first transistor M1 also change.

[0046] The input signal VIN is a low-voltage signal. In one embodiment, it can be a signal that jumps between the low positive voltage AVDD and the ground voltage. The input signal VIN passes through the inverter INV to obtain the inverted signal VA in the same voltage domain. When the input signal VIN is low, the first transistor M1 is turned on. At this time, the low-level signal of the shifted output voltage VOUT is HVDD - I0*R2; when the input signal VIN is high, the first transistor M1 is turned off, the bias current I0 flowing through the second resistor R2 disappears, and the output voltage VOUT at the output end of the level shifter rises and finally rises to the second voltage or approaches the second voltage.

[0047] When the input signal VIN changes from low to high, the inverted signal VA output by the inverter INV changes from high to low. At this time, a signal of the same direction is coupled to the gate of the second transistor M2 through the capacitor C1, which will cause the second transistor M2 to be briefly turned on, quickly raising the output voltage VOUT at the output end of the level shifter and accelerating the establishment of the rising edge of the output voltage VOUT; while when the input signal VIN changes from high to low, the signal coupled to the gate of the second transistor M2 will not cause the second transistor M2 to conduct and will not have any impact on the output voltage VOUT. In this way, an output voltage VOUT with a very fast rising edge is obtained. Using the level shifter as Figure 3 shown can ensure an alignable output voltage VOUT under the positive high voltage, precisely control other devices such as the high-voltage output transistor of the subsequent operational amplifier, and obtain good performance.

[0048] Figure 4The related signal timing diagram of the above-mentioned level shifter is given. The ratio of the capacitor C1 to the parasitic capacitance between the node B and the second voltage affects the slope and amplitude of the negative falling edge ph3 of the control signal VB at the node B. The larger the capacitor C1, the larger the amplitude of the negative falling edge ph3 and the faster the edge. The first resistor R1 affects the slope of the negative rising edge ph4. The larger the first resistor R1, the slower the edge of the negative rising edge ph4. Therefore, in order to make the edge of the level shift faster (i.e., the rising edge of the output voltage VOUT is steeper), it is necessary to increase the time constant R1*C1. However, the larger the time constant, the more susceptible it is to interference from other signals. Therefore, attention should be paid to the protection of nodes A and B on the layout (such as no other signal lines are routed around, or ground wires are arranged around nodes A and B), so as not to be coupled by other signals, otherwise the control signal VB will jitter.

[0049] The present invention also discloses a chip, including the above-mentioned level shifter.

[0050] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-mentioned exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention. Any reference signs in the claims should not be regarded as limiting the claimed claims.

[0051] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A level shifter, characterized in that: include: A first transistor, a current unit, a bias unit and a regulating unit; The first end of the first transistor is connected to a first voltage through a current unit, the second end of the first transistor forms an output end of a level shifter and is connected to a second voltage through a bias unit, the control end of the first transistor is used to receive an input signal, the adjustment unit is connected to the control end and the output end of the first transistor, and the adjustment unit increases a rising or falling speed of an output voltage at the output end of the level shifter based on a change in the input signal.

2. The level shifter according to claim 1, wherein: The level shifter further includes an inverter, an input end of the inverter is used to receive an input signal, and an output end of the inverter is connected to a control end of the first transistor.

3. The level shifter according to claim 1, wherein: The regulating unit includes a coupling control unit and a switching unit. The coupling control unit is connected to the control end of the first transistor and the control end of the switching unit. The coupling control unit generates a control signal based on the change of the input signal. The switching unit is simultaneously connected to the output end of the level shifter and the second voltage. The switching unit is turned on based on the control of the control signal and the second voltage to increase the rising or falling speed of the output voltage of the output end of the level shifter.

4. The level shifter according to claim 3, characterized in that: The coupling control unit includes a capacitor and a first resistor, the first end of the capacitor is connected to the control end of the first transistor, the second end of the capacitor is connected to the control end of the switch unit and the first end of the first resistor, and the second end of the first resistor is connected to the second voltage.

5. The level shifter according to claim 3, characterized in that: The switch unit includes a second transistor, a control terminal of the second transistor is connected to the coupling control unit to receive a control signal, a first terminal of the second transistor is connected to a second voltage, and a second terminal of the second transistor is connected to an output terminal of the level shifter.

6. The level shifter according to claim 1, wherein: The current unit includes a current mirror or a third transistor.

7. The level shifter according to claim 1, wherein: The bias unit includes a second resistor.

8. The level shifter according to claim 2, wherein: The inverter operates in a low voltage domain.

9. The level shifter according to any one of claims 1 to 8, characterized in that: The second voltage is a negative high voltage, or the second voltage is a positive high voltage.

10. A chip, characterized in that: It comprises the level shifter as claimed in any one of claims 1 to 9.

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