Fractional frequency division all-digital phase-locked loop based on parallel four-order Sigma-delta modulator

Abstract

The invention relates to a fractional frequency division all-digital phase-locked loop based on a parallel fourth-order Sigma-delta modulator, and belongs to the field of radio frequency integrated circuit design. The phase-locked loop adopts an all-digital architecture and comprises a time-to-digital converter (TDC), a digital loop filter (DLF), a digital controlled oscillator (DCO), a programmable frequency divider (MMD) and a parallel four-order Sigma-delta modulator. A phase-locked loop adopts an all-digital closed-loop feedback structure, the phase difference between a reference signal and a feedback signal is detected through a TDC without dead-zone influence, DCO output is fed back to a loop after being subjected to MMD frequency division, parallel four-order Sigma-delta modulators dynamically control the frequency division ratio of MMD, a bit adder and an accumulator of each stage of modulator are split to obtain four low-order adders for parallel computing, and the low-order adders are used for parallel computing. The signal-to-noise ratio and the noise shaping capability of the modulator are improved, and quantization noise and fractional spurious are suppressed by using the high-order noise shaping characteristic.

Description

Technical Field

[0001] The present invention belongs to the field of radio frequency integrated circuit design, and relates to a fractional-N all-digital phase-locked loop based on a parallel fourth-order Sigma-delta modulator. Background Art

[0002] A phase-locked loop, known as PLL (Phase-Locked Loop), is a frequency synthesizer, which is mainly a negative feedback control system that can generate a target frequency. In high-performance system-on-chip (SoC), the phase-locked loop plays an important role in aspects such as clock generation, distribution, and synchronization. With the development of integrated circuits and the higher-precision and higher-performance requirements for clock frequencies inside chips, fractional-N phase-locked loops with high frequency resolution phase-locking synthesis and good noise characteristics have become the mainstream technical means in the market. And the phase-locked loops realized by analog circuits in the early stage are not conducive to integration with the advancement of technology. Therefore, digital phase-locked loops have received extensive attention in recent years. Among them, an all-digital phase-locked loop (ADPLL), as a closed-loop feedback system, the control signals between each module are digital signals, which improves the circuit integration, locking speed, and portability, and reduces the cost of the circuit. At the same time, the low phase noise, low spurious local oscillator, or low jitter clock signal provided by the ADPLL has an important impact on the sensitivity of the system.

[0003] In order to achieve fast locking and break through the limitations of the integer-N all-digital phase-locked loop in terms of frequency modulation resolution and loop bandwidth, the fractional-N all-digital phase-locked loop based on a Sigma-delta modulator has been widely used. It realizes fractional division of the input signal through cycle averaging, thereby improving the flexibility of the reference signal and the frequency divider.

[0004] However, the fractional-N phase-locked loop will cause problems such as bit modulation and fractional spurs. Its quantization noise will have some negative impacts on the signal purity of the phase-locked loop output. Therefore, Sigma-Delta modulation technology is generally used to solve these problems. The present invention mainly aims at the high-precision frequency resolution and noise characteristics of the fractional-N phase-locked loop, improves the fractional-N phase-locked loop circuit, and realizes high-precision and low-spurious output. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a fractional-N all-digital phase-locked loop based on a parallel fourth-order Sigma-delta modulator.

[0006] To achieve the above purpose, the present invention provides the following technical solutions:

[0007] A fractional-N all-digital phase-locked loop based on a parallel fourth-order Sigma-delta modulator, the loop including: a time-to-digital converter (TDC), a digital loop filter (DLF), a numerically controlled oscillator (DCO), a programmable divider (MMD), and a parallel fourth-order Sigma-delta modulator.

[0008] The working process of the entire circuit is that the system continuously compares the phases of the input signal ref and the feedback signal f_out, digitizes the phase difference between the two through the TDC, and realizes the detection of the phase error between the two. Subsequently, the loop detects the phase difference between the reference signal and the feedback signal through the TDC without dead zone influence and converts it into a digital value. After being processed by the DLF, a DCO frequency control signal is generated, generating a numerically controlled signal proportional to the phase difference between the two, which is used as the input of the DCO to change the output frequency of the numerically controlled oscillator. In order to improve the effective frequency accuracy of the numerically controlled oscillator, another ΔΣ modulator exists in the numerically controlled oscillator. Then, the output signal of the DCO is fed back to the divider to divide it into the low-frequency range of the reference clock. According to the parallel fourth-order Sigma-delta modulator, the control word change of the fractional-N division is adjusted to achieve fractional-N division, so that the phase error between ref and f_out continuously decreases, that is, the digital value of the phase difference output by the TDC is 0. When the ADPLL system enters the locked state, an output signal f_out with a frequency of (N +.F) × ref will be generated, where N is the integer part of the division ratio and F is the fractional part of the division ratio. When the ADPLL loop is locked, the output signal frequency and the input signal frequency will be strictly synchronized, achieving the effect of ultra-low fractional spurs and precise frequency synchronization and tracking.

[0009] Furthermore, the TDC without dead zone influence is characterized in that: a two-step TDC design scheme based on a hybrid architecture is adopted, and its structure is as Figure 2 shown. The two-step TDC has two levels of delay quantization structures. The first level uses a 32-stage Flash-type TDC to achieve coarse quantization. This structure quickly captures the input time signal through a delay chain; the second level is a 16-stage vernier-type TDC for fine quantization, and high-precision measurement is achieved by using the time difference between two delay chains. The remainder extraction module accurately transfers the phase difference remainder of the first-level quantization to the second-level quantizer, and finally outputs the digitized phase difference through the decoding module.

[0010] Furthermore, the TDC without dead zone influence is characterized in that: for the Flash-type TDC delay chain is composed of inverters, and due to the asymmetry of the rise / fall time of the inverter and the delay of the first-stage flip-flop of the Flash-type TDC, a dead zone area of the delay chain is caused, as Figure 3As shown in the figure. When the Flash-type TDC quantifies the phase difference between Start and Stop, if Stop appears in the dead zone, it will cause an error signal. The margin extraction module uses digital codes to avoid the influence of the dead zone on the TDC, making the system more stable and fast.

[0011] Furthermore, the margin extraction module is characterized in that: by detecting whether the rising edge of Stop is in the dead zone area, it dynamically switches the phase difference calculation mode to eliminate the dead zone interference; when the rising edge of Stop is not in the dead zone, it directly calculates the phase difference in the normal mode and superimposes a fixed offset compensation value; when the rising edge of Stop is in the dead zone, it determines the leading or lagging state of the Stop signal relative to the Start signal, and selects different fine quantization paths according to whether the leading amount exceeds the resolution threshold of the phase quantization TDC: if it lags behind Start, it inputs Start to the slow delay chain of the fine quantization cursor-type TDC and Stop to the fast delay chain; if it does not exceed the threshold, it exchanges the input paths so that Start is connected to the fast delay chain and Stop is connected to the slow delay chain. If the leading amount is greater than the threshold, it prevents overflow through the full-scale output of the cursor-type TDC, thereby accurately capturing the tiny phase difference and eliminating the non-linear error caused by the dead zone. The code flow is as Figure 4 shown. Finally, through digital logic integration of the quantization results of the Flash-type TDC and the cursor-type TDC, high-precision time interval measurement without dead zone is realized.

[0012] Furthermore, the fractional-N phase-locked loop circuit is characterized in that: by temporarily storing the accumulation overflow of the low-order adder in a register and compensating it in the next accumulation process, the total data volume remains unchanged during the overall accumulation process, ensuring normal error output, thereby realizing the splitting of the adder.

[0013] Furthermore, the fractional-N phase-locked loop circuit is characterized in that: the output error is obtained by judging an accumulator containing an accumulation reference factor. The judgment method is: when the accumulation reference factor is greater than or equal to the accumulation result value, the carry output signal is 0, otherwise the carry output signal is 1. When the carry output signal is 1, the accumulation overflow is temporarily stored in the register.

[0014] Furthermore, the parallel fourth-order Sigma-delta modulator is composed of four cascaded first-order Sigma-delta modulators. By splitting the adder and accumulator into low-order parallel calculation units, high-speed operation and high-order noise shaping are realized;

[0015] Further, the parallel fourth-order Sigma-delta modulator digital circuit includes an accumulator, an adder, and a delay element composed of D flip-flops; in the cascade structure, the number of bits of the first-order Sigma-delta modulator is 32 bits, and the adder and accumulator of each stage of the Sigma-delta modulator are split to obtain four low-bit adders for parallel calculation. The specific splitting of the adder and accumulator is as follows: the 32-bit adder and accumulator are split into four 16-bit adders to improve the modulator rate.

[0016] The beneficial effects of the present invention are as follows:

[0017] (1) The fractional-N phase-locked loop circuit proposed by the present invention can improve the signal-to-noise ratio of the modulator, reduce the output periodicity, and suppress the fractional spurious output by cascading four first-order Sigma-delta modulators.

[0018] (2) By splitting the adder and accumulator into low-bit adders for parallel operation, the present invention can improve the modulator rate.

[0019] (3) In the two-step TDC without dead zone effect proposed by the present invention, the margin extraction module realizes high-precision time interval measurement without dead zone through logical judgment of codes.

[0020] Other advantages, objectives, and features of the present invention will be described to some extent in the subsequent description, and to some extent, will be obvious to those skilled in the art based on the study of the following text, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. Description of the Drawings

[0021] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be described in detail with reference to the accompanying drawings, where:

[0022] Figure 1 It is a schematic diagram of the overall implementation circuit framework of the fractional-N all-digital phase-locked loop based on a parallel fourth-order Sigma-delta modulator in the embodiment;

[0023] Figure 2 It is a circuit implementation diagram of the two-step TDC of the fractional-N all-digital phase-locked loop based on a parallel fourth-order Sigma-delta modulator in the embodiment;

[0024] Figure 3 It is a dead zone area diagram of the two-step TDC of the fractional-N all-digital phase-locked loop based on a parallel fourth-order Sigma-delta modulator in the embodiment;

[0025] Figure 4Flowchart of the margin extraction module in the two-step TDC of the fractional-N all-digital phase-locked loop based on a parallel fourth-order Sigma-delta modulator described in the embodiment;

[0026] Figure 5 Simulink simulation diagram of the improved Sigma-delta structure of the fractional-N all-digital phase-locked loop based on a parallel fourth-order Sigma-delta modulator described in the embodiment;

[0027] Figure 6 Simulation spectrum diagram of the first-order Sigma-delta modulator of the fractional-N all-digital phase-locked loop based on a parallel fourth-order Sigma-delta modulator described in the embodiment;

[0028] Figure 7 Simulink simulation diagram of the MASH1-1-1-1 structure of the fractional-N all-digital phase-locked loop based on a parallel fourth-order Sigma-delta modulator described in the embodiment;

[0029] Figure 8 Frequency output waveform diagram of the Sigma-delta modulator of the fractional-N all-digital phase-locked loop based on a parallel fourth-order Sigma-delta modulator described in the embodiment;

[0030] Figure 9 Structure diagram of the MASH fourth-order accumulator of the fractional-N all-digital phase-locked loop based on a parallel fourth-order Sigma-delta modulator described in the embodiment;

[0031] Figure 10 Structure diagram of the single-stage accumulator of the fractional-N all-digital phase-locked loop based on a parallel fourth-order Sigma-delta modulator described in the embodiment. Specific implementation

[0032] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0033] Among them, the attached drawings are only for illustrative purposes, showing only schematic diagrams rather than actual physical diagrams, and should not be construed as limiting the present invention; in order to better illustrate the embodiments of the present invention, some components in the attached drawings will be omitted, enlarged or reduced, which do not represent the dimensions of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the attached drawings may be omitted.

[0034] In the attached drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc. indicating the orientation or positional relationship based on the orientation or positional relationship shown in the attached drawings, it is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the attached drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0035] The present invention provides the following specific implementation manners:

[0036] Please refer to Figures 1 to 10 , a fractional-N all-digital phase-locked loop based on a parallel fourth-order Sigma-delta modulator. The loop includes: a time-to-digital converter (TDC), a digital loop filter (DLF), a numerically controlled oscillator (DCO), a programmable divider (MMD), and a parallel fourth-order Sigma-delta modulator. The fractional-N of this circuit is realized by the Sigma-delta modulator, and the structure of the Sigma-delta modulator is as Figure 5 shown. Four first-order 32-bit Sigma-delta modulators are cascaded to implement a fourth-order Sigma-delta modulator to improve the signal-to-noise ratio of the modulator, reduce the output periodicity, and suppress the fractional spurious output.

[0037] The working process of the entire circuit is that the system continuously compares the phases of the input signal ref and the feedback signal f_out, digitizes the phase difference between the two through the TDC, and realizes the detection of the phase error between the two. Subsequently, the loop detects the phase difference between the reference signal and the feedback signal through the TDC without dead zone influence and converts it into a digital value. After being processed by the DLF, a DCO frequency control signal is generated, generating a numerically controlled signal proportional to the phase difference between the two, which is used as the input of the DCO to change the output frequency of the numerically controlled oscillator. In order to improve the effective frequency accuracy of the numerically controlled oscillator, there is another ΔΣ modulator in the numerically controlled oscillator. Then, the output signal of the DCO is fed back to the frequency divider, which divides it into the low-frequency range of the reference clock. According to the parallel fourth-order Sigma-delta modulator, the control word change for fractional frequency division is adjusted to achieve fractional frequency division, so that the phase error between ref and f_out is continuously reduced, that is, the digital value of the phase difference output by the TDC is 0. When the ADPLL system enters the locked state, an output signal f_out with a frequency of (N +.F) × ref will be generated, where N is the integer part of the frequency division ratio and F is the fractional part of the frequency division ratio. When the ADPLL loop is locked, the output signal frequency and the input signal frequency will be strictly synchronized, achieving the effect of ultra-low fractional spurs and precise frequency synchronization and tracking.

[0038] Among them, the TDC without dead zone influence adopts a two-step TDC design scheme based on a hybrid architecture, and its structure is as Figure 2 shown. The two-step TDC has two levels of delay quantization structures. The first level uses a 32-stage Flash-type TDC to achieve coarse quantization. This structure quickly captures the input time signal through a delay chain; the second level is a 16-stage vernier-type TDC for fine quantization, and high-precision measurement is achieved by using the time difference between two delay chains. The residue extraction module accurately transfers the phase difference residue of the first-level quantization to the second-level quantizer, and finally outputs the digitized phase difference through the decoding module.

[0039] And for the Flash-type TDC, the delay chain is composed of inverters. Due to the asymmetry of the rise / fall time of the inverter and the delay of the first-stage flip-flop of the Flash-type TDC, a dead zone area is caused in the delay chain, as Figure 3 shown. When the Flash-type TDC quantifies the phase difference between Start and Stop, if Stop appears in the dead zone, it will cause an error signal. The residue extraction module completes avoiding the influence of the dead zone on the TDC through digital codes, making the system more stable and fast.

[0040] Among them, the margin extraction module dynamically switches the phase difference calculation mode by detecting whether the rising edge of Stop is in the dead zone area to eliminate dead zone interference; when the rising edge of Stop is not in the dead zone, the normal mode is adopted to directly calculate the phase difference and superimpose a fixed offset compensation value; when the rising edge of Stop is in the dead zone, it determines whether the Stop signal is ahead or behind the Start signal, and selects different fine quantization paths according to whether the leading amount exceeds the resolution threshold of the phase quantization TDC: if it is behind the Start, the Start is input to the slow delay chain of the fine quantization cursor type TDC, and the Stop is input to the fast delay chain; if it does not exceed the threshold, the input paths are exchanged so that the Start is connected to the fast delay chain and the Stop is connected to the slow delay chain. If the leading amount is greater than the threshold, overflow is prevented through the full-scale output of the cursor type TDC, so as to accurately capture the tiny phase difference and eliminate the non-linear error caused by the dead zone. The code flow is as Figure 4 shown. Finally, the quantization results of the Flash type TDC and the cursor type TDC are integrated through digital logic to achieve high-precision time interval measurement without dead zone.

[0041] The principle of the Sigma-delta modulator is to utilize two technologies of oversampling and noise shaping, and use an accumulator, an adder, and a delay element to implement the Sigma-delta digital circuit design, and utilize the accumulator and its overflow accumulation function to achieve an oversampling effect. According to the linear structure of the first-order Sigma-delta modulator, its input-output relationship can be obtained: Y(z) = X(z)z -1 +E(z)(1 - z -1 ). It can be obtained that the input signal X(z) is output after being delayed by one cycle, and the quantization noise E(z) undergoes a noise shaping process. The simulation results of the first-order Sigma-Delta show that its amplitude response of the noise transfer function is smaller in the low-frequency band and larger in the high-frequency band. According to Figure 6 the shown simulation spectrogram, it shows that the noise is more concentrated in the high-frequency band, that is, the low-frequency noise is transferred to the high-frequency band after being processed.

[0042] The high-order design based on the Sigma-delta modulator is to utilize a multi-stage cascaded Sigma-delta modulator to improve the signal-to-noise ratio while enhancing the noise shaping effect. The adopted fourth-order Sigma-delta modulator circuit is realized by cascading four first-order 32-bit Sigma-delta modulators. From Figure 7 the simulink simulation model of the MASH1-1-1-1 structure shown, the transfer function of the system can be obtained as:

[0043] Y(z) = X(z) + (1 - z -1 ) 4 E4(z)

[0044] The noise transfer function is as follows:

[0045] N(z) = (1 - z -1 ) 4

[0046] where Z is the Z-domain, which is the complex frequency domain of discrete-time signals. The Z-domain and the S-domain are fundamental concepts in signal processing and system analysis, and each domain provides a different perspective for understanding and analyzing signals or systems.

[0047] Let Then the noise transfer function is:

[0048]

[0049] N TF is the noise transfer function, f is the frequency, and f ref is the reference frequency, i.e., the sampling frequency.

[0050] The power spectral density of the quantization noise can be obtained as:

[0051]

[0052] E is the amplitude of the baseband power spectral density of the quantization noise; Δ is the quantization step of the quantizer.

[0053] The noise shaping effect of the Sigma-delta modulator makes the quantization noise smaller and improves the signal-to-noise ratio. Moreover, when the structure order is increased, the noise shaping result becomes more obvious, thereby improving the system performance. The output signal waveform of the fourth-order Sigma-delta modulator is as Figure 8 shown.

[0054] For the digital circuit design of the Sigma-delta modulator, the digital circuit includes an accumulator, an adder, and a delay element composed of D flip-flops. Four 16-bit adders obtained by splitting the 32-bit adder and accumulator in each stage of the modulator (as Figure 9 ) are used for parallel calculation to improve the modulator rate. The structure and operation principle of the fourth-order accumulator are as Figure 10 shown. The input signal transmits the quantization noise to the next-stage modulator after modulation, and the output signal undergoes noise integration to obtain the final output signal.

[0055] Among them, splitting the 32-bit adder into two 16-bit adders for high-speed design is carried out on the premise of normally outputting the error value in each clock cycle. The output error can be obtained by judging the accumulator containing the accumulation reference factor. The judgment process is as follows: when the accumulation reference factor is greater than or equal to the accumulation result value, the carry output signal is 0; otherwise, the carry output signal is 1. In a specific circuit, the carry output signal value can be obtained by subtracting the accumulation reference factor from the accumulation result and then judging the sign bit. Similarly, the split circuit can obtain the correct carry output signal value in a subtraction form and obtain the carry output signal value by combining high-bit comparison and low-bit comparison. When the carry output signal is 1, the addition error, that is, the carry and overflow of the low-bit adder, is temporarily stored in the register and compensated in the next accumulation process to keep the total data volume unchanged during the overall accumulation process, so as to ensure the normal output of the error. For example, for the fractional frequency, when accumulating twice, the accumulation result value is 14. At this time, the accumulation reference factor (20) is greater than the accumulation result value, and the carry output signal is 0; when accumulating three times, the accumulation result value is 21. At this time, the accumulation reference factor is less than the accumulation result value, and the carry output signal is 1. The overflow value (accumulation result value - accumulation reference factor) needs to be temporarily stored in the register. In the next accumulation, this overflow value is added to the accumulation result value. Through the above processing, the same effect as that of the 32-bit adder is achieved throughout the process. As can be seen from the above, the present invention has advantages such as improving the locking speed and noise suppression technology.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the present technical solution, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A fractional-frequency all-digital phase-locked loop based on a parallel fourth-order sigma-delta modulator, characterized by: include: Time-to-digital converter TDC, digital loop filter DLF, digitally controlled oscillator DCO, programmable frequency divider MMD and parallel fourth-order Sigma-delta modulator; The TDC is used to detect the phase difference between the input reference signal ref and the feedback signal f_out and output a digitized phase error signal; The DLF is connected to the TDC and is used to filter the phase error signal and generate a digital controlled oscillator control signal; The DCO is connected to the DLF and adjusts the output frequency according to the control signal; The programmable frequency divider is connected to the output end of the DCO and is used to divide the output signal of the DCO to generate the feedback signal; The parallel fourth-order Sigma-delta modulator is connected to the programmable frequency divider, and the dynamic adjustment of the frequency division ratio is achieved by adjusting the fractional frequency division control word. The parallel fourth-order Sigma-delta modulator is composed of four first-order Sigma-delta modulators in cascade, and the adder and accumulator of each first-order Sigma-delta modulator are split into low-bit parallel computing units.

2. The fractional-frequency all-digital phase-locked loop based on parallel fourth-order sigma-delta modulator according to claim 1, characterized in that: The TDC is a two-step TDC without dead zone influence, comprising: The first-stage Flash TDC uses a 32-stage delay chain to achieve coarse quantization; The second-stage vernier TDC uses a 16-stage delay chain to achieve fine quantization; The residual extraction module is used to pass the quantization residual of the first stage to the second stage and dynamically switch the calculation mode according to whether the Stop signal is in the dead zone area; The decoding module integrates the two-level quantization results and outputs a phase difference digital value without dead zone.

3. The fractional-frequency all-digital phase-locked loop based on parallel fourth-order sigma-delta modulator according to claim 2, characterized in that: The working method of the residual extraction module includes: When the rising edge of the Stop signal is not in the dead zone, the normal mode is used to calculate the phase difference and superimpose the fixed offset compensation value; When the rising edge of the Stop signal is in the dead zone, different delay chain input paths are selected according to the lead or lag state, and overflow is prevented by the full-scale output of the vernier TDC.

4. The fractional-frequency all-digital phase-locked loop based on parallel fourth-order sigma-delta modulator according to claim 1, characterized in that: In each first-order Sigma-delta modulator of the parallel fourth-order Sigma-delta modulator, a 32-bit adder and accumulator is split into four 16-bit adders for parallel operation.

5. The fractional-frequency all-digital phase-locked loop based on parallel fourth-order sigma-delta modulator according to claim 4, characterized in that: The split adder generates a carry output signal by judging the relative size of the accumulation reference factor and the accumulation result value, and temporarily stores the overflow value in the register when the carry output signal is 1 for compensation in the next accumulation process.

6. The fractional-frequency all-digital phase-locked loop based on parallel fourth-order sigma-delta modulator according to claim 1, characterized in that: The digital controlled oscillator DCO has a Delta-sigma modulator integrated therein to improve the frequency control accuracy.

7. The fractional-frequency all-digital phase-locked loop based on parallel fourth-order sigma-delta modulator according to claim 2, characterized in that: The delay chain of the first-stage Flash TDC is composed of inverters, and the dead zone is formed by the asymmetry of the inverter rise / fall time and the trigger delay.

8. The fractional-frequency all-digital phase-locked loop based on parallel fourth-order sigma-delta modulator according to claim 1, characterized in that: The z-domain noise transfer function of the parallel fourth-order sigma-delta modulator is: N(z)=(1-z -1 ) 4 Here, z represents the z domain, and the quantization noise is transferred to the high frequency band through fourth-order noise shaping.

9. The fractional-frequency all-digital phase-locked loop based on parallel fourth-order sigma-delta modulator according to claim 1, characterized in that: The frequency division ratio of the programmable frequency divider is (NF), where N is the integer part and F is the fractional part dynamically adjusted by the parallel fourth-order sigma-delta modulator.

10. The fractional-frequency all-digital phase-locked loop based on parallel fourth-order sigma-delta modulator according to claim 5, characterized in that: The judgment logic of the carry output signal includes: determining the carry state by the sign bit of the difference between the accumulated reference factor and the accumulated result value, and generating a final carry signal based on the comparison result of the high bit and the low bit.

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