Multi-phase frequency eliminator and multi-phase frequency elimination method

Abstract

The embodiment of the invention discloses a multi-phase frequency eliminator and a multi-phase frequency elimination method, and relates to the field of clock circuit design, and the method comprises a sequence control unit which is used for determining a control sequence based on a pre-configured frequency elimination ratio and an output clock phase adjustment demand; the clock combination unit is used for dynamically selecting clock signals of corresponding phases from a plurality of input clock signals of which the frequencies are f1 and the phases are equally spaced according to the determined control sequence and combining the clock signals so as to generate output clock signals of which the frequencies are f2 and the phases are set; wherein, the f1gt; f1, f2. The embodiment of the invention can be suitable for the scene of clock delay adjustment between different digital modules on the SOC, so as to solve the problems of large delay fluctuation, complex circuit design and cumbersome control mode caused by PVT condition change of a delay adjustment unit in the prior art.

Description

Technical Field

[0001] The present invention relates to the field of clock circuit design, and particularly to a multi-phase divider and a multi-phase frequency division method. Background Art

[0002] In the design of SOC (System on Chip), MPD (Multi-Phase Divider) plays a crucial role. It is responsible for effectively converting the input multi-phase high-frequency clock signal into a low-frequency clock signal with a specific phase to meet the working requirements of various digital modules inside the SOC. This conversion process ensures that the digital modules can operate at an appropriate clock frequency, thereby efficiently and stably executing various functions. As the core component of the clock management system, the performance of the MPD directly affects the timing characteristics and operating efficiency of the entire SOC system.

[0003] In practical applications, different digital modules inside the SOC need to communicate frequently to cooperate. To ensure smooth communication, strict timing constraints must be met between two communicating digital modules. In the general design process, EDA (Electronic Design Automation) tools can solve part of the timing constraint problems under specific PVT (Process-Voltage-Temperature) conditions. However, due to various PVT variations that the SOC will face during actual production and use, the predictions and solutions of EDA tools often cannot fully cover all cases. These PVT deviations may cause the timing constraints of the actually produced SOC chips not to be met, thereby leading to functional failures, seriously reducing the yield and reliability of the chips. Therefore, additional design means are needed to adjust the timing to ensure that the timing constraints can be met under various PVT conditions.

[0004] Currently, a commonly adopted strategy is that two MPDs receive the same multi-phase high-frequency clock signal, and respectively output low-frequency clock signals to the corresponding digital modules according to the set frequency division ratios. At the same time, additional delay adjustment units are introduced on the paths where the two MPDs transmit clock signals to their respective corresponding digital modules. When the timing constraints of the actual chip fail to meet the standard, the timing relationship can be optimized by dynamically adjusting (increasing or decreasing) the delays on these two paths to ensure the normal operation of the chip function, thereby improving the yield. However, this approach also has the following problems: The delay adjustment unit is usually composed of digital standard cells, and the delay provided by it will fluctuate significantly with the change of PVT conditions, making it more difficult to meet the timing constraints; To cover a sufficient adjustment range, it may be necessary to deploy multi-stage delay adjustment units, which not only increases the complexity of circuit design but also makes the control method of delay adjustment more cumbersome. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a multi-phase frequency divider and a multi-phase frequency division method to solve the problems of large fluctuations in delay caused by PVT condition changes, complex circuit design, and cumbersome control methods in existing delay adjustment units.

[0006] In a first aspect, embodiments of the present invention provide a multi-phase frequency divider, including: A sequence control unit, configured to determine a control sequence based on a pre-configured frequency division ratio and output clock phase adjustment requirements; A clock combination unit, configured to dynamically select clock signals with corresponding phases from multiple input clock signals with a frequency of f1 and equally spaced phases according to the determined control sequence for combination to generate an output clock signal with a frequency of f2 and a set phase; wherein, the f1 > f2。

[0007] Further, the sequence control unit is specifically configured to: obtain a binary bit ring designed based on a pre-configured frequency division ratio; determine the control sequence based on the pre-configured output clock phase adjustment requirements and the binary bit ring.

[0008] In an implementation, the sequence control unit includes a sequence generator and a sequence distributor. The sequence generator is configured to obtain a binary bit ring designed based on a pre-configured frequency division ratio and the starting node position on the ring; under the drive of its own working clock signal, starting from the starting node position, cyclically read the binary bits at the next node position on the binary bit ring to generate the control sequence and output it, where the change of the output binary bits is related to the phase of the working clock signal adjusted according to the output clock phase adjustment requirements; the sequence distributor is configured to distribute the control sequence output by the sequence generator to the enable terminals of each input clock signal with a frequency of f1 and equally spaced phases.

[0009] Further, the sequence control unit further includes: a phase selector, configured to select clock signals with corresponding phases from multiple input clock signals with a frequency of f1 and equally spaced phases based on the pre-configured output clock phase adjustment requirements; a frequency divider, configured to divide the frequency of the clock signals selected by the phase selector to obtain the working clock signal of the sequence generator itself.

[0010] In another embodiment, the sequence control unit includes a sequence generator and a sequence distributor. The sequence generator is configured to obtain a binary bit ring designed based on a preconfigured frequency division ratio; determine a starting node position on the binary bit ring based on a preconfigured output clock phase adjustment requirement, and starting from this starting node position, cyclically traverse the binary bits at each node position on the binary bit ring in a set rotation direction to obtain the control sequence; output the control sequence under the drive of its own working clock signal. The sequence distributor is configured to correspondingly distribute the control sequence output by the sequence generator to the enable terminals of each input clock signal with a frequency of f1 and equal interval phases.

[0011] In yet another embodiment, the sequence control unit includes a sequence generator and a sequence distributor. The sequence generator is configured to obtain a binary bit ring designed based on a preconfigured frequency division ratio and output it to the sequence distributor. The sequence distributor is configured to determine the cyclic distribution order of the binary bits on the binary bit ring based on a preconfigured output clock phase adjustment requirement; and correspondingly distribute the binary bits on the binary bit ring to the enable terminals of each input clock signal with a frequency of f1 and equal interval phases.

[0012] In a second aspect, an embodiment of the present invention provides a multi-phase frequency division method, the method including: determining a control sequence based on a preconfigured frequency division ratio and an output clock phase adjustment requirement; dynamically selecting clock signals with corresponding phases from multiple input clock signals with a frequency of f1 and equal interval phases for combination to generate an output clock signal with a frequency of f2 and a set phase; wherein the f1 > f2。

[0013] Further, determining a control sequence based on a preconfigured frequency division ratio and an output clock phase adjustment requirement includes: obtaining a binary bit ring designed based on a preconfigured frequency division ratio; and determining the control sequence based on a preconfigured output clock phase adjustment requirement and the binary bit ring.

[0014] In a specific embodiment, determining the control sequence based on a preconfigured output clock phase adjustment requirement and the binary bit ring includes: under the drive of its own working clock signal, starting from the starting node position on the binary bit ring, cyclically reading the binary bit at the next node position on the binary bit ring in a set rotation direction to generate and output the control sequence, wherein the change of the output binary bit is related to the phase of the working clock signal adjusted according to the output clock phase adjustment requirement; and correspondingly distributing the output control sequence to each frequency of f1And the enable terminal of the input clock signal with equally spaced phases.

[0015] Further, the method further includes: Based on the pre-configured output clock phase adjustment requirement, select the clock signal with the corresponding phase from multiple input clock signals with the same frequency f1 And equally spaced phases; Divide the selected clock signal by frequency to obtain the working clock signal.

[0016] In another specific implementation, the determining the control sequence based on the pre-configured output clock phase adjustment requirement and the binary bit ring includes: Based on the pre-configured output clock phase adjustment requirement, determine the starting node position on the binary bit ring, and starting from this starting node position, cyclically traverse the binary bits at each node position on the binary bit ring in the set rotation direction to obtain the control sequence; Output the control sequence under the drive of its own working clock signal; Distribute the output control sequence to the enable terminals of each input clock signal with the same frequency f1 And equally spaced phases.

[0017] In yet another specific implementation, the determining the control sequence based on the pre-configured output clock phase adjustment requirement and the binary bit ring includes: Based on the pre-configured output clock phase adjustment requirement, determine the cyclic distribution order of the binary bits on the binary bit ring; Distribute the binary bits on the binary bit ring to the enable terminals of each input clock signal with the same frequency according to the cyclic distribution order f1 And equally spaced phases.

[0018] The technical solution provided by the embodiments of the present invention does not require any additional deployment of delay adjustment units. Instead, it improves the multi-phase frequency divider that provides clock signals for different digital modules. The improved multi-phase frequency divider realizes precise control of the phase of the low-frequency output clock signal by dynamically selecting and combining multi-phase high-frequency input clock signals. This solution not only simplifies the circuit design, reduces the dependence on delay adjustment units, but also improves the robustness and reliability of the system, effectively solves the problems of large delay fluctuation, complex circuit design, and cumbersome control method existing in the prior art, enables the SOC to maintain a stable timing relationship in the face of PVT changes, and thus improves the overall performance and yield of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0020] Figure 1 Schematic diagram of the structure of a multi-phase frequency divider provided in the first embodiment of the present invention; Figure 2 Schematic diagram of the structure of a multi-phase frequency divider provided in the second embodiment of the present invention; Figure 3 Waveform diagram of each AND-OR logic input / output signal in a combinational logic unit provided in the second embodiment of the present invention; Figure 4 Another waveform diagram of each AND-OR logic input / output signal in a combinational logic unit provided in the second embodiment of the present invention; Figure 5 Schematic diagram of the structure of a multi-phase frequency divider provided in the third embodiment of the present invention; Figure 6 Schematic diagram of the structure of a multi-phase frequency divider provided in the fourth embodiment of the present invention; Figure 7 Schematic diagram of the flow of a multi-phase frequency division method provided in the fifth embodiment of the present invention. Detailed implementation manners

[0021] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0023] Next, the technical solutions of the present invention will be introduced in detail through each embodiment.

[0024] Embodiment 1 This embodiment provides a multi-phase frequency divider, which can be applied to an SOC to provide a low-frequency working clock signal for the internal digital module of the SOC. Refer to Figure 1 , the multi-phase frequency divider includes: A sequence control unit 101, configured to determine a control sequence based on a pre-configured frequency division ratio and an output clock phase adjustment requirement; A clock combination unit 102, configured to dynamically select clock signals with corresponding phases from multiple input clock signals with a frequency of f1 and equally spaced phases (exemplified as n phases in the figure) according to the determined control sequence for combination to generate an output clock signal with a frequency of f2 and a set phase (exemplified as m in the figure), where the f1 > f2。

[0025] The functions of each unit in the multi-phase frequency divider are introduced in detail below.

[0026] I. Sequence control unit 101 This unit is used to output a control sequence to control the clock combination unit 102 to combine input clock signals with the same frequency but different phases.

[0027] Among them, the control sequence is used to indicate when to select which phase of the input clock signal as part of the output clock signal. In other words, the control sequence defines which phases of the input clock signals will be selected to participate in the generation of the output clock signal, and the time order of the selected phases, so as to achieve precise control of the frequency and phase of the output clock signal. To meet the pre-configured output clock phase adjustment requirements, a corresponding control sequence will be determined first in this embodiment. This control sequence is then used to control the output clock signal to be output according to the set phase. It should be noted that under different output clock phase adjustment requirements, when the control sequence is selected for the first time, it will correspondingly select input clock signals of different phases. This means that the control sequence can be flexibly adjusted according to specific requirements to achieve precise control of the output clock signal phase.

[0028] The specific composition of the control sequence can vary depending on the application scenario and the specific clock control mechanism, and can be any of the following forms: (1) Binary code elements In this method, the control sequence can be a series of binary bits; for example, binary "0" and "1" are used to represent different selections of input clock phases. Assuming there are four input clock phases, two binary bits can be used for selection. "00" can represent selecting the first phase, "01" represents selecting the second phase, and so on; the sequence of these binary bits is arranged in a certain time order to form the control sequence, which is used to select input clock signals of different phases at different times; (2) Pulse signals The control sequence can also be a series of pulse signals. The occurrence time and width of these pulse signals can be used to trigger the selection of a specific clock phase; for example, a positive pulse signal can trigger the selection of a specific input clock phase as part of the output; parameters such as the period and duty cycle of the pulse signal can also be designed to precisely control the selection order and time length of the clock phase; (3) Logic level sequence A series of logic levels composed of high and low levels can also be used as the control sequence; different logic level combinations can control the on and off states of logic gates such as AND gates and OR gates, thereby selecting input clock signals of different phases; these logic levels change in a pre-designed order to form the control sequence for controlling the generation of the output clock signal.

[0029] Preferably, the control sequence can be formed according to a binary bit ring, which has multiple nodes, and each node position corresponds to a binary bit: 0 or 1. The arrangement of the nodes determines the relative positional relationship between the respective binary bits. The process of forming the control sequence may include: specifying the starting node position on the binary bit ring; starting from this starting node position, traversing the binary bits at each node position on the binary bit ring in a set rotation direction (clockwise or counterclockwise) in a loop to obtain an infinitely looping control sequence. Among them, the sequence composed of the binary bits on the binary bit ring in one cycle is called the basic period sequence, which is used to control the clock combination unit 102 to generate an output clock signal for one period. Each binary bit in the control sequence has its own corresponding control duration (usually one period of the input clock signal), and according to the preset phase order (usually from the minimum phase to the maximum phase), it is sequentially and cyclically mapped to a specific phase of multiple input clock signals with a frequency of f1 and equally spaced phases. Specifically, each binary bit corresponds to a unique phase. After mapping to the last phase, it will cycle back to the starting phase and continue mapping. For example, the input clock signal has a total of 4 phases ph0 (i.e., 0 。 phase), ph90 (i.e., 90 。 phase), ph180 (i.e., 180 。 phase), ph270 (i.e., 270 。 phase), and the control sequence is: 111001110011100……, that is, composed of the cyclic basic period sequence 11100. The preset phase order is from the minimum phase to the maximum phase. Then, the mapping relationship between each binary bit and the phase is shown in Table 1 below:

[0030] The binary bit "1" represents a high level state or an active state, indicating that the input clock signal corresponding to its phase is selected as part of the output clock signal during the current control duration; the binary bit "0" represents a low level state or an inactive state, indicating that the input clock signal corresponding to its phase is skipped during the current control duration and is not used as part of the output clock signal. The specific selection logic is determined by the configuration of the clock combination unit 102, and the functions of "1" and "0" can be reversed according to the design requirements.

[0031] From the process of forming the control sequence, it can be seen that the binary bit ring and the starting point position on the ring are the keys to forming the control sequence. The composition of the binary bit ring is related to the division ratio and each phase of the input clock signal. The division ratio is a parameter that describes the relationship between the frequency of the input clock signal f1 and the frequency of the output clock signal f2 and reflects the multiple by which the frequency of the output clock signal is reduced relative to the input clock signal. It can be expressed by the following formula: K= f1 / f2 , in this embodiment, the division ratio K is greater than 1. Specifically, when the phases of the input clock signal are known, those skilled in the art can design the binary bit ring and the control duration of each binary bit on the ring according to the pre-configured division ratio, as long as it can meet the frequency of the output clock signal f2 = f1 / K condition. Suppose the division ratio is 2.25 and the input clock signal is a clock signal with 4 equally spaced phases, then the binary bit ring can be: , the basic cycle sequence can be: 111000000, correspondingly, the control sequence is: 111000000111000000111000000..., cycling in turn, and the control duration of each binary bit is one cycle of the input clock signal.

[0032] For different multi-phase frequency dividers, when the binary bit rings are the same, if the starting node position on the ring is adjusted so that the phases of the input clock signals selected for the first time in the formed control sequence are different, then it will cause different time offsets in the output clock signals of the different multi-phase frequency dividers, that is, different delays are generated. Based on this, the starting node positions on the binary bit rings in the two multi-phase frequency dividers can be dynamically adjusted to change the delay amount between the working clock signals provided for the two digital modules respectively, so as to effectively optimize the timing relationship between the two digital modules.

[0033] Correspondingly, the sequence control unit 101 can be specifically used to: obtain the binary bit ring designed based on the pre-configured division ratio; determine the control sequence based on the pre-configured output clock phase adjustment requirement and the binary bit ring. For each multi-phase frequency divider used inside the SOC, the binary bit rings can be the same, and each constructs the control sequence starting from the corresponding starting node position on the binary bit ring according to its own output clock phase adjustment requirement. The corresponding relationship between different output clock phase adjustment requirements and different starting node positions can be pre-configured and stored by those skilled in the art.

[0034] It should be noted that to ensure the accurate selection of the input clock signals of each phase, it should be ensured that the control time of the binary bits in the control sequence (including the starting point of the control time and the control duration) accurately matches the start and end time ranges of the input clock signals of the phases it selects or skips, that is, they are strictly aligned with each other.

[0035] II. Clock combination unit 102 The control sequence output by the sequence control unit 101 is sent to the clock combination unit 102. The clock combination unit 102 is responsible for mapping each bit in the control sequence to the input clock signal of the corresponding phase, and generating a corresponding enable signal according to the state of this bit (such as "1" or "0"). In this embodiment, each input clock signal of a phase has an enable terminal. When the corresponding enable signal is at an effective level (for example, a high level, corresponding to the binary bit "1"), the clock signal of this phase will be selected and transmitted to the output; conversely, if the enable signal is at an ineffective low level (for example, a low level, corresponding to the binary bit "0"), the clock signal of this phase will be ignored.

[0036] After the above selection process, the input clock signals of the selected phases are combined in the manner specified by the control sequence to form the final output clock signal.

[0037] Embodiment 2 Based on the above Embodiment 1, this embodiment provides a specific example. Refer to Figure 2 , a multi-phase frequency divider includes: (1) Sequence control unit 201 This unit is a specific implementation of the sequence control unit 101 in Embodiment 1, and includes a phase selector 2011, a frequency divider 2012, a sequence generator 2013, and a sequence distributor 2014.

[0038] ① The phase selector 2011 is used to select the clock signal of the corresponding phase from multiple input clock signals with a frequency of f1 and equally spaced phases (4 phases are shown in the figure) based on the pre-configured output clock phase adjustment requirement.

[0039] The output clock phase adjustment requirement can be a clear specification of the selected phase in the input clock signal, and can be specifically determined by those skilled in the art according to the timing constraint requirements of different digital modules and the control of the input clock signal selection represented by the binary bits in the control sequence.

[0040] ② The frequency divider 2012 is used to divide the frequency of the clock signal selected by the phase selector 2011 to obtain the working clock signal of the sequence generator 2013.

[0041] In this embodiment, the low-frequency clock signal obtained by the frequency divider 2012 is different from the low-frequency clock signal output by the multi-phase frequency divider. The former is used to provide the working clock signal for the sequence generator 2013 inside the multi-phase frequency divider, and the latter is used to provide the working clock signal for the digital module outside the multi-phase frequency divider on the SOC. The frequency division ratio of the frequency divider 2012 and the pre-configured frequency division ratio used to determine the control sequence are two different descriptions and there is no correlation.

[0042] ③ The sequence generator 2013 is used to obtain the binary bit ring designed based on the preconfigured frequency division ratio and the starting node position on the ring; driven by its own working clock signal, starting from the starting node position, it cyclically reads the binary bits of the next node position on the binary bit ring in the set rotation direction (clockwise or counterclockwise) to generate the control sequence and output it, where the change of the output binary bits is related to the phase of the working clock signal adjusted according to the output clock phase adjustment requirement.

[0043] In specific implementation, the sequence generator 2013 can be implemented as a digital state machine, where each state uniquely corresponds to a node position on the binary bit ring, the state value is equal to the binary bit of that node position ("0" or "1"), and the transition between states follows the arrangement order of the nodes on the binary bit ring. Assume the binary bit ring is: , the state machine has a total of 9 states: S0, S1, S2,..., S8, and the state values are in turn: 1, 1, 1, 0, 0, 0, 0, 0, 0, and the state transition: S0->S1->S2,... ->S8->S0->S1->S2... ->S8->…. The working process of the digital state machine includes: Initialization: The state machine starts from a default initial state, and for all multi-phase frequency dividers, the initial state can be the same; Receiving input: The state machine continuously receives the working clock signal provided by the frequency divider 2012; State evaluation: According to the current state and the received working clock signal, determine whether a state transition is required; State transition: If the state transition condition is met, jump from the current state to a new state; Generating output: Output the control signal corresponding to the state value of the new state to the sequence distributor 2014.

[0044] The state transition is triggered by the effective clock edge of the working clock signal of the sequence generator 2013. By delaying the phase of the working clock signal, the time point of the state transition can be postponed. This delay further causes the time for the digital state machine to output the control signal corresponding to the next state value to be postponed, and the final result is that the phase of the output clock signal is also delayed accordingly.

[0045] ④ The sequence distributor 2014 is used to: distribute the control sequence output by the sequence generator 2013 to the enable terminals of the input clock signals with each frequency of f1 and equal interval phases.

[0046] (2) The combinational logic unit 202 This unit is the specific implementation of the clock combination unit 102 in Embodiment 1, and is used to combine each frequency off1 And the input clock signals with equally spaced phases are combined under the enabling of the corresponding enabling terminal signals to generate an output clock signal with a frequency of f2 and a set phase.

[0047] In specific implementation, each phase of the input clock signal has an enabling terminal in the combinational logic unit 202. The phase of the enabling signal of the enabling terminal is aligned with the corresponding phase in the input clock signal, and the control duration of each binary bit in the distributed control sequence is the same as the period of the input clock signal. For example, the i th phase ph i input clock signal corresponds to the i th enabling terminal en i in the clock combination unit 202. The phase of the enabling signal of the enabling terminal en i is aligned with the phase ph i , and the control duration of each binary bit in the control sequence distributed to the enabling terminal en i is the same as the period of the input clock signal.

[0048] Exemplarily, the combinational logic unit 202 includes a plurality of "AND" logic units and an "OR" logic unit, as Figure 2 shown. Each "AND" logic unit uniquely corresponds to an input clock signal of one phase. Its two input terminals are respectively connected to: an input clock signal of the uniquely corresponding one phase, the enabling terminal signal of this input clock signal, and the output terminal is the input of the "OR" logic unit. The output terminal of the "OR" logic unit generates an output clock signal with a frequency of f2 and a set phase (the example in the figure is m ).

[0049] It should be noted that Figure 2 only shows the composition structure of the combinational logic unit 202 under the input clock signals of 4 phases, but it does not mean that the number of phases of the input clock signal and the combinational logic unit 202 are limited to this. The number of phases of the input clock signal can be flexibly set according to actual needs, and the number of "AND" logic units in the combinational logic unit 202 can be adjusted accordingly. This embodiment does not limit this.

[0050] In addition, in this embodiment, the phase selector 2011 and the frequency divider 2012 are not necessary components of the multi-phase frequency divider and can be omitted according to design requirements. Other devices can also provide a working clock signal adjusted according to the output clock phase adjustment requirements for the sequence generator 2013, as long as it can ensure that the change of the binary bits output by the sequence generator 2013 is related to the phase of this working clock signal. By adjusting the phase of the working clock signal, the time of the change of the binary bits output by the sequence generator 2013 can be controlled.

[0051] The following is an example. The input clock signal is: 4 input clock signals with the same frequency of f1 and equally spaced phases. The phases are: pll0 (i.e., 0 。 phase), pll90 (i.e., 90 。 phase), pll180 (i.e., 180 。 phase), pll270 (i.e., 270 。 phase); the preconfigured frequency division ratio is 2.25, and the designed binary bit ring is: , and the control sequence is: 111000000111000000111000000... cycling; If the phase selector 2011 selects the input clock signal with the phase pll0 as the input of the frequency divider 2012 for frequency division, and then obtains the working clock signal of the sequence generator 2013, then: the 4-phase input clock signals input to the combinational logic unit 202 and their enable signals (en0, en90, en180, en270), the signals after the "AND" logic operation, and the waveform of the first output clock signal after the "OR" logic operation are as Figure 3 shown.

[0052] If the phase selector 2011 selects the input clock signal with the phase pll90 as the input of the frequency divider 2012 for frequency division, and then obtains the working clock signal of the sequence generator 2013, then: the 4-phase input clock signals input to the combinational logic unit 202 and their enable signals (en0, en90, en180, en270), the signals after the "AND" logic operation, the waveform of the second output clock signal after the "OR" logic operation, and the waveform of the first output clock signal are as Figure 4 shown. Compared with the first output clock signal, the phase of the second output clock signal is delayed backward by 0.25 clock cycles of the input clock signal.

[0053] And so on, if the phase selector 2011 selects the input clock signal with the phase pll180 as the input of the frequency divider 2012 for frequency division, and then obtains the working clock signal of the sequence generator 2013, then: the third output clock signal after the "OR" logic operation in the combinational logic unit 202 is delayed backward by 0.5 clock cycles of the input clock signal compared with the first output clock signal.

[0054] If the phase selector 2011 selects the input clock signal with the phase pll270 as the input of the frequency divider 2012 for frequency division, and then obtains the working clock signal of the sequence generator 2013, then: the fourth output clock signal after the "OR" logic operation in the combinational logic unit 202 is delayed backward by 0.75 clock cycles of the input clock signal compared with the first output clock signal.

[0055] As can be seen from the above, when the phase selector 2011 selects input clock signals with different phases, the phase of the final output clock signal can be linearly adjusted, is not affected by PVT variations, and has good consistency. Moreover, the adjustment range is close to one clock cycle of the input clock signal, can cover the PVT variations of the chip, and can meet the timing constraints required between different subsequent digital modules.

[0056] Embodiment III Based on the above Embodiment I, this embodiment provides a specific example. Refer to Figure 5 , a multi-phase frequency divider includes: (1) Sequence control unit 501 This unit is a specific implementation of the sequence control unit 101 in Embodiment I, and includes a phase selector 5011, a frequency divider 5012, a sequence generator 5013, and a sequence distributor 5014.

[0057] ① Phase selector 5011, which is used to: select a clock signal with one phase from multiple input clock signals with a frequency of f1 and equally spaced phases.

[0058] Among them, the selection can be arbitrary selection or fixed selection according to configuration. When different multi-phase frequency dividers are used inside the SOC to provide required clock signals for different digital modules, their respective phase selectors 5011 select clock signals with the same phase from the multiple input clock signals with a frequency of f1 and equally spaced phases.

[0059] ② Frequency divider 5012, which is used to: divide the frequency of the clock signal selected by the phase selector 5011 to obtain the working clock signal of the sequence generator 5013.

[0060] In this embodiment, the low-frequency clock signal obtained by the frequency divider 5012 is different from the low-frequency clock signal output by the multi-phase frequency divider. The former is used to provide the working clock signal for the sequence generator 5013 inside the multi-phase frequency divider, and the latter is used to provide the working clock signal for the digital modules outside the multi-phase frequency divider on the SOC. The frequency division ratio of the frequency divider 5012 and the pre-configured frequency division ratio used to determine the control sequence are two different descriptions and have no correlation.

[0061] ③ Sequence generator 5013, which is used to: obtain a binary bit ring designed based on the pre-configured frequency division ratio; determine the starting node position on the binary bit ring based on the pre-configured output clock phase adjustment requirement, and starting from this starting node position, cyclically traverse the binary bits at each node position on the binary bit ring in a set rotation direction (clockwise or counterclockwise) to obtain the control sequence; and output the control sequence under the drive of its own working clock signal.

[0062] When multiple multi-phase frequency dividers use the same binary bit ring structure, if the control sequence is adjusted by changing the starting node position on the binary bit ring such that these multi-phase frequency dividers are different when first selecting the phase of the input clock signal, then this adjustment will cause their output clock signals to be offset in time, that is, it will result in different delay times for their respective output clock signals. Specifically, after reading the pre-configured output clock phase adjustment requirement (as a specific delay amount), the corresponding relationship between the starting node positions on different binary bit rings and different delay times stored in advance can be searched to determine the starting node position on the binary bit ring corresponding to the specific delay time. Or, directly configure the starting node position on the binary bit ring by those skilled in the art in advance and use it as the output clock phase adjustment requirement.

[0063] ④ The sequence distributor 5014 is used to distribute the control sequence output by the sequence generator 5013 to the enable terminals of each input clock signal with f1 the same frequency and equally spaced phases.

[0064] (2) The combinational logic unit 502 This unit is a specific implementation of the clock combination unit 102 in Embodiment 1 and is used to: combine the input clock signals with f1 the same frequency and equally spaced phases together under the enable of the enable terminal signals of the corresponding input clock signals to generate an output clock signal with f2 the set frequency and set phase. It is the same as the combinational logic unit 202 in Embodiment 2 and will not be elaborated here.

[0065] It should be noted that Figure 5 only the composition structure of the combinational logic unit 502 under the input clock signal with 4 phases is shown, but it does not mean that the number of phases of the input clock signal and the combinational logic unit 502 are limited to this. The number of phases of the input clock signal can be flexibly set according to actual needs, and the number of "AND" logic units in the combinational logic unit 502 can be adjusted accordingly. This embodiment does not limit this. In addition, in this embodiment, the phase selector 5011 and the frequency divider 5012 are not necessary components of the multi-phase frequency divider and can be omitted according to design requirements, and other devices provide the working clock signal for the sequence generator 5013. When using different multi-phase frequency dividers, their respective sequence generators 5013 use the working clock signals with the same phase and the same frequency.

[0066] Embodiment 4 Based on the above Embodiment 1, this embodiment provides a specific example. Refer to Figure 6 , a multi-phase frequency divider includes: (1) The sequence control unit 601 This unit is a specific implementation of the sequence control unit 101 in Embodiment 1, including a phase selector 6011, a frequency divider 6012, a sequence generator 6013, and a sequence distributor 6014.

[0067] ① The phase selector 6011 is used to: select a clock signal with a certain phase from multiple input clock signals with the same frequency f1 and equally spaced phases.

[0068] Among them, the selection can be arbitrary selection or fixed selection according to the configuration. When different multi-phase frequency dividers inside the SOC are used to provide required clock signals for different digital modules, their respective phase selectors 6011 select clock signals with the same phase from the multiple input clock signals with the same frequency f1 and equally spaced phases.

[0069] ② The frequency divider 6012 is used to: divide the frequency of the clock signal selected by the phase selector 6011 to obtain the working clock signal of the sequence generator 6013.

[0070] In this embodiment, the low-frequency clock signal obtained by the frequency divider 6012 is different from the low-frequency clock signal output by the multi-phase frequency divider. The former is used to provide the working clock signal for the sequence generator 6013 inside the multi-phase frequency divider, and the latter is used to provide the working clock signal for the digital modules outside the multi-phase frequency divider on the SOC. The division ratio of the frequency divider 6012 and the pre-configured division ratio used to determine the control sequence are two different descriptions and have no correlation.

[0071] ③ The sequence generator 6013 is used to obtain the binary bit ring designed based on the pre-configured division ratio and output it to the sequence distributor 6014.

[0072] ④ The sequence distributor 6014 is used to: determine the cyclic distribution order of the binary bits on the binary bit ring based on the pre-configured output clock phase adjustment requirement; distribute the binary bits on the binary bit ring to the enable terminals of the input clock signals with the same frequency f1 and equally spaced phases according to the cyclic distribution order.

[0073] In this embodiment, the sequence generator 6013 directly passes the binary bit ring to the sequence distributor 6014. The sequence distributor 6014 is responsible for determining the cyclic distribution order of the binary bits at each node position on the ring. This process is essentially equivalent to determining the control sequence. Then, each binary bit in the control sequence will be distributed to the enable terminals of the input clock signals of the corresponding phases, so that the input clock signals of each phase can be selectively enabled or disabled according to the received binary bits. The cyclic distribution order refers to: starting from the specified starting node position on the binary bit ring, in accordance with the set rotation direction (clockwise or counterclockwise), the binary bits at each node position on the binary bit ring are sequentially and cyclically distributed to the enable terminals of the corresponding input clock signals. For example, the binary bit ring is: , and the cyclic distribution order includes the following 5 orders: 111001110011100... are cycled in sequence, and the obtained is control sequence 1; 110011100111001... are cycled in sequence, and the obtained is control sequence 2; 100111001110011... are cycled in sequence, and the obtained is control sequence 3; 001110011100111... are cycled in sequence, and the obtained is control sequence 4; 011100111001110... are cycled in sequence, and the obtained is control sequence 5.

[0074] Among them, the cyclic distribution order is dynamically adjusted according to the output clock phase adjustment requirement to ensure that the phase of the output clock signal is precisely controllable. Specifically, those skilled in the art can pre - establish the corresponding relationship between different output clock phase adjustment requirements and different cyclic distribution orders according to actual needs. By looking up this corresponding relationship, the cyclic distribution order corresponding to the pre - configured output clock phase adjustment requirement can be obtained.

[0075] In the above - mentioned manner, the sequence generator 6013 is responsible for generating the binary bit ring based on the division ratio, while the sequence distributor 6014 dynamically distributes the binary bits at each node position on the ring to the enable terminals of each input clock signal according to the output clock phase adjustment requirement. This design ensures that the phase of the output clock signal can be flexibly adjusted to meet the strict timing constraint requirements.

[0076] (2) Combinational logic unit 602 This unit is the specific implementation of the clock combination unit 102 in Embodiment 1, and is used for: combining the input clock signals with each frequency of f1 and equally - spaced phases together under the enable of the corresponding enable - terminal signals to generate a frequency of f2And an output clock signal with a set phase. Specifically, it is the same as the combinational logic unit 202 in the second embodiment, and will not be elaborated here.

[0077] It should be noted that Figure 6 only shows the composition structure of the combinational logic unit 602 under the input clock signal with 4 phases, but it does not mean that the number of phases of the input clock signal and the combinational logic unit 602 are limited to this. The number of phases of the input clock signal can be flexibly set according to actual needs, and the number of "AND" logic units in the combinational logic unit 602 can be adjusted accordingly. This embodiment does not limit this. In addition, in this embodiment, the phase selector 6011 and the frequency divider 6012 are not necessary components of the multi-phase frequency divider and can be omitted according to design requirements. Other devices provide the working clock signal for the sequence generator 6013. When different multi-phase frequency dividers are used, their respective sequence generators 6013 use the working clock signal with the same phase and the same frequency.

[0078] Embodiment Five This embodiment provides a multi-phase frequency division method, which can be executed by the multi-phase frequency divider described in the embodiments of the present invention. Refer to Figure 7 , this method includes the following steps: Step 701, determine a control sequence based on a pre-configured frequency division ratio and an output clock phase adjustment requirement; Step 702, according to the determined control sequence, dynamically select clock signals with corresponding phases from multiple input clock signals with a frequency of f1 and equally spaced phases for combination to generate an output clock signal with a frequency of f2 and a set phase, where f1 > f2。

[0079] Further, determining the control sequence based on a pre-configured frequency division ratio and an output clock phase adjustment requirement includes: Obtain a binary bit ring designed based on the pre-configured frequency division ratio; Determine the control sequence based on the pre-configured output clock phase adjustment requirement and the binary bit ring.

[0080] In a specific implementation manner, determining the control sequence based on the pre-configured output clock phase adjustment requirement and the binary bit ring includes: Driven by its own working clock signal, starting from the starting node position on the binary bit ring, cyclically read the binary bit at the next node position on the binary bit ring in a set rotation direction to generate the control sequence and output it, where the change of the output binary bit is related to the phase of the working clock signal adjusted according to the output clock phase adjustment requirement; Distribute the output control sequence to each frequency off1 and the enable terminal of the input clock signal with equally spaced phases.

[0081] Further, the method further includes: Based on the pre-configured output clock phase adjustment requirement, select the clock signal with the corresponding phase from multiple input clock signals with f1 equal frequencies and equally spaced phases; Divide the selected clock signal by a frequency to obtain the working clock signal.

[0082] In another specific implementation manner, the determining the control sequence based on the pre-configured output clock phase adjustment requirement and the binary bit ring includes: Based on the pre-configured output clock phase adjustment requirement, determine the starting node position on the binary bit ring. Starting from this starting node position, traverse the binary bits at each node position on the binary bit ring in a set rotation direction in a loop to obtain the control sequence; output the control sequence under the drive of its own working clock signal; Correspondingly distribute the output control sequence to the enable terminals of each input clock signal with f1 equal frequencies and equally spaced phases.

[0083] In yet another specific implementation manner, the determining the control sequence based on the pre-configured output clock phase adjustment requirement and the binary bit ring includes: Based on the pre-configured output clock phase adjustment requirement, determine the cyclic distribution order of the binary bits on the binary bit ring; correspondently distribute the binary bits on the binary bit ring to the enable terminals of each input clock signal with f1 equal frequencies and equally spaced phases according to the cyclic distribution order.

[0084] The multi-phase frequency division method in this embodiment and the multi-phase frequency divider described in any of the foregoing embodiments have basically the same implementation principle and corresponding technical effects, and will not be elaborated here.

[0085] In summary, the embodiments of the present invention solve the problem that when different digital modules communicate with each other, it is necessary to adjust the clock phases of different digital modules to meet specific timing constraints. Based on the principle of the multi-phase frequency divider, the embodiments of the present invention adjust the clock signal phase of the control sequence generator, or the starting node of the binary bit ring, or the cyclic distribution order of the sequence distributor, so that the phase of the input clock signal initially selected by the control sequence can be adjusted, and then the phase of the output clock signal can be adjusted. The phase adjustment step of the output clock signal is proportional to the input clock period, does not change with PVT, and has a wide adjustment range, and can more conveniently meet the timing constraints.

[0086] In summary, the embodiments of the present invention aim to solve the timing constraint problem faced during the communication between different digital modules, especially the need to adjust the clock phases of each digital module to meet the timing constraints. Based on the principle of a multi-phase frequency divider, the present invention changes the phase of the input clock signal initially selected by the control sequence by adjusting the phase of the clock signal of the control sequence generator, the starting node position of the binary bit ring, or the cyclic distribution order of the sequence distributor, so as to achieve the adjustment of the phase of the output clock signal. The feature of this adjustment method is that there is no need to introduce additional delay adjustment units on the paths where each multi-phase frequency divider transmits clock signals to their respective corresponding digital modules, and the adjustment step of the output clock signal phase is proportional to the input clock period, does not change with the variation of PVT, and has a wide adjustment range, capable of conveniently meeting various timing constraint conditions.

[0087] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

[0088] The term "and / or" in the embodiments of the present invention describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0089] Each embodiment in this specification is described in a related manner. The same or similar parts among the embodiments can be referred to each other, and the differences between each embodiment and other embodiments are emphasized.

[0090] In particular, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0091] For the convenience of description, the above device is described by dividing it into various units / modules according to functions. Of course, when implementing the present invention, the functions of each unit / module can be realized in one or more software and / or hardware.

[0092] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, the storage medium can be a magnetic disk, an optical disc, a read-only memory (ROM), a random access memory (RAM), or the like.

[0093] As described above, the above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A multi-phase frequency divider, characterized in that: include: A sequence control unit, for determining a control sequence based on a preconfigured frequency division ratio and an output clock phase adjustment requirement; The clock combination unit is used to obtain the clocks from multiple frequencies according to the determined control sequence. f1 The clock signals of corresponding phases are dynamically selected from the input clock signals with equal interval phases to generate a clock signal with a frequency of f2 And set the phase of the output clock signal; Among them, the f1>f2.

2. The multi-phase frequency divider according to claim 1, characterized in that: The sequence control unit is specifically used for: Obtaining a binary bit ring designed based on a preconfigured frequency division ratio; The control sequence is determined based on a preconfigured output clock phase adjustment requirement and the binary bit ring.

3. The multi-phase frequency divider according to claim 2, characterized in that: The sequence control unit includes a sequence generator and a sequence distributor, wherein: The sequence generator is used to obtain a binary bit ring designed based on a preconfigured frequency division ratio and a starting node position on the ring; under the drive of its own working clock signal, starting from the starting node position, cyclically read the binary bit of the next node position on the binary bit ring in a set rotation direction to generate the control sequence and output it, wherein the change of the output binary bit is related to the phase of the working clock signal adjusted according to the output clock phase adjustment requirement; The sequence distributor is used to distribute the control sequence output by the sequence generator to each frequency f1 The enable terminal of the input clock signal with equally spaced phases.

4. The multi-phase frequency divider according to claim 3, characterized in that: The sequence control unit further comprises: Phase selector for output clock phase adjustment based on preconfigured requirements from multiple frequencies f1 and selecting a clock signal of corresponding phase from input clock signals of equally spaced phases; A frequency divider is used to divide the clock signal selected by the phase selector to obtain the working clock signal of the sequence generator itself.

5. The multi-phase frequency divider according to claim 2, characterized in that: The sequence control unit includes a sequence generator and a sequence distributor, wherein: The sequence generator is used to obtain a binary bit ring designed based on a preconfigured frequency division ratio; determine a starting node position on the binary bit ring based on a preconfigured output clock phase adjustment requirement, and from the starting node position, traverse the binary bits of each node position on the binary bit ring in a set rotation direction to obtain the control sequence; and output the control sequence under the drive of its own working clock signal; The sequence distributor is used to distribute the control sequence output by the sequence generator to each frequency f1 The enable terminal of the input clock signal with equally spaced phases.

6. The multi-phase frequency divider according to claim 2, characterized in that: The sequence control unit includes a sequence generator and a sequence distributor, wherein: The sequence generator is used to obtain a binary bit ring designed based on a preconfigured frequency division ratio and output it to the sequence distributor; The sequence distributor is used to determine the cyclic distribution order of the binary bits on the binary bit ring based on the preconfigured output clock phase adjustment requirement; distribute the binary bits on the binary bit ring to each frequency in accordance with the cyclic distribution order. f1 The enable terminal of the input clock signal with equally spaced phases.

7. A multi-phase frequency division method, characterized in that: The method comprises: Determine a control sequence based on a preconfigured frequency division ratio and output clock phase adjustment requirements; According to the determined control sequence, from multiple frequencies f1 The clock signals of corresponding phases are dynamically selected from the input clock signals with equal interval phases to generate a clock signal with a frequency of f2 And set the phase of the output clock signal; Among them, the f1>f2.

8. The method according to claim 7, characterized in that Based on the preconfigured division ratio and output clock phase adjustment requirements, determine the control sequence, including: Obtaining a binary bit ring designed based on a preconfigured frequency division ratio; The control sequence is determined based on a preconfigured output clock phase adjustment requirement and the binary bit ring.

9. The method according to claim 8, characterized in that The determining the control sequence based on the preconfigured output clock phase adjustment requirement and the binary bit ring comprises: Driven by its own working clock signal, starting from the starting node position on the binary bit ring, the binary bit of the next node position on the binary bit ring is cyclically read in a set rotation direction to generate the control sequence and output it, wherein the change of the output binary bit is related to the phase of the working clock signal adjusted according to the output clock phase adjustment requirement; The output control sequence is distributed to each frequency f1 The enable terminal of the input clock signal with equally spaced phases.

10. The method according to claim 9, characterized in that The method further comprises: Based on the preconfigured output clock phase adjustment requirements, multiple frequencies are f1 and selecting a clock signal of corresponding phase from input clock signals of equally spaced phases; The selected clock signal is divided by frequency to obtain the working clock signal.

11. The method according to claim 8, characterized in that The determining the control sequence based on the preconfigured output clock phase adjustment requirement and the binary bit ring comprises: Based on the pre-configured output clock phase adjustment requirements, determine the starting node position on the binary bit ring, and from the starting node position, traverse the binary bits of each node position on the binary bit ring in a set rotation direction to obtain the control sequence; output the control sequence under the drive of its own working clock signal; The output control sequence is distributed to each frequency f1 The enable terminal of the input clock signal with equally spaced phases.

12. The method according to claim 8, characterized in that The determining the control sequence based on the preconfigured output clock phase adjustment requirement and the binary bit ring comprises: Based on the preconfigured output clock phase adjustment requirement, determine the cyclic distribution order of the binary bits on the binary bit ring; distribute the binary bits on the binary bit ring to each frequency in accordance with the cyclic distribution order. f1 The enable terminal of the input clock signal with equally spaced phases.

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