Method and system for calibrating mismatch of off-chip capacitor of analog front end based on digital foreground

Abstract

The invention discloses a method and system for calibrating mismatch of an off-chip capacitor of an analog front end based on a digital foreground, and relates to the technical field of circuits, and the method comprises the steps: connecting a first capacitor and a second capacitor to a non-inverting input end and an inverting input end of the analog front end respectively; short-circuiting the in-phase input end and the reverse input end to a common-mode voltage, and further calculating to obtain a mismatch error voltage; comparing the common-mode voltage with the mismatch error voltage by using a comparator so as to compare the capacitance value of the first capacitor with the capacitance value of the second capacitor; and the capacitors in the capacitor array are connected in parallel to one of the first capacitor and the second capacitor with the smaller capacitance value one by one according to the capacitance values from large to small until the compensation capacitor meets the target compensation amount. Through digital logic control of the digital foreground, the capacitor array is dynamically configured to perform calibration compensation on the first capacitor or the second capacitor outside the analog front end chip, capacitance compensation can be realized without additionally adding a hardware circuit, and the complexity and the cost of the analog front end are reduced.

Description

Technical Field

[0001] This application relates to the field of circuit technologies, and in particular, to a method and system for calibrating off-chip capacitor mismatch of an analog front end based on a digital front end. Background Art

[0002] In a wearable medical monitoring system, the analog front-end circuit for biological signal acquisition serves as the core hub of the signal chain, and its performance directly determines the clinical effectiveness and reliability of the entire system. Such a circuit undertakes the core task of accurately extracting microvolt-level physiological signals (such as electrocardiogram, electroencephalogram, electromyogram, etc.) from complex environmental interferences. Its design needs to face three major technical challenges: First, the extreme weakness of physiological signals (typical amplitude is 10 μV to 5 mV), making it extremely easy to be overwhelmed by circuit background noise (<5 μVrms requirement), electrode contact impedance fluctuations (>1 GΩ input impedance requirement), and common-mode interference (such as 50 / 60 Hz power frequency interference); Second, the stringent restrictions on power consumption and volume of wearable devices (battery life >7 days, chip area <2 mm 2 ), requiring the circuit to achieve high-precision signal conditioning at sub-milliwatt power consumption; Third, the need for dynamic environment adaptability (such as motion artifacts, temperature and humidity changes), urgently requiring the front-end circuit to have real-time noise suppression and self-calibration capabilities.

[0003] Existing solutions address the noise problem by cascading high-gain amplifiers (sacrificing power consumption), increasing the supply voltage (increasing system complexity), or external filtering networks (occupying PCB area), etc. Essentially, it is to exchange additional hardware circuits for performance improvement, resulting in a significant deterioration of the system figure of merit (FoM). Summary of the Invention

[0004] The main objective of the embodiments of this application is to propose a method and system for calibrating off-chip capacitor mismatch of an analog front end based on a digital front end, so as to calibrate and compensate the off-chip capacitors of the analog front end without adding additional hardware circuits.

[0005] To achieve the above objective, on the one hand, an embodiment of this application proposes a method for calibrating off-chip capacitor mismatch of an analog front end based on a digital front end, and the method includes the following steps:

[0006] Connect a first capacitor and a second capacitor to the non-inverting input terminal and the inverting input terminal of the analog front end respectively;

[0007] Short-circuit the non-inverting input terminal and the inverting input terminal to the common-mode voltage, and then calculate the mismatch error voltage;

[0008] Use a comparator to compare the voltage magnitudes of the common-mode voltage and the mismatch error voltage to compare the capacitance values of the first capacitor and the second capacitor;

[0009] Connect each capacitor in the capacitor array in parallel to the side with the smaller capacitance value between the first capacitor and the second capacitor one by one from largest to smallest capacitance value until the compensation capacitor meets the target compensation amount; wherein, the compensation capacitor is the capacitor in the capacitor array that is connected in parallel to the side with the smaller capacitance value between the first capacitor and the second capacitor.

[0010] In some embodiments, the step of connecting the first capacitor and the second capacitor to the in-phase input terminal and the anti-phase input terminal of the analog front end respectively includes the following steps:

[0011] Connect the upper plates of the first capacitor and the second capacitor to the in-phase input terminal and the anti-phase input terminal of the analog front end respectively, and connect the lower plates of the first capacitor and the second capacitor to ground, so as to initialize the charges of the first capacitor and the second capacitor to zero.

[0012] In some embodiments, the step of calculating the mismatch error voltage includes the following steps:

[0013] Calculate the mismatch error voltage according to the principle of charge conservation;

[0014] The expression of the principle of charge conservation is:

[0015] Q = C n *V cm = C p *V error ;

[0016] Wherein, Q represents charge; C n is the first capacitor, C p is the second capacitor, V cm is the common-mode voltage, V error is the mismatch error voltage;

[0017] Furthermore, the calculation formula of the mismatch error voltage is:

[0018]

[0019] In some embodiments, the step of using a comparator to compare the voltage magnitudes of the common-mode voltage and the mismatch error voltage to compare the capacitance values of the first capacitor and the second capacitor includes the following steps:

[0020] Use a comparator to compare the voltage magnitudes of the common-mode voltage and the mismatch error voltage;

[0021] If the common-mode voltage is greater than the mismatch error voltage, use the comparator to output a first logic signal to indicate that the capacitance value of the first capacitor is less than the capacitance value of the second capacitor;

[0022] If the common-mode voltage is less than the mismatch error voltage, the comparator is used to output a second logic signal to indicate that the capacitance value of the first capacitor is greater than that of the second capacitor.

[0023] In some embodiments, the step of connecting each capacitor in the capacitor array in parallel to the smaller-capacitance one of the first capacitor and the second capacitor one by one from the largest to the smallest capacitance value until the compensation capacitor meets the target compensation amount includes the following steps:

[0024] Take the smaller-capacitance one of the first capacitor and the second capacitor as the small capacitor, and the other as the large capacitor. Connect each capacitor in the capacitor array in parallel to the small capacitor one by one from the largest to the smallest capacitance value, and sequentially determine the capacitance value relationship between the small capacitor after connecting the compensation capacitor and the large capacitor;

[0025] If the capacitance value of the small capacitor after connecting the compensation capacitor is still less than that of the large capacitor, connect the next smaller-capacitance capacitor in the capacitor array in parallel to the small capacitor from the largest to the smallest capacitance value until the smallest-capacitance capacitor in the capacitor array is connected in parallel to the small capacitor or the compensation capacitor meets the target compensation amount;

[0026] If the capacitance value of the small capacitor after connecting the compensation capacitor is greater than that of the large capacitor, disconnect the parallel connection between the compensation capacitor and the small capacitor, and then connect the next smaller-capacitance capacitor in the capacitor array in parallel to the small capacitor from the largest to the smallest capacitance value until the smallest-capacitance capacitor in the capacitor array is connected in parallel to the small capacitor or the compensation capacitor meets the target compensation amount.

[0027] In some embodiments, after the compensation is completed, the first capacitor, the second capacitor, and the compensation capacitor satisfy the following relationship:

[0028]

[0029] where C n is the first capacitor, C p is the second capacitor; is the sum of the compensation capacitors, C k represents a single compensation capacitor, and N represents the total number of capacitors connected in parallel to the small capacitor.

[0030] In some embodiments, the step of connecting each capacitor in the capacitor array in parallel to the smaller-capacitance one of the first capacitor and the second capacitor one by one from the largest to the smallest capacitance value until the compensation capacitor meets the target compensation amount includes the following steps:

[0031] Connect each capacitor in the capacitor array in parallel one by one from the largest capacitance value to the smaller one of the first capacitor and the second capacitor until the compensation capacitor is half the capacitance value of the second capacitor; wherein, half the capacitance value of the second capacitor is used as the target compensation amount.

[0032] To achieve the above object, on the other hand, an embodiment of the present application proposes a system for calibrating off-chip capacitor mismatch of an analog front end based on a digital front end. The system includes:

[0033] An initialization module for connecting a first capacitor and a second capacitor to the in-phase input terminal and the anti-phase input terminal of the analog front end respectively.

[0034] A voltage calculation module for shorting the in-phase input terminal and the reverse input terminal to a common-mode voltage, and then calculating a mismatch error voltage.

[0035] A voltage comparison module for using a comparator to compare the magnitudes of the common-mode voltage and the mismatch error voltage to compare the capacitance values of the first capacitor and the second capacitor.

[0036] A capacitor compensation module for connecting each capacitor in the capacitor array in parallel one by one from the largest capacitance value to the smaller one of the first capacitor and the second capacitor until the compensation capacitor meets the target compensation amount; wherein, the compensation capacitor is the capacitor in the capacitor array that is connected in parallel to the smaller one of the first capacitor and the second capacitor.

[0037] To achieve the above object, on the other hand, an embodiment of the present application proposes an electronic device. The electronic device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the above method is implemented.

[0038] To achieve the above object, on the other hand, an embodiment of the present application proposes a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the above method is implemented.

[0039] The embodiments of the present application at least include the following beneficial effects:

[0040] The solution of this application includes: connecting a first capacitor and a second capacitor to the non-inverting input terminal and the inverting input terminal of the analog front end respectively; shorting the non-inverting input terminal and the inverting input terminal to the common-mode voltage, and then calculating the mismatch error voltage; using a comparator to compare the magnitudes of the common-mode voltage and the mismatch error voltage to compare the capacitance values of the first capacitor and the second capacitor; connecting each capacitor in the capacitor array in parallel to the one with the smaller capacitance value among the first capacitor and the second capacitor one by one from largest to smallest until the compensation capacitor meets the target compensation amount; wherein, the compensation capacitor is the capacitor in the capacitor array that is connected in parallel to the one with the smaller capacitance value among the first capacitor and the second capacitor. This application dynamically configures the capacitor array through the digital logic control of the digital front end to calibrate and compensate the first capacitor or the second capacitor outside the analog front end, and can achieve capacitance compensation without adding additional hardware circuits, reducing the complexity and cost of the analog front end. Description of the Drawings

[0041] To more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0042] Figure 1 It is an example circuit diagram of an instrumentation amplifier provided by an embodiment of this application;

[0043] Figure 2 It is a schematic flowchart of a method for calibrating the mismatch of an external capacitor of an analog front end based on a digital front end provided by an embodiment of this application;

[0044] Figures 3(a) to 3(e) It is an example flowchart of a calibration compensation capacitor provided by an embodiment of this application;

[0045] Figure 4 It is a relationship diagram between the number of bits of the compensation capacitor and the relative error provided by an embodiment of this application;

[0046] Figure 5 It is a relationship diagram between the number of bits of the mismatch compensation capacitor and the relative error provided by an embodiment of this application considering the mismatch;

[0047] Figure 6 It is a relationship diagram between the external capacitor mismatch error and the CMRR provided by an embodiment of this application;

[0048] Figure 7 It is a relationship diagram between the external capacitor mismatch error and the PSRR provided by an embodiment of this application;

[0049] Figure 8Schematic structural diagram of the system for calibrating the off-chip capacitor mismatch of the analog front end based on the digital front end provided by the embodiment of the present application;

[0050] Figure 9 Schematic hardware structure diagram of an electronic device provided by the embodiment of the present application. Detailed implementation manners

[0051] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application detailed in the appended claims.

[0052] It can be understood that the terms "first", "second", etc. used in the present application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if", "when" as used herein may be interpreted as "when...", "while...", or "in response to determining".

[0053] The terms "at least one", "a plurality", "each", "any one", etc. used in the present application, at least one includes one, two or more than two, a plurality includes two or more than two, each refers to each of the corresponding plurality, and any one refers to any one of the plurality.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0055] Before elaborating on the embodiments of the present application in detail, some related technologies involved in the embodiments of the present application are described as follows:

[0056] Some existing analog front-end designs focus on multi-dimensional collaborative optimization: using chopper stabilization technology to shift the 1 / f noise spectrum to the high-frequency band, combined with an active electrode buffer to suppress the electrode polarization effect; using a current-reuse operational transconductance amplifier to achieve a common-mode rejection ratio (CMRR) of more than 90 dB at a 100 nA bias current; introducing an adaptive biasing mechanism to dynamically adjust the power consumption mode according to the signal amplitude, enabling the system to maintain an input-referred noise of 0.8 μVrms even at an ultra-low supply voltage of 0.5 V. These innovative technologies achieve the optimal balance of noise-power-area through architectural-level reconstruction rather than simple parameter optimization, providing fundamental technical support for high-density bio-signal monitoring in wearable medical devices.

[0057] Among them, the instrumentation amplifier (IA) serves as the input stage of the AFE (analog front-end) ( Figure 1 as an example circuit diagram of an instrumentation amplifier), and its performance is the most critical part restricting the performance of the AFE and the subsequent ADC. The three-op-amp instrumentation amplifier, as the most widely used structure in the industrial field, is known for its stability and robustness. In addition, it isolates the input from the feedback loop, and the input is directly connected to the gate of the MOS transistor, greatly increasing the equivalent input impedance. The gain of the instrumentation amplifier is approximately 40 - 60 dB. Therefore, in order to avoid the output saturation of the instrumentation amplifier, it is necessary to suppress the DC offset voltage (the offset voltage of traditional electrodes is approximately 100 mV). In the first-stage structure, the feedback resistor R1 is connected to the ground voltage through the capacitor Cp, and the DC current flowing through the resistor R1 is cut off by Cp, thereby achieving the suppression of the DC component in the signal. It can be seen that the -3 dB high-pass frequency point of the circuit is determined by R1 and Cp. Since the -3 dB high-pass node applied to the ECG signal acquisition circuit is generally below 1 Hz, the value of the capacitor Cp is relatively large and can be implemented outside the chip. The -3 dB high-pass node of the circuit can be expressed as:

[0058]

[0059] Among them, the initial value of the capacitor Cp is taken as 3 μF, and the -3dB high-pass frequency of the circuit can be obtained to be about 1 Hz. The -3dB high-pass frequency point of the circuit can be flexibly adjusted by externally adjusting the size of the capacitor Cp. However, in the capacitor datasheets provided by some current manufacturers, the actual capacitance value of capacitors in the μF level generally deviates from the ideal capacitance value by 10%-20%. Assuming that the worst-case mismatch is 20%, and the worst-case mismatches of the upper and lower Cp are in opposite directions, then the overall actual mismatch of the two capacitors reaches about 40% at worst. This will cause great damage to the fully differential symmetric structure of the first stage, and indicators such as CMRR and PSRR that rely on symmetry will drop severely, making the actual indicators not meet the requirements of the design indicators.

[0060] To solve the problem of capacitor mismatch, the currently adopted relatively traditional method for solving the mismatch of off-chip large capacitors is to manually or automatically adjust circuit parameters through adjustable elements (such as fuses, antifuses, programmable capacitor / resistor arrays) after manufacturing to compensate for capacitor mismatch. This requires additional circuit trimming, increases chip area and cost, only supports one-time calibration, cannot adapt to dynamic environmental changes (such as temperature drift), has a complex process, and is not suitable for the low-cost requirements and mass production requirements of wearable devices.

[0061] Another method is dynamic component matching, which periodically switches the capacitor connection method and offsets the mismatch error through time averaging. Different capacitor units are rotated and used within multiple clock cycles, and capacitor combinations are randomly selected to reduce fixed pattern noise. However, the disadvantage is that it is only effective for periodic signals, cannot completely eliminate DC mismatch; introduces additional switching noise and reduces the signal-to-noise ratio (SNR); requires a high-frequency clock drive, increasing system power consumption.

[0062] Based on this, the embodiments of the present application provide a method for calibrating off-chip capacitor mismatch of an analog front end based on a digital front end. Referring to Figure 2 , this method may include but is not limited to S200 to S230, specifically as follows:

[0063] S200: Connect the first capacitor and the second capacitor to the non-inverting input terminal and the inverting input terminal of the analog front end respectively.

[0064] Further, S200 may include the following steps S201:

[0065] S201: Connect the upper plates of the first capacitor and the second capacitor to the non-inverting input terminal and the inverting input terminal of the analog front end respectively, and connect the lower plates of the first capacitor and the second capacitor to ground, so as to initialize the charges of the first capacitor and the second capacitor to zero.

[0066] S210: Short-circuit the in-phase input terminal and the anti-phase input terminal to the common-mode voltage, and then calculate the mismatch error voltage.

[0067] Further, the calculation of the mismatch error voltage in S210 may include the following steps S211:

[0068] S211: Calculate the mismatch error voltage according to the principle of charge conservation;

[0069] The expression of the principle of charge conservation is:

[0070] Q = C n *V cm = C p *V error ;

[0071] wherein, Q represents charge; C n is the first capacitor, C p is the second capacitor, V cm is the common-mode voltage, V error is the mismatch error voltage;

[0072] Furthermore, the calculation formula of the mismatch error voltage is:

[0073]

[0074] S220: Use a comparator to compare the magnitudes of the common-mode voltage and the mismatch error voltage to compare the capacitance values of the first capacitor and the second capacitor.

[0075] Further, S220 may include the following steps S221 to S223:

[0076] S221: Use a comparator to compare the magnitudes of the common-mode voltage and the mismatch error voltage;

[0077] S222: If the common-mode voltage is greater than the mismatch error voltage, use the comparator to output a first logic signal to indicate that the capacitance value of the first capacitor is less than the capacitance value of the second capacitor;

[0078] S223: If the common-mode voltage is less than the mismatch error voltage, use the comparator to output a second logic signal to indicate that the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.

[0079] S230: Connect each capacitor in the capacitor array in parallel one by one from the largest to the smallest capacitance value to the side with the smaller capacitance value between the first capacitor and the second capacitor until the compensation capacitor meets the target compensation amount; wherein, the compensation capacitor is the capacitor in the capacitor array that is connected in parallel to the side with the smaller capacitance value between the first capacitor and the second capacitor.

[0080] Further, S230 may include the following steps S231 to S233:

[0081] S231: Take the capacitor with the smaller capacitance value among the first capacitor and the second capacitor as the small capacitor, and the other as the large capacitor. Connect each capacitor in the capacitor array to the small capacitor in parallel one by one in descending order of capacitance value, and sequentially determine the capacitance value relationship between the small capacitor after connecting the compensation capacitor and the large capacitor;

[0082] S232: If the capacitance value of the small capacitor after connecting the compensation capacitor is still smaller than that of the large capacitor, then connect the next capacitor with a smaller capacitance value in the capacitor array to the small capacitor in parallel in descending order of capacitance value until the capacitor with the smallest capacitance value in the capacitor array is connected to the small capacitor or the compensation capacitor meets the target compensation amount;

[0083] S233: If the capacitance value of the small capacitor after connecting the compensation capacitor is greater than that of the large capacitor, disconnect the parallel connection between the compensation capacitor and the small capacitor, and then connect the next capacitor with a smaller capacitance value in the capacitor array to the small capacitor in parallel in descending order of capacitance value until the capacitor with the smallest capacitance value in the capacitor array is connected to the small capacitor or the compensation capacitor meets the target compensation amount.

[0084] As an alternative implementation manner, after the compensation is completed, the first capacitor, the second capacitor, and the compensation capacitor satisfy the following relational expression:

[0085]

[0086] Where C n is the first capacitor, C p is the second capacitor; is the total sum of the compensation capacitors, C k represents a single compensation capacitor, and N represents the total number of capacitors connected to the small capacitor in parallel.

[0087] As another alternative implementation manner, S230 may include the following step S234:

[0088] S234: Connect each capacitor in the capacitor array to the capacitor with the smaller capacitance value among the first capacitor and the second capacitor in parallel one by one in descending order of capacitance value until the compensation capacitor is half of the capacitance value of the second capacitor; where, half of the capacitance value of the second capacitor is used as the target compensation amount.

[0089] Next, specific application examples will be combined to introduce and illustrate the solution of the embodiment of the present application in detail.

[0090] Exemplarily, in this embodiment, a digital front end can be utilized to calibrate an analog front end, thereby compensating for the errors generated by the off-chip capacitors used to suppress the DC offset voltage.

[0091] This embodiment discloses a method and system for compensating for the mismatch errors of off-chip large capacitors in an analog front end (AFE) using digital calibration technology. In this embodiment, for the off-chip capacitor mismatch problems in the AFE circuit caused by process deviations, temperature drift, bond wire parasitics, etc., a binary-weighted compensation capacitor array is dynamically configured through a binary search algorithm to precisely offset the mismatch errors, thereby suppressing the DC offset voltage and significantly improving the full-differential symmetry and high-pass pole stability of the system, especially for the two indexes of CMRR and PSRR, which have relatively high symmetry requirements in the full-differential system. The core innovation of this embodiment is to digitalize the traditional analog compensation scheme and combine charge detection with logic control to achieve high-robustness and low-cost error calibration, which is applicable to fields such as high-precision sensor interfaces, medical electronic devices, and industrial control systems.

[0092] To make up for the problems such as the decrease in CMRR and PSRR of IA caused by off-chip capacitor mismatch, the high cost of existing technologies, and the difficulty in large-scale application, in this embodiment, by dynamically configuring a binary-weighted compensation capacitor array, the capacitor mismatch error is controlled below 0.1%, and the compensation capacitor array is compatible with a process deviation of ±20%, without additional redundant design, and through pure digital logic control, the system complexity and cost are reduced.

[0093] The hardware modules involved in this embodiment may include:

[0094] 1. Off-chip capacitor network: including the capacitor to be calibrated Cn, Cp, and a binary-weighted compensation capacitor array (C / 2, C / 4, C / 8, etc.), and the total compensation capacity is 0.2Cp;

[0095] 2. Switch matrix: composed of S1 - S12, used to switch the capacitor connection state;

[0096] 3. Comparator: detects the mismatch error voltage Verror and outputs it to the digital logic controller;

[0097] 4. SAR logic controller (digital front end): drives the switch matrix based on the comparator result and gradually approximates the target compensation value according to the binary search algorithm.

[0098] Exemplarily, Figures 3(a) to 3(e) It is an example flowchart for calibrating the compensation capacitor.

[0099] Specifically, the calibration method steps of this embodiment are as follows:

[0100] Step 1: Initialize the mode.

[0101] Close switches S1, S3, and S4. Connect the upper plates of Cn (the first capacitor) and Cp (the second capacitor) to the VIP (non-inverting input terminal) and VIN (inverting input terminal) of the AFE (analog front end) respectively, and ground the lower plates. Initialize the charge to zero. This is the normal operating state of the instrumentation amplifier.

[0102] Step 2: Mismatch detection.

[0103] Disconnect S4 and short-circuit VIP and VIN to the common-mode voltage V CM (such as 0.9V). Calculate the mismatch error voltage according to the principle of charge conservation:

[0104] Q = C n *V cm = C p *V error ;

[0105] It can be deduced that:

[0106]

[0107] Comparator Comp compares Verror with V CM and outputs a logic signal 0 or 1 to indicate the relative magnitudes of Cn and Cp.

[0108] Step 3: Binary search compensation.

[0109] High-order first: Starting from the largest compensation capacitor C / 2, successively attempt to parallel it to Cp. If Comp outputs a high level (Cn > Cp), close S8 and S9 to parallel C / 2 with Cp. If the output is a low level (Cn < Cp), close S7 and S9 to parallel C / 2 with Cn. At the next moment, judge the size of the smaller capacitor plus C / 2 and the larger capacitor. If the larger capacitor is still larger after compensation, keep the previous switch closed. If the larger capacitor is larger after compensation, disconnect the previous switch and discard this compensation bit of C / 2, and iterate to converge: Repeat the above process until the least significant bit (LSB). Finally, the sum of the compensation capacitors satisfies:

[0110]

[0111] Assume that Cn and Cp are 1.2C and 1C respectively, the compensation capacitor array has no error and the sum is 0.2C. Then the relationship between the error and the number of compensation bits is as Figure 4 shown. From Figure 4 it can be obtained that when the compensation capacitor is 8 bits, the accuracy can reach 0.6% ideally.

[0112] Step 4: Error tolerance control.

[0113] Overcompensation Design: In this embodiment, the worst-case scenario will be considered. Assuming a 20% deviation for each off-chip capacitor, with Cn being 1.2C and Cp being 0.8C, the target compensation amount is set to 0.5Cp (instead of 0.4Cp), leaving a 25% margin to offset the -20% process deviation of the compensation capacitor; Monte Carlo Simulation Verification: Through 2000 random samplings (±20% capacitance error), the minimum number of bits required (N = 11 bits can ensure an error < 0.1% with a 99.7% confidence level) is determined, while only 9 samplings are needed to achieve an error < 0.1% in the case of an ideal compensation capacitor. Exemplarily, Figure 5 It is a graph showing the relationship between the number of bits of the mismatch compensation capacitor and the relative error.

[0114] The circuit-level simulation verification is as follows:

[0115] In cadence, the ideal values of Cp and Cn are selected as 10u, the actual value of Cn is 12u, and the actual value of Cp is 8u. Cp is scanned in a binary search decreasing manner from 8u to 12u. It can be seen that in the ideal case, the CMRR of IA at 1HZ is -228db. When Cp is binary-compensated from 8u to nearly 12u (with an error of 0.1%) through 9 bits, the CMRR is improved from -37.9db to -91.9db, basically meeting the design requirements. At this time, Avdm is 46db. Exemplarily, Figure 6 It is a graph showing the relationship between the off-chip capacitor mismatch error and the CMRR.

[0116] In cadence, the ideal values of Cp and Cn are selected as 10u, the actual value of Cn is 12u, and the actual value of Cp is 8u. Cp is scanned in a binary search decreasing manner from 8u to 12u. It can be seen that in the ideal case, the PSRR of IA at 1HZ is -220db. When Cp is binary-compensated from 8u to nearly 12u (with an error of 0.13%) through 9 bits, the PSRR is improved from -38db to -92db, basically meeting the design requirements. At this time, Avdm is 46db. Exemplarily, Figure 7 It is a graph showing the relationship between the off-chip capacitor mismatch error and the PSRR.

[0117] Referring to Figure 8 , the embodiment of the present application also provides a system for calibrating off-chip capacitor mismatch of an analog front end based on digital front-end, which can implement the method for calibrating off-chip capacitor mismatch of an analog front end based on digital front-end as described above. The system includes:

[0118] An initialization module, configured to connect a first capacitor and a second capacitor to the non-inverting input terminal and the inverting input terminal of the analog front end respectively;

[0119] A voltage calculation module, configured to short-circuit the non-inverting input terminal and the inverting input terminal to the common-mode voltage, and then calculate the mismatch error voltage;

[0120] A voltage comparison module, configured to compare the magnitudes of the common-mode voltage and the mismatch error voltage by using a comparator, so as to compare the capacitance values of the first capacitor and the second capacitor;

[0121] A capacitance compensation module, configured to connect each capacitor in the capacitor array in parallel to the capacitor with the smaller capacitance value among the first capacitor and the second capacitor one by one from the largest to the smallest capacitance value until the compensation capacitance meets the target compensation amount; wherein, the compensation capacitance is the capacitor in the capacitor array that is connected in parallel to the capacitor with the smaller capacitance value among the first capacitor and the second capacitor.

[0122] It can be understood that the content in the above method embodiments is applicable to the system embodiments of the present application. The functions specifically implemented in the system embodiments of the present application are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0123] An embodiment of the present application further provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the method of the embodiment of the present application is implemented. The electronic device can be any intelligent terminal including a tablet computer, a vehicle-mounted computer, etc.

[0124] It can be understood that the content in the above method embodiments is applicable to the device embodiments of the present application. The functions specifically implemented in the device embodiments of the present application are the same as those of the method of the present application, and the beneficial effects achieved are also the same as those achieved by the method of the present application.

[0125] Please refer to Figure 9 , Figure 9 which schematically shows the hardware structure of an electronic device according to another embodiment. The electronic device includes:

[0126] A processor 901, which can be implemented in a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, etc., and is configured to execute relevant programs to implement the technical solutions provided by the embodiments of the present application;

[0127] The memory 902 can be implemented in the form of a read only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM), etc. The memory 902 can store an operating system and other application programs. When implementing the technical solutions provided in the embodiments of this specification through software or firmware, the relevant program codes are stored in the memory 902 and are called by the processor 901 to execute the methods of the embodiments of this application;

[0128] The input / output interface 903 is used to implement information input and output;

[0129] The communication interface 904 is used to implement communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or through wireless means (such as mobile network, WIFI, Bluetooth, etc.);

[0130] The bus 905 transmits information between the various components of the device (such as the processor 901, the memory 902, the input / output interface 903, and the communication interface 904);

[0131] Among them, the processor 901, the memory 902, the input / output interface 903, and the communication interface 904 achieve communication connections with each other inside the device through the bus 905.

[0132] The embodiments of this application also provide a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the methods of this application are implemented.

[0133] It can be understood that the content in the above method embodiments is applicable to the embodiments of this storage medium. The functions specifically implemented by the embodiments of this storage medium are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those of the above method embodiments.

[0134] As a non-transitory computer-readable storage medium, the memory can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory can include high-speed random access memory, and can also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory optionally includes a memory remotely provided relative to the processor, and these remote memories can be connected to the processor through a network. Examples of the above networks include but are not limited to the Internet, enterprise intranets, local area networks, mobile communication networks, and combinations thereof.

[0135] The embodiments described in the embodiments of this application are for more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will know that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are equally applicable to similar technical problems.

[0136] Those skilled in the art can understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than those shown in the figures, or combine certain steps, or different steps.

[0137] The system embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separated, that is, they may be located in one place, or may be distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0138] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, and their appropriate combinations.

[0139] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of this application and the above drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of this application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules does not necessarily have to be limited to those steps or modules clearly listed, but may include other steps or modules that are not clearly listed or are inherent to these processes, methods, products, or devices.

[0140] It should be understood that in this application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects and indicates that there can be three relationships. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist at the same time. Here, A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one (one)" or a similar expression below refers to any combination of these items, including any combination of single items (one) or plural items (ones). For example, at least one (one) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0141] In several embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the above-mentioned module division is only a logical function division. In actual implementation, there can be other division methods. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of systems or modules can be in electrical, mechanical, or other forms.

[0142] The modules described above as separate components may or may not be physically separated. The components shown as modules may or may not be physical modules, that is, they can be located in one place or distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0143] In addition, the functional modules in each embodiment of this application can be integrated into a processing module, or each module can exist physically alone, or two or more modules can be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software functional modules.

[0144] When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes: various media that can store programs, such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0145] The preferred embodiments of the embodiments of this application have been described above with reference to the accompanying drawings. This does not limit the scope of the rights of the embodiments of this application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of this application shall fall within the scope of the rights of the embodiments of this application.

Claims

1. A method for calibrating analog front-end off-chip capacitor mismatch based on a digital front end, characterized in that: The method comprises the following steps: Connecting the first capacitor and the second capacitor to the non-inverting input terminal and the inverting input terminal of the analog front end respectively; Short-circuiting the in-phase input terminal and the inverting input terminal to a common mode voltage, thereby calculating a mismatch error voltage; Comparing the common mode voltage with the mismatch error voltage using a comparator to compare the capacitance of the first capacitor with the capacitance of the second capacitor; The capacitors in the capacitor array are connected in parallel to the first capacitor and the second capacitor with the smaller capacitance one by one in descending order of capacitance until the compensation capacitor meets the target compensation amount; wherein the compensation capacitor is the capacitor in the capacitor array connected in parallel to the first capacitor and the second capacitor with the smaller capacitance one.

2. The method for calibrating analog front-end off-chip capacitance mismatch based on digital front-end according to claim 1, characterized in that: The method of connecting the first capacitor and the second capacitor to the in-phase input terminal and the inverting input terminal of the analog front end respectively comprises the following steps: The upper plate of the first capacitor and the upper plate of the second capacitor are respectively connected to the in-phase input terminal and the inverting input terminal of the analog front end, and the lower plate of the first capacitor and the lower plate of the second capacitor are grounded, thereby initializing the charges of the first capacitor and the second capacitor to zero.

3. The method for calibrating analog front-end off-chip capacitance mismatch based on digital front-end according to claim 1, characterized in that: The calculation to obtain the mismatch error voltage includes the following steps: Calculating the mismatch error voltage according to the charge conservation principle; The expression of the charge conservation principle is: Q=C n *V cm =C p *V error ; Where Q represents the charge; C n is the first capacitor, C p is the second capacitor, V cm is the common mode voltage, V error is the mismatch error voltage; Then the calculation formula of the mismatch error voltage is:

4. The method for calibrating analog front-end off-chip capacitance mismatch based on digital front-end according to claim 1, characterized in that: The method of comparing the common mode voltage with the mismatch error voltage by using a comparator to compare the capacitance of the first capacitor with the capacitance of the second capacitor includes the following steps: Comparing the common mode voltage with the mismatch error voltage using a comparator; If the common mode voltage is greater than the mismatch error voltage, the comparator is used to output a first logic signal to indicate that the capacitance of the first capacitor is less than the capacitance of the second capacitor; If the common mode voltage is less than the mismatch error voltage, the comparator is used to output a second logic signal to indicate that the capacitance of the first capacitor is greater than the capacitance of the second capacitor.

5. The method for calibrating analog front-end off-chip capacitance mismatch based on digital front-end according to claim 1, characterized in that: The method of connecting the capacitors in the capacitor array in parallel to the first capacitor and the second capacitor with the smaller capacitance one by one according to the capacitance from large to small, until the compensation capacitance meets the target compensation amount, comprises the following steps: The first capacitor and the second capacitor with a smaller capacitance are used as a small capacitor, and the other capacitor is used as a large capacitor, and the capacitors in the capacitor array are connected in parallel to the small capacitor one by one according to the capacitance from large to small, and the capacitance of the small capacitor and the large capacitor after the compensation capacitor is connected in parallel is determined in turn; If the capacitance of the small capacitor after the compensation capacitor is connected in parallel is still smaller than the capacitance of the large capacitor, then the capacitor with the next smaller capacitance in the capacitor array is connected in parallel to the small capacitor in descending order of capacitance, until the capacitor with the smallest capacitance in the capacitor array is connected in parallel to the small capacitor or the compensation capacitor meets the target compensation amount; If the capacitance of the small capacitor after being connected in parallel with the compensation capacitor is greater than the capacitance of the large capacitor, the parallel connection between the compensation capacitor and the small capacitor is disconnected, and then the next capacitor with a smaller capacitance in the capacitor array is connected in parallel to the small capacitor in descending order of capacitance, until the capacitor with the smallest capacitance in the capacitor array is connected in parallel to the small capacitor or the compensation capacitor meets the target compensation amount.

6. The method for calibrating analog front-end off-chip capacitance mismatch based on digital front-end according to claim 5, characterized in that: After the compensation is completed, the first capacitor, the second capacitor and the compensation capacitor satisfy the following relationship: Among them, C n is the first capacitor, C p is the second capacitor; is the sum of the compensation capacitance, C k represents a single compensation capacitor, and N represents the total number of capacitors connected in parallel to the small capacitor.

7. The method for calibrating analog front-end off-chip capacitance mismatch based on digital front-end according to any one of claims 1 to 6, characterized in that: The method of connecting the capacitors in the capacitor array in parallel to the first capacitor and the second capacitor with the smaller capacitance one by one according to the capacitance from large to small, until the compensation capacitance meets the target compensation amount, comprises the following steps: The capacitors in the capacitor array are connected in parallel to the first capacitor and the second capacitor with the smaller capacitance one by one in descending capacitance, until the compensation capacitor has half the capacitance of the second capacitor; wherein half the capacitance of the second capacitor is used as the target compensation amount.

8. A system for calibrating analog front-end off-chip capacitor mismatch based on a digital front end, characterized in that: The system comprises: An initialization module, used to connect the first capacitor and the second capacitor to the same-phase input terminal and the opposite-phase input terminal of the analog front end respectively; A voltage calculation module, used for short-circuiting the in-phase input terminal and the inverting input terminal to a common mode voltage, and then calculating a mismatch error voltage; A voltage comparison module, used for comparing the voltage magnitudes of the common mode voltage and the mismatch error voltage by using a comparator, so as to compare the capacitance magnitudes of the first capacitor and the second capacitor; The capacitor compensation module is used to connect the capacitors in the capacitor array in parallel to the first capacitor and the second capacitor with the smaller capacitance one by one according to the capacitance from large to small, until the compensation capacitor meets the target compensation amount; wherein the compensation capacitor is the capacitor in the capacitor array connected in parallel to the first capacitor and the second capacitor with the smaller capacitance.

9. An electronic device, characterized in that: The electronic device comprises a memory and a processor, the memory stores a computer program, and the processor implements the method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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