Oversampling ADC switched capacitor circuit with starting charge clearing function

Abstract

An oversampling ADC switched capacitor circuit with a starting charge clearing function relates to the technical field of integrated circuits, and is mainly structurally characterized in that a second output end of an operational amplifier OP is connected with a first input end of the operational amplifier OP through a capacitor C7, a first output end of the operational amplifier OP is connected with a second input end of the operational amplifier OP through a capacitor C8, and capacitors C1, C2, C3 and C4 on four input branches are respectively connected with switches S1, S2, S3 and S4 in parallel; one end of the capacitor C7 is connected with common-mode voltage through a switch S5, and the other end of the capacitor C7 is grounded through a switch S ' / 2f; one end of the capacitor C8 is connected with common-mode voltage through a switch S6, and the other end of the capacitor C8 is grounded through a switch S / 2f; and a switch S / 2s is connected between the other end of the capacitor C7 and the other end of the capacitor C8. According to the invention, on the basis of a traditional switched capacitor circuit, an additional switch tube and a digital circuit are added to complete a charge zero clearing process, so that the power-on initialization time of a chip is shortened, the time of an unstable stage is reduced, and the circuit stability is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly relates to an oversampling ADC switched-capacitor circuit with a startup charge clearing function. Background Art

[0002] An analog-to-digital converter (ADC) is an important component of various electronic devices and is a bridge for analog-digital interaction. According to different sampling methods, it can be divided into a Nyquist analog-to-digital converter and an oversampling converter. The Nyquist analog-to-digital converter includes a successive approximation analog-to-digital converter (SAR ADC), a flash analog-to-digital converter (Flash ADC), and a pipelined analog-to-digital converter (Pipelined ADC). The ADCs of these structures all adopt a linear coding method, and the accuracy will be limited by the circuit design difficulty and temperature process. The oversampling analog-to-digital converter (Sigma delta ADC) adopts a non-linear coding method and uses oversampling far higher than the Nyquist frequency, so relatively high accuracy can be obtained.

[0003] The structure of the Sigma delta ADC includes an analog part and a digital part. The analog part includes an anti-aliasing filter and a modulator, and the digital part includes a digital low-pass filter and a decimation module. Among them, the modulator is the core part of the Sigma Delta ADC, which realizes the integral summation function of the signal, completes the sampling and quantization of the input signal. The switched-capacitor circuit is a commonly used circuit to realize the function of the modulator. A traditional switched-capacitor circuit structure is as Figure 1 shown. When the traditional switched-capacitor circuit is powered on and working, due to incomplete charge discharge in the capacitor, the sampling values are unstable in the first dozens of cycles of oversampling, resulting in a long startup time.

[0004] Some existing related patents, such as CN202210014341.9 "Switched-capacitor circuit and switch control method for differential input SAR ADC" and CN201610454408.5 "Integrator applied to a sigma-delta analog-to-digital conversion circuit with DAC function", do not consider solving the problem of capacitor charge discharge in the power-on startup stage. Summary of the Invention

[0005] The purpose of the present invention is to optimize the structure of the switched-capacitor circuit in the traditional oversampling ADC, accelerate the initialization time of chip power-on, and reduce the time of the unstable stage.

[0006] To achieve the above object, the technical solution adopted by the present invention is as follows: An oversampling ADC switched-capacitor circuit with a startup charge clearing function, including an operational amplifier OP. The first input circuit of the operational amplifier OP includes a capacitor C2 branch and a capacitor C1 branch, and the second input circuit includes a capacitor C3 branch and a capacitor C4 branch. The second output terminal of the operational amplifier OP is connected to its first input terminal through a capacitor C7, and the first output terminal is connected to its second input terminal through a capacitor C8;

[0007] A switch S1 is connected in parallel with the capacitor C1 in the capacitor C1 branch, a switch S2 is connected in parallel with the capacitor C2 in the capacitor C2 branch, a switch S3 is connected in parallel with the capacitor C3 in the capacitor C3 branch, and a switch S4 is connected in parallel with the capacitor C4 in the capacitor C4 branch;

[0008] A switch S1' is also connected in series between one end of the capacitor C7 and the first input terminal of the operational amplifier OP, and a switch S3' is also connected in series between the other end of the capacitor C7 and the second output terminal of the operational amplifier OP;

[0009] One end of the capacitor C7 is connected to the common-mode voltage VCOM through a switch S5, and the other end of the capacitor C7 is grounded through a switch S' / 2f;

[0010] A switch S2' is also connected in series between one end of the capacitor C8 and the second input terminal of the operational amplifier OP, and a switch S4' is also connected in series between the other end of the capacitor C8 and the first output terminal of the operational amplifier OP;

[0011] One end of the capacitor C8 is connected to the common-mode voltage VCOM through a switch S6, and the other end of the capacitor C8 is grounded through a switch S / 2f;

[0012] A switch S / 2s is also connected between the other end of the capacitor C7 and the other end of the capacitor C8.

[0013] Further, the first input terminal of the operational amplifier OP is the non-inverting input terminal, the second input terminal is the inverting input terminal, the first output terminal is the non-inverting output terminal OUTP, and the second output terminal is the inverting output terminal OUTN.

[0014] Furthermore, in the capacitor C2 branch, one end of the switch Φ1 serves as the non-inverting input terminal INP of the switched-capacitor circuit, and the other end is connected to one end of the switch Φ1' and the capacitor C2; the other end of the switch Φ1' is connected to the common-mode voltage VCOM, the other end of the capacitor C2 is connected to one end of the switch Φ6', the other end of the switch Φ6' is connected to one end of the switch Φ9' and the non-inverting input terminal of the operational amplifier OP; the other end of the switch Φ9' is connected to one end of the switch Φ5 and the capacitor C5, the other end of the switch Φ5 is connected to the common-mode voltage VCOM, and the other end of the capacitor C5 is grounded;

[0015] In the capacitor C1 branch, the positive reference voltage VREFP is connected to node A through switch Δ1, and the negative reference voltage VREFN is connected to node A through switch Δ1'. Node A is simultaneously connected to switch Φ3' and one end of capacitor C1; the other end of switch Φ3' is connected to the common-mode voltage VCOM, and the other end of capacitor C1 is connected to the non-inverting input terminal of operational amplifier OP through switch Φ5'.

[0016] In the capacitor C3 branch, one end of switch Φ2 serves as the inverting input terminal INN of the switched-capacitor circuit, and the other end is connected to switch Φ2' and one end of capacitor C3; the other end of switch Φ2' is connected to the common-mode voltage VCOM, the other end of capacitor C3 is connected to one end of switch Φ7', and the other end of switch Φ7' is connected to one end of switch Φ 10 ' and the inverting input terminal of operational amplifier OP; the other end of switch Φ 10 ' is connected to one end of switch Φ6 and one end of capacitor C6, the other end of switch Φ6 is connected to the common-mode voltage VCOM, and the other end of capacitor C6 is connected to the ground potential;

[0017] In the capacitor C4 branch, the negative reference voltage VREFN is connected to node B through switch Δ2, and the positive reference voltage VREFP is connected to node B through switch Δ2'. Node B is simultaneously connected to switch Φ4' and one end of capacitor C4; the other end of switch Φ4' is connected to the common-mode voltage VCOM, and the other end of capacitor C4 is connected to the inverting input terminal of operational amplifier OP through switch Φ8'.

[0018] The other end of capacitor C1 is connected to the other end of capacitor C4 through switch Φ3;

[0019] The other end of capacitor C2 is connected to the other end of capacitor C3 through switch Φ4.

[0020] Furthermore, switches Δ1 and Δ2 are controlled by clock Δ, switches Δ1' and Δ2' are controlled by clock Δ', switches Φ1, Φ2, Φ3, Φ4, Φ5, Φ6 are controlled by clock Φ, switches Φ1', Φ2', Φ3', Φ4', Φ5', Φ6', Φ7', Φ8', Φ9' and Φ 10 ' are controlled by clock Φ', switches S1, S2, S3, S4, S5 and S6 are controlled by clock S, switches S1', S2', S3' and S4' are controlled by clock S', switch S / 2f is controlled by clock s / 2f, switch S' / 2f is controlled by clock s' / 2f, and switch S / 2s is controlled by clock s / 2s.

[0021] Moreover, clock S and clock S' are opposite to each other, the pulse width of the high level of clock s / 2f is half of the pulse width of the high level of clock S, clock s' / 2f and clock s / 2f are opposite to each other, and clock s / 2s is a delay of clock s / 2f.

[0022] The beneficial effects of the present invention are as follows:

[0023] Aiming at the problem of unstable system startup caused by incomplete capacitor charge clearing in the switched-capacitor circuit, the present invention adds additional switching transistors and digital circuits to the traditional switched-capacitor circuit as shown in Figure 1 to complete the charge zeroing process, which accelerates the chip power-on initialization time, reduces the time of the unstable stage, and improves the circuit stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 FIG. is a schematic diagram of a traditional switched-capacitor circuit structure;

[0025] Figure 2 FIG. is a schematic diagram of the circuit structure of an embodiment of the present invention;

[0026] Figure 3 FIG. is a schematic diagram of the charge zeroing clock signal of an embodiment of the present invention;

[0027] Figure 4 FIG. is a schematic diagram of the comparison of system startup using the traditional structure and the structure of the present invention;

[0028] Figure 5 FIG. is a schematic diagram of the subsequent digital system using the charge clearing technology for startup of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0029] In order to more clearly understand the above objects, features and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] Figure 2 A specific embodiment of the present invention is shown as follows. An oversampling ADC switched-capacitor circuit with a startup charge clearing function includes an operational amplifier OP. The first input circuit of the operational amplifier OP includes a capacitor C2 branch and a capacitor C1 branch, and the second input circuit includes a capacitor C3 branch and a capacitor C4 branch. The second output terminal of the operational amplifier OP is connected to its first input terminal through a capacitor C7, and the first output terminal is connected to its second input terminal through a capacitor C8;

[0031] A switch S1 is connected in parallel with the capacitor C1 in the capacitor C1 branch, a switch S2 is connected in parallel with the capacitor C2 in the capacitor C2 branch, a switch S3 is connected in parallel with the capacitor C3 in the capacitor C3 branch, and a switch S4 is connected in parallel with the capacitor C4 in the capacitor C4 branch;

[0032] A switch S1' is also connected in series between one end of the capacitor C7 and the first input terminal of the operational amplifier OP, and a switch S3' is also connected in series between the other end of the capacitor C7 and the second output terminal of the operational amplifier OP;

[0033] One end of the capacitor C7 is connected to the common-mode voltage VCOM through the switch S5, and the other end of the capacitor C7 is grounded through the switch S′ / 2f;

[0034] A switch S2′ is also connected in series between one end of the capacitor C8 and the second input terminal of the operational amplifier OP, and a switch S4′ is also connected in series between the other end of the capacitor C8 and the first output terminal of the operational amplifier OP;

[0035] One end of the capacitor C8 is connected to the common-mode voltage VCOM through the switch S6, and the other end of the capacitor C8 is grounded through the switch S / 2f;

[0036] A switch S / 2s is also connected between the other end of the capacitor C7 and the other end of the capacitor C8.

[0037] The first input terminal of the operational amplifier OP is the non-inverting input terminal, the second input terminal is the inverting input terminal, the first output terminal is the non-inverting output terminal OUTP, and the second output terminal is the inverting output terminal OUTN.

[0038] In the capacitor C2 branch, one end of the switch Φ1 serves as the non-inverting input terminal INP of the switched-capacitor circuit, and the other end is connected to one end of the switch Φ1′ and the capacitor C2; the other end of the switch Φ1′ is connected to the common-mode voltage VCOM, the other end of the capacitor C2 is connected to one end of the switch Φ6′, the other end of the switch Φ6′ is connected to one end of the switch Φ9′ and the non-inverting input terminal of the operational amplifier OP; the other end of the switch Φ9′ is connected to one end of the switch Φ5 and the capacitor C5, the other end of the switch Φ5 is connected to the common-mode voltage VCOM, and the other end of the capacitor C5 is grounded;

[0039] In the capacitor C1 branch, the positive reference voltage VREFP is connected to the node A through the switch △1, the negative reference voltage VREFN is connected to the node A through the switch △1′, and the node A is simultaneously connected to one end of the switch Φ3′ and the capacitor C1; the other end of the switch Φ3′ is connected to the common-mode voltage VCOM, and the other end of the capacitor C1 is connected to the non-inverting input terminal of the operational amplifier OP through the switch Φ5′;

[0040] In the capacitor C3 branch, one end of the switch Φ2 serves as the inverting input terminal INN of the switched-capacitor circuit, and the other end is connected to one end of the switch Φ2′ and the capacitor C3; the other end of the switch Φ2′ is connected to the common-mode voltage VCOM, the other end of the capacitor C3 is connected to one end of the switch Φ7′, and the other end of the switch Φ7′ is connected to one end of the switch Φ 10 ′ and the inverting input terminal of the operational amplifier OP; the other end of the switch Φ 10 ′ is connected to one end of the switch Φ6 and the capacitor C6, the other end of the switch Φ6 is connected to the common-mode voltage VCOM, and the other end of the capacitor C6 is grounded;

[0041] In the branch of capacitor C4, the negative reference voltage VREFN is connected to node B through switch Δ2, and the positive reference voltage VREFP is connected to node B through switch Δ2'. Node B is simultaneously connected to one end of switch Φ4' and capacitor C4; the other end of switch Φ4' is connected to the common-mode voltage VCOM, and the other end of capacitor C4 is connected to the inverting input terminal of operational amplifier OP through switch Φ8'.

[0042] The other end of capacitor C1 is connected to the other end of capacitor C4 through switch Φ3.

[0043] The other end of capacitor C2 is connected to the other end of capacitor C3 through switch Φ4.

[0044] Switches Δ1 and Δ2 are controlled by clock Δ, switches Δ1' and Δ2' are controlled by clock Δ', switches Φ1, Φ2, Φ3, Φ4, Φ5, Φ6 are controlled by clock Φ, switches Φ1', Φ2', Φ3', Φ4', Φ5', Φ6', Φ7', Φ8', Φ9' and Φ 10 ' are controlled by clock Φ', switches S1, S2, S3, S4, S5 and S6 are controlled by clock S, switches S1', S2', S3' and S4' are controlled by clock S', switch S / 2f is controlled by clock s / 2f, switch S' / 2f is controlled by clock s' / 2f, and switch S / 2s is controlled by clock s / 2s.

[0045] Clock S and clock S' are reverse to each other. The pulse width of the high level of clock s / 2f is half of the pulse width of the high level of clock S. Clock s' / 2f and clock s / 2f are reverse to each other. Clock s / 2s is a delay of clock s / 2f.

[0046] The charge clearing clock signal of this embodiment is as Figure 3 shown. The clock signal is generated by a pulse signal generating circuit of the prior art and will not be described in detail here.

[0047] The charge clearing clock of the switched-capacitor circuit is generated by a pulse signal generating circuit, where the S and S' pulses are the main pulses. In order to ensure the stable charge clearing process of the chip, in the present invention, three additional sub-pulses, s / 2f, s / 2s, and s' / 2f, are added to direct the residual charge in the circuit at the start of the chip, so as to ensure that the charge can be completely cleared and thus improve the circuit stability.

[0048] When the charge clearing function of the circuit in this embodiment is in progress, switches S1, S2, S3, S4 are closed, and switches S1', S2', S3', S4' are open; when the switched-capacitor circuit is operating normally, switches S1, S2, S3, S4 are open, and switches S1', S2', S3', S4' are closed.

[0049] When the charge clearing function is in progress, s' / 2f and s / 2f serve as complementary pulses. That is, when s / 2f is at a high level, the switch S / 2f closes, and the capacitor C8 is connected to the ground potential GND. The charge on C8 near the OUTP terminal is cleared. At the same time, the capacitor C7 near the OUTN terminal is turned off; in the second half of the beat, s' / 2f becomes high, the switch S′ / 2f closes, the capacitor C7 is connected to the ground GND, and at the same time the clock s / 2s becomes high and the switch S / 2s closes. In this way, the capacitors C7 and C8 are connected near the output terminal of the operational amplifier OP, and the extra charge on the plates is balanced. At the same time, the plates of the capacitors C7 and C8 near the input terminal of the operational amplifier OP are always connected to the common-mode voltage VCOM during charge clearing. While ensuring sufficient discharge, a certain voltage bias is maintained, which is beneficial to the charge clearing operation of the corresponding plates. Clearing the two ends of the differential current separately in this way can avoid unnecessary power consumption losses caused by simultaneous activation and charge uncertainty caused by simultaneous switch overshoot. When the charge clearing function is completed, all the switches that played a role in charge clearing return to the off state. When the switched-capacitor circuit is working properly, they are not turned on again. The charge clearing function works only once after the chip is powered on. If clearing is required again, the chip needs to be powered on again.

[0050] The effects obtained by using the present invention are as Figure 4 shown. By comparison, it can be seen that for the traditional switched-capacitor circuit without using the structure of the present invention, there is a risk of instability in the sampling values in the first dozens of cycles of oversampling. Adding the clearing function of the present invention will significantly reduce the time of the unstable stage and effectively shorten the startup time.

[0051] The flow of the technology of the present invention during chip operation is as Figure 5 shown. During the actual operation of the chip involved in the present invention, after the power-on is completed, the power-on reset circuit sends a power-on reset signal POR to the pulse signal generation circuit to generate a clearing signal CLEAR. The CLEAR signal includes clock signals S, S′, s / 2f, s / 2s, and s′ / 2f. The CLEAR signal acts on the analog modulator (switched-capacitor circuit) to complete charge clearing. After charge clearing is completed, the analog modulator enters the normal working state.

Claims

1. An oversampling ADC switch capacitor circuit with a startup charge clearing function, comprising an operational amplifier OP, wherein a first input circuit of the operational amplifier OP comprises a capacitor C2 branch and a capacitor C1 branch, and a second input circuit comprises a capacitor C3 branch and a capacitor C4 branch, a second output terminal of the operational amplifier OP is connected to its first input terminal via a capacitor C7, and a first output terminal is connected to its second input terminal via a capacitor C8, wherein: Capacitor C1 is connected in parallel with switch S1, capacitor C2 is connected in parallel with switch S2, capacitor C3 is connected in parallel with switch S3, and capacitor C4 is connected in parallel with switch S4; A switch S1′ is connected in series between one end of the capacitor C7 and the first input end of the operational amplifier OP, and a switch S3′ is connected in series between the other end of the capacitor C7 and the second output end of the operational amplifier OP; One end of the capacitor C7 is connected to the common mode voltage VCOM through the switch S5, and the other end of the capacitor C7 is connected to the ground potential through the switch S′ / 2f; A switch S2′ is also connected in series between one end of the capacitor C8 and the second input end of the operational amplifier OP, and a switch S4′ is also connected in series between the other end of the capacitor C8 and the first output end of the operational amplifier OP; One end of capacitor C8 is connected to common mode voltage VCOM through switch S6, and the other end of capacitor C8 is connected to ground potential through switch S / 2f; A switch S / 2s is also connected between the other end of the capacitor C7 and the other end of the capacitor C8.

2. The oversampling ADC switched capacitor circuit with startup charge clearing function according to claim 1, characterized in that: The first input terminal of the operational amplifier OP is a non-inverting input terminal, the second input terminal is a non-inverting input terminal, the first output terminal is a non-inverting output terminal OUTP, and the second output terminal is a non-inverting output terminal OUTN.

3. The oversampling ADC switched capacitor circuit with startup charge clearing function according to claim 2, characterized in that: In the capacitor C2 branch, one end of the switch Φ1 serves as the same-direction input end INP of the switch capacitor circuit, and the other end is connected to the switch Φ1′ and one end of the capacitor C2; the other end of the switch Φ1′ is connected to the common-mode voltage VCOM, the other end of the capacitor C2 is connected to one end of the switch Φ6′, the other end of the switch Φ6′ is connected to one end of the switch Φ9′ and the same-direction input end of the operational amplifier OP; the other end of the switch Φ9′ is connected to one end of the switch Φ5 and one end of the capacitor C5, the other end of the switch Φ5 is connected to the common-mode voltage VCOM, and the other end of the capacitor C5 is connected to the ground potential; In the capacitor C1 branch, the positive reference voltage VREFP is connected to the node A through the switch △1, and the negative reference voltage VREFN is connected to the node A through the switch △1′, and the node A is connected to the switch Φ3′ and one end of the capacitor C1 at the same time; the other end of the switch Φ3′ is connected to the common mode voltage VCOM, and the other end of the capacitor C1 is connected to the non-inverting input end of the operational amplifier OP through the switch Φ5′; In the capacitor C3 branch, one end of the switch Φ2 serves as the inverting input terminal INN of the switch capacitor circuit, and the other end is connected to the switch Φ2′ and one end of the capacitor C3; the other end of the switch Φ2′ is connected to the common mode voltage VCOM, the other end of the capacitor C3 is connected to one end of the switch Φ7′, and the other end of the switch Φ7′ is connected to the switch Φ 10 ′ and the inverting input terminal of the operational amplifier OP; the switch Φ 10 The other end of ′ is connected to one end of the switch Φ6 and one end of the capacitor C6, the other end of the switch Φ6 is connected to the common mode voltage VCOM, and the other end of the capacitor C6 is connected to the ground potential; In the capacitor C4 branch, the negative reference voltage VREFN is connected to the node B through the switch △2, and the positive reference voltage VREFP is connected to the node B through the switch △2′, and the node B is connected to the switch Φ4′ and one end of the capacitor C4 at the same time; the other end of the switch Φ4′ is connected to the common mode voltage VCOM, and the other end of the capacitor C4 is connected to the inverting input end of the operational amplifier OP through the switch Φ8′; The other end of the capacitor C1 is connected to the other end of the capacitor C4 through a switch Φ3; The other end of the capacitor C2 is connected to the other end of the capacitor C3 via a switch Φ4.

4. The oversampling ADC switched capacitor circuit with startup charge clearing function according to claim 3, characterized in that: The switches △1 and △2 are controlled by a clock △, the switches △1′ and △2′ are controlled by a clock △′, the switches Φ1, Φ2, Φ3, Φ4, Φ5, Φ6 are controlled by a clock Φ, and the switches Φ1′, Φ2′, Φ3′, Φ4′, Φ5′, Φ6′, Φ7′, Φ8′, Φ9′ and Φ10′ are controlled by a clock Φ11. 10 ′ is controlled by clock Φ′, switches S1, S2, S3, S4, S5 and S6 are controlled by clock S, switches S1′, S2′, S3′ and S4′ are controlled by clock S′, switch S / 2f is controlled by clock s / 2f, switch S′ / 2f is controlled by clock s′ / 2f, and switch S / 2s is controlled by clock s / 2s.

5. The oversampling ADC switched capacitor circuit with startup charge clearing function according to claim 4, characterized in that: The clock S and clock S' are inverse to each other, the high level pulse width of clock s / 2f is half of the high level pulse width of clock S, clock s' / 2f and clock s / 2f are inverse to each other, and clock s / 2s is a delay of clock s / 2f.

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