Digital intermediate frequency band-pass sampling type satellite-borne high-speed launching device

Abstract

The invention relates to a digital intermediate frequency band-pass sampling type satellite-borne high-speed launching device which comprises an on-satellite unit and a ground unit. The on-satellite unit comprises a parameter secondary unloading module, a digital pre-distortion actuator module, a pre-emphasis digital filter, a digital up-conversion module, a radio frequency sampling digital-to-analog converter, a radio frequency selection filtering and amplifying module and an antenna which are connected in sequence; and the ground unit is used for generating a pre-distortion parameter according to the target mirror image signal output by the radio frequency selection filtering and amplifying module and transmitting the pre-distortion parameter to the parameter secondary unloading module. The up-conversion process from intermediate frequency to radio frequency is realized by using the non-ideal characteristic of the radio frequency sampling digital-to-analog converter, the process of outputting the radio frequency modulation signal does not need an external mixer, a local oscillator radio frequency link and a radio frequency module are simpler, and the cost is lower. The digital pre-distortion actuator module, the pre-emphasis digital filter and the digital up-conversion module all adopt high-speed parallel look-up table structures, so that hardware multiplier resources are saved, and the high-speed modulation circuit is suitable for high-speed modulation scenes.

Description

Technical Field

[0001] This application relates to the field of satellite high-speed data transmission, and specifically, to a digital intermediate-frequency band-pass sampling type spaceborne high-speed transmitting device. Background Art

[0002] In recent years, spaceborne transmitting devices applied to microsatellites have started to develop towards the direction of high speed, integration, and generalization. The implementation approaches of traditional spaceborne transmitting devices mainly include analog I / Q modulation mode and superheterodyne mode. Among them, the spaceborne transmitting device of the analog I / Q modulation mode uses analog I / Q modulation devices to directly up-convert the input I and Q baseband signals from the baseband to the radio frequency output. This technical approach is relatively dependent on the hardware platform. After the analog radio frequency link is determined, it will be difficult to change the system function mode. The spaceborne transmitting device of the superheterodyne mode first up-converts the baseband I and Q signals from the baseband to the intermediate frequency through up-conversion, and then the last stage is up-converted from the intermediate frequency to the radio frequency through an analog mixing circuit. This technical approach still requires an analog mixer and a local oscillator circuit, and the radio frequency hardware structure is relatively complex. With the development of software radio technology, the sampling frequency of digital-to-analog conversion devices has been continuously improved, and the radio transmitting architecture of the intermediate-frequency band-pass sampling mode has become the focus of attention in the field of satellite high-speed transmitting technology. The radio transmitting structure of the intermediate-frequency band-pass sampling mode saves the up-conversion process from the intermediate frequency to the radio frequency, and the radio frequency module circuit is simpler.

[0003] However, when implementing a spaceborne high-speed transmitting device by using the intermediate-frequency band-pass sampling method, the following problems exist in practical applications: The bit error performance of satellite communication will be affected by both the SINC function fading of the DAC device and the nonlinear distortion of the power amplification circuit. When the input of the on-board radio frequency front end is an ultra-wideband and high-order modulation signal, the influence is particularly obvious; and when the operating frequency band or rate mode changes, the effect of the non-ideal characteristics of the satellite on the on-board modulation signal will change accordingly. Summary of the Invention

[0004] In order to overcome at least one deficiency in the prior art, this application provides a digital intermediate-frequency band-pass sampling type spaceborne high-speed transmitting device.

[0005] The digital intermediate-frequency band-pass sampling type spaceborne high-speed transmitting device of this application includes: an on-board unit and a ground unit; the on-board unit includes a parameter secondary storage module, a digital pre-distortion actuator module, a pre-emphasis digital filter, a digital up-conversion module, a radio frequency sampling digital-to-analog converter, a radio frequency selection filtering and amplification module, and an antenna that are connected in sequence;

[0006] The digital pre-distortion actuator module is used to receive parallel M-channel original digital baseband signals, and perform nonlinear distortion compensation based on pre-distortion parameters to obtain parallel M-channel compensated digital baseband signals;

[0007] The pre-emphasis digital filter is used to perform pre-emphasis compensation on the digital baseband signals after parallel M-channel compensation, and obtain the digital baseband signals after parallel M-channel pre-emphasis compensation;

[0008] The digital up-conversion module is used to perform digital up-conversion on the digital baseband signals after parallel M-channel pre-emphasis compensation, and obtain the parallel M-channel intermediate-frequency digital signals;

[0009] The radio frequency sampling digital-to-analog converter is used to perform digital-to-analog conversion on the parallel M-channel intermediate-frequency digital signals to generate a multi-image signal;

[0010] The radio frequency selection filtering and amplification module performs selection filtering and power amplification on the multi-image signal, and suppresses harmonics and clutter to obtain the target image signal;

[0011] The antenna is used to radiate the target image signal to the ground station in the form of electromagnetic waves;

[0012] The ground unit is used to generate pre-distortion parameters according to the target image signal output by the radio frequency selection filtering and amplification module, encapsulate the pre-distortion parameters into a parameter upload data frame, and transmit the parameter upload data frame to the parameter secondary storage module through the satellite-ground TT&C link;

[0013] The parameter secondary storage module is used to parse the pre-distortion parameters from the parameter upload data frame and transfer the pre-distortion parameters to the non-volatile memory of the on-board unit; after the entire satellite is powered off and then powered on again, read the pre-distortion parameters in the non-volatile memory according to the satellite-wide command, and input the pre-distortion parameters into the digital pre-distortion actuator module.

[0014] In one embodiment, the ground unit includes a ground acquisition and reception module, a data preprocessing module, a model coefficient extraction module, and a parameter data frame upload module connected in sequence; the parameter data frame upload module is connected to the parameter secondary storage module;

[0015] The ground acquisition and reception module is used to perform radio frequency direct sampling on the target image signal to obtain the observed digital baseband signal;

[0016] The data preprocessing module is used to perform time-domain correlation alignment processing on the observed digital baseband signal and the original digital baseband signal, and output the aligned observed digital baseband signal and the original digital baseband signal;

[0017] The model coefficient extraction module is used to generate pre-distortion parameters based on the aligned observed digital baseband signal and the original digital baseband signal, based on the memory polynomial model with a memory depth of 3 and an order of 9;

[0018] The parameter data frame upload module is used to encapsulate the pre-distortion parameters into a parameter upload data frame, and transmit the parameter upload data frame to the parameter secondary storage module through the satellite-ground TT&C link.

[0019] In one embodiment, the on-board unit further includes a sampling clock generator, which is connected to the RF sampling digital-to-analog converter and the ground acquisition and receiving module of the ground unit, and is used to provide a sampling clock signal for the RF sampling digital-to-analog converter and the ground acquisition and receiving module.

[0020] In one embodiment, the digital predistortion actuator module includes M branches, and each branch processes one path of the original digital baseband signal and outputs one path of the compensated digital baseband signal.

[0021] The branch includes a CORDIC module, a first delay unit, a second delay unit, a third delay unit, a fourth delay unit, a fifth delay unit, a sixth delay unit, a seventh delay unit, an eighth delay unit, a ninth delay unit, a tenth delay unit, a first RAM, a second RAM, a third RAM, a fourth RAM, a first complex multiplier, a second complex multiplier, a third complex multiplier, a fourth complex multiplier; a first adder, a second adder, and a third adder.

[0022] For the l-th branch, the input of the CORDIC module is the original baseband signal (x i (l), x q (l)), where x i (l) and x q (l) are respectively the two components of the original baseband signal. The CORDIC module is used to calculate the modulus values of x i (l) and x q (l). One output port of the CORDIC module is connected to the read address signal port of the first RAM, and the other is connected to the second delay unit.

[0023] The first delay unit, the second delay unit, the third delay unit, the fourth delay unit, the fifth delay unit, and the sixth delay unit are respectively used to delay the input data by one clock. The input of the first delay unit is the original baseband signal (x i (l), x q(l)), the output of the first delay unit is connected to the eighth delay unit on the one hand and the third delay unit on the other hand; the input of the third delay unit is connected to the output of the first delay unit, and the output of the third delay unit is connected to the ninth delay unit on the one hand and the fifth delay unit on the other hand; the input of the fifth delay unit is connected to the output of the third delay unit, and the output of the fifth delay unit is connected to the tenth delay unit on the one hand; the input of the second delay unit is connected to the output of the CORDIC module, and the output of the second delay unit is connected to the read address signal port of the second RAM on the one hand and the fourth delay unit on the other hand; the input of the fourth delay unit is connected to the output of the second delay unit, and the output of the fourth delay unit is connected to the read address signal port of the third RAM on the one hand and the sixth delay unit on the other hand; the input of the sixth delay unit is connected to the output of the fourth delay unit, and the output of the sixth delay unit is connected to the read address signal port of the fourth RAM;

[0024] The first RAM, the second RAM, the third RAM, and the fourth RAM are used to store pre-distortion parameters; the read address signal port of the first RAM is connected to the CORDIC module, the read data signal port is connected to the first complex multiplier, and the write address signal port and the write data signal port are connected to the parameter secondary transfer module of the on-board unit; the read address signal port of the second RAM is connected to the second delay unit, the read data signal port is connected to the second complex multiplier, and the write address signal port and the write data signal port are connected to the parameter secondary transfer module of the on-board unit; the read address signal port of the third RAM is connected to the fourth delay unit, the read data signal port is connected to the third complex multiplier, and the write address signal port and the write data signal port are connected to the parameter secondary transfer module of the on-board unit; the read address signal port of the fourth RAM is connected to the sixth delay unit, the read data signal port is connected to the fourth complex multiplier, and the write address signal port and the write data signal port are connected to the parameter secondary transfer module of the on-board unit;

[0025] The seventh delay unit, the eighth delay unit, the ninth delay unit, and the tenth delay unit are used to delay the input data by several clock cycles to align the input data of the connected complex multipliers in time; the input signal of the seventh delay unit is the original baseband signal (x i (l), x q (l)), and the output is connected to the first complex multiplier; the input of the eighth delay unit is connected to the first delay unit, and the output is connected to the second complex multiplier; the input of the ninth delay unit is connected to the third delay unit, and the output is connected to the third complex multiplier; the input of the tenth delay unit is connected to the fifth delay unit, and the output is connected to the fourth complex multiplier;

[0026] The first complex multiplier, the second complex multiplier, the third complex multiplier, and the fourth complex multiplier are all used for performing complex multiplication operations. One input of the first complex multiplier is connected to the seventh delay unit, and the other is connected to the read data signal port of the first RAM, and its output is connected to the first adder. One input of the second complex multiplier is connected to the eighth delay unit, and the other is connected to the read data signal port of the second RAM, and its output is connected to the first adder. One input of the third complex multiplier is connected to the third delay unit, and the other is connected to the read data signal port of the third RAM, and its output is connected to the second adder. One input of the fourth complex multiplier is connected to the tenth delay unit, and the other is connected to the read data signal port of the fourth RAM, and its output is connected to the second adder.

[0027] The first adder, the second adder, and the third adder are used for addition operations. The inputs of the first adder are respectively connected to the outputs of the first complex multiplier and the second complex multiplier, and its output is connected to the third adder. The inputs of the second adder are respectively connected to the outputs of the third complex multiplier and the fourth complex multiplier, and its output is connected to the third adder. The inputs of the third adder are respectively connected to the outputs of the first adder and the second adder, and the output of the third adder is the output signal of the l-th branch of the digital predistortion actuator.

[0028] In one embodiment, the digital up-conversion module includes: M branches, each branch processes one pre-emphasis compensated digital baseband signal and outputs one intermediate frequency digital signal.

[0029] A branch includes a phase accumulator, a sine and cosine waveform memory, and a multiply-accumulate unit.

[0030] For the l-th branch, the input is the pre-emphasis compensated digital baseband signal (B i (l), B q (l)), (B i (l), B q (l) are respectively two components of the pre-emphasis compensated digital baseband signal. The read address input terminal of the sine and cosine waveform memory is connected to the output of the phase accumulator, and the clock input terminal is connected to the f s / M clock, where f s is the sampling frequency. The sine and cosine waveform memory is used to store the sine and cosine waveform data with a frequency of f c / M and outputs the cosine data cos l and the sine data sin l to the multiply-accumulate unit.

[0031] The multiply-accumulate unit is used to complete sin l ×B q (l)+cos l ×B i(l) Multiplication and addition operation, and the output of the multiplication and addition unit is the output signal of the l-th branch of the digital up-conversion module.

[0032] Compared with the prior art, the present application has the following beneficial effects:

[0033] 1. The present application utilizes the non-ideal characteristics of the radio frequency sampling digital-to-analog converter to achieve the up-conversion process from intermediate frequency to radio frequency. The process of outputting the radio frequency modulation signal no longer requires an external mixer and local oscillator radio frequency link. The radio frequency module is simpler. The on-board digital pre-distortion actuator, pre-emphasis digital filter, and digital up-conversion all adopt a high-speed parallel look-up table structure, saving hardware multiplier resources and being applicable to high-speed modulation scenarios.

[0034] 2. The present application has strong adaptability to multiple operating frequency bands, multiple rates, and multiple modes. During the ground test process, the satellite channel nonlinear digital pre-distortion compensation coefficient is pre-stored in the on-board parameter secondary transfer module. After the satellite is in orbit, the specified pre-distortion parameters are bound to the digital pre-distortion actuator according to the current operating frequency band or rate mode, and different compensation effects are achieved according to the actual application scenario. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The present application can be better understood by referring to the description given below in conjunction with the accompanying drawings. The drawings, together with the following detailed description, are included in this specification and form a part of this specification. In the drawings:

[0036] Figure 1 Shows a schematic structural diagram of a digitized intermediate frequency band-pass sampling type on-board high-speed transmitting device;

[0037] Figure 2 Shows a schematic structural diagram of the l-th branch of the digital pre-distortion actuator module;

[0038] Figure 3 Shows a schematic structural diagram of the l-th branch of the digital up-conversion module.

[0039] REFERENCE SIGNS:

[0040] 1 - First delay unit, 2 - Second delay unit, 3 - Third delay unit, 4 - Fourth delay unit, 5 - Fifth delay unit, 6 - Sixth delay unit, 7 - Seventh delay unit, 8 - Eighth delay unit, 9 - Ninth delay unit, 10 - Tenth delay unit, 11 - CORDIC module, 12 - First RAM, 13 - Second RAM, 14 - Third RAM, 15 - Fourth RAM, 16 - First complex multiplier, 17 - Second complex multiplier, 18 - Third complex multiplier, 19 - Fourth complex multiplier; 20 - First adder, 21 - Second adder, 22 - Third adder. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] In the following, exemplary embodiments of the present application will be described in conjunction with the accompanying drawings. For the sake of clarity and conciseness, not all features of the actual embodiments are described in the specification. However, it should be understood that many embodiment-specific decisions may be made during the development of any such actual embodiment to achieve the specific goals of the developer, and these decisions may vary with different embodiments.

[0042] Here, it should also be noted that in order to avoid obscuring the present application with unnecessary details, only the device structures closely related to the solution of the present application are shown in the drawings, while other details less relevant to the present application are omitted.

[0043] It should be understood that the present application is not limited to the described embodiments due to the following description with reference to the accompanying drawings. In this document, where feasible, embodiments can be combined with each other, features can be replaced or borrowed between different embodiments, and one or more features can be omitted in one embodiment.

[0044] An embodiment of the present application provides a digital intermediate-frequency bandpass sampling type spaceborne high-speed transmitting device. Figure 1 The structural schematic diagram of the digital intermediate-frequency bandpass sampling type spaceborne high-speed transmitting device is shown. Refer to Figure 1 , the device includes: an on-board unit and a ground unit; the on-board unit includes a parameter secondary storage module, a digital pre-distortion actuator module, a pre-emphasis digital filter, a digital up-conversion module, a radio frequency sampling digital-to-analog converter, a radio frequency selection filtering and amplification module, and an antenna that are connected in sequence.

[0045] The digital pre-distortion actuator module is used to receive parallel M-channel original digital baseband signals, and perform non-linear distortion compensation based on pre-distortion parameters to obtain parallel M-channel compensated digital baseband signals; here, M can be 12. The digital pre-distortion actuator is used to compensate for the non-linear distortion introduced by the power amplification circuit in the radio frequency selection filtering and amplification module for broadband high-order signals.

[0046] The pre-emphasis digital filter is used to perform pre-emphasis compensation on the parallel M-channel compensated digital baseband signals to obtain parallel M-channel pre-emphasis compensated digital baseband signals; here, the pre-emphasis digital filter is used to compensate for the SINC function fading introduced by the radio frequency sampling digital-to-analog converter for the target image signal. The amplitude-frequency response of the pre-emphasis digital filter is H(ω), and it is implemented using a 24th-order polyphase filter structure, with 12 parallel inputs and 12 parallel outputs.

[0047] The digital up-conversion module is used to perform digital up-conversion on the parallel M-channel pre-emphasis compensated digital baseband signals to obtain parallel M-channel intermediate-frequency digital signals, and the intermediate frequency f c is 1.8 GHz.

[0048] The radio frequency sampling digital-to-analog converter is used to perform digital-to-analog conversion on parallel M-channel intermediate frequency digital signals to generate multi-image signals. The multi-image signals refer to the fact that due to the "zero-order hold" characteristic of the radio frequency sampling digital-to-analog converter, in the output signal spectrum of the radio frequency sampling digital-to-analog converter, in the first Nyquist sampling domain, there is not only a signal component of 1.8 GHz, but also mirror signal components of 6.4n ± 1.8m GHz in the multi-Nyquist sampling domain, and the amplitude-frequency response of each mirror signal component has a SINC function decay, where n and m are integers. According to the application scenario, the radio frequency sampling digital-to-analog converter can adopt devices of the DAC38RFxx series, DAC39RF1x series or E2V12DSxx series, with a sampling rate of up to several GHz to dozens of GHz, and the transmission signal bandwidth can reach 2 GHz.

[0049] The radio frequency selection filtering and amplification module performs selection filtering and power amplification on the multi-image signals, suppresses harmonics and clutter, and obtains the target mirror signals. The target mirror signals selected and output by the radio frequency selection filtering and amplification module are 6.4x ± 1.8y, while the non-target mirror signals suppressed are 6.4n ± 1.8m (n ≠ x, m ≠ y), where x = 1 and y = 1. That is, the up-conversion process from intermediate frequency to radio frequency is completed by the sampling clock generator, radio frequency sampling digital-to-analog converter and radio frequency selection filtering and amplification module, and no external mixer and local oscillator radio frequency circuit module are required.

[0050] The antenna is used to radiate the target mirror signals to the ground station in the form of electromagnetic waves;

[0051] The ground unit is used to generate pre-distortion parameters according to the target mirror signals output by the radio frequency selection filtering and amplification module, encapsulate the pre-distortion parameters into parameter upload data frames, and transmit the parameter upload data frames to the parameter secondary storage module through the satellite-ground TT&C link;

[0052] The parameter secondary storage module is used to parse the pre-distortion parameters from the parameter upload data frames and transfer the pre-distortion parameters to the non-volatile memory of the on-board unit. After the entire satellite is powered off and then powered on again, the pre-distortion parameters in the non-volatile memory are read according to the satellite-wide command, and the pre-distortion parameters are input into the digital pre-distortion actuator module.

[0053] In this embodiment, the non-ideal characteristics of the radio frequency sampling digital-to-analog converter are used to realize the up-conversion process from intermediate frequency to radio frequency. The process of outputting radio frequency modulation signals no longer requires an external mixer and local oscillator radio frequency link. The radio frequency module is simpler. The on-board digital pre-distortion actuator, pre-emphasis digital filter and digital up-conversion all adopt high-speed parallel look-up table structures, saving hardware multiplier resources and being suitable for high-speed modulation scenarios.

[0054] Specifically, the ground unit includes a ground acquisition and reception module, a data preprocessing module, a model coefficient extraction module, and a parameter data frame uploading module that are connected in sequence; the parameter secondary storage module is connected to the digital predistortion actuator module; the parameter data frame uploading module is connected to the parameter secondary storage module;

[0055] The ground acquisition and reception module is used to perform radio frequency direct sampling on the target mirror signal to obtain an observed digital baseband signal;

[0056] The data preprocessing module is used to perform time-domain correlation alignment processing on the observed digital baseband signal and the original digital baseband signal, and output the aligned observed digital baseband signal and the original digital baseband signal;

[0057] The model coefficient extraction module is used to generate predistortion parameters based on the aligned observed digital baseband signal and the original digital baseband signal, based on a memory polynomial model with a memory depth of 3 and an order of 9;

[0058] The parameter data frame uploading module is used to encapsulate the predistortion parameters into a parameter uploading data frame, and transmit the parameter uploading data frame to the parameter secondary storage module through the satellite-ground TT&C link.

[0059] Furthermore, the on-satellite unit further includes a sampling clock generator, which is connected to the radio frequency sampling DAC and the ground acquisition and reception module of the ground unit, and is used to provide a sampling clock signal for the radio frequency sampling DAC and the ground acquisition and reception module. According to the application scenario, existing LMX series radio frequency synthesizers and ADF series radio frequency synthesizers can be used as the sampling clock generator to provide a sampling clock signal of several GHz to dozens of GHz for the radio frequency sampling DAC.

[0060] In one embodiment, the digital predistortion actuator module includes M branches, each branch processes one path of the original digital baseband signal, and outputs one path of the compensated digital baseband signal;

[0061] Figure 2 The structural schematic diagram of the l-th branch of the digital predistortion actuator module is shown, see Figure 2 , the branch includes a CORDIC module 11, a first delay unit 1, a second delay unit 2, a third delay unit 3, a fourth delay unit 4, a fifth delay unit 5, a sixth delay unit 6, a seventh delay unit 7, an eighth delay unit 8, a ninth delay unit 9, a tenth delay unit 10, a first RAM 12, a second RAM 13, a third RAM 14, a fourth RAM 15, a first complex multiplier 16, a second complex multiplier 17, a third complex multiplier 18, a fourth complex multiplier 19; a first adder 20, a second adder 21, and a third adder 22;

[0062] For the l-th branch, the inputs to the CORDIC module 11 are the original baseband signals (x i (l), x q (l)), where x i (l) and x q (l) are the two components of the original baseband signal. The CORDIC module 11 is used to calculate the magnitudes of x i (l) and x q (l). One output port of the CORDIC module 11 is connected to the read address signal port rd_addr0 of the first RAM 12, and the other is connected to the second delay unit 2;

[0063] The first delay unit 1, the second delay unit 2, the third delay unit 3, the fourth delay unit 4, the fifth delay unit 5, and the sixth delay unit 6 are respectively used to delay the input data by one clock cycle. The input to the first delay unit 1 is the original baseband signal (x i (l), x q (l)). One output of the first delay unit 1 is connected to the eighth delay unit 8, and the other is connected to the third delay unit 3. The input to the third delay unit 3 is connected to the output of the first delay unit 1. One output of the third delay unit 3 is connected to the ninth delay unit 9, and the other is connected to the fifth delay unit 5. The input to the fifth delay unit 5 is connected to the output of the third delay unit 3. One output of the fifth delay unit 5 is connected to the tenth delay unit 10. The input to the second delay unit 2 is connected to the output of the CORDIC module 11. One output of the second delay unit 2 is connected to the read address signal port rd_addr1 of the second RAM 13, and the other is connected to the fourth delay unit 4. The input to the fourth delay unit 4 is connected to the output of the second delay unit 2. One output of the fourth delay unit 4 is connected to the read address signal port rd_addr2 of the third RAM 14, and the other is connected to the sixth delay unit 6. The input to the sixth delay unit 6 is connected to the output of the fourth delay unit 4. The output of the sixth delay unit 6 is connected to the read address signal port rd_addr3 of the fourth RAM 15;

[0064] The first RAM 12, the second RAM 13, the third RAM 14, and the fourth RAM 15 are used to store predistortion parameters; the read address signal port rd_addr0 of the first RAM 12 is connected to the CORDIC module 11, the read data signal port rd_dat0 is connected to the first complex multiplier 16, and the write address signal port wt_addr0 and the write data signal port wt_dat0 are connected to the parameter secondary transfer module of the on-board unit; the read address signal port rd_addr1 of the second RAM 13 is connected to the second delay unit 2, the read data signal port rd_dat1 is connected to the second complex multiplier 17, and the write address signal port wt_addr1 and the write data signal port wt_dat1 are connected to the parameter secondary transfer module of the on-board unit; the read address signal port rd_addr2 of the third RAM 14 is connected to the fourth delay unit 4, the read data signal port rd_dat2 is connected to the third complex multiplier 18, and the write address signal port wt_addr2 and the write data signal port wt_dat2 are connected to the parameter secondary transfer module of the on-board unit; the read address signal port rd_addr3 of the fourth RAM 15 is connected to the sixth delay unit 6, the read data signal port rd_dat3 is connected to the fourth complex multiplier 19, and the write address signal port wt_addr3 and the write data signal port are connected to the parameter secondary transfer module of the on-board unit;

[0065] The seventh delay unit 7, the eighth delay unit 8, the ninth delay unit 9, and the tenth delay unit 10 are used to delay the input data by several clock cycles to align the input data of the connected complex multipliers in time; the input signal of the seventh delay unit 7 is the original baseband signal (x i (l), x q (l)), and the output is connected to the first complex multiplier 16; the input of the eighth delay unit 8 is connected to the first delay unit 1, and the output is connected to the second complex multiplier 17; the input of the ninth delay unit 9 is connected to the third delay unit 3, and the output is connected to the third complex multiplier 18; the input of the tenth delay unit 10 is connected to the fifth delay unit 5, and the output is connected to the fourth complex multiplier 19;

[0066] The first complex multiplier 16, the second complex multiplier 17, the third complex multiplier 18, and the fourth complex multiplier 19 are used to perform complex multiplication operations. One input of the first complex multiplier 16 is connected to the seventh delay unit 7, and the other is connected to the read data signal port rd_dat0 of the first RAM 12, and the output is connected to the first adder 20. One input of the second complex multiplier 17 is connected to the eighth delay unit 8, and the other is connected to the read data signal port rd_dat1 of the second RAM 13, and the output is connected to the first adder 20. One input of the third complex multiplier 18 is connected to the third delay unit 3, and the other is connected to the read data signal port rd_dat2 of the third RAM 14, and the output is connected to the second adder 21. One input of the fourth complex multiplier 19 is connected to the tenth delay unit 10, and the other is connected to the read data signal port rd_dat3 of the fourth RAM 15, and the output is connected to the second adder 21.

[0067] The first adder 20, the second adder 21, and the third adder 22 are used for addition operations. The inputs of the first adder 20 are respectively connected to the outputs of the first complex multiplier 16 and the second complex multiplier 17, and the output is connected to the third adder 22. The inputs of the second adder 21 are respectively connected to the outputs of the third complex multiplier 18 and the fourth complex multiplier 19, and the output is connected to the third adder 22. The inputs of the third adder 22 are respectively connected to the outputs of the first adder 20 and the second adder 21, and the output of the third adder 22 is the output signal of the l-th branch of the digital pre-distortion actuator.

[0068] In one embodiment, the digital up-conversion module includes: M branches, each branch processes a pre-emphasis compensated digital baseband signal and outputs an intermediate frequency digital signal.

[0069] Figure 3 The structural schematic diagram of the l-th branch of the digital up-conversion module is shown. Refer to Figure 3 The branch includes a phase accumulator, a sine-cosine waveform memory, and a multiply-accumulate unit.

[0070] For the l-th branch, the input is the pre-emphasis compensated digital baseband signal (B i (l), B q (l)), where (B i (l), B q (l) are respectively two components of the pre-emphasis compensated digital baseband signal. The read address input terminal of the sine-cosine waveform memory is connected to the output of the phase accumulator, and the clock input terminal is connected to the f s / M clock, where f s is the sampling frequency. The sine-cosine waveform memory is used to store a signal with a frequency of f cThe sine and cosine waveform data of / M, and output the cosine data cos l and the sine data sin l to the multiply-accumulate unit;

[0071] The multiply-accumulate unit is used to complete sin l ×B q (l)+cos l ×B i (l) multiply-accumulate operation, and the output of the multiply-accumulate unit (143) is the output signal of the l-th branch of the digital upconversion module.

[0072] In summary, the present application has strong adaptability to multiple working frequency bands, multiple rates and multiple modes. During the ground test, the satellite channel nonlinear digital predistortion compensation coefficient is pre-stored in the on-board parameter secondary transfer module. After the satellite is in orbit, the specified predistortion parameters are bound to the digital predistortion actuator according to the current working frequency band or rate mode, and different compensation effects are achieved according to the actual application scenario.

[0073] The above is only various embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claimed rights.

Claims

1. A digital intermediate frequency bandpass sampling satellite-borne high-speed transmitting device, characterized in that: include: On-board unit and ground unit; the on-board unit comprises a parameter secondary transfer module, a digital pre-distortion actuator module, a pre-emphasis digital filter, a digital up-conversion module, a radio frequency sampling digital-to-analog converter, a radio frequency selection filter amplifier module and an antenna which are connected in sequence; The digital predistortion actuator module is used to receive M parallel original digital baseband signals and perform nonlinear distortion compensation based on predistortion parameters to obtain M parallel compensated digital baseband signals; The pre-emphasis digital filter is used to perform pre-emphasis compensation on the parallel M-channel compensated digital baseband signal to obtain the parallel M-channel pre-emphasis compensated digital baseband signal; The digital up-conversion module is used to perform digital up-conversion on the parallel M-channel pre-emphasis compensated digital baseband signals to obtain parallel M-channel intermediate frequency digital signals; The RF sampling digital-to-analog converter is used to perform digital-to-analog conversion on the parallel M intermediate frequency digital signals to generate multiple image signals; The radio frequency selective filtering and amplifying module selectively filters and power amplifies the multiple image signals, and suppresses harmonics and clutter to obtain a target image signal; The antenna is used to radiate the target image signal to the ground station in the form of electromagnetic waves; The ground unit is used to generate the pre-distortion parameter according to the target image signal output by the radio frequency selection filtering and amplification module, encapsulate the pre-distortion parameter into a parameter injection data frame, and transmit the parameter injection data frame to the parameter secondary transfer module through the satellite-to-ground measurement and control link; The parameter secondary transfer module is used to parse the pre-distortion parameters according to the parameter injection data frame, and transfer the pre-distortion parameters to the power-off non-loss memory of the on-board unit; After the whole satellite is powered off and then powered on again, the pre-distortion parameters in the power-off non-lost memory are read according to the whole satellite instruction, and the pre-distortion parameters are input into the digital pre-distortion actuator module.

2. The device according to claim 1, characterized in that The ground unit comprises a ground acquisition receiving module, a data preprocessing module, a model coefficient extraction module, and a parameter data frame annotation module which are connected in sequence; the parameter data frame annotation module is connected to the parameter secondary transfer module; The ground acquisition and receiving module is used to perform radio frequency direct sampling on the target image signal to obtain an observed digital baseband signal; The data preprocessing module is used to perform time domain correlation alignment processing on the observed digital baseband signal and the original digital baseband signal, and output the aligned observed digital baseband signal and the original digital baseband signal; The model coefficient extraction module is used to generate predistortion parameters based on a memory polynomial model with a memory depth of 3 and an order of 9 according to the aligned observed digital baseband signal and the original digital baseband signal; The parameter data frame injection module is used to encapsulate the pre-distortion parameters into a parameter injection data frame, and transmit the parameter injection data frame to the parameter secondary transfer module through a satellite-to-ground measurement and control link.

3. The device according to claim 1, characterized in that The onboard unit also includes a sampling clock generator, which is connected to the RF sampling DAC and the ground acquisition receiving module of the ground unit and is used to provide a sampling clock signal for the RF sampling DAC and the ground acquisition receiving module.

4. The device according to claim 1, characterized in that The digital pre-distortion actuator module includes M branches, each branch processes one original digital baseband signal and outputs one compensated digital baseband signal; The branch comprises a CORDIC module (11), a first delay unit (1), a second delay unit (2), a third delay unit (3), a fourth delay unit (4), a fifth delay unit (5), a sixth delay unit (6), a seventh delay unit (7), an eighth delay unit (8), a ninth delay unit (9), a tenth delay unit (10), a first RAM (12), a second RAM (13), a third RAM (14), a fourth RAM (15), a first complex multiplier (16), a second complex multiplier (17), a third complex multiplier (18), and a fourth complex multiplier (19); a first adder (20), a second adder (21), and a third adder (22); For the lth branch, the input of the CORDIC module (11) is the original baseband signal (x i (l),x q (l)), x i (l),x q (l) are two components of the original baseband signal, respectively. The CORDIC module (11) is used to calculate x i (l) and x q (1), the output port of the CORDIC module (11) is connected to the read address signal port of the first RAM (12) on the one hand, and is connected to the second delay unit (2) on the other hand; The first delay unit (1), the second delay unit (2), the third delay unit (3), the fourth delay unit (4), the fifth delay unit (5), and the sixth delay unit (6) are respectively used to delay the input data by one clock. The input of the first delay unit (1) is the original baseband signal (x i (l),x q (1)), the output of the first delay unit (1) is connected to the eighth delay unit (8) on the one hand, and to the third delay unit (3) on the other hand; the input of the third delay unit (3) is connected to the output of the first delay unit (1), the output of the third delay unit (3) is connected to the ninth delay unit (9) on the one hand, and to the fifth delay unit (5) on the other hand; the input of the fifth delay unit (5) is connected to the output of the third delay unit (3), the output of the fifth delay unit (5) is connected to the tenth delay unit (10) on the one hand; the input of the second delay unit (2) is connected to the CORDIC module The output of the second delay unit (2) is connected to the read address signal port of the second RAM (13) on the one hand, and is connected to the fourth delay unit (4) on the other hand; the input of the fourth delay unit (4) is connected to the output of the second delay unit (2), and the output of the fourth delay unit (4) is connected to the read address signal port of the third RAM (14) on the one hand, and is connected to the sixth delay unit (6) on the other hand; the input of the sixth delay unit (6) is connected to the output of the fourth delay unit (4), and the output of the sixth delay unit (6) is connected to the read address signal port of the fourth RAM (15); The first RAM (12), the second RAM (13), the third RAM (14), and the fourth RAM (15) are used to store the predistortion parameters; the read address signal port of the first RAM (12) is connected to the CORDIC module (11), the read data signal port is connected to the first complex multiplier (16), and the write address signal port and the write data signal port are connected to the parameter secondary transfer module of the on-board unit; the read address signal port of the second RAM (13) is connected to the second delay unit (2), the read data signal port is connected to the second complex multiplier (17), and the write address signal port and the write data signal port are connected to the parameter secondary transfer module of the on-board unit; The read address signal port and the write data signal port are connected to the parameter secondary transfer module of the on-board unit; the read address signal port of the third RAM (14) is connected to the fourth delay unit (4), the read data signal port is connected to the third complex multiplier (18), and the write address signal port and the write data signal port are connected to the parameter secondary transfer module of the on-board unit; the read address signal port of the fourth RAM (15) is connected to the sixth delay unit (6), the read data signal port is connected to the fourth complex multiplier (19), and the write address signal port and the write data signal port are connected to the parameter secondary transfer module of the on-board unit; The seventh delay unit (7), the eighth delay unit (8), the ninth delay unit (9) and the tenth delay unit (10) are used to delay the input data by a number of clock cycles and perform time alignment on the input data of the connected complex multipliers; the input signal of the seventh delay unit (7) is the original baseband signal (x i (l),x q (l)), the output of which is connected to the first complex multiplier (16); the input of the eighth delay unit (8) is connected to the first delay unit (1), and the output is connected to the second complex multiplier (17); the input of the ninth delay unit (9) is connected to the third delay unit (3), and the output is connected to the third complex multiplier (18); the input of the tenth delay unit (10) is connected to the fifth delay unit (5), and the output is connected to the fourth complex multiplier (19); The first complex multiplier (16), the second complex multiplier (17), the third complex multiplier (18) and the fourth complex multiplier (19) are all used for performing complex multiplication operations; the input of the first complex multiplier (16) is connected to the seventh delay unit (7) on the one hand, and is connected to the read data signal port of the first RAM (12) on the other hand, and the output is connected to the first adder (20); the input of the second complex multiplier (17) is connected to the eighth delay unit (8) on the one hand, and is connected to the second R The input of the third complex multiplier (18) is connected to the third delay unit (3) on the one hand, and is connected to the read data signal port of the third RAM (14) on the other hand, and is connected to the second adder (21); the input of the fourth complex multiplier (19) is connected to the tenth delay unit (10) on the one hand, and is connected to the read data signal port of the fourth RAM (15) on the other hand, and is connected to the second adder (21); The first adder (20), the second adder (21) and the third adder (22) are used for addition operations; the input of the first adder (20) is respectively connected to the outputs of the first complex multiplier (16) and the second complex multiplier (17), and the output is connected to the third adder (22); the input of the second adder (21) is respectively connected to the outputs of the third complex multiplier (18) and the fourth complex multiplier (19), and the output is connected to the third adder (22); the input of the third adder (22) is respectively connected to the outputs of the first adder (20) and the second adder (21), and the output of the third adder (22) is the output signal of the first branch of the digital pre-distortion actuator.

5. The device according to claim 1, characterized in that The digital up-conversion module comprises: M branches, each branch processes a digital baseband signal after pre-emphasis compensation and outputs an intermediate frequency digital signal; The branch includes a phase accumulator, a sine-cosine waveform memory and a multiplication-addition unit; For the lth branch, the input is the digital baseband signal after pre-emphasis compensation (B i (l),B q (l)), (B i (l),B q (l) are two components of the digital baseband signal after pre-emphasis compensation, the read address input terminal of the sine and cosine waveform memory is connected to the output of the phase accumulator, and the clock input terminal is connected to f s / M clock connected, f s The sine and cosine waveform memory is used to store the sampling frequency f c / M sine and cosine waveform data, and output cosine data cos l and sine data sin l to the multiply-add unit; The multiplication and addition unit is used to complete the sin l ×B q (l)+cos l ×B i (1) Multiplication and addition operation, the output of the multiplication and addition unit is the output signal of the lth branch of the digital up-conversion module.

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