Control circuit and control method

Abstract

The invention provides a control circuit and a control method, which can be applied to the technical field of circuits. The control circuit includes: a controller; the N candidate devices are cascaded, and N is a positive integer greater than 1; wherein the N candidate devices are used for sending N response signals corresponding to the N candidate devices to the controller according to a position judgment signal from the controller, and a judgment value of a position judgment bit of the nth response signal represents the relative position of the nth candidate device in the N candidate devices; the address value of the address bit of the nth response signal represents the address of the nth candidate device; wherein the controller is used for determining the target address value of the target device according to the decision values and the address values of the N response signals, and sending control signals to the N candidate devices according to the target address value, so that the matching sub-circuit of the target device is electrically connected with the control circuit under the condition that the target device receives the control signals.

Description

Technical Field

[0001] The present disclosure relates to the field of circuit technologies, and in particular, to a control circuit and a control method. Background Art

[0002] RS485 is a communication protocol that defines the electrical characteristics of drivers and receivers in a balanced digital multi-point system. A digital communication network using this communication protocol can effectively transmit signals under long-distance conditions and in an environment with high electronic noise.

[0003] For a circuit that transmits signals based on the RS485 communication protocol, technicians can close the DIP switches at the head and end of the circuit to connect matching resistors at the head and end of the circuit, thereby improving the anti-interference ability of the signals. However, there is a problem of low efficiency in connecting the matching resistor at the end. Summary of the Invention

[0004] In view of the above problems, the present disclosure provides a control circuit and a control method.

[0005] According to a first aspect of the present disclosure, a control circuit is provided, including: a controller; and N cascaded candidate devices, where N is a positive integer greater than 1; wherein, the N candidate devices are configured to send N response signals corresponding to the N candidate devices to the controller according to a position determination signal from the controller, where the determination value of the position determination bit of the nth response signal represents the relative position of the nth candidate device among the N candidate devices, and the address value of the nth response signal represents the address of the nth candidate device; wherein, the controller is configured to determine the target address value of the target device according to the determination values and address values of the N response signals, and send a control signal to the N candidate devices according to the target address value, so that when the target device receives the control signal, the matching sub-circuit of the target device is electrically connected to the control circuit.

[0006] According to an embodiment of the present disclosure, the matching sub-circuit of the target device includes a first switch of the target device and a matching resistor of the target device, and the first switch of the target device and the matching resistor of the target device are connected in series; the first switch of the target device is configured to close when receiving the control signal, so as to electrically connect the matching resistor of the target device to the control circuit, thereby electrically connecting the matching sub-circuit of the target device to the control circuit.

[0007] According to an embodiment of the present disclosure, the controller includes a first switch and a matching resistor, and the first switch of the controller and the matching resistor of the controller are connected in series. The first switch of the controller is closed when the candidate device is determined to be the controller, so as to electrically connect the matching resistor of the controller to the control circuit.

[0008] According to an embodiment of the present disclosure, a candidate device includes a signal processing sub-circuit and a matching sub-circuit; wherein, the nth signal processing sub-circuit is connected in series with the (n - 1)th signal processing sub-circuit, and the nth signal processing sub-circuit is configured to output an nth position determination signal according to the (n - 1)th position determination signal, wherein the determination value of the (n - 1)th position determination signal is different from the determination value of the nth position determination signal, and n = 2... N; wherein, the nth matching sub-circuit is connected to the nth signal processing sub-circuit, and the nth matching sub-circuit is configured to output an nth response signal having the same determination value as the nth position determination signal according to the nth position determination signal.

[0009] According to an embodiment of the present disclosure, the nth signal processing sub-circuit is further configured to receive the nth response signal from the nth matching sub-circuit and send the nth response signal to a controller, wherein the flag value of the flag bit of the response signal is different from the flag value of the flag bit of the position determination signal, so that the nth signal processing sub-circuit does not process the nth response signal when receiving the nth response signal.

[0010] According to an embodiment of the present disclosure, the nth signal processing sub-circuit is further configured to calculate a check value of the nth check bit according to the nth determination value and the (n - 1)th position determination signal, and output the nth position determination signal according to the nth determination value, the (n - 1)th position determination signal, and the check value of the nth check bit.

[0011] According to an embodiment of the present disclosure, the nth signal processing sub-circuit includes an nth signal processing unit; wherein, the nth signal processing unit is configured to add a predetermined value to the determination value of the (n - 1)th position determination signal to obtain the nth determination value, and output the nth position determination signal according to the nth determination value and the (n - 1)th position determination signal.

[0012] According to an embodiment of the present disclosure, the N signal processing sub-circuits are connected to each other through a bus based on the RS485 communication protocol, and the bus includes a first bus and a second bus; the nth signal processing sub-circuit further includes a first transceiver and a second transceiver; wherein, the first transceiver, the nth signal processing unit, and the second transceiver are connected in series in sequence; a first input end of the first transceiver and a first input end of the second transceiver are both connected to the first bus, and a second input end of the first transceiver and a second input end of the second transceiver are both connected to the second bus.

[0013] According to an embodiment of the present disclosure, the nth signal processing sub-circuit further includes a second switch and a third switch. The first end of the second switch is connected to the first input end of the first transceiver, the second end of the second switch is connected to the first input end of the second transceiver, the first end of the third switch is connected to the second input end of the first transceiver, and the second end of the third switch is connected to the second input end of the second transceiver. Wherein, the second switch and the third switch are configured to close when receiving a switch closing signal from the controller, so as to disconnect the nth signal processing unit from the bus.

[0014] According to an embodiment of the present disclosure, the second switch and the third switch are further configured to open when receiving a reset signal, so as to electrically connect the nth signal processing unit to the bus.

[0015] According to a second aspect of the present disclosure, there is provided a control method, which is applied to any one of the above signal processing circuits. The method includes: N candidate devices send N response signals corresponding to the N candidate devices to the controller according to the position determination signal from the controller; the controller determines the target address value of the target device according to the determination values and address values of the N response signals, and sends a control signal to the N candidate devices according to the target address value, so that when the target device receives the control signal, the matching sub-circuit of the target device is electrically connected to the control circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above content and other objects, features and advantages of the present disclosure will become clearer. In the drawings:

[0017] Figure 1 Schematically shows a schematic diagram of a control circuit according to a first embodiment of the present disclosure;

[0018] Figure 2 Schematically shows a schematic diagram of a control circuit according to a second embodiment of the present disclosure;

[0019] Figure 3 Schematically shows a schematic diagram of a control circuit according to a third embodiment of the present disclosure;

[0020] Figure 4 Schematically shows a schematic diagram of a signal processing sub-circuit according to an embodiment of the present disclosure;

[0021] Figure 5 Schematically shows a schematic diagram of a control circuit according to a fourth embodiment of the present disclosure;

[0022] Figure 6 Schematically shows a schematic diagram of a response device according to a first embodiment of the present disclosure;

[0023] Figure 7Schematically shows a schematic diagram of a response device according to a second embodiment of the present disclosure;

[0024] Figure 8 Schematically shows a schematic diagram of a control circuit according to a fifth embodiment of the present disclosure; and

[0025] Figure 9 Schematically shows a flowchart of a control method according to an embodiment of the present disclosure. Detailed implementation manners

[0026] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the following detailed description, for the sake of explanation, many specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure. However, obviously, one or more embodiments can also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0027] The terms used herein are merely for describing specific embodiments and are not intended to limit the present disclosure. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0028] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0029] In the case of using expressions such as "at least one of A, B, and C, etc.", generally, it should be interpreted according to the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include, but is not limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0030] In some embodiments, candidate devices to be determined as end devices may include matching resistors and DIP switches. Technicians go to the area where the target device in the candidate device is located according to requirements, and close the DIP switch of the target device on site to electrically connect the matching resistor of the target device to a circuit for signal transmission based on the RS485 communication protocol. Based on this, there is a problem of low efficiency in manually accessing the matching resistor at the end.

[0031] In view of this, embodiments of the present disclosure provide a control circuit, including: a controller, and N cascaded candidate devices, where N is a positive integer greater than 1. Among them, the determination value of the position determination bit of the nth response signal characterizes the relative position of the nth candidate device among the N candidate devices, and the address value of the nth response signal characterizes the address of the nth candidate device. Among them, the controller is configured to determine the target address value of the target device according to the determination values and address values of the N response signals, and send a control signal to the N candidate devices according to the target address value, so that when the target device receives the control signal, the matching sub-circuit of the target device is electrically connected to the control circuit.

[0032] Figure 1 FIG. schematically shows a schematic diagram of a control circuit according to a first embodiment of the present disclosure.

[0033] As Figure 1 shown, the control circuit of this embodiment includes: a controller 110 and N cascaded candidate devices 120_1... 120_N, where N is a positive integer greater than 1.

[0034] The controller 110 includes a first switch and a matching resistor, and the first switch of the controller 110 and the matching resistor of the controller 110 are connected in series. The first switch of the controller 110 is closed when the candidate device is determined to be the controller 110, so as to electrically connect the matching resistor of the controller 110 to the control circuit. For example, through an application installed in the electronic device, a controller determination signal can be sent to another candidate device connected to the N candidate devices 120_1... 120_N to determine the other candidate device as the controller 110, and the first switch of the other candidate device is closed to electrically connect the matching resistor of the other candidate device to the control circuit. Thus, it is possible to electrically connect the matching resistor located at the head end of the control circuit to the control circuit. Based on this, only the controller 110 sends a position determination signal to the N candidate devices 120_1... 120_N, so as to determine the matching resistor of the candidate device located at the end of the control circuit, and the matching resistor of the candidate device located at the end of the control circuit can be electrically connected to the control circuit.

[0035] The N candidate devices 120_1... 120_N can be used to send N response signals corresponding to the N candidate devices 120_1... 120_N to the controller 110 according to the position determination signal from the controller 110. Among them, the determination value of the position determination bit of the nth response signal characterizes the relative position of the nth candidate device among the N candidate devices, and the address value of the nth response signal characterizes the address of the nth candidate device.

[0036] The controller 110 can be used to determine the target address value of the target device according to the determination values of the N response signals and the address value, and send a control signal to the N candidate devices 120_1... 120_N according to the target address value, so that when the target device receives the control signal, the matching sub-circuit of the target device is electrically connected to the control circuit.

[0037] The controller 110 and the N candidate devices 120_1... 120_N can transmit signals based on the RS485 communication protocol. The RS485 signal can be a differential signal. The position determination signal, the response signal, and the control signal can all be RS485 signals based on the RS485 communication protocol. The content of the RS485 signal can include an address bit, a function code, a register address bit, data, a check code, etc. For example, the content example of the RS485 signal can be as shown in Table 1 below.

[0038] Table 1

[0039]

[0040] The address value of the address bit represents the address of the candidate device. The address can be the unique number of the candidate device, and this number can be used for the candidate device for data transmission based on the RS485 communication protocol. For example, the address value can be an 8-bit hexadecimal value, such as 0xFF.

[0041] The register address can include the address of the register of the candidate device, etc. For example, by reading or writing the value of this address, the status information of the register can be read or changed.

[0042] The data can be the data to be written into the register corresponding to the register address.

[0043] The function code can be used to represent the operation to be performed by the signal processing sub-circuit on the RS485 signal. For example, when the function code represents the write function, the signal processing sub-circuit of the candidate device can perform a write operation on the RS485 signal. The function codes of the position determination signal, the response signal, and the control signal can all represent the write function.

[0044] When the RS485 signal is the position determination signal, the response signal, and the control signal, the data can include a flag bit and a determination bit.

[0045] The determination value of the determination bit represents the relative position of the candidate device among the N candidate devices. For example, this relative position can be the ranking of the candidate device among the N candidate devices. For example, this ranking can be the ranking of the device through which the address determination signal passes among the N candidate devices. For example, the relative position of the nth candidate device 120_n among the N candidate devices can be n.

[0046] The flag value of the flag bit indicates whether the RS485 signal is a position determination signal. For example, when the flag value of the flag bit of the RS485 signal is 1, the RS485 signal is a position determination signal; when the flag value of the flag bit of the RS485 signal is 0, the RS485 signal is not a position determination signal.

[0047] An example of the content of the position determination signal is shown in Table 2 below.

[0048] Table 2

[0049]

[0050] The position determination signal can be used to determine the addresses of each of the N candidate devices. For example, the (n - 1)-th position determination signal can be sent to the n-th candidate device 120_n, so that the n-th candidate device 120_n outputs the n-th position determination signal according to the (n - 1)-th position determination signal. Among them, the determination value of the (n - 1)-th position determination signal is different from the determination value of the n-th position determination signal, where n = 2... N. Thus, the N candidate devices 120_1... 120_N can output N position determination signals including different determination values.

[0051] For example, the n-th candidate device 120_n can add a predetermined value to the determination value of the (n - 1)-th position determination signal to obtain the n-th determination value, and output the n-th position determination signal according to the n-th determination value and the (n - 1)-th position determination signal.

[0052] After the N-th candidate device 120_N outputs the N-th position determination signal, the N candidate devices 120_1... 120_N can send response signals to the controller 110. According to the definition of the RS485 communication protocol, within a period, there will be only one signal on the transmission line between the controller 110 and the N candidate devices 120_1... 120_N. Based on this, the N response signals can be sent to the controller 110 in sequence from the first response signal to the N-th response signal. The n-th response signal can be sent to the controller 110 through n - 1 candidate devices in sequence.

[0053] An example of the content of the response signal is shown in Table 3 below.

[0054] Table 3

[0055]

[0056] When receiving the response signal, the controller 110 can store the address value and the determination value of the response signal. Since the larger the determination value is, the more backward the relative position of the candidate device corresponding to the determination value among the N candidate devices is, the controller 110 can also be used to determine the address value of the response signal with the largest determination value among the N response signals as the target address value of the target device located at the end of the control circuit.

[0057] When determining the target address value, the controller 110 can send a control signal to the N candidate devices 120_1... 120_N according to the target address value. The control signal can be sequentially transmitted among the N candidate devices 120_1... 120_N until it is transmitted to the target device.

[0058] An example of the content of the control signal can be as shown in Table 4 below.

[0059] Table 4

[0060]

[0061] Each of the N candidate devices 120_1... 120_N can also include a matching resistor. The resistance values of the matching resistors of the controller 110 and the N candidate devices 120_1... 120_N can be the same. Connecting the matching sub-circuit of the target device to the control circuit can be connecting the matching resistor of the target device to the control circuit. When the matching sub-circuit of the target device is connected to the control circuit, the resistance is matched between the head and the end of the control circuit based on the RS485 communication protocol. The head of the control circuit is determined by the controller 110. The end of the control circuit is determined by the target device. In some embodiments, a switch-off signal can be sent to the controller through an electronic device to disconnect the matching resistor of the controller from the control circuit. Based on this, the controller with the matching resistor disconnected from the control circuit can be used as a candidate device.

[0062] When the matching resistor is connected to the control circuit, the matching resistors of the N - 1 candidate devices other than the target device are not connected to the control circuit, otherwise it will cause an abnormal communication situation in the control circuit.

[0063] The controller 110 sends a position determination signal to the N candidate devices 120_1...120_N, and receives a response signal corresponding to the position determination signal from the N candidate devices 120_1...120_N. Thus, the determination values ​​of the N candidate devices 120_1...120_N can be determined. Based on this, even if the N candidate devices 120_1...120_N are adjusted, the determination values ​​of the N candidate devices 120_1...120_N can be re-obtained through the position determination signal and the response signal. Furthermore, the target device at the end of the control circuit can be re-determined based on the determination value. Based on this, the efficiency of determining the target device is improved, and the efficiency of resistance matching between the head end and the end of the control circuit is further improved.

[0064] Figure 2 The figure schematically shows a control circuit according to the second embodiment of the present disclosure.

[0065] like Figure 2 As shown, the candidate devices include a signal processing sub-circuit and a matching sub-circuit, that is, the N candidate devices 120_1 ... 120_N include N signal processing sub-circuits 121_1 ... 121_N and N matching sub-circuits 122_1 ... 122_N.

[0066] The nth signal processing subcircuit 121_n is connected in series with the n-1th signal processing subcircuit 121_n-1. The nth signal processing subcircuit 121_n is used to output the nth position determination signal according to the n-1th position determination signal. The determination value of the n-1th position determination signal is different from the determination value of the nth position determination signal, and n=2...N.

[0067] The nth matching sub-circuit 122_n is connected to the nth signal processing sub-circuit 121_n. The nth matching sub-circuit 122_n is used to output an nth response signal having the same determination value as the nth position determination signal according to the nth position determination signal.

[0068] By making the nth signal processing subcircuit 121_n output an nth position determination signal having a different determination value from the n-1th position determination signal, different determination values ​​of the N signal processing subcircuits 121_1 ... 121_N can be obtained. Based on this, the determination values ​​of the N candidate devices 120_1 ... 120_N are determined.

[0069] The nth signal processing sub-circuit 121_n is also used to calculate the check value of the nth check bit based on the nth judgment value and the n-1th position judgment signal, and output the nth position judgment signal based on the nth judgment value, the n-1th position judgment signal and the check value of the nth check bit.

[0070] The nth signal processing sub - circuit 121_n can calculate the check value of the nth check bit according to the check value calculation method of the RS485 communication protocol, based on the nth determination value and the values other than the check value in the (n - 1)th position determination signal. It should be noted that the present disclosure does not specifically limit the check value calculation method of the RS485 communication protocol, as long as the check value can be calculated. Among them, the values other than the check value in the (n - 1)th position determination signal can include flag values, function codes, etc.

[0071] The nth position determination signal can be generated based on the nth determination value, the values other than the (n - 1)th determination value and the (n - 1)th check value in the (n - 1)th position determination signal, and the nth check value. Among them, the values other than the (n - 1)th determination value and the (n - 1)th check value in the (n - 1)th position determination signal can include flag values, function codes, etc.

[0072] The nth signal processing sub - circuit 121_n is further configured to receive the nth response signal from the nth matching sub - circuit 122_n and send the nth response signal to the controller 110. The flag value of the flag bit of the response signal is different from the flag value of the flag bit of the position determination signal, so that when the nth signal processing sub - circuit 121_n receives the nth response signal, it does not process the nth response signal.

[0073] The flag bit can be used to enable the signal processing sub - circuit to distinguish the position determination signal from other signals. For example, when receiving a signal with a flag value of 1, the (n - 1)th signal processing sub - circuit 121_n - 1 can determine the signal as a position determination signal. When determining that the signal is a position determination signal, the (n - 1)th signal processing sub - circuit 121_n - 1 can process the signal and output the (n - 1)th position determination signal.

[0074] Also, for example, when receiving a signal with a flag value of 0, the (n - 1)th signal processing sub - circuit 121_n - 1 can determine that the signal is not a position determination signal. When determining that the signal is not a position determination signal, the (n - 1)th signal processing sub - circuit 121_n - 1 does not process the signal and transmits the signal to the nth signal processing sub - circuit 121_n.

[0075] Figure 3 Schematically shows a schematic diagram of a control circuit according to the third embodiment of the present disclosure.

[0076] As Figure 3As shown, the N matching sub - circuits 122_1... 122_N include N matching resistors 1221_1... 1221_N and N first switches 1222_1... 1222_N. Thus, the matching sub - circuit of the target device among the N matching sub - circuits 122_1... 122_N also includes a first switch and a matching resistor.

[0077] When the nth candidate device 120_n is the target device, the first switch 1222_n of the target device and the matching resistor 1222_n of the target device are in series. The first switch 122_n of the target device is used to close upon receiving a control signal, so as to electrically connect the matching sub - circuit 122_n of the target device to the control circuit by electrically connecting the matching resistor 1222_n of the target device to the control circuit.

[0078] The first switch 1222_n of the target device can be an electronic device with a conduction function and an open - circuit function, such as a transistor or a relay, or can be a switch composed of at least two of the above - mentioned transistors and relays with a conduction function and an open - circuit function.

[0079] Figure 4 Schematically shows a schematic diagram of a signal processing sub - circuit according to an embodiment of the present disclosure.

[0080] As Figure 4 shown, the nth signal processing sub - circuit 121_n includes the nth signal processing unit 1211_n. The nth signal processing unit 1211_n can be an MCU (Microcontroller Unit).

[0081] The nth signal processing unit 1211_n is used to add a predetermined value to the determination value of the (n - 1)th position determination signal to obtain the nth determination value, and output the nth position determination signal according to the nth determination value and the (n - 1)th position determination signal.

[0082] The determination value in the position determination signal sent by the controller 110 can be 1. Furthermore, the determination values output by the N signal processing units 1211_1... 1211_N will be accumulated one by one. Based on this, taking the relative position of the controller 110 in the control circuit as a reference, the relative positions of the N candidate devices 120_1... 120_N in the control circuit can be determined in sequence. Furthermore, the determination value of the nth signal processing sub - circuit 121_n can be n, that is, the determination value of the nth candidate device 120_n can be n. For example, the determination value of the controller 110 can be set to 0, and then the determination values of the N candidate devices 120_1... 120_N can be 1... N in sequence, but it is not limited to this. In some embodiments, the determination value of the controller 110 can also be set to 1, and the same applies to others.

[0083] The N signal processing sub - circuits 121_1……121_N are connected to each other through a bus based on the RS485 communication protocol. The bus includes a first bus 140 and a second bus 150. The nth signal processing sub - circuit 121_n further includes a first transceiver 1212_n and a second transceiver 1213_n. Among them, the first transceiver 1212_n, the signal processing unit, and the second transceiver 1213_n are connected in series in sequence. The first input terminal of the first transceiver 1212_n and the first input terminal of the second transceiver 1213_n are both connected to the first bus 140, and the second input terminal of the first transceiver 1212_n and the second input terminal of the second transceiver 1213_n are both connected to the second bus 150.

[0084] The first transceiver 1212_n can be used to process the signals based on the RS485 communication protocol transmitted by the first bus 140 and the second bus 150 into serial port signals that can be processed by the signal processing sub - circuit.

[0085] The second transceiver 1213_n can be used to process the serial port signals output by the signal processing sub - circuit into signals based on the RS485 communication protocol.

[0086] The nth signal processing sub - circuit 121_n further includes a second switch 1214_n and a third switch 1215_n. The first end of the second switch 1214_n is connected to the first input terminal of the first transceiver 1212_n, the second end of the second switch 1214_n is connected to the first input terminal of the second transceiver 1213_n, the first end of the third switch 1215_n is connected to the second input terminal of the first transceiver 1212_n, and the second end of the third switch 1215_n is connected to the second input terminal of the second transceiver 1213_n. Among them, the second switch 1214_n and the third switch 1215_n are used to close when receiving the switch - closing signal from the controller 110, so as to disconnect the nth signal processing unit 1211_n in parallel with the second switch and the third switch from the bus.

[0087] The switch - closing signal can be used to control the second switch 1214_n and the third switch 1215_n to close. For example, both the second switch 1214_n and the third switch 1215_n can be N - type transistors, and the switch - closing signal can be a high - level signal. When the gates of the second switch 1214_n and the third switch 1215_n receive the high - level switch - closing signal, the second switch 1214_n and the third switch 1215_n can close.

[0088] An example of the content of the switch - closing signal can be as shown in Table 5 below.

[0089] Table 5

[0090]

[0091] The switch closing signal can be sent by the controller 110 when the matching sub - circuit of the target device is electrically connected to the control circuit. In some embodiments, the signal processing unit can receive the switch closing signal of the controller 110, and then control the second switch 1214_n and the third switch 1215_n to close, so as to restore the bus topology of the control circuit based on the RS485 communication protocol. Based on this, the N signal processing sub - circuits 121_1……121_N will no longer receive the signals transmitted by the first bus 140 and the second bus 150.

[0092] The second switch 1214_n and the third switch 1215_n are also used to disconnect when receiving the reset signal, so as to electrically connect the nth signal processing unit 1211_n to the bus.

[0093] The second switch 1214_n and the third switch 1215_n can both be electronic devices with path - forming and path - breaking functions such as transistors or relays, or can both be switches composed of at least two of the above - mentioned transistors, metal - oxide semiconductor field - effect transistors and relays with path - forming and path - breaking functions.

[0094] The reset signal can be used to control the disconnection of the second switch 1214_n and the third switch 1215_n. For example, the second switch 1214_n and the third switch 1215_n can both be N - type transistors, and the reset signal can be a low - level signal. When the gates of the second switch 1214_n and the third switch 1215_n receive the low - level reset signal, the second switch 1214_n and the third switch 1215_n can be disconnected. Since the second switch 1214_n, the third switch 1215_n are in parallel with the nth signal processing unit, by disconnecting the second switch 1214_n and the third switch 1215_n, the state of electrically connecting the nth signal processing unit to the bus can be reset.

[0095] An example of the content of the reset signal can be as shown in Table 6 below.

[0096] Table 6

[0097]

[0098] In some embodiments, the nth signal processing unit 1211_n can receive the reset signal and control both the second switch 1214_n and the third switch 1215_n to disconnect, so as to reset the state of electrically connecting the nth signal processing unit to the bus.

[0099] Figure 5Schematically shows a schematic diagram of a control circuit according to a fourth embodiment of the present disclosure.

[0100] As Figure 5 shown, N matching sub-circuits 122_1 …… 122_N can be connected to N response devices 130_1 …… 130_N. Thus, the matching sub-circuit 122_n of the nth candidate device 120_n can be connected to the nth response device 130_n. The nth signal processing unit 1211_n can send the nth position determination signal to the nth response device 130_n. The nth response device 130_n can store the determination value in the nth position determination signal. When the nth response device 130_n receives the nth position determination signal, it can generate the nth response signal according to the nth position determination signal. For example, the nth response device 130_n can generate the nth response signal according to the determination value in the nth position determination signal.

[0101] The controller 110 can sequentially send address reading signals corresponding to the N candidate devices 120_1 …… 120_N to the N candidate devices 120_1 …… 120_N based on the RS485 communication protocol. An example of the content of the address reading signal can be as shown in Table 7 below.

[0102] Table 7

[0103]

[0104] When the nth response device 130_n receives the address reading signal, it can send the nth response signal to the nth signal processing unit 1211_n to send the nth response signal to the controller 110 through the n signal processing units.

[0105] When the nth signal processing unit 1211_n receives a control signal from the controller 110, it can send the control signal to the nth response device 130_n. The nth response device 130_n can match the target address value in the control signal with the nth address value to obtain the nth matching result. When the nth matching result indicates that the address values are the same, the response device can determine the N candidate devices 120_1 …… 120_N as the target device and close the first switch of the target device. When the nth matching result indicates that the address values are different, the nth response device 130_n can discard the control signal.

[0106] Figure 6 Schematically shows a schematic diagram of a response device according to a first embodiment of the present disclosure.

[0107] As Figure 6As shown, the nth response device 130_n may include a response sub-circuit 131_n, a power supply 132_n, a transistor 133_n, a resistor 134_n, and a light-emitting diode 135_n.

[0108] The gate of the transistor 133_n may be connected to the response sub-circuit 131_n, one of the source or drain may be connected to the power supply 132_n, and the other of the source or drain may be connected to the first end of the resistor 134_n and the anode of the light-emitting diode 135_n. The cathode of the light-emitting diode 135_n and the second end of the resistor 134_n may both be connected to the ground terminal 136_n. For example, when the transistor 133_n is a P-type transistor, the source may be connected to the power supply 132_n, and the drain may be connected to the first end of the resistor 134_n and the anode of the light-emitting diode 135_n. Also for example, when the transistor 133_n is an N-type transistor, the drain may be connected to the power supply 132_n, and the source may be connected to the first end of the resistor 134_n and the anode of the light-emitting diode 135_n.

[0109] The first switch of the Nth candidate devices 120_1……120_N may be a light-controlled switch. Based on this, when the first switch is illuminated, the first switch may close; when the first switch is not illuminated, the first switch may open.

[0110] When the Nth candidate devices 120_1……120_N are target devices, and the response sub-circuit 131_n of the nth response device 130_n receives a control signal, the response sub-circuit 131_n of the nth response device 130_n may apply a voltage signal to the gate of the transistor 133_n to make the transistor 133_n in an on state. Thereby, the voltage of the power supply 132_n may supply power to the light-emitting diode 135_n to make the light-emitting diode 135_n emit light, so that the first switch 1222_n closes.

[0111] Figure 7 Schematically shows a schematic diagram of a response device according to a second embodiment of the present disclosure.

[0112] As Figure 7 shown, the nth response device 130_n may include a response sub-circuit 131_n, a power supply 132_n, a transistor 133_n, and a relay 137_n.

[0113] The gate of transistor 133_n can be connected to the response sub-circuit 131_n. One of the source or drain of transistor 133_n can be connected to the ground terminal 136_n, and the other of the source or drain of transistor 133_n can be connected to the first terminal of relay 137_n. The second terminal of relay 137_n can be connected to the power supply 132_n. For example, when transistor 133_n is a P-type transistor, the source can be connected to the first terminal of relay 137_n, and the drain can be connected to the ground terminal 136_n. Also for example, when transistor 133_n is an N-type transistor, the drain can be connected to the first terminal of relay 137_n, and the source can be connected to the ground terminal 136_n.

[0114] Relay 137_n can be used to control the closing state of the first switch according to the current in the loop where relay 137_n is located. For example, when the value of the current in the loop where relay 137_n is located is greater than or equal to a predetermined threshold, relay 137_n can control the first switch to conduct; when the value of the current in the loop where relay 137_n is located is less than the predetermined threshold, relay 137_n can control the first switch to turn off.

[0115] When the nth candidate device 120_n is the target device and the response sub-circuit 131_n of the nth response device 130_n receives a control signal, the response sub-circuit 131_n of the nth response device 130_n can apply a voltage signal to the gate of transistor 133_n to make transistor 133_n in a conducting state. Thereby, the current value in the loop where relay 137_n is located increases to be greater than or equal to the predetermined threshold, so that the first switch 1222_n can be closed.

[0116] Figure 8 Schematically shows a schematic diagram of a control circuit according to the fifth embodiment of the present disclosure.

[0117] As Figure 8 shown, the control circuit of this embodiment can include a central controller 811, a humidity control device 812, a central controller 821, a humidity control device 822, a central controller 831, and a humidity control device 832 deployed on multiple floors.

[0118] The facilities 810 deployed on the first floor can include a central controller 811 and a humidity control device 812. The facilities 820 deployed on the second floor can include a central controller 821 and a humidity control device 822. The facilities 830 deployed on the third floor can include a central controller 831 and a humidity control device 832.

[0119] The central controller 811 may include a matching sub-circuit. The matching sub-circuit of the central controller 811 may include a matching resistor 8111 and a switch 8112, but is not limited thereto. In some embodiments, the central controller 811 may further include a signal processing sub-circuit, etc. In some embodiments, the matching sub-circuits of the central controller 811 may be connected in parallel with the matching sub-circuits of the humidity adjusting device 812, the central controller 821, the humidity adjusting device 822, the central controller 831, and the humidity adjusting device 832 respectively. The signal processing sub-circuit of the central controller 811 may be connected in series with the signal processing sub-circuits of the humidity adjusting device 812, the central controller 821, the humidity adjusting device 822, the central controller 831, and the humidity adjusting device 832 respectively. The matching resistor 8111 may be electrically connected to the control circuit by closing the switch 8112 of the central controller 811.

[0120] The candidate devices may include the humidity adjusting device 812, the central controller 821, the humidity adjusting device 822, the central controller 831, and the humidity adjusting device 832. The central controller 811 may determine the humidity adjusting device 832 as the target device. The debugging device 832 may include a matching resistor 8321 and a switch 8322. The central controller 811 may send a control signal corresponding to the address value of the humidity adjusting device 832. When the humidity adjusting device 832 receives the control signal, the switch 8322 may be closed to electrically connect the matching resistor 8321 to the control circuit.

[0121] Figure 9 A flowchart of a control method according to an embodiment of the present disclosure is schematically shown. It should be noted that, unless it is clearly stated that there is a sequential execution order between different operations in the flowchart shown in the embodiment of the present disclosure, or there is a sequential execution order between different operations in the technical implementation, the execution order between multiple operations may be unordered, and multiple operations may also be executed simultaneously.

[0122] As Figure 9 shown, the control method of this embodiment can be applied to any of the above signal processing circuits, and the method includes operations S910 to S930.

[0123] In operation S910, N candidate devices send N response signals corresponding to the N candidate devices to the controller according to the position determination signal from the controller.

[0124] In operation S920, the controller determines the target address value of the target device according to the determination value and the address value of the N response signals.

[0125] In operation S930, the controller sends a control signal to the N candidate devices according to the target address value, so that when the target device receives the control signal, the matching sub-circuit of the target device is electrically connected to the control circuit.

[0126] The controller sends a position determination signal to N candidate devices and receives response signals corresponding to the position determination signal from the N candidate devices. Thus, the determination value of each of the N candidate devices can be determined. Based on this, even if the N candidate devices are adjusted, the determination value of each of the N candidate devices can be obtained again through the position determination signal and the response signal. Furthermore, the target device at the end of the control circuit can be re-determined according to the determination value. Based on this, the efficiency of determining the target device is improved, and further the efficiency of resistance matching between the head end and the end of the control circuit is improved.

[0127] The embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It should be noted that, for the implementation manners not depicted or described in the drawings or the text of the specification, they are all forms known to those of ordinary skill in the art and are not described in detail. In addition, the definitions of the above elements and methods are not limited to the specific structures, shapes or manners mentioned in the embodiments, and those of ordinary skill in the art can make simple changes or substitutions thereto.

[0128] Throughout the drawings, the same elements are denoted by the same or similar reference numerals. When it may cause confusion in the understanding of the present disclosure, the conventional structures or configurations will be omitted.

[0129] Moreover, the shapes and sizes of the components in the drawings do not reflect the actual sizes and proportions, but only illustrate the content of the embodiments of the present disclosure. Additionally, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claims.

[0130] Unless otherwise known to the contrary, the numerical parameters in this specification and the appended claims are approximate values and can be changed according to the required characteristics obtained through the content of the present disclosure. Specifically, all the numbers representing the contents of components, reaction conditions, etc. used in the specification and the claims should be understood to be modified by the term "about" in all cases. Furthermore, the word "comprising" does not exclude the existence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the existence of a plurality of such elements.

[0131] The ordinal numbers such as "first", "second", "third", etc. used in the specification and the claims are used to modify the corresponding elements, and do not themselves mean that the elements have any ordinal numbers, nor do they represent the order of one element and another element or the order in the manufacturing method. The use of these ordinal numbers is only to clearly distinguish one element with a certain name from another element with the same name.

[0132] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The structure required to construct such systems will be apparent from the above description. Additionally, the present disclosure is not directed to any particular programming language. It should be understood that the present disclosure described herein can be implemented using various programming languages, and the descriptions of specific languages above are for the purpose of disclosing the best mode of the present disclosure.

[0133] The present disclosure can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. Each component embodiment of the present disclosure can be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art should understand that a microprocessor or a digital signal processor (DSP) can be used in practice to implement some or all of the functions of some or all of the components of the relevant devices according to the embodiments of the present disclosure. The present disclosure can also be implemented as a device or apparatus program (e.g., a computer program and a computer program product) for performing part or all of the methods described herein. Such a program implementing the present disclosure can be stored on a computer-readable medium, or can be in the form of one or more signals.

[0134] Those skilled in the art can understand that the modules in the devices in the embodiments can be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and in addition, they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, any combination can be adopted to combine all the features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all the processes or units of any method or device so disclosed. Unless otherwise explicitly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) can be replaced by an alternative feature that provides the same, equivalent, or similar purpose. And, in the unit claims listing several devices, several of these devices can be embodied by the same hardware item.

[0135] Similarly, it should be understood that, for the purpose of streamlining the present disclosure and facilitating the understanding of one or more of the various disclosed aspects, in the foregoing description of the exemplary embodiments of the present disclosure, the various features of the present disclosure are sometimes grouped together into a single embodiment, figure, or description thereof. However, the disclosed method should not be construed as reflecting an intention that the claimed present disclosure requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, the disclosed aspects lie in less than all of the features of the single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate embodiment of the present disclosure.

[0136] The specific embodiments described above further elaborate on the objectives, technical solutions, and beneficial effects of the present disclosure. It should be understood that the above description is only for the specific embodiments of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A control circuit, comprising: A controller; And N cascaded candidate devices, where N is a positive integer greater than 1; Wherein, the N candidate devices are configured to send N response signals corresponding to the N candidate devices to the controller according to a position determination signal from the controller. Among them, the determination value of the position determination bit of the nth response signal characterizes the relative position of the nth candidate device among the N candidate devices, and the address value of the nth response signal characterizes the address of the nth candidate device; Wherein, the controller is configured to determine the target address value of the target device according to the determination values and address values of the N response signals, and send a control signal to the N candidate devices according to the target address value, so that when the target device receives the control signal, the matching sub-circuit of the target device is electrically connected to the control circuit.

2. The circuit according to claim 1, wherein, The matching sub-circuit of the target device includes a first switch and a matching resistor, and the first switch of the target device and the matching resistor of the target device are connected in series; The first switch of the target device is configured to close when receiving the control signal, so as to electrically connect the matching sub-circuit of the target device to the control circuit by electrically connecting the matching resistor of the target device to the control circuit.

3. The circuit according to claim 1, wherein, The controller includes a first switch and a matching resistor, and the first switch of the controller and the matching resistor of the controller are connected in series. The first switch of the controller closes when the candidate device is determined to be the controller, so as to electrically connect the matching resistor of the controller to the control circuit.

4. The circuit according to claim 1, wherein, The candidate device includes a signal processing sub-circuit and a matching sub-circuit; Wherein, the nth signal processing sub-circuit is connected in series with the (n - 1)th signal processing sub-circuit, and the nth signal processing sub-circuit is configured to output the nth position determination signal according to the (n - 1)th position determination signal. Among them, the determination value of the (n - 1)th position determination signal is different from the determination value of the nth position determination signal, n = 2... N; Wherein, the nth matching sub-circuit is connected to the nth signal processing sub-circuit, and the nth matching sub-circuit is configured to output the nth response signal having the same determination value as the nth position determination signal according to the nth position determination signal.

5. The circuit according to claim 4, wherein, The nth signal processing sub-circuit is further configured to receive the nth response signal from the nth matching sub-circuit and send the nth response signal to the controller, where the flag value of the flag bit of the response signal is different from the flag value of the flag bit of the position determination signal, so that when the nth signal processing sub-circuit receives the nth response signal, it does not process the nth response signal.

6. The circuit according to claim 4, wherein, The nth signal processing sub - circuit is further configured to calculate the check value of the nth check bit according to the nth determination value and the (n - 1)th position determination signal, and output the nth position determination signal according to the nth determination value, the (n - 1)th position determination signal, and the check value of the nth check bit.

7. The circuit according to claim 4, wherein The nth signal processing sub - circuit includes an nth signal processing unit; Wherein, the nth signal processing unit is configured to add a predetermined value to the determination value of the (n - 1)th position determination signal to obtain the nth determination value, and output the nth position determination signal according to the nth determination value and the (n - 1)th position determination signal.

8. The circuit according to claim 7, wherein, The N signal processing sub - circuits are connected to each other through a bus based on the RS485 communication protocol. The bus includes a first bus and a second bus; The nth signal processing sub - circuit further includes a first transceiver and a second transceiver; Wherein, the first transceiver, the nth signal processing unit, and the second transceiver are connected in series in sequence; The first input end of the first transceiver and the first input end of the second transceiver are both connected to the first bus, and the second input end of the first transceiver and the second input end of the second transceiver are both connected to the second bus.

9. The circuit according to claim 8, wherein, The nth signal processing sub - circuit further includes a second switch and a third switch. The first end of the second switch is connected to the first input end of the first transceiver, the second end of the second switch is connected to the first input end of the second transceiver, the first end of the third switch is connected to the second input end of the first transceiver, and the second end of the third switch is connected to the second input end of the second transceiver; Wherein, the second switch and the third switch are configured to close when receiving the switch - closing signal from the controller to disconnect the nth signal processing unit from the bus.

10. The circuit according to claim 9, wherein, The second switch and the third switch are further configured to open when receiving a reset signal to electrically connect the nth signal processing unit to the bus.

11. A control method is applied to the signal processing circuit according to any one of claims 1 - 10. The method includes: The N candidate devices send N response signals corresponding to the N candidate devices to the controller according to the position determination signal from the controller; The controller determines the target address value of the target device according to the determination value and the address value of the N response signals, and sends a control signal to the N candidate devices according to the target address value, so that when the target device receives the control signal, the matching sub - circuit of the target device is electrically connected to the control circuit.

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