Quick and accurate updating method for switch key value cache, electronic equipment and medium

Abstract

The invention discloses a method for quickly and accurately updating a switch key value cache, which comprises the following steps of: distributing enough switch resources according to a cache size specified by a user, realizing logic storage through circulation, and creating two queues for query and key value pairs; allocating switch resources and creating a multi-slot buffer area for matching query and key value pairs; processing read queries through a single producer-single consumer algorithm in a switch pipeline, while write queries are sent to key value storage nodes to maintain cache coherency; identifying a new hotspot key by tracking hit times and using a voting mechanism; and replacing the unpopular key with the new hotspot key, and obtaining new data from the storage node.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer networks, and in particular relates to a method for quickly and accurately updating a switch key-value cache, an electronic device, and a medium. Background Art

[0002] Key-value storage (KV storage) is a widely used storage paradigm that serves various application scenarios, such as distributed file systems and graph storage. In order to speed up reading, a cache is set up in front of the storage system. Programmable switches are often used to improve cache performance and thus speed up data reading due to their hardware advantages, such as customized logic, high throughput and low latency, as well as reasonable prices. However, there are two problems with existing switch-accelerated KV caches: first, the count-min sketch causes a large number of false positives, misleading cache updates; second, cache updates rely on slow paths, resulting in high update delays. These problems prevent hot KV pairs from being updated in real time, affecting performance and query latency. Summary of the invention

[0003] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a method, electronic device, and medium for fast and accurate update of a switch key-value cache. The present invention utilizes the powerful cycle capability of the switch, that is, caches hot key-value pairs by continuously cycling in the switch ASIC pipeline, avoiding caching key-value pairs in the register array at each stage, thereby increasing the cache update speed, bypassing performance bottlenecks, and achieving the purpose of real-time update.

[0004] In a first aspect, an embodiment of the present invention provides a method for quickly and accurately updating a switch key-value cache, the method comprising:

[0005] Allocate switch resources and create query queues and key-value pair queues based on the target key-value cache size;

[0006] In the ASIC pipeline, a multi-slot buffer is created using switch resources, wherein the multi-slot buffer is used to store and match query and key-value pairs;

[0007] When a query is received, for each query, enumerate the cache slots in the multi-slot buffer; for each cache slot, hash the query into a register. If the register is empty, insert the query; if it is busy, continue to traverse the next cache slot. If all cache slots are busy, insert the query request into the query queue and wait for the next switch cycle. If the query request misses the cache or times out, the query request is sent to the key-value storage node. At the same time, continuously take key-value pairs from the key-value pair queue and traverse the multi-slot buffer. If the traversed request is a read query and the keys match, return the value corresponding to the key. If the current query is a write query, regardless of whether the keys match, send the write query to the key-value storage node. If the write query matches the key, discard the key-value pair in the cache to maintain cache consistency.

[0008] For each key in the key-value pair queue, record the number of hits. After exceeding the hit threshold, mark it as a hot key. For keys that are not in the key-value pair queue but are queried, use a voting mechanism in the hash table to determine whether they are hot keys.

[0009] Perform cache update in real time according to the situation of hot keys.

[0010] In a second aspect, an embodiment of the present invention provides an electronic device, including a memory and a processor, where the memory is coupled to the processor. Among them, the memory is used to store program data, and the processor is used to execute the program data to implement the above-mentioned method for quickly and accurately updating the switch key-value cache.

[0011] In a third aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the above-mentioned method for quickly and accurately updating the switch key-value cache is implemented.

[0012] In a fourth aspect, an embodiment of the present invention provides a computer program product, including a computer program / instructions. When the computer program / instructions are executed by a processor, the above-mentioned method for quickly and accurately updating the switch key-value cache is implemented.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0014] The present invention provides a method for quickly and accurately updating the switch key-value cache, which supports precise hotspot detection and fast cache update. By continuously cycling and processing hot key-value pairs in the switch ASIC pipeline, the present invention avoids caching key-value pairs in the register array at each stage. The present invention makes full use of the switch hardware resources, improves the cache update speed and accuracy, and improves the overall throughput and query efficiency. This method not only improves the performance of key-value storage but also reduces query latency, significantly improving the performance of the key-value cache. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0016] Figure 1 It is a schematic diagram of a switch-accelerated key-value cache system and method that supports precise hotspot detection and rapid cache update provided by an embodiment of the present invention;

[0017] Figure 2 It is a schematic diagram of the architecture provided by an embodiment of the present invention;

[0018] Figure 3 It is a processing key-value query diagram provided by an embodiment of the present invention;

[0019] Figure 4 It is a detected hot key diagram provided by an embodiment of the present invention;

[0020] Figure 5 It is a cache update diagram provided by an embodiment of the present invention;

[0021] Figure 6 It is a schematic diagram of an electronic device provided by an embodiment of the present invention. Specific Embodiments

[0022] The present invention will be described in detail below with reference to the drawings and specific embodiments. This embodiment is implemented on the premise of the technical solution of the present invention, and gives detailed implementation manners and specific operation processes. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0023] As Figure 1 shown, the present invention provides a switch-accelerated key-value cache system and method that supports precise hotspot detection and rapid cache update, processes queries at the hardware level, provides low-latency and high-throughput cache services, and at the same time maintains the consistency and dynamic update of cache data. The method specifically includes the following steps:

[0024] Step S1, allocate switch resources and create a query queue and a key-value pair queue according to the target key-value cache size.

[0025] Specifically, according to the maximum number of key-value pairs nkv that can be stored in the set runtime key-value cache, the maximum value lkey of the key in any runtime key-value pair, and the maximum value lval of the value in any runtime key-value pair, set the number of switch ports n in loopback mode and the size λ of the traffic manager buffer allocated for recycling;

[0026] According to the maximum number of key-value pairs nkv that can be stored in the set runtime key-value cache, the maximum value lkey of the key in any runtime key-value pair, and the maximum value lval of the value in any runtime key-value pair, at least nkv·(lkey + lval) bits of storage capacity need to be provided;

[0027] Assume that n switch ports are set to loopback mode (by default, the total number n of loopback ports is set to the number of built-in ports dedicated to recycling in the switch), and the pipeline of each port can cache at most α key-value pairs; when nkv ≤ n·α, there is no need to cache KV pairs in the traffic manager; when nkv > n·α, for the remaining nkv - n·α key-value pairs, they need to be cached in the traffic manager, and the expression for the size λ of the traffic manager buffer allocated for recycling is as follows:

[0028] λ = max(0, nkv - n·α)·(lkey + lval), n ∈ Z

[0029] In the formula, Z is a positive integer.

[0030] Furthermore, the key-value pair queue is used to cache key-value pairs; when a new key-value pair is added to the key-value pair queue, the new key-value pair will be inserted at the tail of the key-value pair queue. When the key-value pair becomes the head of the key-value pair queue, the key-value pair is extracted from the current key-value pair queue for matching with the query execution. After the matching is completed, the key-value pair is inserted back to the tail of the key-value pair queue again.

[0031] Furthermore, the query queue is used to cache those queries waiting to be processed.

[0032] It should be noted that the loopback ability in the programmable switch is as follows: to provide the loopback ability, each programmable switch can set multiple switch ports to loopback mode. Each loopback port is associated with a pipeline that no longer processes external traffic but continuously loops and transmits hot KV pairs. The loopback pipeline consists of two parts: the ingress pipeline and the egress pipeline. When a KV pair that needs to be looped is received, the ingress pipeline forwards the KV pair to the buffer in the traffic manager (TM), and then the egress pipeline extracts the KV pair from the buffer and transfers it back to the starting point of the ingress pipeline. In this way, the switch can cache KV pairs.

[0033] For example, the switch has ports A - E. Port A receives query or hot KV pairs, port B replies with responses, and the other ports are in loopback mode. Each port circularly caches α KV pairs. Each KV pair received by port A is sent to a loopback port (such as port C). The pipeline of port C caches these KV pairs by cycling them back and forth between the input pipeline Ci and the output pipeline Ce. It should be noted that the pipelines of normal ports and loopback ports can access the same switch memory space. Therefore, when a read query enters the pipeline of port A, we can use the shared memory space to match the query processed by port A with the circular KV pairs in the pipelines of other loopback ports.

[0034] It should be noted that the ASIC pipeline of the switch provides line - speed performance, which means that operations on the switch ASIC pipeline can process queries at a high speed of several Tbps. Therefore, even though there is a query cache queue, queries can still be processed in the high - speed pipeline and maintain efficient performance. Through this mechanism, not only can sudden query loads be handled, but also the matching of the switch's processing capacity and query traffic can be ensured, avoiding potential performance bottlenecks or query loss.

[0035] Step S2, in the ASIC pipeline, create a multi - slot buffer using switch resources, and the multi - slot buffer is used to store, match queries and key - value pairs.

[0036] Furthermore, create a multi - slot buffer using the pipeline stage resources of the switch. Among them, the multi - slot buffer consists of several slots, each slot is a register array with several registers, and each register array can match queries and circular key - value pairs.

[0037] Step S3, when a query is received, for each query, enumerate the cache slots in the multi - slot buffer; for each cache slot, hash the query to the register. If the register is empty, insert the query, and if it is busy, continue to traverse the next cache slot; if all cache slots are busy, insert the query request into the query queue and wait for the next switch cycle; if the query request does not hit the cache or times out, the query request is sent to the key - value storage node; at the same time, continuously take out key - value pairs from the key - value pair queue and traverse the multi - slot buffer. If the traversed request is a read query and the keys match, return the value corresponding to the key; if the current query is a write query, regardless of whether the keys match, send the write query to the key - value storage node. If the write query matches the key, discard the key - value pair in the cache to maintain cache consistency.

[0038] Furthermore, as Figure 2 and Figure 3As shown, each query embeds its key fields into the TCP / UDP data payload and assigns a target TCP / UDP port number to the query to distinguish it; set the query fields, and the query fields include: OP (operator, used to specify the query type, and the query type includes read query GET, or write query PUT / DELETE), specify the query type, the sequence number of the query (SEQ, used to identify the query order), key and value; when OP is GET or DELETE, the value is empty;

[0039] When the query arrives at the switch, parse the query; including: parsing the data packet header, and the header includes Ethernet, IP, and TCP / UDP headers; when parsing the TCP / UDP header, determine whether the port number corresponds to the port number of the query, if so, extract the value of the query field from the data payload;

[0040] After the query parsing is completed, use a multi-slot buffer to cache the query, and asynchronously use the key-value pairs stored in the switch loop to match the cached query.

[0041] Furthermore, when the processing of the read query is completed, a response will be generated to respond to this query. Specifically, the packet format of such responses is specified by the user. For example, the user can specify that a query received through port A will receive a UDP-based response sent from port B. In addition, different queries can also be set to receive responses with different field values (for example, different IP addresses).

[0042] Generally speaking, read queries are processed using the producer-consumer algorithm, where the "producer" is the read query in the multi-slot buffer, and the "consumer" is the key-value pairs in the key-value pair queue; write queries are sent to the key-value storage node to maintain cache consistency.

[0043] When a read query enters the switch, it locates a slot in the multi-slot buffer by hashing the query key. It sends the query to that slot. In the slot, it hashes the key again to locate a register within the slot). If the register is empty, the current query is the first query targeting that key. So, it inserts directly into the register and waits for subsequent matches. If the register stores a query marked as unprocessed, the timer of the old query is checked. If the old query times out, i.e., it doesn't match any cached key-value pair, it is sent to the key-value storage node due to a cache miss, and the new query is inserted. Specifically, the timer threshold t for determining timeout is set to the maximum time for any cached key-value pair to complete a full cycle, i.e., the time between two consecutive matches of the same key-value pair on the same register. In our testbed switch, t is set to 2 microseconds. Additionally, if the old query doesn't time out, the new query is cached in the queue of circular queries. If the old query is marked as processed, it is replaced by the new query.

[0044] In addition to new queries, a circular query is continuously extracted from the head of its queue. It processes this query in the same way as described above.

[0045] Meanwhile, a circular KV pair is extracted from its queue. It hashes the key in the KV pair to locate the buffer slot and transfers the key to that slot. In the slot, the key is hashed to locate the register. If the register caches a query that has not been matched yet and the target key is the same as the KV pair, the query is successfully matched with the KV pair. In this case, it generates a response and issues the response. At the same time, it marks the query stored in the register as processed to make room for subsequent queries. It increments the counter associated with the KV pair and records the number of successful matches as one. Finally, the KV pair is cached again in the queue.

[0046] To maintain cache consistency, a simple but effective way is used to handle write queries. When a write query (such as a PUT or DELETE query) is received, it first checks whether the target key exists in the cache. If the key already exists in the cache, the cached KV pair is discarded. Then, the write query is forwarded to the storage node, and the storage node updates the corresponding value and replies to the query.

[0047] This processing method ensures that the data in the cache is consistent with the data in the main storage, avoiding data inconsistency problems caused by stale cache data. In this way, it guarantees the timely update of the cache during write operations and can quickly respond to read requests.

[0048] Step S4: For each key in the key-value pair queue, record the number of hits. After the number of hits exceeds the hit threshold, mark it as a hot key. For a key that is not in the key-value pair queue but is queried, use a voting mechanism in the hash table to determine whether it is a hot key.

[0049] Among them, as Figure 4 shown, for a key that is not in the key-value pair queue but is queried, the process of using a voting mechanism to determine whether it is a hot key includes:

[0050] Use a hash table containing several hash buckets to perform hashing on the key that is not hit but is queried in the key-value pair queue, and locate it to the hash bucket Bi;

[0051] If the hash bucket Bi is empty, fill this key into the hash bucket Bi;

[0052] Initialize the first counter and the second counter; the first counter is used to record the positive vote count, denoted as vote+; the second counter is used to record the negative vote count, denoted as vote-.

[0053] If the hash bucket Bi already contains a key, compare the current key with the old key in the hash bucket Bi. If the current key is the same as the old key in the hash bucket Bi, increment the positive vote count vote+ by 1; otherwise, increment the negative vote count vote- by 1;

[0054] Compare the positive vote count vote+ and the negative vote count vote-. If the negative vote count vote- exceeds the positive vote count vote+, insert the current key into the hash bucket Bi to replace the original key;

[0055] Set the positive vote count threshold θ. If the positive vote count vote+ of the current key in the hash bucket Bi exceeds the positive vote count threshold θ, then regard the current key as a hot key.

[0056] It should be noted that when the positive vote count of a key in the bucket exceeds the threshold θ, this key will be recognized as a hot key. Then it will be sent to the subsequent stage of cache update. And only positive votes, that is, the number of data packets using this key, determine the hot key detection. In contrast, negative votes cannot be used to determine whether the current key is popular because they are contributed by other irrelevant keys.

[0057] Step S5: Update the cache in real time according to the situation of hot keys.

[0058] Specifically, as Figure 5 shown, the step S5 includes:

[0059] Package each hot key into a read query, and input the read query into the storage node to obtain the corresponding value;

[0060] For each obtained value, create a key-value pair and insert the key-value pair into a stack in the switch ASIC pipeline;

[0061] For each key-value pair in the switch loop state, traverse the stack. If the successful match count of a key-value pair is lower than the threshold φ, then the key-value pair is a cold key-value pair; replace the cold key-value pair with the hot key-value pair at the top of the stack, so as to achieve cache update in the switch ASIC pipeline;

[0062] Among them, the stack is implemented on a register array. Each register stores a key-value pair, and the stack is addressed by index j. The initial value of index j is zero. When inserting a new key-value pair, the pair is inserted into stack Φ[j], and at the same time index j is incremented. When extracting the key-value pair at the head from the stack, index j is decremented at the same time.

[0063] Furthermore, it is also possible to set when to perform cache update; specifically including: setting the time tb to start monitoring hot key-value pairs and new hot keys, and the time te to terminate monitoring and start updating its cache by replacing cold key-value pairs with new hot key-value pairs. When the cache update starts, all cached queries will be first flushed to the key-value storage node to reply to these queries in a timely manner and avoid cache inconsistency. When the cache update ends, the successful match counter and the bucket of hot keys will be reset to prepare for subsequent cache updates.

[0064] In addition, one of the following strategies can be selected to handle ongoing read queries (i.e., queries arriving at the switch during cache update):

[0065] The first strategy: During cache update, these queries are directly processed by the key-value storage node;

[0066] The second strategy: Set to pause processing ongoing queries and temporarily cache them until the update is completed.

[0067] To sum up, traditional switch-accelerated KV caches usually use count-min sketch to detect hot KV pairs. However, due to limited resources, this method is prone to false positives, affecting the accuracy of cache update. In addition, traditional methods rely on the slow path of the switch operating system to update the cache, and the update rate is slow, resulting in the cache not being able to update hot KV pairs in real time, affecting query performance. Compared with traditional KV caches, the present invention continuously processes hot KV pairs in the switch ASIC pipeline, avoiding caching KV pairs in the register array at each stage, thus bypassing the bottleneck in traditional designs, making full use of switch hardware resources, improving the cache update speed and accuracy, and enhancing the overall throughput and query efficiency. This method not only improves the performance of key-value storage, but also reduces query latency, significantly improving the performance of key-value caches.

[0068] Example 1

[0069] This method is implemented on an Intel Barefoot 64x100Gbps Tofino and the storage nodes of some independent servers.

[0070] Switch data plane: In this example, the data structure and algorithm of the method of the present invention are implemented using the standard language P4 for programming data plane switches. There are two versions of the implementation of the example, with the same logic but targeting different generations of modern switches. One version is based on P4 14 , supporting existing switches; the other version is written in P4 16 and is suitable for the latest switch chips.

[0071] Storage node: Similar to NetCache, in this example, a KV storage is implemented using TommyDS in each storage node. This storage can provide a throughput of up to 10MQPS. At the same time, in this example, an agent is built in each node, which is responsible for interacting with the KV storage and processing incoming queries. The agent parses the queries, converts each query into an API call of the KV storage, and replies with a response to the source node. It supports multi-core expansion and uses receive-side scaling (RSS) to improve performance.

[0072] Reliability: To avoid service interruption and ensure reliability, the method of the present invention uses a certain fault tolerance mechanism. This mechanism uses another switch as a backup for the primary switch. The primary switch will send a copy of the KV pair to the backup switch, and the backup switch maintains a copy of the KV cache. Once the primary switch fails, the backup switch will become the primary switch and continue to provide services. After the primary switch recovers, it will act as the new backup switch.

[0073] Correspondingly, the present application also provides an electronic device, including: one or more processors; a memory for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the switch-accelerated key-value cache system and method for supporting accurate hot spot detection and fast cache update as described above. As Figure 6 shown, it is a hardware structure diagram of any device with data processing capabilities where the switch-accelerated key-value cache system and method for supporting accurate hot spot detection and fast cache update provided by the embodiment of the present invention are located. Except for Figure 6 the processors, memory, and network interfaces shown, any device with data processing capabilities where the device in the embodiment is located usually includes other hardware according to the actual functions of the any device with data processing capabilities, which will not be elaborated here.

[0074] Correspondingly, the present application further provides a computer-readable storage medium, on which computer instructions are stored. When the instructions are executed by a processor, they implement the switch acceleration key-value cache system and method for supporting accurate hotspot detection and rapid cache update as described above. The computer-readable storage medium may be an internal storage unit of any device with data processing capabilities described in any of the foregoing embodiments, such as a hard disk or memory. The computer-readable storage medium may also be an external storage device, such as a plug-in hard disk, a Smart Media Card (SMC), an SD card, a Flash Card, etc. equipped on the device. Further, the computer-readable storage medium may also include both an internal storage unit of any device with data processing capabilities and an external storage device. The computer-readable storage medium is used to store the computer program and other programs and data required by any device with data processing capabilities, and may also be used to temporarily store data that has been output or will be output.

[0075] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fast and accurate update of a switch key-value cache, characterized in that: The method comprises: Allocate switch resources and create query queues and key-value pair queues based on the target key-value cache size; In the ASIC pipeline, a multi-slot buffer is created using switch resources, wherein the multi-slot buffer is used to store and match query and key-value pairs; When a query is received, for each query, the cache slots in the multi-slot buffer are enumerated; for each cache slot, the query is hashed to the register, and if the register is empty, the query is inserted, and if it is busy, the next cache slot is traversed; if all cache slots are busy, the query request is inserted into the query queue and waits for the next switch cycle; if the query request does not hit the cache or times out, the query request is sent to the key-value storage node; at the same time, key-value pairs are continuously taken out from the key-value pair queue to traverse the multi-slot buffer. If the traversed request is a read query and the keys match each other, the value corresponding to the key is returned; if the current query is a write query, regardless of whether the keys match each other, the write query will be sent to the key-value storage node. If the write query matches the key, the key-value pair in the cache is discarded to maintain cache consistency. For each key in the key-value pair queue, the number of hits is recorded, and it is marked as a hot key after exceeding the hit threshold; for keys that are not in the key-value pair queue but are queried, a voting mechanism is used in the hash table to determine whether they are hot keys; The cache is updated in real time according to the hotkey situation.

2. A method for fast and accurate update of a switch key-value cache according to claim 1, characterized in that: Based on the target key-value cache size, the process of allocating switch resources includes: According to the set maximum number of key-value pairs that can be stored in the runtime key-value cache nkv, the maximum value of the key in any key-value pair lkey at runtime, the maximum value of the value in any key-value pair lval at runtime, the number of switch ports n in loopback mode and the size λ of the traffic manager buffer allocated for recirculation; According to the maximum number of key-value pairs that can be stored in the runtime key-value cache nkv, the maximum value of the key in any key-value pair at runtime lkey, and the maximum value of the value in any key-value pair at runtime lval, a storage capacity of at least nkv (lkey + lval) bits needs to be provided; Assume that n switch ports are set to loopback mode, and the pipeline of each port can cache up to α key-value pairs; when nkv≤n·α, there is no need to cache KV pairs in the traffic manager; when nkv>n·α, the remaining nkv-n·α key-value pairs need to be cached in the traffic manager. The size λ of the traffic manager buffer allocated for recycling is expressed as follows: λ=max(0,nkv-n·α)·(lkey+lval), n∈Z Wherein, Z is a positive integer.

3. A method for fast and accurate update of a switch key-value cache according to claim 1, characterized in that: The key-value pair queue is used to cache key-value pairs; when a new key-value pair is added to the key-value pair queue, the new key-value pair will be inserted into the tail of the key-value pair queue, and when the key-value pair becomes the head of the key-value pair queue, the key-value pair is extracted from the current key-value pair queue to perform matching with the query, and after the matching is completed, the key-value pair is inserted into the tail of the key-value pair queue again; The query queue is used to cache queries waiting to be processed.

4. A method for fast and accurate update of a switch key-value cache according to claim 1, characterized in that: The process of creating a multi-slot buffer using switch resources includes: A multi-slot buffer is created using pipeline stage resources of the switch; the multi-slot buffer is composed of a plurality of slots, each slot is a register array having a plurality of registers, each register can store a query and match the key-value pairs circulating in the key-value pair queue.

5. A method for fast and accurate update of a switch key-value cache according to claim 1, characterized in that: The process of handling a query includes: Each query embeds its key fields into the TCP / UDP data payload and specifies a target TCP / UDP port number for the query to distinguish the query; setting query fields, the query fields including: OP, specifying the query type, a sequence number of the query, a key, and a value; When the query arrives at the switch, the query is parsed; including: parsing the data packet header, the packet header including Ethernet, IP and TCP / UDP headers; when parsing the TCP / UDP header, determining whether the port number corresponds to the queried port number, and if so, extracting the value of the query field from the data payload; After parsing the query, a multi-slot buffer is used to cache the query, and the cached query is matched using the key-value pairs stored in the switch loop in an asynchronous manner.

6. A method for fast and accurate update of a switch key-value cache according to claim 1, characterized in that: For a key that is not in the key-value pair queue but is queried, the process of using a voting mechanism to determine whether it is a hot key includes: Use a hash table containing several hash buckets to hash the keys that are not hit in the key-value pair queue but are queried, and locate them in the hash bucket Bi; If the hash bucket Bi is empty, fill the key into the hash bucket Bi; Initialize a first counter and a second counter; the first counter is used to record the number of positive votes, recorded as vote+; the second counter is used to record the number of negative votes, recorded as vote-; If hash bucket Bi already contains a key, the current key and the old key in hash bucket Bi are compared. If the current key is the same as the old key in hash bucket Bi, the positive vote count vote+ is increased by one, otherwise, the negative vote count vote- is increased by one; Compare the positive votes vote+ and the negative votes vote-. If the negative votes vote- exceeds the positive votes vote+, insert the current key into the hash bucket Bi to replace the original key. Set the positive vote number threshold θ. If the positive vote number vote+ of the current key in the hash bucket Bi exceeds the positive vote number threshold θ, the current key will be used as a hot key.

7. A method for fast and accurate update of a switch key-value cache according to claim 1, characterized in that: The process of real-time cache update based on hotkey conditions includes: Encapsulate each hot key into a read query, and input the read query to the storage node to obtain the corresponding value; For each obtained value, create a key-value pair, and insert the key-value pair into a stack in the switch ASIC pipeline; Each key-value pair in the switch loop state traverses the stack. If the number of successful matches of a key-value pair is lower than the threshold φ, the key-value pair is considered a cold key-value pair. The cold key-value pair is replaced with the hot key-value pair at the top of the stack, thereby implementing cache updates in the switch ASIC pipeline. The stack is implemented on a register array, each register stores a key-value pair, and the stack is addressed by index j, the initial value of index j is zero, when a new key-value pair is inserted, the pair is inserted into the stack Φ[j], and the index j is increased by one, when the head key-value pair is extracted from the stack, the index j is decreased by one.

8. An electronic device, comprising a memory and a processor, characterized in that: The memory is coupled to the processor; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the switch key-value cache fast and accurate update method according to any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method for quickly and accurately updating the switch key-value cache as described in any one of claims 1 to 7 is implemented.

10. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the method for quickly and accurately updating the switch key-value cache described in any one of claims 1 to 7 is implemented.

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