ORU power control and PA protection system suitable for ORAN equipment

Abstract

The invention discloses an ORU power control and PA protection system suitable for ORAN equipment. The ORU power control and PA protection system comprises a power control adjustment system, a Powermeter power calculation system and a Pap protection and Zerofilling system. The power control adjustment system adjusts gains in the downlink and uplink processes; the Powermeter power calculation system calculates the power of uplink and downlink key nodes in real time, and the algorithm is realized by an FPGA (Field Programmable Gate Array); the Pap protection and Zerofilling system is divided into SW protection and FPGA protection, the SW protection is in radio software, and the PAP measure comprises the steps that overheat treatment can avoid PA work under the overheat condition, and DL gain adjustment can avoid abnormal large signals passing through the PA. According to the system, a modular design framework is adopted, different hardware schemes are convenient to transplant, the research and development period is shortened, the whole product research and development and test period is covered, seamless butt joint of equipment of different ORAN manufacturers is supported, signal simulation analysis of deep data simulation and analysis is carried out on multiple module points on a link, and the PA state is monitored and effectively protected in real time.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technologies, and particularly to an ORU power control and PA protection system applicable to ORAN devices. Background Art

[0002] Traditional ORU power control in mobile communication systems usually configures power based on fixed parameters (such as maximum transmit power, preset thresholds), and cannot adapt to dynamic network loads, user distributions, or channel conditions in real time. The core problems lie in staticity, inefficiency, and lack of coordination, making it difficult to meet the requirements of high energy efficiency, low latency, and high reliability in 5G / 6G networks, and it is difficult to dynamically balance energy conservation (such as reducing transmit power) and network performance (such as coverage, throughput).

[0003] Traditional PA (power amplifier) protection schemes rely on external sensors and feedback loops, resulting in long signal processing and decision-making times, making it difficult to cope with rapidly changing loads and input conditions, which may lead to untimely protection; moreover, the architecture uses analog circuits that are vulnerable to temperature, noise, etc., resulting in a decrease in detection accuracy and affecting the protection effect; and the hardware circuit design is fixed, making it difficult to adapt to different operating conditions or PA models, and the parameter adjustment is complex. Summary of the Invention

[0004] The purpose of the present invention is to provide an ORU power control and PA protection system applicable to ORAN devices to solve the problems raised in the above background art.

[0005] To achieve the above purpose, the present invention provides the following technical solution: An ORU power control and PA protection system applicable to ORAN devices, including a power control adjustment system, a Powermeter power calculation system, and a Pap protection and Zerofilling system;

[0006] The power control adjustment system adjusts the gain during the downlink and uplink processes; the Powermeter power calculation system calculates the power of key nodes in the uplink and downlink in real time, and the algorithm is implemented by an FPGA; the Pap protection and Zerofilling system is divided into SW protection and FPGA protection. The SW protection is in the radio software, and the PAP measures include: overheat protection can avoid PA operation in case of overheating, and DL gain adjustment can avoid abnormal large signals passing through the PA; in the FPGA protection, the PAP block is located between the DPD and JESD 204B, and the PAP trigger sources include: DUC overflow, 48V NOT OK, LTU_Unlock, PMU_Alarm, SRL;

[0007] The Pap protection and Zerofilling system includes SRL detection: calculating the difference between two adjacent samples and comparing it with the configured limit. The SRL detection is divided into I-channel detection and Q-channel detection.

[0008] Preferably, in the downlink of the power control adjustment system, the gain adjustment is used to make the output power of the antenna port within the allowable range of the downlink. In the uplink, the gain adjustment system makes the uplink gain within the acceptable range.

[0009] Preferably, the uplink gain adjustment of the power control adjustment system depends on the calibration table. No uplink power meter is required during the uplink gain adjustment process. The downlink gain control is adjusted after DUC, before CFR, after DPD, and after TOR ADC.

[0010] Preferably, the SW protection monitors the temperature and current of the PA. The radio software regularly supervises the PA temperature. Over-temperature processing can keep the PA working within the acceptable temperature range. If the PA temperature > NTB threshold, the O-RU will reduce the output power, so the PA temperature will decrease. If the PA temperature > ETH threshold, the O-RU will turn off the PA to prevent damage to the PA due to high temperature.

[0011] Preferably, the DL gain adjustment is to maintain the accuracy of the output power. The basic inputs of the DL gain adjustment are the TX average power and the FB average power.

[0012] Preferably, the PAP control of the Pap protection and Zerofilling system generates a PA protection control signal according to the trigger event. The trigger sources are:

[0013] Over-average-power protection, which supports detecting excessive DUC power and triggering PA protection;

[0014] Power-down PA protection, which supports detecting the External N48V NOK signal and triggering PA protection;

[0015] PA protection for PLL unlock of the clock unit, which supports detecting PLL unlock of the clock unit and triggering PA protection;

[0016] PA protection for unstable optical fiber link;

[0017] SRL protection;

[0018] PA protection for RU restart PMU, which supports PA protection during the RU soft restart process.

[0019] Preferably, the Pap protection and Zerofilling system displays the expected timing of the output PAP control signal. The output PAP control signal is:

[0020] pap_event_on, PAP event indicates to the power meter, notifying the power meter to stop the VCA due to PAP;

[0021] pap_shut_data, indicating data increase due to PAP;

[0022] pap_shut_pa, indicating PA shutdown due to PAP;

[0023] pap_shut_dpd, indicating stopping DPD due to PAP;

[0024] pap_shut_tx_low, indicating shutting down TX_Low due to PAP

[0025] Preferably, for the SRL detection of the Pap protection and Zerofilling system: If the limit value is exceeded, indicating an unexpected transient signal before JESD, the SRL control block shall perform the following operations:

[0026] Retain the previous sample data;

[0027] Slowly reduce the data to 0;

[0028] Wait for a configurable time;

[0029] Increase the gain.

[0030] Preferably, the process of PA protection configuration in the Pap protection and Zerofilling system in radio software is divided into three steps:

[0031] Initial PAP control delay, SRL parameters, and data rise parameters after radio startup;

[0032] The software configures according to the initial values of the registers;

[0033] After the initialization process is completed, the PA protection function block can start running. When the operator activation command is obtained, the software will enter the activation program.

[0034] Preferably, for the activation of PA protection configuration: Enable the PAP function and SRL detection according to the operator activation request. When the carrier activation request of the O-RU is received, the PA protection activation program will be executed to enable the PA protection to work correctly; Deactivation: Disable the PAP function and SRL detection according to the carrier deactivation request. When the carrier deactivation request of the O-RU is received and this is the last carrier on the O-RU, the PA protection deactivation program will be executed so that the PA protection can disable the PA protection.

[0035] Compared with the prior art, the beneficial effects of the present invention are:

[0036] The system modular design framework enables convenient transplantation of different hardware solutions, accelerates the R & D cycle, covers the entire product R & D and testing cycle, supports seamless docking of devices from different ORAN manufacturers, conducts in-depth data simulation and analysis of signal simulation at multiple module points on the link, and provides instant monitoring and effective protection of the PA status. Brief Description of the Drawings

[0037] Figure 1 It is a schematic diagram of the system of the present invention;

[0038] Figure 2 It is a schematic diagram of the signal chain for gain adjustment of the present invention;

[0039] Figure 3 It is a schematic diagram of the powermeter power calculation system of the present invention;

[0040] Figure 4 It is a schematic diagram of the result conversion module of the FPGA power meter of the present invention;

[0041] Figure 5 It is a schematic diagram of SW protection of the present invention;

[0042] Figure 6 It is a schematic diagram of FPGA PA protection of the present invention;

[0043] Figure 7 It is a schematic diagram of PAP control of the present invention;

[0044] Figure 8 It is a schematic diagram of SRL detection of the present invention;

[0045] Figure 9 It is a schematic diagram of data slow descent of the present invention;

[0046] Figure 10 It is a schematic diagram of data slow ascent of the present invention;

[0047] Figure 11 It is a schematic diagram of the software configuration process of the present invention;

[0048] Figure 12 It is a schematic diagram of the activation request of the present invention;

[0049] Figure 13 It is a schematic diagram of the deactivation request of the present invention. Detailed Description of the Invention

[0050] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0051] Please refer to Figures 1-13 , the present invention provides a technical solution: an ORU power control and PA protection system applicable to ORAN devices, including a power control adjustment system, a Powermeter power calculation system, and a Pap protection and Zerofilling system;

[0052] The power control adjustment system adjusts the gain during the downlink and uplink processes; the Powermeter power calculation system calculates the power of key nodes in the uplink and downlink in real time, and the algorithm is implemented by FPGA; the Pap protection and Zerofilling system is divided into SW protection and FPGA protection. The SW protection is in the radio software, and the PAP measures include: overheat protection can avoid PA operation in case of overheat and DL gain adjustment can avoid abnormal large signals passing through the PA; in the FPGA protection, the PAP block is located between the DPD and JESD 204B, and the PAP trigger sources include: DUC overflow, 48V NOT OK, LTU_Unlock, PMU_Alarm, SRL; the FPGA protection includes most of the PA protection functions because the PA protection needs to take effect as soon as an abnormal signal is detected and can make a quick response within dozens of microseconds. If SW monitoring is used, the response time may be at the millisecond level;

[0053] The Pap protection and Zerofilling system includes SRL detection: calculating the difference between two adjacent samples and comparing it with the configured limit. The SRL detection is divided into I-channel detection and Q-channel detection.

[0054] The RF devices of this system can implement a unified system test and management solution, and realize the docking of RF devices and digital devices from different manufacturers.

[0055] In the Tx chain, the gain control points are as follows:

[0056] Carrier-based gain (DL GA0): Adjust the DL carrier flatness of each carrier. This gain adjustment point is carrier-based.

[0057] 6.5dB resampling gain: It is a fixed gain and does not change during the operation of the RU. The position is before the dpd.

[0058] Gain after DPD (DL GA1): Fine Tx link gain adjustment point and compensate for the nominal output power of the DPD, unified as TX druDig.

[0059] TX VOP (DL GA2): Adjust the Tx analog gain, which is used to cover the main parts of frequency change, temperature change, and component batch problems, unified as TX druVop.

[0060] TX DSA (DL GA3): Simulate the TX external DSA (PA part) separately, mainly used to cover the dynamic range of the Tx power stage, unified as TX extDsa.

[0061] PA VDD Temperature Compensation: Compensate for the temperature drift of PA VDD.

[0062] PA Bias Temperature Compensation: Compensate for the temperature drift of the PA bias.

[0063] In the FB chain, there are two gain control points:

[0064] 1. FB Analog DSA: Used to adjust the FB gain at different power levels and compensate for FB link temperature changes and frequency changes when needed, unified as FB druDsa.

[0065] 2. FB Digital VGA: Mainly used to compensate for FB link temperature changes and frequency changes, unified as FB druDig.

[0066] In the Rx chain, the gain control points are as follows:

[0067] 1. RX VGA (UL GA0): The main point for UL gain adjustment, used to cover RX link frequency changes, temperature changes, and component batch processing issues (step: 1dB), unified as RX Vga.

[0068] 2. RX DSA (UL GA1): Adjust the RX analog gain. In 4T4R micro radio products, considering the strict noise figure requirements, the RX DSA is set to 0dB by default and will not change during the UL gain adjustment, unified as RX druDsa.

[0069] 3. RX Digital Gain (UL GA2): The main point for UL gain adjustment, used to cover RX link frequency changes, temperature changes, and component batch processing issues, (fractional part), unified as RX druDig.

[0070] 4. DDC Gain (UL GA3): Adjust the UL carrier flatness of each carrier. This gain adjustment point is carrier-based, refer to the power scaling function description.

[0071] 5. AGC Gain: Only used to compensate for the AGC gain.

[0072] Frequency Compensation Table:

[0073] Feedback Frequency Compensation Table:

[0074] The format of the frequency compensation table is [x, y]:

[0075] X represents the incremental frequency value relative to the center frequency point of the entire frequency band. The frequency step size shall not be less than the minimum carrier bandwidth supported by the product. It is estimated that the minimum carrier bandwidth supported by the product is 5 MHz, so a 5 MHz step size is defined.

[0076] Y represents the incremental value at different frequencies.

[0077] The following is an example of the FB frequency compensation table. X ranges from -100 MHz to 100 MHz and y is equal to zero.

[0078] [3400000,850],[3405000,850],[3410000,850],[3415000,850],[3420000,850],[3425000,850],[3430000,850],[3435000,850],[3440000,850],[3445000,850],[3450000,850],[3455000,850],[3460000,850],[3465000,850],[3470000,850],[3475000,850],[3480000,850],[3485000,850],[3490000,850],[3500000,850],[3505000,850],[3510000,850],[35

[0079] 15000,850],[3520000,850],[3525000,850],[3530000,850],[3535000,850],[3540000,850],[3545000,850],[3550000,850],[3555000,850],[3560000,850],[3565000,850],[3570000,850],[3575000,850],[3580000,850],[3585000,850],[3590000,850],[3600000,85 0]

[0080] rx link frequency compensation table:

[0081] The format of the frequency compensation table is [x, y]:

[0082] X represents the incremental frequency value relative to the center frequency point of the entire frequency band. The frequency step size shall not be less than the minimum carrier bandwidth supported by the product. It is estimated that the minimum carrier bandwidth supported by the product is 5 MHz, so a 5 MHz step size is defined.

[0083] Y represents the incremental value compared to the average gain exceeding 2.5 MHz at the center frequency of the entire frequency band.

[0084] The following is an example of the Rx frequency compensation table. x ranges from -100 MHz to 100 MHz (center frequency 3500 MHz), y is equal to zero, and FreTabRef represents the average gain for all different x values.

[0085] [3400000,0],[3405000,0],[3410000,0],[3415000,0],[3420000,0],[3425000,0],[3430000,0],[3435000,0],[3440000,0],[3445000,0],[3450000,0],[3455000,0],[3460000,0],[3465000,0],[3470000,0],[3475000,0],[3480000,0],[3485000,0],[3490000,0],[3495000,0],[3500000,0],[3505000,0],[3510000,0],[3515000,0],[3520000,0],[3525000,0],[3530000,0],[3535000,0],[3540000,0],[3545000,0],[3550000,0],[3555000,0],[3560000,0],[3565000,0],[3570000,0],[3575000,0],[3580000,0],[3585000,0],[3590000,0],[3595000,0],[3600000,0]

[0086] Temperature compensation table:

[0087] Feedback temperature compensation table:

[0088] The format of the frequency compensation table is [x, y]:

[0089] X represents temperature. The ambient temperature range outdoors is from -40 degrees Celsius to +55 degrees Celsius. Considering the acceptable temperature range inside the O-RU, its temperature range will be from -40 degrees Celsius to +105 degrees Celsius, and the temperature step is 5 degrees Celsius.

[0090] Y represents the absolute compensation value at different temperatures.

[0091] The following is an example of the FB temperature compensation table. x ranges from -40 degrees Celsius to +105 degrees Celsius, and y is equal to zero.

[0092] [-400,0],[-350,0],[-300,0],[-250,0],[-200,0],[-150,0],[-100,0],[-50,0],[0,0],[50,0],[100,0],[150,0],[200,0],[250,0],[300,0],[350,0],[400,0],[450,0],[500,0],[550,0],[600,0],[650,0],[700,0],[750,0],[800,0],[850,0],[900,0],[950,0],[1000,0],[1050,0]

[0093] RX Link Temperature Compensation Table:

[0094] The format of the frequency compensation table is [x, y]: x represents temperature. The outdoor ambient temperature range is from -40 degrees Celsius to +55 degrees Celsius. Considering the acceptable temperature range inside the O-RU, its temperature range will be from -40 degrees Celsius to +105 degrees Celsius. The temperature step is 5 degrees Celsius, and y represents the compensation value at different temperatures. The following is an example of the RX temperature compensation table, where x ranges from -40 degrees Celsius to +105 degrees Celsius and y equals 0.

[0095] [-400,00],[-350,10],[-250,20],[-150,30],[-50,40],[50,50],[150,60],[250,70],[350,80],[450,90],[550,100],[650,110],[750,120],[850,130],[950,140],[1050,150].

[0096] As Figure 3 shown, the powermeter power calculation system:

[0097] PWR_VCA_IFFT: A frequency domain powermeter placed after the downlink Oran output.

[0098] PWR_VCA_DUC: A powermeter placed after the DUC and before the CFR.

[0099] PWR_VCA_DPD: A powermeter placed after the DPD.

[0100] PWR_VCA_TOR: A powermeter located after the TOR ADC.

[0101] PWR_VCA_RX_ADC: A time domain signal powermeter placed after the ADC input.

[0102] PWR_VCA_FFT: A frequency-domain power meter placed after the uplink OFDM.

[0103] The FPGA power meter result conversion module uses the mantissa number (32 bits) and the shift number (17 bits) to indicate the result.

[0104] As Figure 4 shown, the function of this module is to first detect the most significant bit whose value is not 0, then, starting from this bit, obtain 16 digits, and finally, calculate how many least significant bits are left as the number of shifts.

[0105] Format: (0,48)

[0106] 0 - 31 bits: Mantissa

[0107] 32 - 48 bits: Shift

[0108] Equation:

[0109] num_samples = 491520

[0110] ad_da_full_pwr = 215

[0111]

[0112] PWR_value = mantissa * 2^shift

[0113] PWR_dBFs = 20log10(√(PWR_value / num_samples / ad_da_full_pwr)).

[0114] Pap protection and zerofilling system:

[0115] The Pap protection and zerofilling system is divided into SW protection and FPGA protection.

[0116] For SW protection in the radio software, the PAP measures include: 1) Overheat protection can avoid the PA operation in case of overheating; 2) DL gain adjustment can avoid abnormally large signals passing through the PA.

[0117] In the FPGA, the PAP block is located between the DPD and JESD 204B, and the PAP trigger sources include: 1) DUC overflow; 2) 48V NOT OK; 3) LTU_Unlock; 4) PMU_Alarm; 5) SRL.

[0118] As Figure 5As shown in the figure, over-temperature processing: The radio software should regularly monitor the PA temperature. Over-temperature processing enables the PA to always operate within an acceptable temperature range. Specifically, if the PA temperature > NTB threshold, the O-RU will reduce the output power, thus reducing the PA temperature. If the PA temperature > ETH threshold, the O-RU will turn off the PA to prevent damage to the PA due to high temperature.

[0119] DL gain adjustment: The purpose of DL gain adjustment is to maintain the accuracy of the output power. The basic inputs for DL gain adjustment are the TX average power and the FB average power. Generally, there must be some difference between the TX average power and the FB average power. The Radio software will configure the TX DSA to make the TX average power and the FB average power as close as possible.

[0120] Before adjusting the TX DSA, the radio software should check whether the difference between the TX average power and the FB average power is within an acceptable range.

[0121] The above gain adjustment scheme not only avoids adjusting the TX gain in a large step, thus generating transient signals, but also prevents the TX gain from being adjusted to a very small value, generating large signals through the PA.

[0122] As Figure 6 shown in the figure, FPGA PA protection: The PAP control can generate a PA protection control signal according to the trigger event.

[0123] The trigger sources are:

[0124] 1. Over-high average power protection, supporting detection of over-high DUC power and triggering PA protection (duc overflow);

[0125] 2. Power-down PA protection, supporting detection of the External N48V NOK signal to trigger PA protection;

[0126] 3. PA protection for PLL unlock in the clock unit, supporting detection of PLL unlock in the clock unit to trigger PA protection;

[0127] 4. PA protection for unstable optical fiber link;

[0128] 5. SRL protection;

[0129] 6. RU restart PMU protection, supporting PA protection during the RU soft restart process.

[0130] As Figure 7 shown in the figure, it shows the expected timing of the output PAP control signal. The output PAP control signal is:

[0131] pap_event_on, The PAP event is indicated to the power meter, notifying the power meter to stop the VCA due to PAP;

[0132] pap_shut_data, indicating the data increase due to PAP;

[0133] pap_shut_pa, indicating the PA shutdown due to PAP;

[0134] pap_shut_dpd, indicating the DPD stop due to PAP;

[0135] pap_shut_tx_low, indicating the TX_Low shutdown due to PAP.

[0136] SRL Detection:

[0137] Calculate the difference between two adjacent samples and compare it with the configured limit. If the limit value is exceeded, indicating an unexpected transient signal before JESD, the SRL control block shall perform the following operations:

[0138] 1. Retain the previous sample data

[0139] 2. Slowly reduce the data to 0

[0140] 3. Wait for a configurable time

[0141] 4. Increase the gain

[0142] As Figure 8 shown, when an SRL event is detected, it will trigger an action to reduce the power. This will take 550ns (configurable via the FPGA register) to reduce the data from full gain to 0. Leave 1us (configurable via the FPGA register) as the waiting time to avoid frequent SRL event strikes. When the SRL fault rises, DPD and VCA should be paused due to the distorted data.

[0143] SRL detection is divided into I-channel detection and Q-channel detection. The limit register can be configured, and it is currently designed as 20000, which will be adjusted according to the actual test results. The 20,000 in the following formula represents the limit register value, equivalent to 3db. Formula: 20*LOG10((65535 - 20000) / 65535) = 3db.

[0144] As Figures 9-10 shown, the data ramps up and down slowly: The data increase block is responsible for ramping the data from zero gain to full gain, and the Ramping down module ramps the data from full gain to zero. The recommended ramp-up / ramp-down time is 550ns, which can be configured via the FPGA register.

[0145] The PA protection interface is as follows:

[0146]

[0147] As Figure 11 shown, the process of PA protection configuration of the Pap protection and Zerofilling system in the radio software is divided into three steps:

[0148] The initial PAP control delay, SRL parameters, and data rise parameters after the radio starts;

[0149] The software is configured according to the initial values of the registers;

[0150] After the initialization process is completed, the PA protection function block can start running. When the operator activation command is obtained, the software will enter the activation program.

[0151] As Figures 12-13 shown, PA protection configuration activation: Enable the PAP function and SRL detection according to the operator activation request. When the carrier activation request of the O-RU is received, the PA protection activation program will be executed to enable the PA protection to work correctly; Deactivation: Disable the PAP function and SRL detection according to the carrier deactivation request. When the carrier deactivation request of the O-RU is received and this is the last carrier on the O-RU, the PA protection deactivation program will be executed so that the PA protection can disable the PA protection.

[0152] The system of the present invention is applicable to FDD and TDD digital front-end processing systems, and includes power monitoring and control of key links at all levels of PA in the analog link from the Lowphy, DUC / DDC, Post DPD of the digital link. The greatest advantage of this system lies in its dynamicity. We use digital signal processing technology to calculate and control the power at all levels in real time using FPGA algorithms in the digital domain, and then report the data back to the register through the arm. The parameters are automatically adjusted according to the working conditions, which greatly improves the response speed and accuracy. The PA protection mechanism also passes through a self-developed algorithm, passes the SRL detection, and combines multiple detection mechanisms (average power over-high protection, power-off PA protection, clock unit phase-locked loop unlock PA protection, RU restart PMU protection, PA over-temperature and over-voltage protection, carrier establishment process PA protection) to protect the safety of the PA as much as possible. The present invention can implement a unified system test and management scheme for Oran-based radio frequency devices, and realize the docking of radio frequency devices and digital devices from different manufacturers.

[0153] The content not detailedly described in this specification belongs to the prior art well-known to those skilled in the art. Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An ORU power control and PA protection system applicable to ORAN equipment, characterized in that: Including power control adjustment system, Powermeter power calculation system, Pap protection and Zerofilling system; The power control adjustment system adjusts the gain during the downlink and uplink processes; the Powermeter power calculation system calculates the power of key uplink and downlink nodes in real time, and the algorithm is implemented by FPGA; The Pap protection and Zerofilling system are divided into SW protection and FPGA protection. The SW protection is in the radio software. The PAP measures include: overheating treatment can avoid PA operation under overheating conditions and DL gain adjustment can avoid abnormal large signals passing through the PA. In FPGA protection, the PAP block is located between DPD and JESD204B. The PAP trigger sources include: DUC overflow, 48V NOT OK, LTU_Unlock, PMU_Alarm, SRL. The Pap protection and Zerofilling system includes SRL detection: the difference between two adjacent samples is calculated and compared with the configured limit. SRL detection is divided into I-way detection and Q-way detection.

2. The ORU power control and PA protection system applicable to ORAN equipment according to claim 1, characterized in that: In the downlink of the power control adjustment system, gain adjustment is used to make the output power of the antenna port within the allowable range of the downlink, and in the uplink, the gain adjustment system makes the uplink gain within the acceptable range.

3. The ORU power control and PA protection system applicable to ORAN equipment according to claim 1, characterized in that: The uplink gain adjustment of the power control adjustment system depends on the calibration table. The uplink power table is not required during the uplink gain adjustment process. The downlink gain control is adjusted after DUC, before CFR, after DPD, and after TOR ADC.

4. The ORU power control and PA protection system applicable to ORAN equipment according to claim 1, characterized in that: The SW protection monitors the temperature and current of the PA. The radio software periodically supervises the PA temperature. The over-temperature handling enables the PA to always operate within an acceptable temperature range. If the PA temperature > NTB threshold, the O-RU will reduce the output power, so the PA temperature will decrease. If the PA temperature > ETH threshold, the O-RU will shut down the PA to prevent the PA from being damaged due to high temperature.

5. The ORU power control and PA protection system applicable to ORAN equipment according to claim 1, characterized in that: The DL gain adjustment is to maintain the accuracy of the output power, and the basic inputs of the DL gain adjustment are the TX average power and the FB average power.

6. The ORU power control and PA protection system applicable to ORAN equipment according to claim 1, characterized in that: The PAP protection and PAP control of the Zerofilling system generate a PA protection control signal according to a trigger event, and the trigger source is: Average power over-protection, supports detection of DUC power over-high and triggers PA protection; Power-off PA protection, supports detection of External N48V NOK signal to trigger PA protection; PA protection when the clock unit phase-locked loop loses lock. It supports detecting the clock unit phase-locked loop loss to trigger PA protection. Unstable PA protection for optical fiber links; SRL protection; RU restart PMU protection, supporting PA protection during RU soft restart.

7. The ORU power control and PA protection system applicable to ORAN equipment according to claim 1, characterized in that: The PAP protection and Zerofilling system displays the expected timing of the output PAP control signal, and the output PAP control signal is: pap_event_on, PAP event indication to the power meter, notifying the power meter to stop VCA due to PAP; pap_shut_data, indicating the increase in data due to PAP; pap_shut_pa, indicating that the PA is shut down due to PAP; pap_shut_dpd, which means stopping DPD due to PAP; pap_shut_tx_low, indicating that TX_Low is turned off due to PAP.

8. The ORU power control and PA protection system applicable to ORAN equipment according to claim 1, characterized in that: The Pap protection and SRL detection of the Zerofilling system: If the limit value is exceeded, indicating that there is an unexpected transient signal before JESD, the SRL control block should perform the following operations: Keep the previous sample data; Slowly reduce the data to 0; Wait a configurable amount of time; Increase gain.

9. The ORU power control and PA protection system applicable to ORAN equipment according to claim 1, characterized in that: The process of PA protection configuration in the radio software of the Pap protection and Zerofilling system is divided into three steps: Initial PAP control delay, SRL parameters and data rise parameters after radio startup; The software is configured according to the initial values ​​of the registers; After the initialization process is completed, the PA protection function block can start running. When the operator activation command is obtained, the software will enter the activation procedure.

10. The ORU power control and PA protection system applicable to ORAN equipment according to claim 9, characterized in that: The PA protection configuration activation: enabling the PAP function and SRL detection according to the operator activation request. When receiving the carrier activation request from the O-RU, the PA protection activation procedure will be executed to enable the PA protection to work correctly; Deactivation: Disable PAP function and SRL detection according to carrier deactivation request. When a carrier deactivation request is received from O-RU and this is the last carrier on O-RU, PA protection deactivation procedure will be executed so that PA protection can be disabled.

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