A low-capacity TVS tube and its preparation method

Abstract

The present invention provides a low-capacitance TVS tube and a preparation method thereof. The method comprises providing a P-type substrate with a groove, and a first N+ layer and a first N-layer sequentially provided on the groove. A first isolation dielectric layer is provided on both sides of the first N+ layer perpendicular to the epitaxial growth direction, and a second isolation dielectric layer is provided on both sides of the first N-layer perpendicular to the epitaxial growth direction. A side of the first N-layer remote from the first N+ layer is doped with P-type ions, and a first region of the first N-layer doped with P-type ions is connected to an electrode. Specifically, because a large aspect ratio is used to etch the groove, there are no difficulties in deepening the groove and no risk of insufficient filling of the isolation dielectric layer, thereby greatly reducing the process difficulty. Simultaneously, the isolation dielectric layer is used to provide isolation in advance, and there is no isolation failure caused by diffusion and alignment problems. In addition, the width of the PN junction can be flexibly adjusted according to design requirements without mutual constraints, thereby increasing surge capability and reducing capacitance.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a low-capacitance TVS tube and a preparation method thereof. Background Art

[0002] As the electronics industry booms, various electronic products, such as smartphones, IoT devices, and high-speed communication base stations, are placing increasingly stringent demands on circuit protection components. Low-capacitance TVS diodes are widely used due to their ability to effectively suppress transient overvoltages in capacitance-sensitive environments in high-speed signal lines.

[0003] However, the structural design of traditional low-capacitance TVS tubes limits their surge current carrying capacity. When encountering high-intensity transient surges, it is often difficult to effectively protect the circuit, causing equipment failure or even damage.

[0004] The traditional low-capacitance TVS tube structure uses deep trenches for isolation. There are two problems. First, deep trenches require extremely high equipment capabilities, and the trenching and filling processes are relatively difficult. Second, the low-capacitance diode and TVS diode are stacked vertically and have the same junction area. Although the surge capability of the TVS can be improved by increasing the junction area, the capacitance of the low-capacitance diode above will increase with the increase in area, which is not worth the cost. Summary of the Invention

[0005] Based on this, the purpose of the present invention is to provide a low-capacitance TVS tube and a preparation method thereof, aiming to reduce the process difficulty, reduce the failure caused by trenching and filling, and at the same time, increase the surge capability of the TVS tube and reduce the capacitance of the low-capacitance diode.

[0006] A low capacitance TVS tube according to an embodiment of the present invention includes a first P-type substrate with a groove, a first N+ layer and a first N- layer sequentially provided on the groove;

[0007] In which, a first isolation dielectric layer is arranged on both sides of the first N+ layer perpendicular to the epitaxial growth direction, and a second isolation dielectric layer is arranged on both sides of the first N- layer perpendicular to the epitaxial growth direction. The side of the first N- layer away from the first N+ layer is doped with P-type ions, and the first region doped with P-type ions in the first N- layer is connected to the electrode.

[0008] Furthermore, the doping concentration of the first P-type substrate is 1E17 atom / cm 3 ~9E19 atoms / cm 3 .

[0009] Furthermore, the depth of the groove is 2 μm to 10 μm.

[0010] Furthermore, the thickness of the first isolation dielectric layer is 1 μm to 3 μm.

[0011] Furthermore, the impurity of the first N+ layer is As element, and the doping concentration is 1E13 atom / cm 3 ~9E17atom / cm 3 .

[0012] Furthermore, the thickness of the second isolation dielectric layer is 10 μm to 20 μm.

[0013] Furthermore, the impurity of the first N-layer is P element or As element, and the doping concentration is 1E12 atom / cm 3 ~9E14 atoms / cm 3 .

[0014] Furthermore, the impurity doped with P-type ions in the first N-layer is B element with a concentration of 1E14atom / cm 3 ~9E16atom / cm 3 .

[0015] A method for preparing a low-capacitance TVS tube according to an embodiment of the present invention is used to prepare the aforementioned low-capacitance TVS tube, the method comprising:

[0016] Providing a P-type substrate, and etching a groove on the P-type substrate;

[0017] Depositing an oxide layer in the groove and etching the middle portion of the oxide layer to obtain a first isolation dielectric layer;

[0018] Epitaxially grow the initial N+ layer, and then grind it flat to obtain the first N+ layer;

[0019] Depositing an oxide layer on the entire surface and etching the middle portion of the oxide layer to obtain a second isolation dielectric layer;

[0020] Depositing an initial N- layer in the groove formed by the second isolation dielectric layer and the first N+ layer, and polishing the groove to obtain a first N- layer;

[0021] P-type ions are doped on a side of the first N- layer away from the first N+ layer, and an electrode is deposited to connect to a first region of the first N- layer doped with P-type ions.

[0022] Compared with the existing technology: a P-type substrate with a groove is provided, and a first N+ layer and a first N- layer are sequentially provided on the groove; wherein, a first isolation dielectric layer is provided on both sides of the first N+ layer perpendicular to the epitaxial growth direction, and a second isolation dielectric layer is provided on both sides of the first N- layer perpendicular to the epitaxial growth direction, and the side of the first N- layer away from the first N+ layer is doped with P-type ions, and the first region doped with P-type ions in the first N- layer is connected to the electrode. Specifically, since a larger aspect ratio is used to etch the groove, there will be no difficulty in digging a deep groove and the risk of not filling the isolation dielectric layer, which greatly reduces the process difficulty. At the same time, the isolation dielectric layer is used to perform isolation in advance, and there is no problem of diffusion and alignment that causes isolation failure. In addition, the width of the TVS PN junction and the low-capacitance PN junction can be flexibly adjusted according to design requirements, and they no longer restrict each other, which can increase surge capability and reduce capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic structural diagram of a low-capacitance TVS tube provided in an embodiment of the present invention;

[0024] Figure 2 A flowchart of a method for preparing a low-capacitance TVS tube according to an embodiment of the present invention;

[0025] Figure 3 A schematic diagram of a process flow for producing a low-capacity TVS tube according to Example 1 of the present invention;

[0026] Figure 4 A structural schematic diagram of a low-capacitance TVS tube is provided for comparative example 1.

[0027] Description of main component symbols:

[0028]

[0029] The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0030] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. The drawings illustrate several embodiments of the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present invention.

[0031] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be an intermediate element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0033] refer to Figure 1 , Figure 1 A schematic structural diagram of a low-capacitance TVS tube provided in an embodiment of the present invention. Specifically, the low-capacitance TVS tube includes a first P-type substrate 1 with a groove, a first N+ layer 2 and a first N-layer 3 sequentially arranged on the groove, the width of the first N-layer 3 being smaller than the width of the first N+ layer 2, the height of the first N+ layer 2 being consistent with the depth of the groove, and the impurity of the first N+ layer 2 being As element with a doping concentration of 1E13 atoms / cm 3 ~9E17atom / cm 3 The impurity of the first N-layer 3 is P element or As element, and the doping concentration is 1E12 atom / cm 3 ~9E14 atoms / cm 3 ;

[0034] A first isolation dielectric layer 4 is provided on both sides of the first N+ layer 2 perpendicular to the epitaxial growth direction, and a second isolation dielectric layer 5 is provided on both sides of the first N- layer 3 perpendicular to the epitaxial growth direction. The first N- layer 3 is doped with P-type ions on the side away from the first N+ layer 2. The impurity doped with P-type ions in the first N- layer 3 is element B with a concentration of 1E14 atom / cm 3 ~9E16atom / cm 3 The first region 6 doped with P-type ions in the N-layer is connected to the first electrode 8. In the embodiment of the present invention, the material of the first electrode 8 is metal aluminum. It should be noted that the first isolation dielectric layer 4 and the second isolation dielectric layer 5 are both oxide layers.

[0035] Some other embodiments of the present invention further include a third isolation dielectric layer 7 deposited on the second isolation dielectric layer 5 and the first region 6 doped with P-type ions, and the first electrode 8 is led out through a channel formed by the third isolation dielectric layer 7 .

[0036] Specifically, the doping concentration of the first P-type substrate 1 is 1E17 atom / cm 3 ~9E19 atoms / cm 3 The depth of the groove is 2μm~10μm. For example, the depth of the groove is 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm or 10μm, but is not limited thereto.

[0037] Furthermore, the thickness of the first isolation dielectric layer 4 is 1 μm to 3 μm, and the thickness of the second isolation dielectric layer 5 is 10 μm to 20 μm. Exemplarily, the thickness of the second isolation dielectric layer 5 is 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm or 20 μm, etc., but is not limited thereto.

[0038] refer to Figure 2 , Figure 2 The following is a flowchart of a method for preparing a low-capacitance TVS tube according to an embodiment of the present invention. The method specifically includes the following steps:

[0039] S100: providing a P-type substrate, and etching a groove on the P-type substrate.

[0040] The width of the groove is the width of the TVS PN junction, and the doping concentration of the first P-type substrate where the groove is opened is 1E17 atom / cm 3 ~9E19 atoms / cm 3 .

[0041] S200: depositing an oxide layer in the groove, and etching a middle portion of the oxide layer to obtain a first isolation dielectric layer.

[0042] It can be understood that after depositing an oxide layer in the groove, the middle portion of the oxide layer is etched until a portion of the P-type substrate is exposed, thereby finally obtaining the first isolation dielectric layer.

[0043] S300: epitaxially grow an initial N+ layer, and obtain the first N+ layer after polishing.

[0044] Specifically, the impurity of the first N+ layer is As element, and the doping concentration is 1E13 atom / cm 3 ~9E17atom / cm 3 .

[0045] S400: depositing an oxide layer on the entire surface, and etching the middle portion of the oxide layer to obtain a second isolation dielectric layer.

[0046] It should be noted that an oxide layer is deposited overall, and the middle portion of the oxide layer is etched until a portion of the first N+ layer is exposed, thereby finally obtaining a second isolation dielectric layer having a thickness of 10 μm to 20 μm.

[0047] S500: depositing an initial N- layer in the groove formed by the second isolation dielectric layer and the first N+ layer, and polishing the groove to obtain a first N- layer.

[0048] The impurity of the first N-layer is P element or As element, and the doping concentration is 1E12 atom / cm 3 ~9E14atom / cm 3 .

[0049] S600: doping P-type ions on a side of the first N- layer away from the first N+ layer, and depositing an electrode connected to a first region of the first N- layer doped with P-type ions.

[0050] Specifically, the impurity doped with P-type ions in the N-layer is B element with a concentration of 1E14atom / cm 3 ~9E16atom / cm 3 , the growth temperature is 700℃~1100℃.

[0051] Furthermore, an oxide layer is deposited on the second isolation dielectric layer and the first region doped with P-type ions, and then the through hole is etched until part of the first region doped with P-type ions is exposed. Metal aluminum is deposited at the through hole to form an electrode of the low-capacitance TVS tube.

[0052] The present invention will be further described below with specific embodiments:

[0053] Example 1

[0054] Example 1 of the present invention provides a method for preparing a low-capacity TVS tube and a low-capacity TVS tube, please refer to Figure 3 , is a schematic diagram of a process flow for a low-capacitance TVS tube provided in Example 1 of the present invention. Specifically, the following steps are included:

[0055] (1) A P-type substrate is provided, and a groove is etched on the P-type substrate to obtain a first P-type substrate 1 with a groove.

[0056] Among them, the doping concentration of the P-type substrate is 1E17 atom / cm 3 ~9E19 atoms / cm 3 .

[0057] (2) Depositing an oxide layer in the groove and etching the middle portion of the oxide layer to obtain a first isolation dielectric layer 4.

[0058] It can be understood that after depositing an oxide layer in the groove, the middle portion of the oxide layer is etched until a portion of the P-type substrate is exposed, thereby finally obtaining the first isolation dielectric layer 4 .

[0059] (3) Epitaxially grow the initial N+ layer, and after polishing, obtain the first N+ layer 2.

[0060] Specifically, the impurity of the first N+ layer 2 is As element, and the doping concentration is 1E13 atom / cm 3 ~9E17atom / cm 3 .

[0061] (4) Deposit an oxide layer on the entire surface and etch the oxide layer in the middle portion to obtain a second isolation dielectric layer 5.

[0062] It should be noted that an oxide layer is deposited overall, and the middle portion of the oxide layer is etched until a portion of the first N+ layer 2 is exposed, thereby finally obtaining the second isolation dielectric layer 5 , which has a thickness of 10 μm to 20 μm.

[0063] (5) Depositing an initial N- layer in the groove formed by the second isolation dielectric layer 5 and the first N+ layer 2, and polishing the groove to obtain the first N- layer 3.

[0064] The impurity of the first N-layer 3 is P element or As element, and the doping concentration is 1E12 atom / cm 3 ~9E14atom / cm 3 .

[0065] (6) P-type ions are doped on a side of the first N-layer 3 away from the first N+ layer 2 , and a first electrode 8 is deposited to connect to the first region 6 doped with P-type ions in the first N-layer 3 .

[0066] Specifically, the impurity doped with P-type ions in the first N-layer 3 is B element, with a concentration of 1E14atom / cm 3 ~9E16atom / cm 3 , the growth temperature is 700℃~1100℃.

[0067] Furthermore, an oxide layer is deposited on the second isolation dielectric layer 5 and the first region 6 doped with P-type ions, and then the through-hole is etched until a portion of the first region 6 doped with P-type ions is exposed to obtain a third isolation dielectric layer 7. Metal aluminum is deposited at the through-hole to form the first electrode 8 of the low-capacitance TVS tube.

[0068] Finally, a low-capacitance TVS tube was prepared by the above method.

[0069] Comparative Example 1

[0070] Comparative Example 1 provides a method for preparing a low-capacity TVS tube and a low-capacity TVS tube, comprising the following steps:

[0071] (1) Provide a second P-type substrate 11.

[0072] (2) Ion implantation is performed at a preset position of the second P-type substrate 11 . It should be noted that after the second N- layer 21 is deposited, the ion implantation will diffuse, and eventually an N+ region 41 will be obtained.

[0073] (3) Depositing a second N-layer 21 on the second P-type substrate 11 , and doping P-type ions on a side of the second N-layer 21 away from the second P-type substrate 11 to obtain a second region 31 doped with P-type ions.

[0074] (4) Trench etching is performed while avoiding the N+ region 41 , and an oxide layer is deposited in the trench to serve as an isolation dielectric layer 51 .

[0075] (5) Continue to deposit an oxide layer on the isolation dielectric layer 51 and the second region 31 doped with P-type ions, and then etch the through hole until the middle part of the second region 31 doped with P-type ions is exposed. Metal aluminum is deposited at the through hole to form the second electrode 61 of the low-capacitance TVS tube.

[0076] Finally, a low capacitance TVS tube is prepared by the above method. Figure 4 , a structural schematic diagram of a low-capacitance TVS tube is provided for comparative example 1, including a second P-type substrate 11, a second N-layer 21 and a second region 31 arranged in sequence, wherein an N+ region 41 is provided at the junction of the second P-type substrate 11 and the second N-layer 21, and grooves etched from the P-type ion region to the second P-type substrate 11 are provided on both sides of the N+ region 41, and the grooves are filled with an oxide layer.

[0077] It should be noted that in the solution of Comparative Example 1, since low capacitance requires a thicker low-doped epitaxial layer, the N+ layer needs to be ion-implanted and doped first, and then deep trenches need to be dug for isolation. There are alignment problems and the problem of N+ diffusion is easy to cause, which will cause the isolation function of the deep trench dielectric to fail. If other functional diodes are integrated nearby, it will cause device failure. In addition, the deep trench is deep, and the process of digging trenches and filling dielectric layers is more difficult, which places extremely high requirements on equipment and leads to increased costs. In addition, the low-capacitance PN junction formed by PN- and the TVS PN junction formed by P-subN+ have the same junction area. Low capacitance and high surge capability restrict each other and cannot improve device performance.

[0078] In summary, a low-capacitance TVS tube and a preparation method thereof in an embodiment of the present invention are provided by providing a P-type substrate with a groove, and a first N+ layer and a first N- layer sequentially provided on the groove; wherein, a first isolation dielectric layer is provided on both sides of the first N+ layer perpendicular to the epitaxial growth direction, and a second isolation dielectric layer is provided on both sides of the first N- layer perpendicular to the epitaxial growth direction, and the first N- layer is doped with P-type ions on the side away from the first N+ layer, and the first region doped with P-type ions in the first N- layer is connected to the electrode. Specifically, since a larger aspect ratio is used to etch the groove, there will be no difficulty in digging a deep groove and no risk of not filling the isolation dielectric layer, which greatly reduces the process difficulty. At the same time, the isolation dielectric layer is used to perform isolation in advance, and there is no problem of diffusion and alignment that causes isolation failure. In addition, the width of the TVS PN junction and the low-capacitance PN junction can be flexibly adjusted according to design requirements, and they no longer restrict each other, which can increase the surge capability and reduce the capacitance.

[0079] The low-capacity TVS tube and its preparation method provided by the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only intended to help understand the method and core concept of the present invention. At the same time, for those skilled in the art, according to the concept of the present invention, there may be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

[0080] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0081] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that the process, method, article, or apparatus comprising a series of elements inherent to the elements, or also including elements inherent to these processes, methods, articles, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0082] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A low capacitance TVS tube, characterized in that: It includes a first P-type substrate with a groove, a first N+ layer and a first N- layer sequentially arranged on the groove; wherein, a first isolation dielectric layer is provided on both sides of the first N+ layer perpendicular to the epitaxial growth direction, a second isolation dielectric layer is provided on both sides of the first N- layer perpendicular to the epitaxial growth direction, a side of the first N- layer away from the first N+ layer is doped with P-type ions, and a first region of the first N- layer doped with P-type ions is connected to an electrode; The doping concentration of the first P-type substrate is 1E17 atom / cm 3 ~9E19 atoms / cm 3 ; The impurity of the first N+ layer is As element, and the doping concentration is 1E13 atom / cm 3 ~9E17atom / cm 3 ; The impurity of the first N-layer is P element or As element, and the doping concentration is 1E12 atom / cm 3 ~9E14 atoms / cm 3 ; The impurity doped with P-type ions in the first N-layer is B element with a concentration of 1E14atom / cm 3 ~9E16atom / cm 3 .

2. The low capacitance TVS tube according to claim 1, characterized in that: The depth of the groove is 2 μm to 10 μm.

3. The low capacitance TVS tube according to claim 1, characterized in that: The thickness of the first isolation dielectric layer is 1 μm to 3 μm.

4. The low capacitance TVS tube according to claim 1, characterized in that: The thickness of the second isolation dielectric layer is 10 μm to 20 μm.

5. A method for preparing a low-capacity TVS tube, characterized in that: For preparing the low-capacity TVS tube according to any one of claims 1 to 4, the method comprises: Providing a P-type substrate, and etching a groove on the P-type substrate; Depositing an oxide layer in the groove and etching the middle portion of the oxide layer to obtain a first isolation dielectric layer; Epitaxially grow the initial N+ layer, and then grind it flat to obtain the first N+ layer; Depositing an oxide layer on the entire surface and etching the middle portion of the oxide layer to obtain a second isolation dielectric layer; Depositing an initial N- layer in the groove formed by the second isolation dielectric layer and the first N+ layer, and polishing the groove to obtain a first N- layer; P-type ions are doped on a side of the first N- layer away from the first N+ layer, and an electrode is deposited to connect to a first region of the first N- layer doped with P-type ions.

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