Method for producing nanosheet transistor

Abstract

A fin-shaped structure (5) is formed on a base substrate (1), the structure comprising a stack of alternating sacrificial and semiconductor layers (3, 4). The stacked material is then removed with respect to the dummy gate and with respect to a mask (6) formed before or after the dummy gate, thereby forming a lateral recess (14) having U-shaped sidewalls (15) formed from the stacked U-shaped portions of the sacrificial and semiconductor layers (3, 4). The semiconductor material is grown in the recess by epitaxial growth starting from the U-shaped semiconductor portion. The grown material is lattice mismatched with respect to the material of the U-shaped portion. Since the growth mechanism begins from the U-shaped semiconductor portion, dislocation due to an opposite interfering growth front is not generated, and thus a desired stress can be generated in at least one or more channel sheets of the final transistor. The transistors are arranged in a forked sheet configuration after creating a trench to remove the mask and fill the trench with a dielectric material.

Description

Technical Field

[0001] The present invention relates to semiconductor processing, and more particularly to the production of nanosheet transistors. Background Art

[0002] Nanosheet technology has been developed for many years and is one of the main answers to address the limitations of finFET technology in meeting the ever-expanding requirements of active devices on integrated circuit chips. In a stand-alone nanosheet transistor, the channel is formed by one or more semiconductor sheets stacked on top of each other, and a gate dielectric as well as a gate electrode surround the sheet. The term "gate-all-around" (GAA) is also used for this type of device. A further development is the fork-sheet configuration, in which two nanosheet transistors are built on opposite sides of a separate dielectric wall.

[0003] However, in improving and fine-tuning the performance of nanosheet transistors, further challenges need to be addressed. One problem is related to the epitaxial growth of source and drain regions between adjacent dummy gate structures. In currently applied production methods, multiple fin structures are formed by stacking alternating sacrificial layers and semiconductor layers, such as SiGe and Si in alternation. Then, dummy gates are generated transversely with respect to the fin structure, and then external and internal spacers are formed. Subsequently, the material of the fins between the dummy gates is removed, and source and drain regions are formed by epitaxial growth starting from the side surfaces of the semiconductor layers within the fin structure. The growth starts from opposite sides of the trench formed between two adjacent dummy gates and continues until the bottom region of the trench is filled. However, this growth mode is not ideal in terms of obtaining the stress in the final channel of the transistor, which is beneficial for optimizing carrier mobility. Since a dislocation plane is formed where the two growth fronts meet, the growth along the two opposite fronts may result in near-zero channel stress. These dislocations may cause relaxation defects to propagate to the interface between the seed layer and the growth layer, thereby eliminating any stress accumulated in the growth layer. Summary of the Invention

[0004] The present invention relates to a method for producing one or more nanosheet transistors according to the appended claims. According to the method, a fin structure is formed on a substrate substrate, the structure comprising a stack of alternating sacrificial layers and semiconductor layers, the latter being adapted to form channel sheets in the final one or more transistors. Then, the stack material is removed relative to dummy gates and relative to a mask formed before or after the dummy gates, thereby forming a lateral recess having U-shaped sidewalls formed by U-shaped portions of the stack of sacrificial layers and semiconductor layers. An internal spacer is formed between the U-shaped semiconductor portions. Semiconductor material grows in the recess by epitaxial growth starting from the U-shaped semiconductor portions. The grown material has a lattice mismatch with respect to the channel material. "Lattice mismatch" means that there is a difference between the dimensions of the lattice structures of the channel material (serving as a seed layer for epitaxial growth) and the grown material. Due to the nature of the epitaxial growth process, the lattice of the grown material adapts to the lattice of the seed layer, such that the seed layer and the grown layer can form a crystal structure with uniform stress. Since the growth mechanism starts from the U-shaped semiconductor portions, dislocations are not generated due to opposing interfering growth fronts. Thus, relaxation defects originating from such growth fronts cannot propagate to the interface between the seed layer and the grown layer, and thus desired stress can be generated in at least one or more of the channel sheets in the final transistors. After trenches are formed to remove the mask and the trenches are filled with a dielectric material, these transistors are arranged in a cross-sheet configuration.

[0005] The present invention particularly relates to a method for producing one or more nanosheet transistors, comprising the sequential application of the following steps:

[0006] - On a substrate substrate, generating at least one fin structure extending in a longitudinal direction, the structure comprising a stack of layers stacked in an alternating order, the layers comprising one or more sacrificial layers and one or more crystalline semiconductor layers formed of a first semiconductor material,

[0007] - Generating at least three mutually parallel and spaced-apart dummy gate structures, the dummy gate structures being arranged laterally with respect to the fin structure and a mask and completely overlapping the fin structure and the mask,

[0008] - Generating dielectric spacers at least on the sidewalls of the dummy gate structures,

[0009] - Patterning the stack of layers by removing the material of the sacrificial layers and semiconductor layers relative to the dummy gate structures and the spacers and relative to a mask formed before or after generating the dummy gate structures and extending in the same longitudinal direction as the fin structure, such that two lateral recesses having U-shaped sidewalls are formed on each side of at least one of the dummy gate structures in the stack, the dummy gate structure having adjacent dummy gates on both sides, the sidewalls comprising the exposed U-shaped portions of the sacrificial layers and semiconductor layers,

[0010] - On the U-shaped sidewalls, internal spacers are created by etching back the exposed sacrificial material relative to the exposed semiconductor material and replacing the removed sacrificial material with a dielectric material.

[0011] - By epitaxial growth, a second semiconductor material is grown in the lateral recesses, wherein:

[0012] -

[0013] ο The second semiconductor material is lattice mismatched with respect to the first semiconductor material.

[0014] ο The second semiconductor material grows outwardly starting from the exposed U-shaped portions of the layers of the first semiconductor material.

[0015] ο Growth continues until a volume of the second semiconductor material is obtained in each of the lateral recesses.

[0016] - A dielectric layer is created to fill the space between each pair of adjacent dummy gate structures and the dielectric layer is planarized to the same level as the dummy gate structures.

[0017] - By lithography and etching, trenches are created along the longitudinal direction of the fin structure, the trenches passing through the dummy gate structures and the spacers, the trenches being wider than the mask but narrower than the fin structure such that the mask is removed while leaving portions of a stack of alternating sacrificial layers and first semiconductor layers on both sides of the trenches.

[0018] - The trenches are filled with a dielectric material to form dielectric walls.

[0019] - The dummy gate structures and the remaining portions of the sacrificial layers are removed, a gate dielectric layer is created on the remaining portions of the first semiconductor layer, and metal gates are created on both sides of the dielectric walls in direct contact with the gate dielectric layer.

[0020] - Electrical connections are created to at least one metal gate and two epitaxially grown volumes directly adjacent and on both sides of the gate to obtain at least one nanosheet transistor including a channel, a source region, and a drain region.

[0021] According to one embodiment, the fin structure includes a dielectric layer directly on a substrate baseplate and the stack of alternating sacrificial layers and semiconductor layers is directly formed on the dielectric layer.

[0022] According to one embodiment, spacers are also formed on the sidewalls of the mask and the sidewalls of the fin structure.

[0023] According to one embodiment, the stack of alternating sacrificial layers and semiconductor layers includes at least two semiconductor layers, and an epitaxially grown volume is formed in each recess, the volume being obtained by merging sub-volumes that grow outwardly from the respective exposed U-shaped portions of the semiconductor layers.

[0024] According to one embodiment, after the step of creating the trenches, the dielectric layer that fills the space between each pair of adjacent dummy gate structures is removed, and thereafter a continuous layer of dielectric material is created that fills the trenches and the space between each pair of adjacent dummy gate structures.

[0025] According to one embodiment, the mask is a hard mask that is formed on the fin structure and covers the central elongated portion of the structure, and the hard mask is formed before the dummy gate structures are formed.

[0026] According to one embodiment, the mask is a hard mask or a resist mask that is formed after the dummy gates are formed and covers the central elongated portion of the fin structure.

[0027] The present invention also relates to a finned sheet configuration including a substrate base, dielectric walls, and two nanosheet transistors located on opposite sides of the dielectric walls, each transistor including one or more channel sheets, a metal gate, a gate dielectric between the channel sheet and the metal gate, source and drain regions, characterized in that in any cross-section parallel to the substrate base and passing through at least one of the channel sheets, the source and drain regions and the channel sheet through which the cross-section passes are homogeneously crystalline.

[0028] According to one embodiment of the finned sheet configuration, a dielectric layer is located directly on the substrate base, and the dielectric walls and the transistors are placed on the dielectric layer.

[0029] The present invention also relates to a semiconductor component including one or more transistors produced according to the method of the present invention and a semiconductor component including one or more finned sheet configurations according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 18 Illustrates a plurality of method steps applicable to one embodiment of the method according to the present invention. DETAILED DESCRIPTION

[0031] A particular embodiment of the method according to the present invention will be described in detail below. Any reference to materials and dimensions is made by way of example only and is not intended to limit the scope of the present invention which is defined solely by the appended claims.

[0032] Figure 1A small part of the base substrate 1 is shown, which includes multiple layers on its upper surface. The base substrate 1 can be a standard silicon process wafer with a diameter of 300 mm and a thickness between 0.4 and 0.5 mm. Only the thin upper part of the wafer is shown, with a thickness on the order of 10 - 20 nm. Directly on the Si substrate is a silicon oxide layer (SiO2) 2 with a thickness of about 10 nm. On this SiO2 layer 2, there is a stack of alternating SiGe layers 3 and Si layers 4, with each layer having a thickness of about 5 nm. The stack starts from the bottom SiGe layer 3 and ends with the top Si layer 4. In known process technologies for producing nanosheet devices, as well as in the method according to the illustrated embodiment, the SiGe sheets have the function of sacrificial layers, which will be removed later in the process. The Si layers are formed of crystalline Si. As is known in the art, this can be achieved by epitaxially growing subsequent SiGe and Si layers.

[0033] By performing photolithography and etching on the SiGe and Si layers 3, 4 and the SiO2 layer 2, a fin structure 5 is formed, as Figure 2 shown, including the SiO2 layer 2 and a patterned stack of alternating SiGe and Si layers 3, 4. Only one fin structure 5 is shown, but in most implementations, it will preferably be an array of multiple mutually parallel fin structures 5 with equal widths and constant spacings. In this particular embodiment, the width of the fin structure 5 is about 40 nm, but other widths are also possible.

[0034] Referring to Figure 3 , then a hard mask 6 is formed on top of the fin structure 5. This can be achieved by depositing a layer of hard mask material (such as SiN or SiC) and patterning the layer such that the mask 6 remains in the form of an elongated strip of mask material aligned with and on top of the fin structure 5. In the particular embodiment shown, the width of the hard mask 6 can be between 10 nm and 15 nm. The mask 6 is preferably coaxially arranged with the fin structure 5. The mask 6 enables anisotropic etching of the material of the stack of SiGe and Si layers 3, 4 (hereinafter also referred to as the "SiGe / Si stack 3, 4") relative to the mask material.

[0035] Referring to Figure 4 , then a regular array of dummy gate structures 7 (hereinafter also referred to as "dummy gates") is formed laterally, preferably vertically, with respect to the fin structure 5 and the mask 6. The width of the dummy gate 7 can be on the order of 10 - 15 nm. The material of the dummy gate 7 (such as amorphous silicon) and the production method can be based on known process technologies for producing dummy gate structures suitable for mature replacement metal gate (RMG) technology. In the example shown, the distance between two adjacent dummy gate structures 7 is slightly greater than the dummy gate width, but this distance can generally be of the same order as the dummy gate width.

[0036] Then, as Figure 5 shown, again according to known RMG techniques, a dielectric spacer 8 is applied to the sidewalls of the dummy gate structure 7. The spacer 8 may have a thickness on the order of, for example, 1 to 5 nm. To continue visualizing the fin structure 5, Figure 5 spacers are not shown on the first and last of the three dummy gates shown, but it will be understood that spacers are effectively formed on both sides of each dummy gate 7. As is known in the art, the formation of the spacer 8 can be accomplished by conformal deposition of a thin dielectric layer (i.e., following the topology of the fin structure 5, the mask 6, and the dummy gate 7) and subsequent removal of the dielectric layer from the horizontal surfaces by plasma etching. In the embodiment shown, in the regions between the dummy gate structures 7, spacers are also formed on the sidewalls of the fin structure 5 and the mask 6. Depending on the materials applied in the fin structure 5 and the mask 6 and / or the process parameters used to produce the spacers, no spacer may be formed here, or the spacer may only be formed to a given height. However, this will have no effect on the method according to the invention, as will become apparent. The material of the spacer 8 can be, for example, SiN or SiCN.

[0037] The next step is as Figure 6 and Figure 7 shown. The materials of the SiGe layer 3 and the Si layer 4 are anisotropically removed relative to the dummy gate structure 7, the mask 6, and the dielectric spacer 8. The SiO2 layer 2 can act as an etch stop layer, or the etching process can be timed to stop with substantially no removal of the material of the SiO2 layer 2. Etching recipes having appropriate etch selectivity for removing SiGe and Si relative to the various materials of the dummy gate 7, the mask 6, and the spacer 8 are known in the art. This step creates a lateral recess 14 in the SiGe / Si stack 3, 4, which is better visible in Figure 7 which Figure 7 shows a cross-section taken by a plane A parallel to the substrate 1 and intersecting one of the SiGe layers 3. The U-shaped sidewalls 15 of the lateral recess 14 are formed by the exposed portions of the U-shapes of the SiGe and Si layers 3, 4. In the image shown, the spacers 8 on the sides of the removed portions remain, thus forming a closure at the open ends of the recesses 14. As described above, it is possible that no spacer or only a partially formed spacer is obtained at this location during the spacer formation process. In such a case, the recess 14 can be fully or partially open.

[0038] Then referring to Figure 8 and 9Create an internal spacer 16. The internal spacer is formed by laterally etching the SiGe layer 3 in its exposed U-shaped portion to a depth of about 2-5 nm relative to the Si layer 4, and replacing the removed SiGe with a dielectric spacer material that can be the same as the material of the gate spacer 8. The formation of the internal spacer 16 is known and can be performed according to known techniques. Figure 9 The cross-sectional view in shows the depth to which the internal spacer 16 extends between the Si layers 4. The internal spacer is included to reduce the parasitic capacitance between the gate and the source or drain of the final transistor.

[0039] The next step is described in Figures 10 - 12 The source and drain regions of the final transistor are formed between the dummy gate structures 7 by epitaxially growing a semiconductor material starting from the 3Si surface of each exposed U-shaped sidewall 15 of the lateral recess 14. The semiconductor material is lattice mismatched with respect to Si. For example, for the production of pMOS nanosheet transistors, compressive stress is required to optimize the carrier mobility in the channel. In this case, the source and drain regions can be formed of SiGe, which has an appropriate lattice mismatch with respect to Si to generate the compressive stress. The use of SiGe for this purpose is well known, but as explained in the introduction, the use of the conventional method of growing SiGe between adjacent dummy gates results in dislocation planes, which may cancel out the stress within the SiGe and thus fail to generate the required compressive channel stress.

[0040] As shown in the cross-section taken parallel to the plane A of the substrate 1 in Figure 11 each U-shaped Si surface is part of a continuous crystal structure 4. The material grown from the U-shaped Si surface is also crystalline and is fully strained due to the lattice mismatch and the growth front advancing from the U-shaped Si sidewall portion not interacting with any opposing growth front and thus having no dislocations. As shown in the cross-section taken perpendicular to the plane B of the substrate 1 in Figure 12 an epitaxially grown volume 18 is obtained in the recess 14. In Figure 12 it can be seen that each volume 18 is an agglomeration of sub-volumes 18' growing outwards from the three U-shaped Si surfaces on the sidewalls of the recess 14, the sub-volumes 18' merging along a horizontal interface 19, and the lower sub-volumes being slightly spaced apart from the SiO2 layer 2. The volume 18 can also fill the recess 14 up to its bottom.

[0041] Each Si layer 4 and the volume 18' grown on its side surfaces are single crystals, i.e., they form a single crystal structure and are strained due to the lattice mismatch between the Si layer 4 and the growth material 18'. Thus, the epitaxially grown volume 18 obtained in this way can induce stress in the Si channel of the final transistor, where the volume 18 will serve as the source or drain region. As is known in the art, considering the expected source / drain functionality, appropriate doping elements (e.g., p-dopants in the case of pMOS) can be added to the volume 18' during the epitaxial growth process.

[0042] Now refer to Figure 13 . A dielectric material 20 is deposited so as to completely fill the space between the dummy gates 7 and cover the structure between the dummy gates. Then, the dielectric 20 is planarized to the same level as the dummy gates 7. The dielectric used can be any dielectric suitable as a so-called interlayer dielectric (ILD) for isolating the connections to the gates, sources, and drain regions of the nanosheet transistor. For example, it can be a low-k dielectric. In the illustrated embodiment, the ILD material 20 must be different from the material of the spacers 8 and can be selectively removed relative to the material of the spacers 8 because this material will be removed again relative to the spacers at a later stage of the process (see below).

[0043] Then refer to Figure 14 An additional patterning step is performed. Through photolithography and anisotropic etching, trenches 25 are formed through the dummy gates 7 and the SiGe / Si stacks 3, 4 of the original fin structure 5. The trenches 25 extend in the longitudinal direction of the fin structure 5. The trenches 25 are wider than the mask 6 but narrower than the SiGe / Si stacks 3, 4 such that by removing the mask 6 and (if present) the spacers 8 on its sides, the trenches cut the SiGe / Si stack into two preferably equal parts. The anisotropic etching stops on the SiO2 layer 2 either by using the SiO2 layer 2 as an etch stop layer or by timing the etching. On the sidewalls of the trenches 25, portions of the original SiGe layer 3 and Si layer 4 are exposed, spaced apart from the epitaxially grown volumes 18. Each such volume 18 is formed as an agglomeration of sub-volumes 18' that form a single crystal structure with the Si layer 4 from which they grow.

[0044] Then, as Figure 15 shown, another layer of ILD material is deposited, the material of which can be the same as the previously deposited material 20. The other ILD layer fills the trenches 25 and is subsequently planarized to the same level as the dummy gates 7. Figure 16The cross-sectional view in shows that the obtained structure is suitable for the finned architecture for producing nanosheet transistors. The ILD-filled trench 25 forms a dielectric wall 27 with multiple SiGe / Si stacks 3, 4 separated by the epitaxially grown volumes 18 on both of its sides.

[0045] Therefore, starting from the Figure 15 and 16 shown process stages, the process steps for producing fully operational nanosheet transistors can be carried out according to known techniques. This includes removing the dummy gate structure 7 and then removing the sacrificial SiGe layer 3 with respect to the Si layer 4 such that the Si layer 4 hangs as parallel sheets between two epitaxially grown volumes 18. Referring to Figure 17 and 18 , a dielectric layer 28 is then formed on the exposed surface of each Si layer 4 and a metal gate 29 is formed around the dielectric layer 28. As shown in the cross-sectional view in Figure 18 , multiple pairs of two transistors can be obtained from this architecture, one transistor on each side of the dielectric wall 27, each transistor including a source or drain region 18, a channel formed by three parallel Si sheets 4, and a metal gate 29 spaced from the channel by a gate dielectric 28. The gate 29 can be cut and connections to any number of source / drain regions 18 and gates 29 can be made by known techniques and according to a given interconnect layout, thereby creating one or more operational transistors.

[0046] If no more than 3 dummy gates are produced and there is only one fin structure 5, the method will only produce two sets of gates, sources, and drains on both sides of the dielectric wall 27 and may thus only produce two transistors, which defines the minimum architecture obtainable by the method. In the present context, a "transistor" is defined only when the source, drain, and gate are effectively contacted by an electrical conductor coupled to a supply voltage or another transistor or other device. Thus, theoretically, if only one transistor is contacted in the minimum architecture, the method of the present invention is capable of producing only one transistor in the above sense. Therefore, the method is suitable for producing "one or more transistors". Of course, in most practical implementations, the number of dummy gates and fin structures will be significantly increased and the method enables the production of a large number of transistors even if not all of the gate, source, and drain regions are effectively contacted.

[0047] In the above-described embodiment, the transistor is formed on the isolation layer 2. This is a preferred situation because it ensures that the epitaxial growth for creating the source and drain regions 18 starts only on the sidewalls of the recess 14, rather than at its bottom (as would be the case if the transistor were directly built on the crystalline semiconductor wafer). When the growth also starts from the bottom of the recess, this growth may interfere with the lateral growth front and thereby cause dislocations. However, depending on the material of the substrate 1 and the number of semiconductor nanosheets 4 in the initial stack, the bottom-up growth may not have much impact on the lateral growth, such that the main part of the source and drain regions is fully strained and can thus generate stress in one or more channel sheets. Therefore, the production of transistors directly on a semiconductor substrate by the method of the present invention is not excluded from the scope of the present invention.

[0048] In the embodiment shown in the figures and described in detail above, the hard mask 6 is formed on the fin structure 5 before the dummy gate 7 is formed. In an alternative embodiment, the dummy gate can be formed directly on the fin structure 5, and the mask 6 can be a hard mask or a resist mask (i.e., a soft mask) generated after the dummy gate is formed. However, regardless of the mask type or the process stage at which it is produced, the function of the mask is the same as described above: covering the longitudinal part of the fin structure 5 to form the lateral cavity 14 as shown in Figure 6 and Figure 7 shown. In addition, as shown in Figure 14 shown, when the longitudinal trench 25 is generated, whenever and however it is generated, the mask is removed.

[0049] The nanosheet transistor produced by the method of the present invention can be identified by the fact that in any cross-section parallel to the substrate 1 and passing through at least one channel sheet 4, the source and drain regions 18 and the channel sheet 4 are uniformly crystalline, i.e., there are substantially no dislocations present within the cross-section. The inclusion of "at least one" is to account for embodiments of transistors processed directly on a semiconductor substrate, in which case the lower parts of the source and drain may include dislocations as described in the previous paragraph. However, when the transistor is formed on the dielectric layer 2, the source, drain, and channel are uniformly crystalline in any cross-section passing through any channel sheet 4. This is because, as described above, during the method of the present invention, the cross-section passes through the channel sheet 4 and through the volume 18' that grows directly on the side surfaces of the semiconductor layer 4.

[0050] The nanosheet transistor produced according to the present invention can be integrated in any known integration scheme, including a scheme in which complementary pMOS and nMOS transistors are built one on top of the other, also known as CFET integration (complementary field effect transistor). For example, the configuration shown in the figures can be used to produce a pMOS transistor on the bottom isolation layer 2 on a Si process wafer 1. From Figure 18Starting from the shown image, a layer of dielectric material can be produced on the planarized surface, and then an nMOS transistor can be produced on the dielectric layer (referred to as the "intermediate dielectric layer" of the CFET structure). The method steps are the same as those described above, but considering that the stress requirements of the nMOS transistor are different from those of the pMOS transistor, different materials are used. Although the present invention has been described and illustrated in detail in the drawings and the foregoing description, such description and illustration are considered to be illustrative or exemplary, rather than restrictive. By studying the drawings, the present disclosure, and the appended claims, those skilled in the art can understand and implement other variations of the disclosed embodiments when practicing the claimed invention. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used advantageously. Any reference signs in the claims should not be construed as limiting the scope.

Claims

1. A method for producing one or more nanosheet transistors, comprising applying the following steps in succession: On a base substrate (1), at least one fin-shaped structure (5) extending in a longitudinal direction is produced, said structure comprising a stack (3, 4) of layers stacked in an alternating order, said layers comprising one or more sacrificial layers (3) and one or more crystalline semiconductor layers (4) formed of a first semiconductor material, At least three mutually parallel and spaced dummy gate structures (7) are generated, wherein the dummy gate structures are arranged laterally relative to the fin-shaped structure (5) and the mask (6) and completely overlap with the fin-shaped structure (5) and the mask (6), generating a dielectric spacer (8) at least on the sidewalls of the dummy gate structure (7), The stack (3, 4) of sacrificial and semiconductor layers is patterned by removing material of the sacrificial and semiconductor layers relative to the dummy gate structures (7) and the spacers (8) and relative to a mask (6) formed before or after the creation of the dummy gate structures (7) and extending in the same longitudinal direction as the fin-shaped structure (5) so that two lateral recesses (14) with U-shaped side walls (15) are formed in the stack (3, 4) on each side of at least one of the dummy gate structures (7), the dummy gate structures having adjacent dummy gates on both sides, the side walls comprising the exposed U-shaped portions of the sacrificial and semiconductor layers, On the U-shaped sidewall (15), an inner spacer (16) is produced by etching back the exposed sacrificial material relative to the exposed semiconductor material and replacing the sacrificial material thus removed with a dielectric material, A second semiconductor material is grown in the lateral recess (14) by epitaxial growth, wherein: the second semiconductor material is lattice mismatched with respect to the first semiconductor material, the second semiconductor material growing outwardly from the exposed U-shaped portion of the layer (4) of the first semiconductor material, The growth is continued until a volume (18) of the second semiconductor material is obtained in each of the lateral recesses, generating a dielectric layer (20) filling the space between each pair of adjacent dummy gate structures (7), and planarizing the dielectric layer to the same level as the dummy gate structures (7), By photolithography and etching, a groove (25) is generated along the longitudinal direction of the fin-shaped structure (5), the groove passing through the dummy gate structure (7) and the spacer (8), the groove being wider than the mask (6) but narrower than the fin-shaped structure (5), so that the mask (6) is removed, while portions of the stack (3, 4) of alternating sacrificial layers and first semiconductor layers are left on both sides of the groove, filling the trench (25) with a dielectric material, thereby forming a dielectric wall (27), The dummy gate structure (7) and the remaining part of the sacrificial layer (3) are removed, a gate dielectric layer (28) is generated on the remaining part of the first semiconductor layer (4), and a metal gate (29) is generated on both sides of the dielectric wall (27) and is in direct contact with the gate dielectric layer (28). Electrical connections are made to at least one metal gate (29) and to two epitaxially grown volumes (18) directly adjacent and located on either side of said gate, thereby obtaining at least one nanosheet transistor comprising a channel, a source region and a drain region.

2. The method according to claim 1, characterized in that The fin-shaped structure (5) comprises a dielectric layer (2) located directly on the base substrate (1), and wherein the stack (3, 4) of alternating sacrificial and semiconductor layers is formed directly on the dielectric layer (2).

3. The method according to claim 1 or 2, characterized in that: Spacers (8) are also formed on the sidewalls of the mask (6) and on the sidewalls of the fin structure (5).

4. The method according to any one of the preceding claims, characterized in that The stack (3, 4) of alternating sacrificial and semiconductor layers comprises at least two semiconductor layers (4) and wherein an epitaxially grown volume (18) is formed in each recess (14), said volume being obtained by merging sub-volumes (18') growing outwardly from the corresponding exposed U-shaped portion of the semiconductor layer (4).

5. The method according to any one of the preceding claims, characterized in that After the step of producing the trenches (25), the dielectric layer (20) filling the space between each pair of adjacent dummy gate structures (7) is removed, and a continuous layer (26) of dielectric material is thereafter produced, the continuous layer filling the trenches (25) and the space between each pair of adjacent dummy gate structures (7).

6. The method according to any one of the preceding claims, characterized in that The mask is a hard mask (6) formed on the fin-shaped structure (5) and covering a central elongated portion of the structure, and wherein the hard mask is formed before forming the dummy gate structure (7).

7. The method according to any one of claims 1 to 5, characterized in that The mask is a hard mask or a resist mask formed after forming the dummy gate (7) and covers the central elongated portion of the fin-shaped structure (5).

8. A fork sheet structure comprising a base substrate (1), a dielectric wall (27) and two nanosheet transistors located on opposite sides of the dielectric wall, each transistor comprising one or more channel sheets (4), a metal gate (29), a gate dielectric (28) between the channel sheets and the metal gate, and source and drain regions (18), characterized in that In any cross section parallel to the base substrate (2) and through at least one of the channel plates (4), the source and drain regions (18) and the channel plate (4) through which the cross section passes are uniformly crystallized.

9. The fork structure according to claim 8, characterized in that: A dielectric layer (2) is located directly on the base substrate, and wherein the dielectric wall (27) and the transistor are placed on the dielectric layer (2).

10. A semiconductor component comprising one or more transistors produced by the method according to any one of claims 1 to 7.

11. A semiconductor component comprising one or more fork structures according to claim 8 or 9.

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