Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which is internally provided with a first region and a drift region, and the first region is adjacent to the drift region; forming a first dielectric material layer on the substrate by adopting a thermal oxidation process; a part of the first dielectric material layer is removed to obtain a first dielectric layer, the first dielectric layer covers the first region and a part of the drift region adjacent to the first region, and the first dielectric layer above the part of the drift region adjacent to the first region serves as a first field dielectric layer; and forming a second field dielectric layer on the first field dielectric layer. Compared with a mode of directly forming the field dielectric layer with the first thickness on the surface of the drift region through a low-temperature deposition process, the first field dielectric layer is formed through a thermal oxidation process, so that the interface defect density of the field dielectric layer and the drift region can be reduced, and the reliability of the semiconductor structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] Compared with current-controlled power devices, voltage-controlled power devices control the operating current of the device by controlling the gate voltage. At the same time, as multi-carrier devices, they are not affected by the minority-carrier storage effect and have the characteristic that the switching speed is much greater than that of current-controlled devices, and can be used for operation in high-frequency environments.

[0003] However, the electrical performance of existing voltage-controlled power devices is not good.

[0004] Therefore, how to provide a technical solution to improve the electrical performance of voltage-controlled power devices has become a technical problem to be solved urgently. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which can improve the reliability of the semiconductor structure.

[0006] In a first aspect, an embodiment of the present disclosure provides a method for forming a semiconductor structure, including: Providing a substrate, wherein a first region and a drift region are provided in the substrate, and the first region and the drift region are adjacently arranged; Forming a first dielectric material layer on the substrate by a thermal oxidation process; Removing a part of the first dielectric material layer to obtain a first dielectric layer, the first dielectric layer covering the first region and a part of the drift region adjacent to the first region, and the first dielectric layer above the part of the drift region adjacent to the first region serving as a first field dielectric layer; Forming a second field dielectric layer on the first field dielectric layer.

[0007] Optionally, before forming the first dielectric layer, the method for forming the semiconductor structure further includes the step of: Forming a gate main body of a gate structure on the first dielectric material layer above the first region, wherein the first dielectric material layer above the first region serves as a gate dielectric layer of the gate structure, and the gate dielectric layer is adjacent to the first field dielectric layer.

[0008] Optionally, forming the gate main body of the gate structure includes the steps of: Forming a gate material layer on the first dielectric material layer; Forming a patterned first mask layer covering the first gate material layer above the first region; Using the first mask layer as a mask, remove other gate material layers outside the area covered by the first mask layer to obtain the gate body.

[0009] Optionally, the step of removing part of the first dielectric material layer to obtain the first dielectric layer includes the steps of: Form a patterned second mask layer that covers the gate body above the first region and also covers the first dielectric material layer above a part of the drift region adjacent to the first region; Using the second mask layer as a mask, remove other first dielectric material layers outside the area covered by the second mask layer to obtain the first dielectric layer.

[0010] Optionally, before forming the second field dielectric layer, the method for forming the semiconductor structure further includes the steps of: Form a body region with a doping type different from that of the drift region; Form a source region in the body region with a doping type different from that of the body region; Form a drain region in the drift region with a doping type consistent with that of the drift region.

[0011] Optionally, the step of forming the body region includes the steps of: Form a patterned third mask layer that exposes a part of the substrate adjacent to the first region, and this part of the substrate is located on the side of the first region away from the drift region; Using the third mask layer as a mask, dope the part of the substrate exposed by the third mask layer to obtain the body region.

[0012] Optionally, the step of forming the body region further includes the steps of: Anneal the semiconductor structure so that the body region diffuses towards the first region until it is adjacent to the drift region, and the doping concentration of the body region below the gate dielectric layer gradually decreases along the direction adjacent to the drift region.

[0013] Optionally, the step of forming the source region and the drain region includes the steps of: Form a patterned fourth mask layer that exposes the substrate on both sides of the first dielectric layer; Using the fourth mask layer as a mask, dope the substrate exposed by the fourth mask layer to obtain the source region and the drain region.

[0014] Optionally, the step of forming the second field dielectric layer includes the steps of: Form the field dielectric material layer using a low-temperature deposition process; Form a patterned fifth mask layer that covers the field dielectric material layer above the first field dielectric layer; Using the fifth mask layer as a mask, remove other field dielectric material layers outside the area covered by the fifth mask layer to form the second field dielectric layer.

[0015] Optionally, the fifth mask layer also covers the field dielectric material layer on the surface of a partial area of the gate body close to the drain region, so that the obtained second field dielectric layer also covers the surface of the partial area of the gate body close to the drain region.

[0016] Optionally, the method for forming a semiconductor structure further includes the steps of: Form a field plate on the second field dielectric layer, where the field plate is located between the gate body and the drain region in a first direction, and the first direction is the direction from the source region to the drain region.

[0017] Optionally, the number of the field plates is multiple, and the field plates are spaced apart from each other along a second direction on the second field dielectric layer. The second direction and the first direction are both parallel to the surface of the substrate, and the second direction is perpendicular to the first direction.

[0018] Optionally, each of the field plates satisfies one or more of the following: There is a first spacing between each field plate and the source region, where the first spacings corresponding to adjacent field plates are different or the same; There is a second spacing between each field plate and the drain region, where the second spacings corresponding to adjacent field plates are the same or different; Each of the field plates is randomly spaced or evenly spaced along the second direction on the second field dielectric layer; The sizes of each of the field plates along the second direction are different or the same.

[0019] Optionally, the semiconductor structure is a symmetric LDMOS device, the symmetric LDMOS device includes two symmetric semiconductor units, the body region belongs to the semiconductor unit, and the two semiconductor units share the same body region.

[0020] In a second aspect, an embodiment of the present disclosure also discloses a semiconductor structure, including: A substrate having a first region and a drift region therein, the first region and the drift region being adjacent to each other; A first dielectric layer covering the first region and a partial drift region adjacent to the first region. Among them, the first dielectric layer above the partial drift region adjacent to the first region is used as the first field dielectric layer, and the first dielectric layer is formed by a thermal oxidation process; A second field dielectric layer formed by a low-temperature deposition process and covering the first field dielectric layer.

[0021] Optionally, the semiconductor structure further includes: A gate body covering a first dielectric layer above the first region, wherein the first dielectric layer above the first region serves as a gate dielectric layer of the gate structure, and the gate dielectric layer is adjacent to the first field dielectric layer.

[0022] Optionally, the semiconductor structure further includes: A body region located within the substrate, a first portion of the body region being adjacent to the first region and located on a side of the first region away from the drift region, and a second portion of the body region being located within the first region and adjacent to the drift region; wherein the doping type of the body region is different from that of the drift region, and the doping concentration of the second portion of the body region gradually decreases in a direction adjacent to the drift region.

[0023] Optionally, the semiconductor structure further includes: A source region located within the body region and having a doping type different from that of the body region; A drain region located within the drift region and having the same doping type as the drift region; wherein the source region and the drain region are respectively located on two sides of the first dielectric layer.

[0024] Optionally, the semiconductor structure further includes: A field plate located on the second field dielectric layer and located between the gate body and the drain region in a first direction, the first direction being a direction from the source region to the drain region.

[0025] Optionally, the number of the field plates is multiple, and the field plates are spaced apart from each other on the second field dielectric layer along a second direction, the second direction and the first direction being both parallel to the surface of the substrate, and the second direction being perpendicular to the first direction.

[0026] Optionally, each of the field plates satisfies one or more of the following: Each of the field plates has a first spacing from the source region, wherein the first spacings corresponding to adjacent field plates are different or the same; Each of the field plates has a second spacing from the drain region, wherein the second spacings corresponding to adjacent field plates are the same or different; Each of the field plates is randomly spaced or evenly spaced on the second field dielectric layer along the second direction; The sizes of each of the field plates along the second direction are different or the same.

[0027] Optionally, the semiconductor structure is a symmetric LDMOS device, the symmetric LDMOS device includes two symmetric semiconductor units, the body region belongs to the semiconductor unit, and the two semiconductor units share the same body region.

[0028] Compared with the prior art, the technical solution of the embodiment of the present disclosure has the following beneficial effects: An embodiment of the present disclosure provides a method for forming a semiconductor structure, including: providing a substrate having a first region and a drift region therein, the first region and the drift region being adjacent to each other; forming a first dielectric material layer on the substrate by a thermal oxidation process; removing a part of the first dielectric material layer to obtain a first dielectric layer, the first dielectric layer covering the first region and a part of the drift region adjacent to the first region, and the first dielectric layer above the part of the drift region adjacent to the first region being used as a first field dielectric layer; forming a second field dielectric layer on the first field dielectric layer. Compared with directly forming a field dielectric layer with a first thickness on the surface of the drift region by a low-temperature deposition process, the first field dielectric layer in the embodiment of the present disclosure is formed by a thermal oxidation process. Therefore, compared with the former, the technical solution adopted in the embodiment of the present disclosure can reduce the interface defect density between the field dielectric layer and the drift region, thereby improving the uniformity of the electric field distribution near the interface between the drift region and the first dielectric material layer, and further reducing the probability of premature breakdown or hot carrier effect caused by the formation of a local high electric field region, thus improving the reliability of the semiconductor structure. Description of the Drawings

[0029] In order to more clearly illustrate the technical solutions of the embodiments of this specification, the following will briefly introduce the drawings required for use in the description of the embodiments of this specification or the prior art. Obviously, the following described drawings are only some embodiments of this specification. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0030] Figure 1 Shows a flowchart of a method for forming a semiconductor structure in an embodiment of the present disclosure; Figures 2 to 8 Shows a schematic cross-sectional structure diagram corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present disclosure; Figure 9 Shows a top view of a semiconductor structure in an embodiment of the present disclosure.

[0031] Description of the Reference Numerals: Substrate 100, drift region 110, first region 120, body region 130, source region 140, drain region 150, extraction region 160; First dielectric material layer 200, first dielectric layer 210, first field dielectric layer 211, gate dielectric layer 212; Gate material layer 300, gate body 310; Second field dielectric layer 410; Field plate 500; First direction F1, second direction F2. Detailed implementation manners

[0032] As described above, in the structural design of voltage-controlled power devices, it is necessary to improve the reliability of the devices.

[0033] Taking a laterally diffused metal-oxide-semiconductor (LDMOS) device as an example, the LDMOS has a field plate, a field dielectric layer, and a drift region. Among them, the field plate is disposed on the field dielectric layer, the field dielectric layer covers the surface of the drift region, the field plate is isolated from the substrate through the field dielectric layer, and a capacitive structure is formed to modulate the electric field distribution on the surface of the drift region.

[0034] The quality of the interface between the field dielectric layer and the drift region is related to the reliability of the LDMOS. For example, defects at the interface will capture charges. If the defect density at the interface between the two is too high, the captured charge density will be too high, resulting in uneven electric field distribution near the interface between the drift region and the field dielectric layer, forming a local high electric field region that causes premature breakdown or hot carrier effect, thereby reducing the reliability of the LDMOS.

[0035] To solve the above technical problems, an embodiment of the present disclosure provides a method for forming a semiconductor structure, including: providing a substrate having a first region and a drift region adjacent to each other in the substrate; forming a first dielectric material layer on the substrate by a thermal oxidation process; removing a part of the first dielectric material layer to obtain a first dielectric layer, the first dielectric layer covering the first region and a part of the drift region adjacent to the first region, and the first dielectric layer above the part of the drift region adjacent to the first region serving as a first field dielectric layer; forming a second field dielectric layer on the first field dielectric layer.

[0036] Compared with directly forming a field dielectric layer with a first thickness on the surface of the drift region through a low-temperature deposition process, the first field dielectric layer in the embodiment of the present disclosure is formed by a thermal oxidation process. Therefore, compared with the former, the technical solution adopted in the embodiment of the present disclosure can reduce the interface defect density between the field dielectric layer and the drift region, thereby improving the uniformity of the electric field distribution near the interface between the drift region and the first dielectric material layer, and further reducing the probability of forming a local high electric field region that causes premature breakdown or hot carrier effect, and thus can improve the reliability of the semiconductor structure.

[0037] To make the above objects, features, and beneficial effects of the present disclosure more obvious and understandable, the following detailed description of the specific embodiments of the present disclosure will be given with reference to the accompanying drawings.

[0038] Refer to Figure 1 , Figure 1 which is a flowchart of a method for forming a semiconductor structure in an embodiment of the present disclosure. The method for forming a semiconductor structure may include steps S11 to S14: Step S11: Provide a substrate having a first region and a drift region therein, with the first region and the drift region being adjacent to each other. Step S12: Form a first dielectric material layer on the substrate by using a thermal oxidation process. Step S13: Remove a part of the first dielectric material layer to obtain a first dielectric layer, where the first dielectric layer covers the first region and a part of the drift region adjacent to the first region, and the first dielectric layer above the part of the drift region adjacent to the first region serves as the first field dielectric layer. Step S14: Form a second field dielectric layer on the first field dielectric layer.

[0039] The following Figures 2 to 9 is an explanatory description of the above formation method.

[0040] Figures 2 to 8 FIG. is a schematic cross-sectional structure diagram corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present disclosure, Figure 9 and FIG. is a top view of a semiconductor structure according to an embodiment of the present disclosure.

[0041] With reference to Figures 2 to 5 , provide a substrate 100.

[0042] The substrate 100 is used to provide a process platform for the subsequent formation of a semiconductor structure.

[0043] The substrate 100 may be a silicon substrate, or the material of the substrate 100 may further include germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide. The substrate 100 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or a substrate with an epitaxial layer grown thereon.

[0044] In some embodiments, the substrate 100 may have a first region 120 therein, where the first region 120 is used as a diffusion region for the body region 130 and the drift region 110 in subsequent processes.

[0045] In some embodiments, an isolation ring (not shown in the figure) is formed on the substrate 100.

[0046] Specifically, the steps of forming the isolation ring may include: etching the surface of the substrate 100 to obtain an isolation ring groove (not shown); filling the isolation ring groove to obtain an isolation ring.

[0047] Among them, the isolation ring is a ring structure capable of achieving electrical isolation between the structures inside and outside the ring.

[0048] In some embodiments, the material of the isolation ring may be silicon dioxide.

[0049] Form a drift region 110 in the substrate 100.

[0050] Among them, the drift region 110 can be disposed adjacent to the first region 120 in the first direction F1, and the first direction F1 is parallel to the surface of the substrate 100. For example Figure 3 in the first direction F1 is parallel to the upper surface of the substrate 100.

[0051] In some embodiments, the drift region 110 can be formed in the isolation ring by an ion implantation process.

[0052] In some embodiments, the doping type of the drift region 110 can be N-type doping or P-type doping.

[0053] It should be noted that in the following description, N-type doping can be used as an example for illustration, but it does not constitute a limitation on the specific doping type used in the drift region 110.

[0054] Continue to refer to Figure 2 , a first dielectric material layer 200 is formed on the substrate 100 by a thermal oxidation process.

[0055] Specifically, the first dielectric material layer 200 covers the drift region 110. The process temperature of the thermal oxidation process is between 1000 degrees Celsius and 1500 degrees Celsius, and the process temperature of the low-temperature deposition process is between 200 degrees Celsius and 500 degrees Celsius. Compared with the first dielectric material layer 200 prepared by the low-temperature deposition process, the interface state between the first dielectric material layer 200 formed on the substrate 100 by the thermal oxidation process and the substrate 100 is lower, the interface defect density is smaller, and the interface quality is higher.

[0056] In some embodiments, the first dielectric material layer 200 can be a silicon dioxide layer.

[0057] In some embodiments, the thickness of the first dielectric material layer 200 can be between 100 angstroms and 300 angstroms. For example, the thickness of the first dielectric material layer 200 can be 120 angstroms.

[0058] It should be noted that the thickness referred to in this article refers to the dimension in the direction perpendicular to the surface of the substrate 100.

[0059] Continue to refer to Figures 2 to 5 , a gate body 310 of the gate structure is formed on the first dielectric material layer 200 above the first region 120.

[0060] Specifically, forming the gate body 310 of the gate structure may include the steps of: forming a gate material layer 300 on the first dielectric material layer 200; forming a patterned first mask layer (not shown in the figure), the first mask layer covering the gate material layer 300 above the first region 120; using the first mask layer as a mask to remove the other gate material layers 300 outside the covered area of the first mask layer to obtain the gate body 310.

[0061] In some embodiments, a low-temperature deposition process such as Plasma Enhanced Chemical Vapor Deposition (PECVD) or Atomic Layer Deposition (ALD) may be used to form the gate material layer 300.

[0062] It should be noted that, compared with the degree of redistribution of the doping concentration in the substrate 100 during the formation of the gate material layer 300 in the temperature range corresponding to the thermal oxidation process, the degree of redistribution of the doping concentration in the substrate 100 during the formation of the gate material layer 300 in the temperature range corresponding to the low-temperature deposition process can be ignored.

[0063] In some embodiments, the gate material layer 300 may be a polysilicon layer, a metal layer, or a metal silicide layer.

[0064] It can be understood that the material of the subsequently formed gate body 310 is the same as that of the gate material layer 300.

[0065] In some embodiments, the thickness of the gate material layer 300 may be between 100 nanometers and 300 nanometers. For example, the thickness of the gate material layer 300 may be 200 nanometers.

[0066] It can be understood that the thickness of the gate body 310 etched based on the gate material layer 300 is the same as the thickness of the gate material layer 300.

[0067] Continuing with reference to Figure 3 and Figure 5 , removing a part of the first dielectric material layer 200 to obtain the first dielectric layer 210.

[0068] Specifically, forming the first dielectric layer 210 may include the steps of: forming a patterned second mask layer (not shown in the figure), the second mask layer covering the gate body 310 above the first region 120, and the second mask layer also covering the first dielectric material layer 200 above a part of the drift region 110 adjacent to the first region 120; using the second mask layer as a mask to remove the other first dielectric material layers 200 outside the covered area of the second mask layer to obtain the first dielectric layer 210.

[0069] Specifically, the second mask layer serves as a mask to cover the upper surface and the side surface of the gate body 310 above the first region 120, and the upper surface of the first dielectric material layer 200 above the partial drift region 110 adjacent to the first region 120. By removing the portion of the first dielectric material layer 200 exposed by the second mask layer, the obtained first dielectric layer 210 can cover the surface of the first region 120 and the partial drift region 110 adjacent to the first region 120.

[0070] In some embodiments, the first dielectric layer 210 above the first region 120 is used as the gate dielectric layer 212 of the gate structure, and the first dielectric layer 210 above the partial drift region 110 adjacent to the first region 120 is used as the first field dielectric layer 211. The gate dielectric layer 212 is adjacent to the first field dielectric layer 211. Wherein, the material of the gate dielectric layer 212 is the same as that of the first field dielectric layer 211, and the thickness of the gate dielectric layer 212 is the same as that of the first field dielectric layer 211.

[0071] It can be understood that both the first field dielectric layer 211 and the gate dielectric layer 212 belong to the first dielectric layer 210. Actually, they are different names of the first dielectric layer 210 in different regions, and belong to adjacent layer structures formed in the same process. The electrical properties of the first field dielectric layer 211 and the gate dielectric layer 212 are continuously distributed on both sides of their interface, and the interface between the first field dielectric layer 211 and the gate dielectric layer 212 will not cause an electric field spike at the corresponding position of the substrate 100.

[0072] It should be noted that by separating the gate body 310 and the substrate 100, the first dielectric layer 210 can reduce the intensity of the electric field spike caused by the edge position of the gate body 310 at the corresponding position of the substrate 100, which is beneficial to the adjustment of the lateral electric field in the substrate 100. Herein, the lateral direction refers to the direction parallel to the top surface of the substrate 100.

[0073] It should also be noted that compared with the semiconductor structure in which the electrical properties of the first field dielectric layer 211 and the gate dielectric layer 212 are discontinuously distributed on both sides of their interface, the electrical properties of the first field dielectric layer 211 and the gate dielectric layer 212 of the semiconductor structure in the embodiments of the present disclosure are continuously distributed on both sides of their interface. Compared with the former, the switching speed of the semiconductor structure in the embodiments of the present disclosure is lower and the dynamic loss is higher.

[0074] In some embodiments, at least one of dry etching processes such as reactive ion etching (RIE) or wet etching processes such as hydrofluoric acid solution etching can be used to remove the other first dielectric material layer 200 outside the region covered by the second mask layer.

[0075] Continuing with reference to Figures 4 to 5 , a body region 130 is formed.

[0076] Specifically, the step of forming the body region 130 may include: forming a patterned third mask layer (not shown in the figure), the third mask layer exposing a portion of the substrate 100 adjacent to the first region 120, the portion of the substrate 100 being located on a side of the first region 120 away from the drift region 110; using the third mask layer as a mask, doping the portion of the substrate 100 exposed by the third mask layer to obtain the body region 130.

[0077] Wherein, the doping type of the body region 130 is different from the doping type of the drift region 110, and at this time, the body region 130 is located on a side of the first region 120 away from the drift region 110.

[0078] It should be noted that the interface between the body region 130 and the drift region 110, as well as the edge of the gate body 310, will introduce electric field spikes in the substrate 100. The overlap of their corresponding projections on the surface of the substrate 100 will cause the superposition of the electric field spikes introduced by the two, resulting in an excessively high local electric field, premature breakdown, or hot carrier effect, thereby reducing the reliability of the LDMOS.

[0079] With reference to Figures 5 to 6 , in some embodiments, the step of forming the body region 130 may further include: annealing the semiconductor structure so that both the body region 130 and the drift region 110 diffuse toward the first region 120 until the diffused body region 130 is adjacent to the drift region 110.

[0080] Wherein, the projection of the interface between the body region 130 and the drift region 110 after annealing on the surface of the substrate 100 is located within the projection of the gate body 310 on the surface of the substrate 100, and there is a spacing between the projection of the interface on the surface of the substrate 100 and the boundary of the projection of the gate body 310 on the surface of the substrate 100.

[0081] It can be understood that by optimizing the concentration parameters of the body region 130 and the concentration parameters of the drift region 110, the value of the spacing can be controlled, thereby adjusting the interface between the first region 120 and the drift region 110 and the coverage boundary of the gate body 310 in the first dielectric layer 210, thereby improving the problem of the superposition of the electric field spikes introduced by the two.

[0082] Wherein, the doping concentration of the portion of the body region 130 formed in the first region 120 below the gate dielectric layer gradually decreases in a direction adjacent to the drift region 110, and the doping concentration of the portion of the drift region 110 formed in the first region 120 below the gate dielectric layer gradually decreases in a direction adjacent to the body region 130.

[0083] This can reduce the doping concentration at the interface between the body region 130 and the drift region 110, thereby increasing the widths of the depletion regions in the body region 130 and the drift region 110, and further improving the breakdown voltage of the semiconductor structure.

[0084] Continue to refer to Figure 6 , a source region 140 is formed in the body region 130 exposed by the first dielectric layer 210, and a drain region 150 is formed in the drift region 110 exposed by the first dielectric layer 210.

[0085] Among them, the doping type of the source region 140 is different from that of the body region 130, the doping type of the drain region 150 is the same as that of the source region 140 and the drift region 110, and the doping concentration of the drain region 150 is higher than that of the drift region 110.

[0086] In some embodiments, the source region 140 and the drain region 150 can have various formation sequences. For example, during the formation of the source region 140, the drain region 150 is formed. For example, the source region 140 can be formed after the drain region 150. For example, the source region 140 can be formed before the drain region 150.

[0087] As a specific example, the steps of forming the source region 140 and the drain region 150 may include: forming a patterned fourth mask layer (not shown in the figure), the fourth mask layer exposing the substrate 100 on both sides of the first dielectric layer 210, and using the fourth mask layer as a mask to dope the substrate 100 exposed by the fourth mask layer to obtain the source region 140 and the drain region 150.

[0088] It can be understood that forming the source region 140 and the drain region 150 synchronously can simplify the doping steps, reduce the number of photomasks, and reduce the process cost during the preparation process.

[0089] Continue to refer to Figure 6 , an extraction region 160 is formed in the source region 140.

[0090] Specifically, the bottom surface of the extraction region 160 is adjacent to the body region 130, the doping type of the extraction region 160 is the same as that of the body region 130, and the doping concentration is higher than that of the body region 130, so that the extraction region 160 can extract the charges accumulated in the body region 130, thereby reducing the potential fluctuation of the body region 130.

[0091] Refer to Figure 7 , a second field dielectric layer 410 is formed on the first field dielectric layer 211.

[0092] Specifically, the steps of forming the second field dielectric layer 410 may include: forming a field dielectric material layer (not shown in the figure); forming a patterned fifth mask layer (not shown in the figure), the fifth mask layer covering the field dielectric material layer above the first field dielectric layer 211; using the fifth mask layer as a mask to remove other field dielectric material layers outside the area covered by the fifth mask layer to obtain the second field dielectric layer 410.

[0093] In some embodiments, a low-temperature deposition process may be used to form the field dielectric material layer.

[0094] It can be understood that the process temperature of the low-temperature deposition process is between 200 degrees Celsius and 500 degrees Celsius. Forming the field dielectric material layer within this temperature range can reduce the redistribution of the doping concentration in each doped region within the substrate 100 during the formation process.

[0095] In some embodiments, the thickness of the second field dielectric layer 410 is greater than the thickness of the first dielectric layer 210. The thickness of the second field dielectric layer 410 may be between 100 nanometers and 300 nanometers. For example, the thickness of the second field dielectric layer 410 may be 200 nanometers.

[0096] In some embodiments, the second field dielectric layer 410 may be a silicon dioxide layer.

[0097] It should be noted that the field dielectric layer in the embodiments of the present disclosure includes: the first field dielectric layer 211 formed on the surface of the drift region 110 through a thermal oxidation process, and the second field dielectric layer 410 formed on the surface of the first field dielectric layer 211 through a low-temperature deposition process. The sum of the thickness of the first field dielectric layer 211 and the thickness of the second field dielectric layer 410 is the first thickness. The advantages of the preparation process in the embodiments of the present disclosure are specifically analyzed below: First, the degree of redistribution of the doping concentration in each doped region within the substrate 100 caused by the low-temperature deposition process is much smaller than the degree of redistribution of the doping concentration in each doped region within the substrate 100 during the thermal oxidation process. Compared with directly forming a field dielectric layer with the first thickness on the surface of the drift region 110 through a thermal oxidation process, in the embodiments of the present disclosure, only the first field dielectric layer 211 is formed through a thermal oxidation process, and the second field dielectric layer 410 is formed through a low-temperature deposition process. Therefore, compared with the former, the technical solution adopted in the embodiments of the present disclosure can reduce the process time of the thermal oxidation process, thereby reducing the degree of redistribution of the doping concentration in each doped region within the substrate 100 and improving the reliability of the semiconductor structure; In a second aspect, the interface defect density between the field dielectric layer formed by the thermal oxidation process and the drift region 110 is lower than that between the field dielectric layer formed by the low-temperature deposition process and the drift region 110. Compared with directly forming a field dielectric layer with a first thickness on the surface of the drift region 110 by the low-temperature deposition process, in the embodiment of the present disclosure, the first field dielectric layer 211 is formed by the thermal oxidation process. Therefore, compared with the former, the technical solution adopted in the embodiment of the present disclosure can reduce the interface defect density between the field dielectric layer and the drift region 110, thereby improving the uniformity of the electric field distribution near the interface between the drift region 110 and the first dielectric material layer 200, and further reducing the probability of premature breakdown or hot carrier effect caused by the formation of a local high electric field region, thus improving the reliability of the semiconductor structure.

[0098] In summary, the formation method of the field dielectric layer in the embodiment of the present disclosure can achieve a balance between reducing the "interface defect density between the field dielectric layer and the drift region 110" and reducing the "degree of redistribution of the doping concentration in each doping region within the substrate 100 during the formation process of the field dielectric layer".

[0099] It should be noted that the first field dielectric layer 211 and the second field dielectric layer 410 are formed successively by different processes, and due to the process temperature difference, a large number of defects exist at the interface between the first field dielectric layer 211 and the second field dielectric layer 410. These defects can capture and accumulate carriers, resulting in threshold voltage drift.

[0100] Refer to Figure 8 , a field plate 500 is formed on the second field dielectric layer 410.

[0101] In actual use, the field plate 500 is used to connect an external electrode (not shown in the figure). By connecting to the external electrode, the field plate 500 can form an electric field perpendicular to the top surface of the substrate 100. This electric field can disperse the carriers captured and accumulated at the interface between the first field dielectric layer 211 and the second field dielectric layer 410, reducing the drift amount of the threshold voltage.

[0102] In addition, by connecting to the external electrode, the field plate 500 can also introduce a fixed potential, avoiding the introduction of random potentials in the first field dielectric layer 211 and the second field dielectric layer 410 due to the floating effect, ensuring that the first field dielectric layer 211 and the second field dielectric layer 410 are at a fixed potential, thereby stabilizing the lateral electric field within the substrate 100.

[0103] Specifically, the steps of forming the field plate 500 may include: forming a patterned sixth mask layer (not shown in the figure), the sixth mask layer exposing a partial region of the second field dielectric layer 410, the partial region being located between the gate body 310 and the drain region 150 in a first direction F1, where the first direction F1 refers to the direction from the source region 140 pointing to the drain region 150; using the sixth mask layer as a mask to remove the partial region of the second field dielectric layer 410 exposed by the sixth mask layer to form a field plate groove; forming a field plate material layer by a low-temperature deposition process; forming a patterned seventh mask layer (not shown in the figure), the seventh mask layer covering the field plate material layer above the field plate groove; using the seventh mask layer as a mask to remove the field plate 500 material layer exposed by the seventh mask layer to form the field plate 500, where the field plate 500 is located in the field plate groove.

[0104] In some embodiments, after forming the field plate 500, an annealing process is further performed on the semiconductor structure.

[0105] The annealing process can promote the atomic diffusion at the interface between the first field dielectric layer 211 and the second field dielectric layer 410, thereby reducing the amount of defects at this interface, and thus reducing the amount of carriers trapped and accumulated at the interface between the first field dielectric layer 211 and the second field dielectric layer 410, and further reducing the drift amount of the threshold voltage.

[0106] In some embodiments, the thickness of the field plate 500 is greater than or equal to the depth of the field plate groove.

[0107] In some embodiments, the material of the field plate 500 can be polysilicon.

[0108] It should be noted that, in some embodiments, the fifth mask layer also covers the field dielectric material layer on the surface of a partial region of the gate body 310 near the drain region 150.

[0109] This can enable the obtained second field dielectric layer 410 to also cover the surface of a partial region of the gate body 310 near the drain region 150. The second field dielectric layer 410 covering the surface of a partial region of the gate body 310 near the drain region 150 can play an isolation role and reduce the probability of forming an electrical path due to the direct contact between the field plate 500 and the gate body 310.

[0110] In some embodiments, the number of the field plates 500 can be one or more.

[0111] In some embodiments, there is a first spacing between each field plate 500 and the source region 140, where the first spacings corresponding to adjacent field plates 500 can be different or the same.

[0112] In some embodiments, there is a second spacing between each field plate 500 and the drain region 150, where the second spacings corresponding to adjacent field plates 500 may be the same or different.

[0113] In some embodiments, each field plate 500 may be randomly spaced or evenly spaced along the second direction.

[0114] In some embodiments, the sizes of each field plate 500 along the second direction may be different or the same.

[0115] As a specific example, with reference to Figure 8 and Figure 9 , the number of field plates 500 may be multiple. Each field plate 500 is spaced along the second direction F2 on the second field dielectric layer 410. The first spacings corresponding to adjacent field plates 500 are different, and the second spacings corresponding to adjacent field plates 500 are the same. Each field plate 500 is randomly spaced along the second direction F2, and the sizes of each field plate 500 along the second direction F2 are different. Wherein, the second direction F2 and the first direction F1 are both parallel to the surface of the substrate 100, and the second direction F2 is perpendicular to the first direction F1.

[0116] Specifically, each field plate 500 is spaced along the second direction F2 on the second field dielectric layer 410. The edges of each field plate 500 can introduce more evenly spaced electric field peaks at the corresponding positions along the second direction F2 in the substrate 100, so as to further optimize the lateral electric field in the substrate 100 in the second direction F2; the first spacings corresponding to adjacent field plates 500 are different, so the edges of adjacent field plates 500 close to the source region 140 are not on a straight line, thereby reducing the superposition intensity of the electric fields introduced by each field plate 500 in the second direction F2.

[0117] In some embodiments, the semiconductor structure may be an LDMOS device, and the LDMOS device includes a semiconductor cell. Wherein, the semiconductor cell may include a drift region 110, a body region 130, a source region 140, a drain region 150, an extraction region 160, a gate body 310, a first dielectric layer 210, and a second field dielectric layer 410.

[0118] Furthermore, the semiconductor structure may be a symmetric LDMOS device, and the symmetric LDMOS device includes two symmetric semiconductor cells, and the two symmetric semiconductor cells share the same body region, source region, and extraction region.

[0119] Specifically, sharing the same body region, source region, and extraction region can improve the current driving ability of the LDMOS device, and at the same time simplify the layout and improve the integration of the device.

[0120] It should be noted that, except for the shared body region, source region, and extraction region, each semiconductor unit in the symmetric LDMOS device may have its own drift region, drain region, gate body, first dielectric layer, and second field dielectric layer, and the above-mentioned various parts may be completely identical or may not be completely identical. It should also be noted that each semiconductor unit has its own first direction F1. The first direction of each semiconductor unit refers to the direction from the source region 140 to the drain region 150 in the semiconductor unit. The first directions F1 of different semiconductor units may be different. For example Figures 1 to 9 the first directions F1 of two semiconductor units under the same semiconductor structure in

[0121] In an embodiment of the present disclosure, a semiconductor structure may also be provided. With reference to Figures 2 to 9 , the semiconductor structure may include: a substrate 100, a first dielectric layer 210, and a second field dielectric layer 410. The substrate 100 has a first region 120 and a drift region 110 therein, and the first region 120 and the drift region 110 are adjacent to each other; the first dielectric layer 210 covers the first region 120 and a part of the drift region 110 adjacent to the first region 120. Among them, the first dielectric layer 210 above the part of the drift region 110 adjacent to the first region 120 is used as the first field dielectric layer 211, and the first dielectric layer 210 is formed by a thermal oxidation process; the second field dielectric layer 410 is formed by a low-temperature deposition process and covers the first field dielectric layer 211.

[0122] In some embodiments, the semiconductor structure may further include: a gate body 310.

[0123] Among them, the gate body 310 covers the first dielectric layer 210 above the first region 120. The first dielectric layer 210 above the first region 120 serves as the gate dielectric layer 212 of the gate structure, and the gate dielectric layer 212 is adjacent to the first field dielectric layer 211.

[0124] In some embodiments, the semiconductor structure may further include: a body region 130.

[0125] Among them, the body region 130 is located in the substrate 100. The first part of the body region 130 is adjacent to the first region 120 and is located on the side of the first region 120 away from the drift region 110. The second part of the body region 130 is located in the first region 120 and is adjacent to the drift region 110; the doping type of the body region 130 is different from that of the drift region 110, and the doping concentration of the second part of the body region 130 gradually decreases along the direction adjacent to the drift region 110.

[0126] In some embodiments, the semiconductor structure may further include: a source region 140 and a drain region 150.

[0127] Among them, the source region 140 is located within the body region 130 and has a different doping type from that of the body region 130; the drain region 150 is located within the drift region 110 and has the same doping type as that of the drift region 110; among them, the source region 140 and the drain region 150 are respectively located on both sides of the first dielectric layer 210.

[0128] In some embodiments, the semiconductor structure may further include: a field plate 500.

[0129] Among them, the field plate 500 is located on the second field dielectric layer 410 and is located between the gate body 310 and the drain region 150 in the first direction F1, and the first direction F1 is the direction from the source region 140 to the drain region 150.

[0130] In some embodiments, the number of the field plates 500 is multiple, and the respective field plates 500 are spaced apart along the second direction F2 on the second field dielectric layer 410. The second direction F2 and the first direction F1 are both parallel to the surface of the substrate 100, and the second direction F2 is perpendicular to the first direction F1.

[0131] In some embodiments, each of the field plates 500 satisfies one or more of the following: there is a first spacing between each of the field plates 500 and the source region 140, and among them, the first spacings corresponding to adjacent field plates 500 are different or the same; there is a second spacing between each of the field plates 500 and the drain region 150, and among them, the second spacings corresponding to adjacent field plates 500 are the same or different; each of the field plates 500 is randomly spaced or evenly spaced along the second direction F2 on the second field dielectric layer 410; the sizes of each of the field plates 500 along the second direction F2 are different or the same.

[0132] In some embodiments, the semiconductor structure is a symmetric LDMOS device. The symmetric LDMOS device includes two symmetric semiconductor units. The body region 130 belongs to the semiconductor unit, and the two semiconductor units share the same body region 130.

[0133] It should be noted that for the principle, specific implementation, and beneficial effects of this semiconductor structure, please refer to the foregoing and Figures 2 to 9 the related description of the formation method of the semiconductor structure shown, which will not be elaborated here.

[0134] It can be understood that the term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0135] It can be understood that the "plurality" mentioned in this text refers to two or more. The descriptions such as first and second in the embodiments of this application are only for schematic and differentiating the described objects, without order, nor do they represent special limitations on the number of devices in the embodiments of this application, and cannot constitute any limitation to the embodiments of this application.

[0136] It can be understood that the above text describes multiple embodiment solutions provided by the embodiments of the present disclosure. The optional methods described in each embodiment solution can be combined and cross-referenced with each other without conflict, so as to extend multiple possible embodiment solutions, and all of these can be considered as the embodiment solutions disclosed and made public by the present disclosure.

[0137] Although the embodiments of the present disclosure are disclosed as above, the present disclosure is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: Includes: Providing a substrate, wherein the substrate has a first region and a drift region, wherein the first region and the drift region are adjacently arranged; forming a first dielectric material layer on the substrate by a thermal oxidation process; Removing part of the first dielectric material layer to obtain a first dielectric layer, wherein the first dielectric layer covers the first region and a part of the drift region adjacent to the first region, and the first dielectric layer above the part of the drift region adjacent to the first region serves as a first field dielectric layer; A second field dielectric layer is formed on the first field dielectric layer.

2. The forming method according to claim 1, characterized in that: Before forming the first dielectric layer, the method further comprises the following steps: A gate body of a gate structure is formed on a first dielectric material layer above the first region, wherein the first dielectric material layer above the first region serves as a gate dielectric layer of the gate structure, and the gate dielectric layer is adjacent to the first field dielectric layer.

3. The forming method according to claim 2, characterized in that: The method for forming a gate body of a gate structure comprises the following steps: forming a gate material layer on the first dielectric material layer; forming a patterned first mask layer, wherein the first mask layer covers the first gate material layer above the first region; Using the first mask layer as a mask, other gate material layers outside the area covered by the first mask layer are removed to obtain the gate body.

4. The forming method according to claim 3, characterized in that: The method of removing part of the first dielectric material layer to obtain the first dielectric layer comprises the following steps: forming a patterned second mask layer, wherein the second mask layer covers the gate body above the first region and also covers the first dielectric material layer above a portion of the drift region adjacent to the first region; Using the second mask layer as a mask, other first dielectric material layers outside the area covered by the second mask layer are removed to obtain the first dielectric layer.

5. The forming method according to claim 4, characterized in that: Before forming the second field dielectric layer, the method further comprises the following steps: forming a body region, wherein the body region and the drift region have a different doping type; forming a source region in the body region, wherein the source region and the body region have different doping types; A drain region is formed in the drift region, and the drain region has the same doping type as the drift region.

6. The forming method according to claim 5, characterized in that: Forming the body region comprises the steps of: forming a patterned third mask layer, wherein the third mask layer exposes a portion of the substrate adjacent to the first region, the portion of the substrate being located on a side of the first region away from the drift region; The third mask layer is used as a mask to dope a portion of the substrate exposed by the third mask layer to obtain the body region.

7. The forming method according to claim 6, characterized in that: The forming of the body region further comprises the steps of: The semiconductor structure is annealed so that the body region diffuses toward the first region until it is adjacent to the drift region, and the doping concentration of the body region below the gate dielectric layer gradually decreases along a direction adjacent to the drift region.

8. The forming method according to claim 5, characterized in that: The source region and the drain region are formed, comprising the steps of: forming a patterned fourth mask layer, wherein the fourth mask layer exposes the substrate on both sides of the first dielectric layer; The fourth mask layer is used as a mask to dope the substrate exposed by the fourth mask layer to obtain the source region and the drain region.

9. The forming method according to claim 5, characterized in that: The second field dielectric layer is formed, comprising the steps of: Forming the field dielectric material layer by a low temperature deposition process; forming a patterned fifth mask layer, wherein the fifth mask layer covers the field dielectric material layer above the first field dielectric layer; Using the fifth mask layer as a mask, other field dielectric material layers outside the area covered by the fifth mask layer are removed to form the second field dielectric layer.

10. The forming method according to claim 9, characterized in that: The fifth mask layer also covers the field dielectric material layer on a partial surface area of ​​the gate body near the drain region, so that the obtained second field dielectric layer also covers a partial surface area of ​​the gate body near the drain region.

11. The forming method according to claim 5, characterized in that: Also includes the steps: A field plate is formed on the second field dielectric layer. The field plate is located between the gate body and the drain region in a first direction. The first direction is a direction from the source region to the drain region.

12. The forming method according to claim 11, characterized in that: There are multiple field plates, each of which is spaced apart and distributed on the second field dielectric layer along a second direction. The second direction and the first direction are both parallel to the surface of the substrate, and the second direction is perpendicular to the first direction.

13. The forming method according to claim 12, characterized in that: Each field plate satisfies one or more of the following: There is a first distance between each field plate and the source region, wherein the first distances corresponding to adjacent field plates are different or consistent; There is a second distance between each field plate and the drain region, wherein the second distances corresponding to adjacent field plates are consistent or different; The field plates are randomly or evenly distributed on the second field dielectric layer along the second direction; The sizes of the field plates along the second direction are different or the same.

14. The forming method according to claim 5, characterized in that: The semiconductor structure is a symmetrical LDMOS device, which includes two symmetrical semiconductor units. The body region belongs to the semiconductor unit, and the two semiconductor units share the same body region.

15. A semiconductor structure, characterized in that: include: A substrate, wherein the substrate has a first region and a drift region, and the first region and the drift region are adjacently arranged; a first dielectric layer covering the first region and a portion of the drift region adjacent to the first region, wherein the first dielectric layer above the portion of the drift region adjacent to the first region is used as a first field dielectric layer, and the first dielectric layer is formed by a thermal oxidation process; The second field dielectric layer is formed by adopting a low temperature deposition process and covers the first field dielectric layer.

16. The semiconductor structure according to claim 15, characterized in that Also includes: The gate body covers the first dielectric layer above the first region, wherein the first dielectric layer above the first region serves as a gate dielectric layer of the gate structure, and the gate dielectric layer is adjacent to the first field dielectric layer.

17. The semiconductor structure according to claim 16, characterized in that: Also includes: a body region located in the substrate, wherein a first portion of the body region is adjacent to the first region and located on a side of the first region away from the drift region, and a second portion of the body region is located in the first region and adjacent to the drift region; The body region and the drift region have different doping types, and the doping concentration of the second portion of the body region gradually decreases along a direction adjacent to the drift region.

18. The semiconductor structure according to claim 17, characterized in that: Also includes: a source region, located in the body region and having a doping type different from that of the body region; a drain region, located in the drift region and having the same doping type as the drift region; Wherein, the source region and the drain region are respectively located on two sides of the first dielectric layer.

19. The semiconductor structure according to claim 18, characterized in that Also includes: The field plate is located on the second field dielectric layer and between the gate body and the drain region in a first direction, wherein the first direction is a direction from the source region to the drain region.

20. The semiconductor structure according to claim 19, characterized in that There are multiple field plates, each of which is spaced apart and distributed on the second field dielectric layer along a second direction. The second direction and the first direction are both parallel to the surface of the substrate, and the second direction is perpendicular to the first direction.

21. The semiconductor structure according to claim 20, characterized in that Each field plate satisfies one or more of the following: There is a first distance between each field plate and the source region, wherein the first distances corresponding to adjacent field plates are different or consistent; There is a second distance between each field plate and the drain region, wherein the second distances corresponding to adjacent field plates are consistent or different; The field plates are randomly or evenly distributed on the second field dielectric layer along the second direction; The sizes of the field plates along the second direction are different or the same.

22. The semiconductor structure according to claim 17, wherein: The semiconductor structure is a symmetrical LDMOS device, which includes two symmetrical semiconductor units. The body region belongs to the semiconductor unit, and the two semiconductor units share the same body region.

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