Semiconductor structure and forming method thereof
By introducing a bottom isolation layer into the FinFET structure, the problem of poor gate control capability of traditional MOSFETs after the feature size is reduced is solved, and better DC performance and lower leakage current are achieved.
Patent Information
- Application Number
- CN202311745297.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-18
- Publication Date
- 2025-06-24
AI Technical Summary
After the integrated circuit characteristic size is reduced, the gate structure's control ability of the channel becomes worse, resulting in an increase in leakage current and affecting device performance.
It adopts a fin field effect transistor (FinFET) structure, which includes a substrate, fin portion, gate structure, source-drain doped layer and bottom isolation layer. The bottom of the source-drain doped layer and the substrate are isolated by forming a groove in the fin and forming a bottom isolation layer at the bottom thereof, thereby improving leakage problems.
It improves the DC performance of the semiconductor structure, enhances the gate control ability to channel, reduces leakage current, and thus improves the overall performance of the device.
Smart Images
Figure CN120201745A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art
[0002] In semiconductor manufacturing, as the feature size of integrated circuits continues to decrease, the channel length of traditional planar Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) also continuously shortens accordingly, the distance between the source and drain of the device also shortens, and the control ability of the gate structure over the channel becomes worse, especially for the part of the channel region far from the gate. Therefore, after semiconductor devices are scaled down, the corresponding short gate length of traditional planar transistors can lead to gate failure, thereby substantially cutting off the channel region.
[0003] With the development of semiconductor technology, FinField-Effect Transistors (FinFETs) have emerged as an effective alternative to further reduce the leakage current in semiconductor devices. In a FinFET, the active region includes a drain, a channel region, and a source, where the active region is located on a semiconductor substrate. Similar to fins, the active region of a FinFET is rectangular in cross-section. In addition, the gate structure of a FinFET surrounds the active region from three sides like an inverted U. Therefore, the control of the gate structure over the channel becomes stronger. The short-channel leakage effect of traditional planar transistors has been reduced. Thus, when the FinFET is turned off, the gate structure can better control the channel to reduce the leakage current.
[0004] Although current FinFET devices and methods for manufacturing FinFET devices are generally sufficient for their intended purposes, the performance of FinFET devices still needs to be improved. Summary of the Invention
[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, to improve the performance of the semiconductor structure.
[0006] To solve the above problems, embodiments of the present invention provide a semiconductor structure, including: a substrate; a fin portion protruding from the substrate; a gate structure spanning the fin portion, and the gate structure covering a part of the top and a part of the sidewalls of the fin portion; source-drain doping layers located in the fin portions on both sides of the gate structure; and a bottom isolation layer located at the bottom of the source-drain doping layers and in contact with the bottoms of the source-drain doping layers.
[0007] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate with fins formed thereon; forming a gate structure on the substrate, the gate structure straddling the fins, and the gate structure covering a part of the top and part of the sidewalls of the fins; forming grooves in the fins on both sides of the gate structure; forming a bottom isolation layer in the grooves, and the top surface of the bottom isolation layer is lower than the top surface of the grooves; forming source-drain doping layers on the bottom isolation layer in the grooves.
[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0009] An embodiment of the present invention provides a semiconductor structure, where the source-drain doping layers are located in the fins on both sides of the gate structure, and the bottom isolation layer (Bottom dielectric insulator, BDI) is located at the bottom of the source-drain doping layers and is in contact with the bottom of the source-drain doping layers. In the embodiment of the present invention, the bottom isolation layer is used to isolate the bottom of the source-drain doping layers from the substrate, thereby improving the leakage problem between the substrate and the fins. Moreover, compared with the case where only the source-drain doping layers exist, the overall thickness of the source-drain doping layers and the bottom isolation layer is greater. Therefore, the overall morphology formed by the source-drain doping layers and the bottom isolation layer is more likely to meet the requirements for improving the DC performance of the device, thereby improving the performance of the semiconductor structure.
[0010] An embodiment of the present invention provides a method for forming a semiconductor structure. After forming grooves in the fins on both sides of the gate structure, a bottom isolation layer is formed in the grooves, and the top surface of the bottom isolation layer is lower than the top surface of the grooves. Then, source-drain doping layers are formed on the bottom isolation layer. By forming the bottom isolation layer at the bottom of the grooves, the bottom isolation layer can isolate the bottom of the source-drain doping layers from the substrate, thereby improving the substrate leakage problem. Moreover, both the source-drain doping layers and the bottom isolation layer are formed in the grooves. Compared with the grooves only used to accommodate the source-drain doping layers, the depth of the grooves in the embodiment of the present invention is equal to the sum of the thicknesses of the parts of the source-drain doping layers located in the grooves and the bottom isolation layer. The depth of the grooves is greater, and the morphology of the grooves with a greater depth is more likely to meet the requirements for improving the DC performance of the device, thereby improving the performance of the semiconductor structure. Description of the Drawings
[0011] Figures 1 to 7 are schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure;
[0012] Figures 8 to 17 are schematic structural diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention;
[0013] Figure 18 is a schematic structural diagram of an embodiment of the semiconductor structure of the present invention. Detailed implementation manners
[0014] Currently, the performance of semiconductor structures needs to be improved. In combination with a method for forming a semiconductor structure, the reasons why the performance of semiconductor structures needs to be improved are analyzed.
[0015] Figures 1 to 7 FIGs. are schematic diagrams of structures corresponding to respective steps in a method for forming a semiconductor structure. Specifically, Figures 1 to 3 is a cross-sectional view along a direction perpendicular to the extending direction of the fin, Figures 4 to 7 is a cross-sectional view along a direction parallel to the extending direction of the fin.
[0016] Referring to Figure 1 , a substrate 10 is provided.
[0017] Referring to Figure 2 , the substrate 10 is patterned, and fins 19 are formed on the remaining substrate 10, and the fins 19 protrude from the substrate 10;
[0018] Referring to Figure 3 , an isolation structure 12 is formed on the substrate 10 on the side of the fins 19, and the top of the isolation structure 12 is lower than the top of the fins 19 and covers a part of the sidewalls of the fins 19.
[0019] Referring to Figure 4 , a gate structure 14 is formed on the isolation structure 12, the gate structure straddles the fins 19, and the gate structure 14 covers a part of the top and a part of the sidewalls of the fins 19.
[0020] Specifically, the step of forming the gate structure 14 includes: depositing a polysilicon material layer (not shown in the figure) on the substrate 10; depositing a silicon nitride material layer 13 on the polysilicon material layer; depositing a silicon oxide layer 12B on the silicon nitride material layer 13; patterning the silicon oxide layer 12B, and using the patterned silicon oxide layer 12B as a mask to pattern the silicon nitride material layer 13 and the polysilicon material layer in sequence, and patterning the polysilicon material layer into the gate structure 14.
[0021] Referring to Figure 5 , a spacer material layer 15 is formed on the fins 19 and the gate structure 14.
[0022] Referring to Figure 6 , the spacer material layer 15 on the fins 19 on both sides of the gate structure 14 is removed; after removing the spacer material layer 15 on the fins 19, grooves 11 are formed in the fins 19 on both sides of the gate structure 14.
[0023] Referring to Figure 7 , source / drain doping layers 16 are formed in the grooves 11.
[0024] It has been found through research that the DC characteristics of semiconductor devices are related to the groove morphology of the source-drain doping layer. The groove morphology is U-shaped, and the better the DC characteristics of the semiconductor device. However, in the current prior art, the depth of the groove of the source-drain doping layer is small, and the morphology of the groove is close to a bowl shape, resulting in poor DC performance of the semiconductor device.
[0025] To solve the above technical problems, an embodiment of the present invention provides a structure of a semiconductor structure, including: a substrate; a fin portion protruding from the substrate; a gate structure spanning the fin portion, and the gate structure covering a part of the top and a part of the sidewall of the fin portion; source-drain doping layers located in the fin portions on both sides of the gate structure; a bottom isolation layer located at the bottom of the source-drain doping layers and in contact with the bottom of the source-drain doping layers.
[0026] In the solution disclosed in the embodiment of the present invention, the source-drain doping layers are located in the fin portions on both sides of the gate structure, and the bottom isolation layer is located at the bottom of the source-drain doping layers and in contact with the bottom of the source-drain doping layers. The embodiment of the present invention isolates the bottom of the source-drain doping layers from the substrate through the bottom isolation layer, thereby improving the leakage problem between the substrate and the fin portion. Moreover, compared with the case where only the source-drain doping layers exist, the overall thickness of the source-drain doping layers and the bottom isolation layer is greater. Therefore, the overall morphology formed by the source-drain doping layers and the bottom isolation layer is more likely to meet the requirement of improving the DC performance of the device, thereby improving the performance of the semiconductor structure.
[0027] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.
[0028] Figure 18 It is a schematic structural diagram of an embodiment of the semiconductor structure of the present invention.
[0029] The semiconductor structure includes: a substrate (not shown in the figure); a fin portion 39 protruding from the substrate; a gate structure 34 spanning the fin portion 39, and the gate structure 34 covering a part of the top and a part of the sidewall of the fin portion 39; source-drain doping layers 36 located in the fin portions 39 on both sides of the gate structure 34; a bottom isolation layer 38 located at the bottom of the source-drain doping layers 36 and in contact with the bottom of the source-drain doping layers 36.
[0030] The substrate is used to provide a process platform for the formation of the semiconductor structure.
[0031] In this embodiment, the material of the substrate is silicon. In other embodiments, the material of the substrate can also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium. The substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
[0032] In this embodiment, the semiconductor structure is a fin field-effect transistor, and the discrete fin portions 39 on the substrate are used to provide the channels of the fin field-effect transistor.
[0033] In this embodiment, the fin portions 39 are located on the substrate.
[0034] The material of the fin portions 39 includes one or more of silicon, silicon germanide, germanium, and group III-V semiconductor materials, and the material of the fin portions 39 is determined according to the channel conduction type and performance requirements of the transistor.
[0035] In this embodiment, the material of the fin portions 39 located on the substrate is silicon germanide.
[0036] In this embodiment, the semiconductor structure is a fin field-effect transistor, and the gate structure 34 is used to control the opening and pinching off of the conductive channel (not labeled) in the fin portions 39.
[0037] The gate structure 34 straddles the fin portions 39, and the gate structure 34 covers part of the top and part of the sidewalls of the fin portions 39.
[0038] In this embodiment, the gate structure 34 is a polysilicon gate structure. In other embodiments, the gate structure can also be a metal gate structure.
[0039] The source / drain doping layer 36 is used to provide a carrier source for the channel during device operation.
[0040] In this embodiment, the source / drain doping layer 36 is located in the fin portions 39 on both sides of the gate structure 34.
[0041] In this embodiment, the source / drain doping layer 36 includes a stressed layer doped with ions, so as to be able to provide stress for the channel, which is beneficial to improving the carrier mobility in the channel region.
[0042] When forming a PMOS transistor, the material of the stressed layer is Si or SiGe, and the doping ions in the stressed layer are P-type ions; when forming an NMOS transistor, the material of the stressed layer is Si or SiC, and the doping ions in the stressed layer are N-type ions.
[0043] The bottom isolation layer 38 is located at the bottom of the source / drain doping layer 36 and is in contact with the bottom of the source / drain doping layer 36. The bottom isolation layer 38 isolates the bottom of the source / drain doping layer 36 from the substrate, thereby improving the leakage problem between the substrate and the fin portions 39. Moreover, compared with the case where only the source / drain doping layer exists, the overall thickness of the source / drain doping layer 36 and the bottom isolation layer 38 is larger, so the morphology of the source / drain doping layer 36 and the bottom isolation layer 38 is more likely to meet the requirements for improving the DC performance of the device.
[0044] In this embodiment, the distance from the bottom surface of the bottom isolation layer 38 to the top surface of the fin 39 is equal to the sum of the thickness of the bottom isolation layer 38 and the target thickness of the source / drain doping layer 36 located in the fin 39, so that the overall thickness of the source / drain doping layer 36 and the bottom isolation layer 38 is greater. Here, the target thickness of the source / drain doping layer 36 located in the fin 39 refers to the target thickness of the part of the source / drain doping layer 36 located in the fin 39.
[0045] The material of the bottom isolation layer 38 includes silicon oxide or silicon carbide.
[0046] In this embodiment, the overall morphology formed by the source / drain doping layer 36 and the bottom isolation layer 38 includes a U shape.
[0047] Specifically, the overall morphology formed by the source / drain doping layer 36 and the bottom isolation layer 38 includes a U shape, which improves the current gain (I on ) by shortening the average channel length, thereby improving the DC performance of the semiconductor structure.
[0048] In this embodiment, the semiconductor structure further includes: grooves 21 (refer to Figure 16 ), which are located in the fins 39 on both sides of the gate structure 34.
[0049] The grooves 21 are used to accommodate the bottom isolation layer 38 and the source / drain doping layer 36.
[0050] Correspondingly, the bottom isolation layer 38 is located in the grooves 21 in the fins 39 on both sides of the gate structure 34, and the top surface of the bottom isolation layer 38 is lower than the top surface of the grooves 21, and the source / drain doping layer 36 is located on the bottom isolation layer 38 in the grooves 21.
[0051] Specifically, both the source / drain doping layer 36 and the bottom isolation layer 38 are formed in the grooves 21. Compared with the grooves only used to accommodate the source / drain doping layer, since the depth of the grooves 21 is equal to the sum of the thickness of the part of the source / drain doping layer 36 located in the grooves 21 and the thickness of the bottom isolation layer 38, the depth of the grooves 21 is greater, and the morphology of the source / drain doping layer 36 and the bottom isolation layer 38 is U-shaped, meeting the requirement of improving the DC performance of the semiconductor device.
[0052] Meanwhile, in order to make the morphology of the groove 21 U-shaped, it is necessary to increase the depth of the groove 21. At this time, if only the source-drain doping layer 36 is filled in the groove 21, it is easy to cause excessive epitaxial growth of the source-drain doping layer 36, resulting in an increase in the defects of the source-drain doping layer 36. In this embodiment, the bottom isolation layer 38 is filled into the groove 21, that is, a part of the depth of the groove 21 is occupied by the bottom isolation layer 38. Therefore, the depth of the groove 21 becomes shallower. Subsequently, the source-drain doping layer 36 is formed on the bottom isolation layer 38 in the groove 21, which can improve the problem of excessive epitaxial growth of the source-drain doping layer, thereby reducing the defects of the source-drain doping layer 36.
[0053] It should be noted that the thickness of the bottom isolation layer 38 should not be too large or too small. The bottom isolation layer 38 is located at the bottom of the source-drain doping layer 36, which means that the bottom isolation layer 38 occupies the effective thickness of the source-drain doping layer 36. If the thickness of the bottom isolation layer 38 is too small, the thickness of the source-drain doping layer 36 will increase, resulting in an increase in the defects of the source-drain doping layer 36, thereby affecting the performance of the semiconductor structure; if the thickness of the bottom isolation layer 38 is too large, the thickness of the source-drain doping layer 36 will decrease, resulting in leakage current even when the conductive channel (not marked) is closed, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, the thickness of the bottom isolation layer 38 is 5 nm to 10 nm.
[0054] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 8 to 17 FIG. is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure according to the present invention. Specifically, Figures 8 to 10 is a cross-sectional view along a direction perpendicular to the extending direction of the fin, Figures 11 to 17 is a cross-sectional view along a direction parallel to the extending direction of the fin.
[0055] With reference to Figures 8 to 10 , a substrate 20 is provided, and fins 29 are formed on the substrate 20.
[0056] The substrate 20 provides a process platform for subsequent process steps.
[0057] Specifically, the substrate 20 is used to form fins.
[0058] In this embodiment, the material of the substrate 20 is silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium arsenide. The substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
[0059] In this embodiment, the semiconductor structure is a fin field-effect transistor, and the discrete fins 29 on the substrate 20 are used to provide the channels of the fin field-effect transistor.
[0060] The material of the fin portion 29 includes one or more of silicon, silicon germanide, germanium, and III-V group semiconductor materials, and the material of the fin portion 29 is determined according to the channel conduction type and performance requirements of the transistor.
[0061] In this embodiment, the material of the fin portion 29 located on the substrate 20 is silicon germanide.
[0062] The step of forming the fin portion 29 on the substrate 20 includes: referring to Figure 8 , providing the substrate 20; referring to Figure 9 , patterning the substrate 20 to form the fin portion 29 on the remaining substrate 20, and the fin portion 29 protrudes from the substrate 20.
[0063] Referring to Figure 10 , in the step of providing the substrate 20, an isolation structure 22 is further formed on the substrate 20 on the side of the fin portion 29, and the top of the isolation structure 22 is lower than the top of the fin portion 29 and covers a part of the side wall of the fin portion 29.
[0064] The isolation structure 22 is used to isolate adjacent devices. The material of the isolation structure 22 can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation structure 22 is silicon oxide.
[0065] Continuing to refer to Figure 10 , after forming the isolation structure 22, the forming method further includes: forming a gate oxide layer 22A covering the fin portion 29.
[0066] In this embodiment, the material of the gate oxide layer 22A is silicon oxide. In other embodiments, the material of the gate oxide layer 22A can also be other gate dielectric materials, such as silicon oxynitride, etc.
[0067] Referring to Figure 11 , forming a gate structure 24 on the substrate 20, the gate structure 24 straddles the fin portion 29, and the gate structure 24 covers a part of the top and a part of the side wall of the fin portion 29.
[0068] The gate structure 24 can be used as a dummy gate structure to occupy a spatial position for forming a device gate structure subsequently. Or, the gate structure 24 can also be a device gate structure, and the gate structure 24 is used to control the opening and pinching off of a conductive channel (not labeled) in the fin portion 29.
[0069] In this embodiment, the material of the gate structure 24 is polysilicon. In other embodiments, the gate structure can also be a metal gate structure.
[0070] In this embodiment, the steps of forming the gate structure 24 include: depositing a gate material layer (not shown in the figure) on the substrate 20; depositing a buffer layer 22B on the gate material layer; depositing a hard mask layer 23 on the buffer layer 22B; patterning the buffer layer 22B; using the patterned buffer layer 22B as a mask to pattern the hard mask layer 23 and the gate material layer in sequence, and patterning the gate material layer into the gate structure 24.
[0071] The patterned hard mask layer 23 is used as a mask for patterning the gate material layer. As an example, the material of the hard mask layer 23 is silicon nitride.
[0072] When patterning the hard mask layer 23, a pattern definition layer (for example, a photoresist layer) is usually required, and the buffer layer 22B is used to improve the adhesion between the hard mask layer 23 and the pattern definition layer. As an example, the material of the buffer layer 22B is silicon oxide.
[0073] Reference Figure 12 , in this embodiment, the method for forming the semiconductor structure further includes: depositing a sidewall material layer 25 on the gate structure 24 and the fin 29.
[0074] The sidewall material layer 25 is used for electrically isolating the source / drain doping layer 26 and the gate structure 24.
[0075] Specifically, the sidewall material layer 25 located on the sidewalls of the gate structure 24 is used as a sidewall structure (not labeled), the sidewall structure is used to protect the sidewalls of the gate structure 24, and the sidewall structure is also used to define the formation position of the source / drain doping layer 26.
[0076] In this example, the material of the sidewall material layer 25 is silicon nitride. In other embodiments, the material of the sidewall material layer 25 can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitroxide, silicon oxynitride, boron nitride, and boron carbonitride, and the sidewall material layer 25 can be a single-layer structure or a stacked-layer structure.
[0077] Reference Figure 13 , grooves 21 are formed in the fins 29 on both sides of the gate structure 24.
[0078] In this embodiment, the grooves 21 are used to fill the source / drain doping layer 26 and the bottom isolation layer 28.
[0079] In this embodiment, the steps of forming the grooves 21 in the fins 29 on both sides of the gate structure 24 include: removing at least the sidewall material layer 25 on the top of the fins 29 on both sides of the gate structure 24 to expose the fins 29; after exposing the fins 29, forming the grooves 21 in the fins 29 on both sides of the gate structure 24.
[0080] In this embodiment, the groove 21 is formed by a step-by-step etching method.
[0081] Specifically, the steps of forming the groove 21 include: longitudinally etching the fins 29 on both sides of the gate structure 24 through an anisotropic etching process to form an initial groove (not shown in the figure) in the fins 29; laterally etching the sidewalls of the initial groove through an isotropic etching process to form the groove 21.
[0082] Forming the initial groove through an anisotropic etching process is conducive to obtaining an initial groove with a relatively large depth and improving the width stability of the initial groove.
[0083] By laterally etching the sidewalls of the initial groove through an isotropic etching process, the sidewalls of the formed groove 21 facing the gate structure 24 are closer to the gate structure 24, thereby shortening the channel length and further reducing the turn-on voltage.
[0084] In this embodiment, in the step of forming the groove 21, before etching the fins 29, the spacer material layer 25 on the fins 29 on both sides of the gate structure 24 is etched through an anisotropic etching process to expose the fins 29, thereby facilitating the etching of the fins 29.
[0085] It should be noted that in the step of etching the spacer material layer 25 on the fins 29 on both sides of the gate structure 24, part of the spacer material layer 25 on the sidewalls of the fins 29 with a certain height can also be removed to expose part of the sidewalls of the fins 29 with a certain height.
[0086] In this embodiment, the depth of the groove 21 is greater than the target thickness of the part of the source-drain doping layer 26 located in the groove 21. Therefore, compared with the groove only used for forming the source-drain doping layer, the depth of the groove 21 becomes larger.
[0087] In this embodiment, the depth of the groove 21 is equal to the sum of the thickness of the bottom isolation layer and the target thickness of the source-drain doping layer located in the fins 29, thereby making the depth of the groove 21 greater. Here, the depth of the groove 21 refers to the vertical distance from the bottom surface of the groove 21 to the top surface of the fins 29.
[0088] In this embodiment, in the step of forming the groove 21, the shape of the groove 21 includes a U shape.
[0089] The groove 21 is used to fill the source-drain doping layer 26 and the bottom isolation layer 28. The shape of the groove 21 includes a U shape, that is, the overall morphology formed by the source-drain doping layer 26 and the bottom isolation layer 28 includes a U shape, which can improve the DC performance of the semiconductor structure.
[0090] Reference Figures 14 to 16, a bottom isolation layer 28 is formed in the groove 21, and the top surface of the bottom isolation layer 28 is lower than the top surface of the groove 21.
[0091] The bottom isolation layer 28 can isolate the source / drain doping layer 26 and the substrate 20, thereby improving the leakage current situation.
[0092] It should be noted that the thickness of the bottom isolation layer 28 should not be too large or too small. The bottom isolation layer 28 is located at the bottom of the source / drain doping layer 26, which means that the bottom isolation layer 28 occupies the effective thickness of the source / drain doping layer 26. If the thickness of the bottom isolation layer 28 is too small, the thickness of the source / drain doping layer 26 will increase, resulting in an increase in defects in the source / drain doping layer 26, thereby affecting the performance of the semiconductor structure; if the thickness of the bottom isolation layer 28 is too large, the thickness of the source / drain doping layer 26 will decrease, resulting in leakage current even when the conductive channel (not labeled) is closed, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the bottom isolation layer 28 is 5 nm to 10 nm.
[0093] In this embodiment, the forming step of the bottom isolation layer 28 includes: as Figure 14 shown, filling the groove 21 with a bottom isolation material 27; as Figure 15 and Figure 16 shown, removing a part of the thickness of the bottom isolation material 27 in the groove 21 to form the bottom isolation layer 28 located at the bottom of the groove 21.
[0094] First forming a bottom isolation material 27 with a larger thickness and then removing a part of the thickness of the bottom isolation material 27 is beneficial to improving the quality and thickness uniformity of the bottom isolation layer 28.
[0095] In this embodiment, there is an etching selectivity between the bottom isolation material 27 and the isolation structure 22.
[0096] Specifically, due to the etching selectivity between the bottom isolation material 27 and the isolation structure 22, the loss of the isolation structure 22 can be reduced during the subsequent etching process.
[0097] It should be noted that the materials of the isolation structure 22 and the gate oxide layer 22A are the same or similar. Correspondingly, there is also an etching selectivity between the bottom isolation material 27 and the gate oxide layer 22A, so that the loss of the gate oxide layer 22A is also reduced during the subsequent etching process.
[0098] In this embodiment, the etching selectivity between the bottom isolation material 27 and the isolation structure 22 is greater than 5:1.
[0099] It should be noted that since the etching selectivity between the bottom isolation material 27 and the isolation structure 22 is greater than 5:1, the loss of the isolation structure 22 can be reduced during the subsequent etching process.
[0100] In this embodiment, in the step of filling the bottom isolation material 27 in the groove 21, the bottom isolation material 27 can be modified into the material of the bottom isolation layer 28.
[0101] The material of the bottom isolation layer 28 is usually a dielectric material. If the bottom isolation material 27 and the material of the bottom isolation layer 28 are the same, it is likely to result in poor effect of improving the etching selectivity between the bottom isolation material 27 and the isolation structure 22. Therefore, by selecting a material that can be modified into the bottom isolation layer 28 to form the bottom isolation material 27, it is convenient to select a bottom isolation material 27 with a high etching selectivity to the isolation structure 22.
[0102] In addition, the bottom isolation material 27 can be transformed into the required bottom isolation layer 28 by modification. On the one hand, this is conducive to simplifying the process steps; on the other hand, it is compatible with the current mainstream process and can better control the leakage current.
[0103] As an example, the material of the bottom isolation material 27 can be modified into silicon oxide.
[0104] Specifically, since the material of the bottom isolation material 27 can be modified into silicon oxide, that is, the bottom isolation layer 28 is an insulating material, it can isolate the source-drain doping layer 26 and the substrate 20, thereby improving the leakage current between the substrate 20 and the source-drain doping layer 26. Moreover, using the modified bottom isolation material 27 to prepare the bottom isolation layer 28 is also beneficial to reducing the cost.
[0105] In this embodiment, the bottom isolation material 27 filled in the groove 21 includes hydrogen silsesquioxane (HSQ).
[0106] On the one hand, the etching selectivity between hydrogen silsesquioxane and the isolation structure 22 is relatively large (for example, it can meet the requirement that the etching selectivity is greater than 5:1). When removing a part of the thickness of the bottom isolation material 27 in the groove 21, the loss of the isolation structure 22 is reduced; on the other hand, this material can be modified into silicon oxide in the subsequent process, which can reduce the leakage current and thus improve the performance of the semiconductor structure.
[0107] In this embodiment, the process of filling the bottom isolation material 27 includes a spin coating process.
[0108] The spin coating process can uniformly coat liquid or thin film materials on a substrate, ensuring a consistent coating thickness. It can coat a large-area substrate in a relatively short time, improving productivity, and the thickness of the resulting coating can be controlled by adjusting the spin coating process parameters. Therefore, a bottom isolation material layer with a uniform thickness can be obtained.
[0109] In this embodiment, in the step of filling the bottom isolation material 27, the top surface of the bottom isolation material 27 is higher than the top surface of the gate structure 24.
[0110] Specifically, the top surface of the bottom isolation material 27 is higher than the top surface of the gate structure 24. The bottom isolation material 27 can protect the gate oxide layer 22A on the sidewall of the gate structure 24. When removing a part of the thickness of the bottom isolation material 27 in the groove 21, the exposure time of the gate oxide layer 22A to the etching environment is reduced, thereby reducing the loss of the gate oxide layer 22A.
[0111] It should be noted that the thickness of the filled bottom isolation material 27 should not be too large or too small. Subsequently, a part of the thickness of the bottom isolation material 27 needs to be etched away. If the thickness of the filled bottom isolation material 27 is too large, during the process of etching away a part of the thickness of the bottom isolation material 27, uneven etching or over-etching may occur, resulting in uneven thickness of the remaining bottom isolation material 27, and further affecting the performance of the semiconductor structure. If the thickness of the filled bottom isolation material 27 is too small, during the process of etching away a part of the thickness of the bottom isolation material 27, the gate oxide layer 22A on the sidewall of the gate structure 24 may be etched away, resulting in an increase in the loss of the gate oxide layer 22A on the sidewall of the gate structure 24, and further affecting the performance of the semiconductor structure. For this reason, in this embodiment, the thickness of the filled bottom isolation material 27 is 200 nm to 300 nm.
[0112] In this embodiment, the process of removing a part of the thickness of the bottom isolation material 27 in the groove 21 includes a dry etching process.
[0113] The dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has anisotropic characteristics, so its longitudinal etching rate is much greater than the lateral etching rate, which is beneficial to precisely removing a part of the thickness of the bottom isolation material 27 in the groove 21, thereby improving the morphological quality and dimensional accuracy of the remaining thickness of the bottom isolation material 27.
[0114] Correspondingly, as Figure 16As shown, the step of forming the bottom isolation layer 28 further includes: after removing a part of the thickness of the bottom isolation material 27 in the groove 21, performing a modification process on the remaining thickness of the bottom isolation material 27 to convert the remaining thickness of the bottom isolation material 27 into the bottom isolation layer 28.
[0115] In this embodiment, the process of the modification process includes ultraviolet light irradiation or electron beam exposure.
[0116] The ultraviolet light irradiating the bottom isolation material 27 can quickly initiate a chemical reaction of the bottom isolation material 27, causing the bottom isolation material 27 to be quickly modified, thereby improving the production efficiency of the semiconductor structure.
[0117] The electron beam exposure is fast, which can quickly modify the bottom isolation material 27 and improve the production efficiency of the semiconductor structure. At the same time, the electron beam exposure is a non-contact process, so it will not cause physical damage or wear to the surface of the bottom isolation material 27, thereby improving the morphological quality of the bottom isolation material 27.
[0118] Reference Figure 17 , form the source / drain doping layer 26 on the bottom isolation layer 28 in the groove 21.
[0119] In this embodiment, the source / drain doping layer 26 is used to provide a carrier source for the channel when the device is operating.
[0120] Specifically, the source / drain doping layer 26 includes a stress layer doped with ions, so as to be able to provide stress for the channel, which is beneficial to improving the carrier mobility in the channel region.
[0121] When forming a PMOS transistor, the material of the stress layer is Si or SiGe, and the doping ions in the stress layer are P-type ions; when forming an NMOS transistor, the material of the stress layer is Si or SiC, and the doping ions in the stress layer are N-type ions.
[0122] In this embodiment, the source / drain doping layer 26 is located on the bottom isolation layer 28 in the groove 21, and the bottom isolation layer 28 can isolate the bottom of the source / drain doping layer 26 from the substrate 20, thereby improving the leakage problem between the substrate 20 and the fin 29 and improving the performance of the semiconductor structure.
[0123] In this embodiment, the process of forming the source / drain doping layer 26 includes an epitaxial process.
[0124] The epitaxial process has the characteristics of low cost and simple process, can grow in a specific area, has the characteristic of area selectivity, and moreover, the epitaxial growth process is easy to form a film layer with fewer impurities, making the quality of the source / drain doping layer 26 higher.
[0125] It should be noted that the semiconductor structure provided by the embodiments of the present invention can be formed by the formation method described in the foregoing embodiments, or can be formed by other formation methods. For the specific description of the semiconductor structure described in the embodiments of the present invention, reference can be made to the corresponding description in the foregoing embodiments.
[0126] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that, Comprising: A substrate; Fin portions protruding from the substrate; A gate structure spanning the fin portions, and the gate structure covering a part of the top and part of the sidewalls of the fin portions; Source / drain doping layers located in the fin portions on both sides of the gate structure; A bottom isolation layer located at the bottom of the source / drain doping layers and in contact with the bottoms of the source / drain doping layers.
2. The semiconductor structure according to claim 1, wherein The material of the bottom isolation layer includes silicon oxide or silicon carbide.
3. The semiconductor structure according to claim 1, wherein, The thickness of the bottom isolation layer is 5 nm to 10 nm.
4. The semiconductor structure according to claim 1, wherein The distance from the bottom surface of the bottom isolation layer to the top surface of the fin portion is equal to the sum of the thickness of the bottom isolation layer and the target thickness of the source / drain doping layer in the fin portion.
5. The semiconductor structure according to claim 1 or 4, characterized in that, The overall morphology formed by the source / drain doping layers and the bottom isolation layer includes a U shape.
6. A method for forming a semiconductor structure, characterized in that, Including; Providing a substrate with fin portions formed thereon; Forming a gate structure on the substrate, the gate structure spanning the fin portions, and the gate structure covering a part of the top and part of the sidewalls of the fin portions; Forming grooves in the fin portions on both sides of the gate structure; Forming a bottom isolation layer in the grooves, and the top surface of the bottom isolation layer being lower than the top surface of the grooves; Forming source / drain doping layers on the bottom isolation layer in the grooves.
7. The method for forming a semiconductor structure according to claim 6, wherein The step of forming the bottom isolation layer includes: filling a bottom isolation material in the grooves; removing a part of the thickness of the bottom isolation material in the grooves to form a bottom isolation layer at the bottom of the grooves.
8. The method for forming a semiconductor structure according to claim 7, wherein, In the step of providing the substrate, an isolation structure is further formed on the substrate on the side of the fin portions, the top of the isolation structure being lower than the top of the fin portions and covering a part of the sidewalls of the fin portions; There is an etching selectivity between the bottom isolation material and the isolation structure.
9. The method for forming a semiconductor structure according to claim 8, wherein, The etching selectivity between the bottom isolation material and the isolation structure is greater than 5:
1.
10. The method for forming a semiconductor structure according to any one of claims 7 to 9, characterized in that, In the step of filling the bottom isolation material in the grooves, the bottom isolation material can be modified into the material of the bottom isolation layer; The step of forming the bottom isolation layer further includes: after removing a part of the thickness of the bottom isolation material in the grooves, performing a modification treatment on the remaining thickness of the bottom isolation material to convert the remaining thickness of the bottom isolation material into a bottom isolation layer.
11. The method for forming a semiconductor structure according to claim 10, wherein, The bottom isolation material includes hydrogen silsesquioxane.
12. The method for forming a semiconductor structure according to claim 11, wherein, The process of filling the bottom isolation material includes a spin coating process.
13. The method for forming a semiconductor structure according to claim 11, wherein The process of the modification treatment includes ultraviolet light irradiation or electron beam exposure.
14. The method for forming a semiconductor structure according to claim 7, wherein In the step of filling the bottom isolation material, the top surface of the bottom isolation material is higher than the top surface of the gate structure.
15. The method for forming a semiconductor structure according to claim 7, wherein, In the step of filling the bottom isolation material, the thickness of the bottom isolation material is 200 nm to 300 nm.
16. The method for forming a semiconductor structure according to claim 7, wherein, The process of removing a part of the thickness of the bottom isolation material in the grooves includes a dry etching process.
17. The method for forming a semiconductor structure according to claim 6, wherein, In the step of forming the bottom isolation layer in the grooves, the thickness of the bottom isolation layer is 5 nm to 10 nm.
18. The method for forming a semiconductor structure according to claim 6, wherein, The step of forming the grooves includes: longitudinally etching the fin portions on both sides of the gate structure through an anisotropic etching process to form initial grooves in the fin portions; laterally etching the sidewalls of the initial grooves through an isotropic etching process to form grooves.
19. The method for forming a semiconductor structure according to claim 6, wherein, The depth of the groove is equal to the sum of the thickness of the bottom isolation layer and the target thickness of the source / drain doping layer located in the fin.
20. The method for forming a semiconductor structure according to claim 6 or 19, characterized in that, In the step of forming the groove, the shape of the groove includes a U shape.