Semiconductor power device with termination ring

Abstract

Aspects of the present disclosure relate to a semiconductor power device, in particular to a silicon carbide (SiC) merged P-I-N Schottky (MPS) diode. The semiconductor power device includes a semiconductor body including a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate, in which an active region and a termination region adjacent to the active region are arranged in the epitaxial layer. The termination region includes a plurality of first rings of a first polarity, and a plurality of second rings of a second polarity different from the first polarity. The semiconductor substrate and the epitaxial layer have a second polarity, and wherein a dopant concentration in the epitaxial layer associated with the second polarity is less than a dopant concentration in the second ring associated with the second polarity. The termination region includes a first portion directly adjacent to the active region, and a second portion spaced apart from the active region by the first portion, and wherein the plurality of first rings and the plurality of second rings are arranged in the second portion.

Description

Technical Field

[0001] Aspects of the present disclosure generally relate to a semiconductor power device, and more particularly to a silicon carbide (SiC) merged P-I-N Schottky (MPS) diode. Background Art

[0002] General high-voltage power semiconductor devices and especially silicon carbide (SiC) products use many structures around the active region. These structures are collectively referred to as the termination region. For these devices, it is extremely important to design a robust termination region that can withstand high voltages in the kV range. The main function of the termination region is to spread the potential lines in a way that avoids crowding in specific areas of the termination region. Thus, the termination region helps to reduce the electric field at the edge of the active region, and when well-designed, the termination region spreads the electric field evenly over all elements of the termination region, avoiding any extreme field crowding at weak points.

[0003] Weak points or weak regions can be caused by design issues, such as unoptimized dimensions, process variations, such as lithography misalignment, ion implantation, and diffusion, such as dose, energy, and activation temperature, and interface charges caused by the presence of passivants in the termination region. When using nitride-based passivants, these charges are "positive", meaning that ionized acceptors will accumulate in the semiconductor body in the termination region to compensate for the holes trapped at the interface. The effect of passivation charges can be crucial. This results in an undesired depletion region at 0V, which reduces the effectiveness of the termination region, leading to low or unstable reverse blocking capability, poor non-clamped inductive switching durability, high-temperature and high-voltage reliability failures, and limits the application fields of such products.

[0004] In known termination regions, the effect of passivation charges is always visible. An example of a termination region uses the concept of p-doped rings implemented in an n-doped semiconductor substrate. As the distance from the active region increases, e.g., towards the end or saw track of the semiconductor device, the width and distance of these p-doped rings increase. These rings are also referred to as floating guard rings or Kao rings. These rings can be coupled to a large lightly doped p-type region called the junction termination extension boundary. Summary of the Invention

[0005] The following presents an overview of aspects of certain embodiments disclosed herein. It should be understood that presenting these aspects is merely to provide a brief overview of these certain embodiments to the reader, and these aspects are not intended to limit the scope of the present disclosure. Indeed, the present disclosure may cover various aspects and / or combinations of aspects that may not be set forth.

[0006] According to one aspect of the present disclosure, a semiconductor power device is provided, which includes a semiconductor body including a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate. An active region and a terminal region adjacent to the active region are disposed in the epitaxial layer. The terminal region includes a plurality of first rings of a first polarity and a plurality of second rings of a second polarity different from the first polarity. The first rings may be referred to as the floating protection rings described above. The semiconductor substrate and the epitaxial layer have the second polarity. The dopant concentration in the epitaxial layer associated with the second polarity is less than the dopant concentration in the second rings associated with the second polarity. In addition, the terminal region includes a first part directly adjacent to the active region and a second part spaced apart from the active region by the first part, and wherein the plurality of first rings and the plurality of second rings are disposed in the second part.

[0007] The applicant has found that by including the second rings having the second polarity, the above-described effect of the surface charge on the performance degradation of the semiconductor power device can be observed. In addition, by including the second rings, a controlled depletion region between the first rings can be obtained, which makes the semiconductor power device less sensitive to process variations such as variations in lithography or ion implantation.

[0008] In addition, the applicant has found that by disposing the plurality of first rings and the plurality of second rings in a region spaced apart from the active region (i.e., in the second part spaced apart from the active region by the first part), the manufacturing process for the terminal region can be more easily separated from the manufacturing process for the active region without affecting the performance of the semiconductor power device or having a limited impact on the performance of the semiconductor power device. For example, the plurality of first rings and the plurality of second rings can be formed relatively independently of various components and regions corresponding to the active region and are less dependent on alignment with the active region.

[0009] The first part may be directly adjacent to the nearest first ring among the plurality of first rings closest to the active region. In another embodiment, the nearest second ring among the plurality of second rings closest to the active region may be spaced apart from the first part by the nearest first ring.

[0010] The width of the first part may be equal to or greater than the width of each of the first rings among the plurality of first rings and / or the width of each of the second rings among the plurality of second rings.

[0011] Multiple first rings may extend further towards the semiconductor substrate than multiple second rings. For example, the first and second rings may extend from the upper surface of the semiconductor body towards the semiconductor substrate. The depth to which the first ring extends into the semiconductor body typically ranges between 200 and 300 nanometers, and the depth to which the second ring extends into the semiconductor body typically ranges between 50 and 150 nanometers. In an embodiment, the first ring extends into the semiconductor body more than the second ring. For example, the first ring extends more than the second ring by more than 100 nanometers, preferably more than 150 nanometers, and more preferably more than 200 nanometers. Alternatively, the first ring may extend more than the second ring by more than 100%, preferably more than 150%, and more preferably more than 200%.

[0012] The dopant concentration in the second ring associated with the second polarity may be greater than the dopant concentration in the epitaxial layer associated with the second polarity, at least 100 times, preferably at least 1000 times, and more preferably at least 10000 times the dopant concentration in the epitaxial layer associated with the second polarity. As an example, the dopant concentration in the second ring associated with the second polarity may range between 1E19 and 1E20 # / cm3.

[0013] The first and second rings may be arranged alternately. Additionally or alternatively, the first and second rings may be configured to be electrically floating during operation.

[0014] The dopant concentration in the first portion may be substantially the same as the dopant concentration of the epitaxial layer associated with the second polarity. In other words, the first portion may be substantially occupied by the epitaxial layer and not occupied by any of the intentionally doped regions discussed above.

[0015] The terminal region may further include a junction termination extension (JTE) boundary of the first polarity type, where the first and second rings are arranged within the JTE boundary. The dopant concentration of the JTE boundary associated with the first polarity may be less than the dopant concentration of the first ring associated with the first polarity, 1 / 20, preferably 1 / 50, and more preferably 1 / 100 of the dopant concentration of the first ring associated with the first polarity. For example, the dopant concentration of the first ring associated with the first polarity may range between 1E19 and 1E20 # / cm3, and the dopant concentration of the JTE boundary associated with the first polarity may range between 1E17 and 1E20 # / cm3. In a preferred embodiment, the JTE boundary may extend from the active region in the first portion into a part of the second portion.

[0016] The terminal region may also include a plurality of floating JTE rings of a first polarity, which are arranged to be spaced apart from the first and second rings and, where applicable, from the above-mentioned JTE boundary. The dopant concentration of the floating JTE rings associated with the first polarity may be in the range between 1E17 and 1E18 # / cm3.

[0017] The terminal region may be at least partially covered by a passivation layer. The passivation layer may include a passivation layer made of silicon nitride, silicon oxynitride, silicon oxide, or metal oxide. Additionally or alternatively, the passivation layer may include, for example, a field oxide layer made of silicon oxide. When the passivation layer includes a field oxide layer, the field oxide layer may substantially completely cover the terminal region and optionally also cover a part of the active region. The field oxide layer may be covered by other passivation layers, such as one or more of the above-mentioned layers. When the passivation layer does not include a field oxide layer, the passivation layer may only partially cover the terminal region.

[0018] The semiconductor power device may also include a channel stop ring arranged at or near the edge of the semiconductor power device, where the terminal region is arranged between the channel stop ring and the active region, and where the channel stop ring has a second polarity. The dopant concentration of the channel stop ring associated with the second polarity may be in the range between 1E18 and 1E20 # / cm3.

[0019] The above-mentioned passivation layer may extend over the terminal region from the region directly above the channel stop ring towards the active region, so as to cover at least a part of the plurality of first rings and the plurality of second rings. For example, it may cover at least 90%, preferably at least 95%, more preferably at least 98% of the first and second rings.

[0020] The above-mentioned field oxide layer may extend over the terminal region from the region directly above the channel stop ring towards the active region, so as to completely cover the plurality of first rings and the plurality of second rings.

[0021] The semiconductor power device may include a merged P-I-N Schottky MPS diode. Other semiconductor power devices include, but are not limited to, metal oxide semiconductor field effect transistors "MOSFETs", junction FETs "JFETs", Schottky barriers, and PN diodes.

[0022] Regarding an MPS diode, an active region includes a conductive layer assembly that includes one or more conductive layers, such as metal layers, and a plurality of mutually separated islands of a first polarity that are disposed in a current distribution layer of a second polarity. The conductive layer assembly forms a Schottky contact with the current distribution layer and forms an ohmic contact with the plurality of islands of the first polarity. In some embodiments, the ohmic contact is formed by a metal or conductive layer different from the Schottky contact. The combination of these different metals or conductive layers is referred to as the conductive layer assembly. Additionally, the conductive layer assembly may include a relatively thick metal layer for providing a low ohmic resistance, especially when handling high currents.

[0023] Furthermore, the conductive layer assembly may form a first contact of the MPS diode, and the MPS diode may include a second contact disposed on a semiconductor substrate.

[0024] The current distribution layer may be formed by a well of the second polarity formed in an epitaxial layer, wherein the dopant concentration of the current distribution layer associated with the second polarity is greater than the dopant concentration of the epitaxial layer associated with the second polarity, being at least 2 times, preferably at least 3 times, more preferably at least 5 times the dopant concentration of the epitaxial layer associated with the second polarity.

[0025] The semiconductor substrate may include a silicon carbide substrate. However, the present disclosure equally relates to silicon substrates, II-VI semiconductor material substrates, or III-V semiconductor material substrates, such as GaN or AlGaN substrates.

[0026] The first polarity may correspond to p-type, and the second polarity may correspond to n-type. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Next, the present disclosure will be described in more detail with reference to the accompanying drawings, in which:

[0028] Figure 1 is an overall top view of a semiconductor power device;

[0029] Figure 2 is a cross-sectional view of a semiconductor power device according to an embodiment of the present disclosure; and

[0030] Figure 3 is Figure 2 an enlarged view of a part of the cross-section of; and

[0031] Figure 4 is a cross-sectional view of a semiconductor power device according to another aspect of the present disclosure.

[0032] The present disclosure is described in conjunction with the accompanying drawings. It should be emphasized that, according to standard practices in the industry, the various features are not drawn to scale. In fact, for the sake of clear discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0033] In the drawings, like parts and / or features may have the same reference numerals. Additionally, each of the same type of parts may be distinguished by following the reference numeral with a dash and a second numeral that differentiates between similar parts. If only the first reference numeral is used in the specification, the description may apply to any one of the similar parts having the same first reference numeral regardless of the second reference numeral. Detailed Description

[0034] Unless the context clearly dictates otherwise, throughout the specification and claims, the words "comprising," "including," and the like shall be construed in an inclusive sense, rather than an exclusive or exhaustive sense; that is, in the sense of "including, but not limited to." As used herein, the term "connected," "coupled," or any variant thereof refers to any direct or indirect connection or coupling between two or more elements; the coupling or connection between elements may be physical, logical, electromagnetic, or a combination thereof. Additionally, when used in this application, the words "herein," "above," "below," and words of similar import shall refer to the entire application, and not to any particular part of the application. Where context permits, the singular or plural words used in the "Detailed Description" section may also each include the plural or singular, respectively. When referring to a list of two or more items, the word "or" covers all of the following interpretations of the word: any item in the list, all items in the list, and any combination of the items in the list.

[0035] The teachings of the technology provided herein may be applied to other systems and not necessarily to the systems described below. The elements and acts of the various examples described below may be combined to provide further embodiments of the technology. Some alternative embodiments of the technology may include not only additional elements of these embodiments noted above, but also fewer elements.

[0036] These and other changes to the technology are made in accordance with the following detailed description. Although the description is of certain embodiments of the technology and describes the best mode contemplated, no matter how detailed the description may appear, the technology may be practiced in many ways. Details of the system may vary significantly in its implementation while still being covered by the technology disclosed herein. As noted above, the specific terms used in describing certain features or aspects of the technology should not be taken to imply that the term is redefined herein to be limited to any specific property, feature, or aspect of the technology associated with that term. In general, the terms used in the following claims should not be construed to limit the technology to the specific examples disclosed in the specification unless the detailed description section clearly defines these terms. Thus, the actual scope of the technology not only covers the disclosed examples but also includes all equivalent ways of practicing or implementing the technology under the claims.

[0037] To reduce the number of claims, certain aspects of the technology are presented below in the form of certain claims, but the applicant contemplates the various aspects of the technology in any number of claim forms.

[0038] In Figure 1 a general top view of a semiconductor power device 100 is shown, which includes an active region 101 where semiconductor devices are implemented, a terminal region 102 adjacent to the active region 101, and a channel stop ring 103. Typically, the semiconductor power device 100 is made from a semiconductor wafer on which multiple devices 100 are formed simultaneously. Before separating the devices, the channel stop ring 103 may include a structure that allows device separation, such as a saw street. Another structure that is present or may be present in or on top of the channel stop ring 103 is part of a passivation layer.

[0039] In Figure 2 a cross-sectional view corresponding to the dashed line a-a' indicated in Figure 1 is provided. It should be noted here that these figures present exemplary embodiments of semiconductor power devices in the form of SiC MPS diodes. However, the present disclosure is not limited thereto, and aspects of the present disclosure can be equivalently applied to other semiconductor power devices implemented on different semiconductor material technologies such as Si, GaN, AlGaN, and other II-VI or III-V semiconductor materials, such as metal oxide semiconductor field effect transistors (MOSFETs), junction FETs (JFETs), Schottky barriers, or PN diodes.

[0040] Now refer to Figure 2, the 100A MPS diode includes a semiconductor body 130, which includes an n-type SiC substrate 110 on which an n-type SiC epitaxial layer 111 has been grown. The typical dopant concentrations in these layers are 1E19 # / cm3 and 1E16 # / cm3 respectively. Inside the epitaxial layer 111, an n-type current diffuser 112 with a typical dopant concentration of 5E16 # / cm3 has been formed using ion implantation. Furthermore, inside the current diffuser 112, multiple p-type wells 113 have been formed using ion implantation. Inside the wells 113, highly doped p-type contact regions 114 have been formed using ion implantation to allow for a low ohmic contact resistance with the NiSi conductive layer 115. The typical dopant concentrations of the wells 113 and the contact regions 114 are 1E18 # / cm3 and 1E20 # / cm3 respectively.

[0041] The 100A MPS diode also includes a Ti / TiN layer 116 that covers the top surfaces of the current diffuser 112 and the NiSi layer 115. In the region where the layer 116 contacts the current diffuser 112, i.e., between the wells 113, a Schottky contact is formed, while the NiSi layer 115 forms an ohmic contact with the contact region 114. The Ti / TiN layer 116 is covered by a relatively thick AlCu layer 117 that forms the first contact terminal of the 100A MPS diode. The NiSi layer 115, the Ti / TIN layer 116, and the AlCu layer 117 can be collectively referred to as the conductive layer assembly or the conductive layer stack. In addition, the second contact terminal of the 100A MPS diode is formed at the back surface of the SiC substrate 110.

[0042] The terminal region 102 includes multiple p-type first rings 120 with a typical dopant concentration of 1E20 # / cm3. Between the p-type first rings 120, multiple n-type second rings 121 with a typical dopant concentration of 5E19 # / cm3 are arranged. As shown, the first rings 120 extend further towards the SiC substrate 110 than the rings 121. For example, the depth of the first rings 120 is equal to 0.3 microns, while the height of the second rings 121 is equal to 0.15 microns.

[0043] The first rings 120 and the second rings 121 can be arranged using ion implantation separate from the ion implantation steps for the regions 112 - 114. More specifically, in the manufacturing process, separate implantation steps can be performed for the regions in the terminal region 102 compared to the regions in the active region 101.

[0044] Both the first rings 120 and the second rings 121 are disposed within a p-type JTE boundary 122 that has a typical dopant concentration of 5E17 # / cm3. Multiple p-type JTE rings 124 with a typical dopant concentration of 5E17 # / cm3 are arranged adjacent to the JTE boundary 122.

[0045] Although Figure 2 the illustrated embodiment includes four first rings 120 and three second rings 121, the present disclosure is not limited thereto, and more or fewer first rings 120, second rings 121, and / or JTE rings 124 than those shown in Figure 2 are equally contemplated.

[0046] A passivation layer 123 made of silicon nitride, silicon oxynitride, silicon oxide, metal oxide, or a suitable combination thereof is provided between the channel cutoff ring 103 and the active region 101. As shown, the passivation layer 123 does not extend over the entire surface between the channel cutoff ring 103 and the active region 101.

[0047] The rings 120, 121, 124 are generally electrically floating during operation.

[0048] Figure 2 Several structures within the terminal region 102 are presented. More specifically, in the embodiment shown in Figure 2 , the MPS diode 100A includes a first ring 120, a second ring 121, a JTE boundary 122, and a JTE ring 124. Among these structures, the JTE boundary 122 and the JTE ring 124 are optional. Thus, several different embodiments are possible according to aspects of the present disclosure outlined in the following list:

[0049] Embodiment 1: Ring 120, Ring 121, JTE boundary 122, JTE ring 124 (as shown in Figure 2 )

[0050] Embodiment 2: Ring 120, Ring 121

[0051] Embodiment 3: Ring 120, Ring 121, JTE boundary 122

[0052] Embodiment 4: Ring 120, Ring 121, JTE ring 124

[0053] The above list indicates which structures are possible in various different embodiments.

[0054] Figure 3 An enlarged view of a portion of the cross-section shown in Figure 2 is illustrated. Specifically, as shown in Figure 3 , the terminal region 102 includes a first portion 102a directly adjacent to the active region 101, and a second portion 102b spaced apart from the active region 101 by the first portion 102a. The first ring 120 and the second ring 121 are arranged in the second portion and are thus both spaced apart from the active region 101.

[0055] The first part 102a may have a width w1 taken in an outward direction with respect to the active region 101. The width w1 may be equal to or greater than the width of the first ring 120 and / or the second ring 121 taken in the same direction. For example, the width w1 may be about 0.5 micrometers, the width of each first ring 120 may be about 0.5 micrometers or greater, and the width of each second ring 121 may be about 0.5 micrometers. Specifically, the width and the mutual distance of the first ring 120 and / or the second ring 121 may increase as the distance from the active region increases, for example, towards the end of the semiconductor device 100 or the saw street of the wafer.

[0056] As Figure 3 shown, the nearest first ring 120-1 among the plurality of first rings 120 is arranged closer to the active region 101 than the nearest second ring 121-1 among the plurality of second rings 121. Thus, the nearest first ring 120-1 is spaced apart from the active region 101 by the first part 102a of the terminal region 102, while the nearest second ring 121-1 is spaced apart from the active region 101 by the first part 102a and the nearest first ring 120-1.

[0057] In embodiments including the JTE boundary 122 (i.e., the above-described Embodiments 1 and 3), the first ring 120 and the second ring 121 may be spaced apart from the active region 101 by the JTE boundary 122. On the other hand, if the JTE boundary 122 is omitted (i.e., the above-described Embodiments 2 and 4), the epitaxial layer 111 may extend in the first part 102a between the active region 101 and the second part 102b. In other words, the region between the nearest first ring 120-1 and the active region 101 (specifically, the well 113) is then occupied by the epitaxial layer 111.

[0058] Although Figure 3 not explicitly shown in the figure, the second part 102b may extend upward from the first part 102a until Figure 2 the channel cutoff ring 103. Thus, the first ring 120, the second ring 121, and, if applicable, the JTE ring 124 may all be provided in the second part 102b. Further, if applicable, the JTE boundary 122 may extend through the first part 102a and into a part of the second part 102b.

[0059] Figure 4 Another MPS diode 100B is illustrated, which is related to Figure 2 and Figure 3The MPS diode of 100 A is different in that a field oxide layer 125 made of silicon oxide is used as a passivation layer, as an alternative to the passivation layer 123, for directly contacting the top surface of the semiconductor body 130. Contrary to the passivation layer 123, the field oxide layer 125 spans the entire surface between the channel stop ring 103 and the active region 101. In addition, the Ti / TiN layer 116 partially covers the field oxide layer 125. In addition, the passivation layer 123 is disposed above the Ti / TiN layer 116 and a part of the field oxide layer 125.

[0060] has been referred to Figure 2 the remaining elements described in the embodiments shown in Figure 4 the embodiments shown in can be applied in the same or similar manner, and thus their detailed descriptions are omitted.

[0061] In Figures 2 to 4 the embodiment of, a separate conductive layer, namely the NiSi layer 115, is used to achieve an ohmic contact. In other embodiments, for example, the same conductive layer including one or more metal layers can be used to simultaneously form an ohmic contact to the p-type well 113 and a Schottky contact to the current diffuser 112.

[0062] The above description provides only preferred exemplary embodiments and is not intended to limit the scope, applicability, or configuration of the present disclosure. On the contrary, the subsequent description of the preferred exemplary embodiments will provide a description of the preferred exemplary embodiments of implementing the present disclosure to those skilled in the art. Various changes can be made to the functions and arrangements of the elements, including combinations of features from different embodiments, without departing from the scope of the present disclosure defined by the appended claims and their equivalents in at least some jurisdictions.

Claims

1. A semiconductor power device, comprising: a semiconductor body comprising a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate, wherein an active region and a termination region adjacent to the active region are arranged in the epitaxial layer, wherein the terminal region comprises a plurality of first rings of a first polarity and a plurality of second rings of a second polarity different from the first polarity, wherein the semiconductor substrate and the epitaxial layer have the second polarity, and wherein a dopant concentration in the epitaxial layer associated with the second polarity is less than a dopant concentration in the second ring associated with the second polarity, The termination region includes a first portion directly adjacent to the active region and a second portion spaced apart from the active region by the first portion, and wherein the plurality of first rings and the plurality of second rings are arranged in the second portion. 2 . The semiconductor power device of claim 1 , wherein the first portion is directly adjacent to a nearest first ring among the plurality of first rings that is closest to the active region. 3 . The semiconductor power device of claim 2 , wherein a nearest second ring among the plurality of second rings that is closest to the active region is spaced apart from the first portion by the nearest first ring. 4 . The semiconductor power device according to claim 1 , wherein a width of the first portion is equal to or greater than a width of each first ring of the plurality of first rings and / or a width of each second ring of the plurality of second rings.

5. The semiconductor power device according to any one of the preceding claims, wherein the plurality of first rings extend further toward the semiconductor substrate than the plurality of second rings, wherein the first ring preferably extends beyond the second ring by more than 100 nanometers, more preferably more than 150 nanometers, and even more preferably more than 200 nanometers, and / or wherein the first ring preferably extends beyond the second ring by more than 100%, more preferably more than 150%, and even more preferably more than 200%.

6. A semiconductor power device according to any of the preceding claims, wherein the dopant concentration in the second ring associated with the second polarity is greater than the dopant concentration in the epitaxial layer associated with the second polarity, and is at least 100 times, preferably at least 1000 times, and more preferably at least 10000 times the dopant concentration in the epitaxial layer associated with the second polarity. 7 . The semiconductor power device according to claim 1 , wherein the first rings and the second rings are arranged alternately.

8. The semiconductor power device of any one of the preceding claims, wherein the first ring and the second ring are configured to electrically float during operation.

9. A semiconductor power device according to any one of the preceding claims, wherein the dopant concentration in the first portion and the dopant concentration of the epitaxial layer associated with the second polarity are substantially the same.

10. The semiconductor power device according to any one of claims 1 to 8, wherein the termination region further comprises a junction termination extension (JTE) boundary of the first polarity type, wherein the first ring and the second ring are arranged within the junction termination extension boundary, in, Preferably, the dopant concentration of the JTE boundary associated with the first polarity is less than the dopant concentration of the first ring associated with the first polarity, which is 1 / 20, more preferably 1 / 50, even more preferably 1 / 100 of the dopant concentration of the first ring associated with the first polarity. More preferably, the JTE boundary extends from the active area in the first portion into a portion of the second portion.

11. The semiconductor power device of any of the preceding claims, wherein the termination region further comprises a plurality of floating JTE rings of the first polarity arranged to be spaced apart from the first ring and the second ring and, in the case of claim 10, spaced apart from the JTE boundary.

12. A semiconductor power device according to any one of the preceding claims, wherein the termination region is at least partially covered by a passivation layer; The passivation layer preferably comprises a passivation layer made of silicon nitride, silicon oxynitride, silicon oxide or metal oxide; and / or The passivation layer preferably comprises a field oxide layer, preferably made of silicon oxide, wherein the semiconductor power device preferably further comprises a channel stop ring arranged at or near an edge of the semiconductor power device, wherein the termination region is arranged between the channel stop ring and the active region, and wherein the channel stop ring has the second polarity, in, More preferably: When the passivation layer comprises a passivation layer made of silicon nitride, silicon oxynitride, silicon oxide or metal oxide, the passivation layer extends from a region directly above the channel stop ring toward the active region over the termination region, thereby covering a portion of the plurality of first rings and the plurality of second rings; or When the passivation layer includes the field oxide layer, it extends from the area directly above the channel stopper ring toward the active area over the termination region, thereby completely covering the plurality of first rings and the plurality of second rings.

13. A semiconductor power device according to any one of the preceding claims, wherein the semiconductor power device comprises a Merged PIN Schottky (MPS) diode, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a Junction FET (JFET), a Schottky barrier or a PN diode.

14. The semiconductor power device of claim 13, wherein the semiconductor power device comprises a MPS diode, and wherein the active region comprises: a conductive layer assembly comprising one or more conductive layers, such as a metal layer; as well as a plurality of mutually separated islands of the first polarity arranged in a current distribution layer of the second polarity, wherein the conductive layer component forms a Schottky contact with the current distribution layer and forms an ohmic contact with the plurality of islands of the first polarity, wherein the conductive layer assembly forms a first contact of the MPS diode, and wherein the MPS diode comprises a second contact arranged on the semiconductor substrate, Wherein, preferably, the current distribution layer is formed by a well of the second polarity formed in the epitaxial layer, and wherein the dopant concentration of the current distribution layer associated with the second polarity is greater than the dopant concentration of the epitaxial layer associated with the second polarity, and is at least 2 times, more preferably at least 3 times, and even more preferably at least 5 times the dopant concentration of the epitaxial layer associated with the second polarity.

15. The semiconductor power device according to any one of the preceding claims, wherein the semiconductor substrate comprises a silicon carbide substrate; and / or The first polarity corresponds to the p-type, and the second polarity corresponds to the n-type.

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