Semiconductor structure, manufacturing method thereof and electronic equipment
By adopting the ring channel structure of the write transistor and the planar structure of the read transistor in the semiconductor structure and adopting a specific manufacturing method, the challenge of efficiently manufacturing device units on a limited substrate is solved, achieving high integration, low cost and low manufacturing difficulty.
Patent Information
- Application Number
- CN202311754841.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-19
- Publication Date
- 2025-06-24
AI Technical Summary
In semiconductor technology, as device size shrinks, small differences in process production have an increasing impact on device performance, and there are challenges in design and process optimization when manufacturing as many device units as possible on a limited substrate to reduce costs.
A semiconductor structure is designed in which the write transistor adopts a ring channel structure and the read transistor adopts a planar structure, and through a specific manufacturing method, including forming a stacked structure, etching a conductive layer, deposition and removal of materials to form a circuit structure of the write transistor and the read transistor.
It realizes high integration, low process cost and low manufacturing difficulty of semiconductor structures, while maintaining the performance advantages of read transistors and reducing manufacturing difficulty.
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Figure CN120201776A_ABST
Abstract
Description
Technical Field
[0001] This application relates to, but is not limited to, semiconductor technology, and particularly to a semiconductor structure, a manufacturing method thereof, and an electronic device. Background Art
[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking day by day, and the types and quantities of devices included in a single chip are increasing accordingly. As a result, any minor difference in the process production may affect the device performance.
[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's Law came into being, the industry has proposed various semiconductor structure designs and process optimizations to meet the needs of current products. Summary of the Invention
[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.
[0005] In one aspect, some embodiments of this application provide a semiconductor structure, including:
[0006] A substrate;
[0007] At least one memory cell located on the substrate, the memory cell including a write transistor and a read transistor arranged along a first direction, and the first direction is parallel to the substrate;
[0008] The write transistor includes a first gate, a first semiconductor layer insulated from the first gate, and a first source / drain and a second source / drain respectively connected to the first semiconductor layer;
[0009] The read transistor includes a second gate arranged along the first direction, a third source / drain insulated from the second gate, a second semiconductor layer, and a fourth source / drain, and the third source / drain and the fourth source / drain are respectively connected to the second semiconductor layer;
[0010] The first source / drain of the write transistor is connected to the second gate of the read transistor.
[0011] In some embodiments, the read transistor further includes a second gate insulating layer, and the second gate insulating layer is located between the second gate and the third source / drain and separates the second gate from the third source / drain.
[0012] In some embodiments, the second gate insulating layers of a plurality of read transistors stacked at intervals along a third direction are of an integral structure, and the third direction is perpendicular to the substrate.
[0013] In some embodiments, the third source / drain electrodes of a plurality of read transistors stacked at intervals along the third direction are interconnected to form a read bit line.
[0014] In some embodiments, the second semiconductor layers of a plurality of read transistors stacked at intervals along the third direction are of an integral structure.
[0015] In some embodiments, the fourth source / drain electrodes of a plurality of read transistors arranged at intervals along the second direction are commonly connected to a read word line extending along the second direction, where the second direction is parallel to the substrate and intersects with the first direction.
[0016] In some embodiments, the first gate electrodes of a plurality of write transistors stacked at intervals along the third direction are interconnected to form a write word line.
[0017] In some embodiments, the write word line includes a vertical portion extending along the third direction and an extending portion extending from the vertical portion.
[0018] In some embodiments, the write transistor further includes a first gate insulating layer located between the first semiconductor layer and the extending portion.
[0019] In some embodiments, the first semiconductor layer at least partially surrounds the write word line.
[0020] In some embodiments, the write transistor further includes a gate isolation layer that is located between the vertical portion and the first semiconductor layer and between the vertical portion and the first gate insulating layer in a direction parallel to the substrate.
[0021] In some embodiments, the gate isolation layer includes a material different from that of the first gate insulating layer.
[0022] In some embodiments, the first semiconductor layers of different write transistors sharing the same write word line are separated from each other.
[0023] In some embodiments, a plurality of memory cells arranged along the second direction share a write bit line extending along the second direction.
[0024] On the other hand, some embodiments of the present application provide a method for manufacturing a semiconductor structure, including the following steps:
[0025] Form an insulating layer and a conductive layer alternately on a substrate along a third direction perpendicular to the substrate to form a stacked structure;
[0026] Etch the stacked structure to form one vertical conductive part extending in the second direction and a plurality of transverse sub-conductive parts extending in the first direction separated by the vertical conductive part in the conductive layer, where the first direction intersects the second direction and both are perpendicular to the third direction;
[0027] In the word line preset area of the write transistor in the transverse sub-conductive part, form a first through hole penetrating the stacked structure;
[0028] Form a first semiconductor layer and a write word line of the write transistor in the first through hole;
[0029] Form a first source / drain and a second source / drain of the write transistor on both sides of the first semiconductor layer in the first direction;
[0030] In the semiconductor layer preset area of the read transistor in the transverse sub-conductive part, form a second through hole penetrating the stacked structure;
[0031] Deposit an insulating material and a conductive material in sequence in the second through hole;
[0032] Remove part of the insulating material and the conductive material to form a third through hole, a second gate insulating layer, and a third source / drain;
[0033] Fill the third through hole with a semiconductor material to form a second semiconductor layer of the read transistor; connect the first source / drain of the write transistor to the second gate of the read transistor.
[0034] In some embodiments, forming a plurality of transverse sub-conductive parts includes:
[0035] Form a plurality of first trenches extending in the first direction in the stacked structure to divide the conductive layer in the stacked structure into one vertical conductive part and a plurality of transverse sub-conductive parts separated by the vertical conductive part;
[0036] Fill the first trenches with an insulating material.
[0037] In some embodiments, forming a first semiconductor layer and a write word line of the write transistor in the first through hole includes:
[0038] Form a first through hole;
[0039] By means of the first through hole, etch the conductive layer in a direction parallel to the substrate at the conductive layer to form a second trench;
[0040] Deposit a semiconductor material thin film, an insulating layer thin film, and a conductive thin film in sequence along the side wall of the first through hole and the side wall of the second trench to form a preset first semiconductor layer, a preset first gate insulating layer, and a preset write word line of the write transistor;
[0041] Remove all the materials of the preset first semiconductor layer, the preset first gate insulating layer, and the preset word line located within the first through hole, and only retain the materials of the preset first semiconductor layer, the preset first gate insulating layer, and the preset word line located within the second trench. Then, form the first through hole again, and the remaining material of the preset word line within the second trench forms the protruding portion of the word line.
[0042] Remove a portion of the materials of the preset first semiconductor layer and the preset first gate insulating layer located within the second trench to form a third trench. The remaining material of the preset first semiconductor layer within the second trench forms the first semiconductor layer, and the remaining material of the preset first gate insulating layer within the second trench forms the first gate insulating layer.
[0043] Fill the third trench with an insulating material to form a gate isolation layer.
[0044] Fill the first through hole with a conductive film again to form the vertical portion of the word line of the write transistor.
[0045] In another aspect, some embodiments of the present application provide an electronic device including the semiconductor structure described in any one of the above.
[0046] In some embodiments, the above electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.
[0047] The manufacturing process of the semiconductor structure of the present application is simple and combines the performance advantages of transistors of two structures. The write transistor of the present application adopts a ring-channel structure, while the read transistor adopts a planar structure, which reduces the manufacturing difficulty without reducing the performance of the read transistor.
[0048] The semiconductor structure of the present application has a high integration degree, low process cost, low process difficulty, and its performance matches that of a semiconductor structure with both read transistors and write transistors adopting a ring-channel structure.
[0049] Other features and advantages of the present application will be described in the subsequent specification, and some of them will become obvious from the specification or be understood by implementing the present application. Other advantages of the present application can be achieved and obtained through the solutions described in the specification and the drawings. Description of the Drawings
[0050] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification. They are used together with the embodiments of the present application to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.
[0051] Figure 1ASchematic horizontal cross - section of a semiconductor structure provided for some embodiments of the present application, taken along a plane parallel to the substrate (through the conductive layer);
[0052] Figure 1B For the cross - section along Figure 1A Schematic vertical cross - section perpendicular to the substrate, taken along the section line aa' in the structure shown;
[0053] Figure 1C For the cross - section along Figure 1A Schematic vertical cross - section perpendicular to the substrate, taken along the section line bb' in the structure shown;
[0054] Figure 1D For the cross - section along Figure 1A Schematic vertical cross - section perpendicular to the substrate, taken along the section line cc' in the structure shown;
[0055] Figure 1E For the cross - section along Figure 1A Schematic vertical cross - section perpendicular to the substrate, taken along the section line dd' in the structure shown;
[0056] Figure 2 Equivalent circuit diagram of a semiconductor structure provided for some embodiments of the present application;
[0057] Figure 3A Schematic vertical cross - section perpendicular to the substrate, taken along the section line aa' of a stacked structure formed in an intermediate step of a manufacturing method of a semiconductor structure provided for some embodiments of the present application;
[0058] Figure 3B Schematic vertical cross - section perpendicular to the substrate, taken along the section line cc' of a stacked structure formed in an intermediate step of a manufacturing method of a semiconductor structure provided for some embodiments of the present application;
[0059] Figure 4A Schematic horizontal cross - section of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for some embodiments of the present application, taken along a plane parallel to the substrate (through the conductive layer);
[0060] Figure 4B Schematic vertical cross - section perpendicular to the substrate, taken along the section line bb' of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for some embodiments of the present application;
[0061] Figure 4C Schematic vertical cross - section perpendicular to the substrate, taken along the section line cc' of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for some embodiments of the present application;
[0062] Figure 4DSchematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line dd';
[0063] Figure 5A Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line bb';
[0064] Figure 5B Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line cc';
[0065] Figure 5C Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line dd';
[0066] Figure 6A Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line aa';
[0067] Figure 6B Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line cc';
[0068] Figure 7A Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line aa';
[0069] Figure 7B Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line cc';
[0070] Figure 8A Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line aa';
[0071] Figure 8B Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line cc';
[0072] Figure 9ASchematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line aa';
[0073] Figure 9B Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line cc';
[0074] Figure 10A Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line aa';
[0075] Figure 10B Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line cc';
[0076] Figure 11A Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line aa';
[0077] Figure 11B Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line dd';
[0078] Figure 12A Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line aa';
[0079] Figure 12B Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line dd';
[0080] Figure 13A Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line aa'; and
[0081] Figure 13B Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line dd'. Detailed embodiments
[0082] To make the objectives, technical solutions and advantages of this application more clear and understandable, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined arbitrarily with each other.
[0083] The embodiments in this document can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the implementation methods and contents can be transformed into various forms without departing from the gist and scope of this application. Therefore, this application should not be construed as being limited only to the contents described in the following embodiments. Without conflict, the embodiments in this application and the features in the embodiments can be combined arbitrarily with each other.
[0084] The size and proportional relationships between the various film layers or components in the drawings of this application can be used as a reference in actual processes, which are embodiments with relatively good technical effects, but are not limited thereto. For example: the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The drawings described in this application are only schematic diagrams of the structure, and one embodiment of this application is not limited to the shape or numerical values shown in the drawings.
[0085] In this specification, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of the constituent elements with reference to the drawings, which are only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to this application. The positional relationships of the constituent elements are appropriately changed according to the directions describing the constituent elements. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the circumstances.
[0086] In this specification, unless otherwise clearly specified and defined, the terms "arrange" and "connect" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0087] In the description of this application, ordinal numbers such as "first" and "second" are set to avoid confusion of the constituent elements, rather than to limit the quantity.
[0088] In this specification, "film" and "layer" can be interchanged. For example, sometimes "metal layer" can be changed to "metal film".
[0089] Some embodiments of the present application provide a semiconductor structure, including a substrate; at least one memory cell located on the substrate, the memory cell including a write transistor and a read transistor arranged along a first direction, the first direction being parallel to the substrate; the write transistor including a first gate, a first semiconductor layer insulatingly disposed from the first gate, and a first source / drain and a second source / drain respectively connected to the first semiconductor layer; the read transistor including a second gate arranged along the first direction, a third source / drain insulatingly disposed from the second gate, a second semiconductor layer, and a fourth source / drain, the third source / drain and the fourth source / drain being respectively connected to the second semiconductor layer; the first source / drain of the write transistor being connected to the second gate of the read transistor.
[0090] As used in the present application, the term "first direction" X is defined as the direction parallel to the arrangement direction of the read transistor and the write transistor; the term "second direction" Y is defined as the direction parallel to the extension direction of the write bit line; the term "third direction" Z is defined as the direction perpendicular to the plane where the substrate is located, that is, the direction parallel to the extension direction of the write word line; the plane formed by the first direction X and the second direction Y is parallel to the substrate. The "first direction" X, the "second direction" Y, and the "third direction" Z can be as Figures 1A - 1E shown, etc.
[0091] As used in the present application, the term "section line aa'" is a line parallel to the first direction X and passing through the source / drains of the read transistor and the source / drains of the write transistor arranged along the first direction; the term "section line bb'" is a line parallel to the first direction X and not passing through the source / drains of the read transistor and the source / drains of the write transistor; the term "section line cc'" is a line parallel to the second direction Y and passing through the first gate of the write transistor; and the term "section line dd'" is a line parallel to the second direction Y and passing through the second semiconductor layer of the read transistor. The specific positions of these section lines can be as Figures 1A - 1E shown, etc.
[0092] As used in the present application, the term "being an integral structure" may mean that there is no obvious fault or gap or other obvious boundary interface between A and B in the microstructure. Generally, a connected film layer patterned on a film layer is an integral body. For example, A and B are made of the same material to form a film layer and have a connected structure formed simultaneously through the same patterning process.
[0093] The present application provides a semiconductor structure, including: a substrate; at least one memory cell located on the substrate, the memory cell including a write transistor and a read transistor arranged along a first direction, the first direction being parallel to the substrate; the write transistor including a first gate, a first semiconductor layer insulated from the first gate, and a first source / drain and a second source / drain respectively connected to the first semiconductor layer; the read transistor including a second gate arranged along the first direction, a third source / drain insulated from the second gate, a second semiconductor layer, and a fourth source / drain, the third source / drain and the fourth source / drain being respectively connected to the second semiconductor layer; the first source / drain of the write transistor being connected to the second gate of the read transistor.
[0094] Figures 1A - 1E It is shown that the semiconductor structure may include a substrate, at least one memory cell located on the substrate, and the memory cell includes a write transistor and a read transistor arranged along a first direction X. Additionally, at the position of each memory cell, there may also be a plurality of memory cells stacked at intervals along a third direction Z perpendicular to the substrate.
[0095] Figure 1A It is also shown that the write transistor may include a first gate 150, a first semiconductor layer 130 insulated from the first gate 150, and a first source / drain 110 and a second source / drain 120 respectively connected to the first semiconductor layer 130.
[0096] Figure 1A It is also shown that the read transistor may include a second gate 250 arranged along the first direction X, a third source / drain 210 insulated from the second gate 250, a second semiconductor layer 230, and a fourth source / drain 220, the third source / drain 210 and the fourth source / drain 220 being respectively connected to the second semiconductor layer 230.
[0097] Figure 1A It is also shown that the read transistor may further include a second gate insulating layer 240, the second gate insulating layer 240 being located between the second gate 250 and the third source / drain 210 and separating the second gate 250 from the third source / drain 210.
[0098] Although the first source / drain and the second source / drain, as well as the third source / drain and the fourth source / drain references are used herein to label two separate and different source / drains, it is not intended that the source / drains referred to as the "first" source / drain, or "second" source / drain, and "third" source / drain and "fourth" source / drain have a unique meaning.
[0099] In some embodiments, the first source / drain and the second source / drain are independent of each other. In some embodiments, one of the first source / drain and the second source / drain may be the source of the write transistor, and the other may be the drain of the write transistor. Similarly, the third source / drain and the fourth source / drain are independent of each other, and one of the third source / drain and the fourth source / drain may be the source of the read transistor, and the other may be the drain of the read transistor.
[0100] Figure 1A It is also shown that the second gate 250 of the read transistor is connected to the first source / drain 110 of the write transistor to form a storage node SN, or they are of an integral structure, thus enabling a capacitorless device structure.
[0101] Figure 1A It is also shown that a plurality of memory cells arranged along the second direction Y share a write bit line 160 extending along the second direction Y. That is, the second source / drains 120 of a plurality of write transistors arranged at intervals along the second direction Y can be commonly electrically connected to the write bit line 160.
[0102] Figure 1A It is also shown that the fourth source / drains 220 of a plurality of read transistors arranged at intervals along the second direction Y are commonly connected to a read word line 270 extending along the second direction Y. The second direction Y is parallel to the substrate 10 and intersects the first direction X. However, in some embodiments, the fourth source / drains of a plurality of read transistors arranged at intervals along the second direction may not be commonly connected to a read word line extending along the second direction.
[0103] Figure 1B It is shown that the second gate insulating layers 240 of a plurality of read transistors stacked at intervals along the third direction Z are of an integral structure; the third source / drains 210 of a plurality of read transistors stacked at intervals along the third direction Z are connected to each other and form a read bit line 260; the second semiconductor layers 230 of a plurality of read transistors stacked at intervals along the third direction Z are of an integral structure.
[0104] In some embodiments, the dimension of the second semiconductor layer 230 along the first direction X may be in the range of 10 nm - 60 nm, and the dimension of the third source / drain 210 along the first direction X may be in the range of 10 nm - 30 nm.
[0105] Continue to refer to Figure 1B, the first gates 150 of a plurality of write transistors stacked at intervals along a third direction Z are interconnected to form a word line 170; the word line 170 may include a vertical portion 151 extending along the third direction Z and an extending portion 152 extending from the vertical portion 151; the write transistor may further include a first gate insulating layer 140, and the first gate insulating layer 140 is located between the first semiconductor layer 130 and the extending portion 152. The first semiconductor layer 130 at least partially surrounds the word line 170.
[0106] Figure 1B It is also shown that the write transistor may further include a gate isolation layer 153, and the gate isolation layer 153 is located between the vertical portion 151 and the first semiconductor layer 130 and between the vertical portion 151 and the first gate insulating layer 140 in a direction parallel to the substrate 10. The gate isolation layer 153 includes a material different from that of the first gate insulating layer 140.
[0107] This structural design of the write transistor can enable the first semiconductor layers 130 of at least some adjacent layers of the write transistors to be disconnected in the third direction Z, that is, the first semiconductor layers 130 of different write transistors sharing the same word line 170 are separated from each other.
[0108] Therefore, the word line configuration of the present application can more easily eliminate parasitic MOS and enhance the stability of the device by designing the extending portion 152 with a lateral extension.
[0109] In some embodiments, a plurality of the write transistors stacked at intervals along the third direction Z share a word line 170 extending in the third direction Z.
[0110] In some embodiments, a plurality of memory cells arranged along the second direction share a write bit line 160 extending along the second direction.
[0111] Figure 2 An equivalent circuit diagram of a semiconductor structure provided for some embodiments of the present application. In Figure 2Among them, SN represents a storage node, and WWL, WBL, RWL, and RBL are a write word line, a write bit line, a read word line, and a read bit line respectively. The third source / drain (such as the drain) of the read transistor is electrically connected to the read bit line (RBL) 260, and the fourth source / drain (such as the source) is electrically connected to the read word line (RWL) 270; the first gate of the write transistor is electrically connected to the write word line (WWL) 170, and the second source / drain 120 (such as the drain) of the write transistor is electrically connected to the write bit line (WBL) 160. The second gate of the read transistor is electrically connected to the first source / drain (such as the source) of the write transistor, that is, the two form an integrated structure, and the second gate of the read transistor serves as the storage node. Data "1" or "0" is stored through the storage node to control the turning on or off of the read transistor, and the data stored in the storage node is determined to be "1" or "0" according to the on and off states of the read transistor.
[0112] The technical solution of the present application will be further described below through the manufacturing process of a semiconductor structure in some embodiments of the present application. The "lithography process" mentioned in some embodiments includes depositing a film layer, coating a photoresist, mask exposure, development, etching, stripping the photoresist, etc., which are mature manufacturing processes in the related art. The "lithography process" mentioned in some embodiments includes coating a film layer, mask exposure, and development, which are mature manufacturing processes in the related art. Deposition can use known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can use known coating processes, and etching can use known methods, which will not be specifically limited here. In the description of some embodiments, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate by using a deposition or coating process. If the "thin film" does not require a lithography process or a lithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a lithography process or a lithography process during the entire manufacturing process, it is called a "thin film" before the lithography process and a "layer" after the lithography process. The "layer" after the lithography process or the lithography process contains at least one "pattern".
[0113] In some embodiments, the manufacturing process of the semiconductor structure may include:
[0114] S100: Form a stacked structure.
[0115] Exemplary steps may include: providing a substrate 10, and alternately depositing an insulating material thin film and a conductive material thin film on the substrate 10 along the third direction Z to form a stacked structure 1 including an insulating layer 20 and a conductive layer 30, as Figure 3A and Figure 3B shown. Figure 3A FIG. is a schematic cross-sectional view perpendicular to the substrate taken along the section line aa' of the stacked structure formed in an intermediate step of a manufacturing method of a semiconductor structure provided in some embodiments of the present application; Figure 3BSchematic cross-sectional view perpendicular to the substrate taken along the cross-section line cc' of a stacked structure formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application.
[0116] In some embodiments, an insulating layer thin film and a conductive layer thin film can be deposited using chemical vapor deposition method or plasma enhanced chemical vapor deposition (PECVD) method.
[0117] In some embodiments, the substrate 10 can be made of glass, silicon, flexible materials, etc. The flexible materials can be materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. In some embodiments, the substrate can be a single-layer structure or a multi-layer stacked structure. The stacked structure substrate can include: flexible material / inorganic material / flexible material, and the inorganic material can be any one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), etc.
[0118] In some embodiments, the substrate 10 can be a semiconductor substrate, such as a silicon substrate.
[0119] In some embodiments, the insulating layer 20 can be independently selected from any one or more of silicon oxide (e.g., SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), SiGe. In some embodiments, the insulating layer 20 can be silicon dioxide.
[0120] In some embodiments, the conductive layer 30 can be made of a metal material, such as tungsten, TiN, or a composite thereof.
[0121] Figure 3A and 3B The stacked structure 1 shown in and can include 4 insulating layers 20 and 3 conductive layers 30. In some other embodiments, the stacked structure 1 can also include more or fewer alternately arranged insulating layers 20 and conductive layers 30.
[0122] S200: Form a preset pattern in the conductive layer.
[0123] Exemplary steps can include: depositing a silicon nitride hard mask layer 40 on the stacked structure 1, and etching the stacked structure to form a preset pattern in the stacked structure, such as Figure 4A , Figure 4B , Figure 4C and Figure 4D shown. Figure 4ASchematic horizontal cross - sectional view of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along a plane parallel to the substrate (through the conductive layer); Figure 4B Schematic cross - sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line bb'; Figure 4C Schematic cross - sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line cc'; Figure 4D Schematic cross - sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line dd'.
[0124] In some embodiments, as Figure 4A shown, the preset pattern may include three vertical conductive portions 31, 32, and 33 extending along the second direction Y and four horizontal conductive portions extending along the first direction X. The one vertical conductive portion 31 divides the four horizontal conductive portions into eight horizontal sub - conductive portions 310. The horizontal sub - conductive portions 310 located on one side of the vertical conductive portion 31 along the first direction X terminate at the vertical conductive portion 32, while the horizontal sub - conductive portions 310 located on the opposite side of the vertical conductive portion 31 along the first direction X terminate at the vertical conductive portion 33. A first trench T1 is formed between two adjacent horizontal sub - conductive portions 310 in the second direction Y, for a total of six first trenches T1.
[0125] In some embodiments, the preset pattern may have other shapes, such as having only one vertical conductive portion and multiple horizontal sub - conductive portions separated by the vertical conductive portion.
[0126] S300: Fill the first trenches.
[0127] Exemplary steps may include: filling each first trench T1 with the same insulating material as the insulating layer 20, and planarizing the upper surface of the stacked structure through a Chemical Mechanical Polishing (CMP) process to form a new insulating layer 20, as Figure 5A , Figure 5B and Figure 5C shown. Figure 5A Schematic cross - sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line bb'; Figure 5B Schematic cross - sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line cc'; Figure 5CSchematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line dd'.
[0128] In some embodiments, an insulating material different from the insulating layer 20 may also be filled into each of the first trenches T1.
[0129] S400: Form a first via hole of the write transistor.
[0130] Exemplary steps may include: forming 1 first via hole K1 at a preset position of the writing line of the write transistor, i.e., in each lateral sub-conductive part 310, by etching (such as dry etching), and exposing the sidewalls of each insulating layer 20 and conductive layer 30, as Figure 6A and Figure 6B shown. Figure 6A Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line aa'; Figure 6B Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line cc'.
[0131] In some embodiments, the orthographic projection of the first via hole K1 on a plane parallel to the substrate 10 may be rectangular, square, circular, elliptical, etc.
[0132] In some embodiments, the orthographic projection of the first via hole K1 on a plane parallel to the substrate 10 may be located within the orthographic projection of each lateral sub-conductive part 310 on a plane parallel to the substrate 10.
[0133] S500: Form a second trench.
[0134] Exemplary steps may include: by means of the formed first via hole K1, laterally etching and removing part of the material of the conductive layer 30 along a direction parallel to the substrate to form a second trench T2 that expands into the conductive layer, thereby exposing the upper and lower surfaces of each insulating layer 20 and the sidewalls of the conductive layer 30. The length of the second trench T2 along the first direction X is W; in each first via hole K1, a plurality of second trenches T2 are formed, as Figure 7A and Figure 7B shown. Figure 7A Schematic cross-sectional view perpendicular to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application, taken along section line aa'; Figure 7BA schematic cross-sectional view perpendicular to the substrate taken along the cross-section line cc' of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application.
[0135] Figure 7B It is clearly shown that at the preset position of the word line of the write transistor, the material of the conductive layer 30 along the second direction Y is removed, leaving only the insulating layer 20.
[0136] S600: Form a preset write word line of the write transistor.
[0137] Exemplary steps may include: sequentially depositing a semiconductor thin film, an insulating layer thin film, and a conductive thin film on the sidewall of the insulating layer 20 exposed in the first through hole K1, the upper and lower surfaces of the insulating layer 20 exposed in the lateral second trench T2, and the sidewall of the conductive layer 30 to form a preset first semiconductor layer 130', a preset first gate insulating layer 140', and a preset write word line 150', as Figure 8A and Figure 8B shown. Figure 8A A schematic cross-sectional view perpendicular to the substrate taken along the cross-section line aa' of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application; Figure 8B A schematic cross-sectional view perpendicular to the substrate taken along the cross-section line cc' of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for some embodiments of the present application.
[0138] In some embodiments, the preset first semiconductor layer 130' may be made of a metal oxide semiconductor material. In some embodiments, the metal oxide semiconductor material may be an amorphous or polycrystalline metal oxide semiconductor material, and the corrosion rate of the metal oxide semiconductor material in a weakly acidic or weakly alkaline solution is relatively slow. In some embodiments, the metal oxide semiconductor material may be an oxide of In, an oxide of Ga, an oxide of Zn, an oxide of Sn, etc. These metal oxide materials such as indium gallium zinc oxide (IGZO) can be used as channel materials.
[0139] In some embodiments, when the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10 -15A), which ensures a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium - zinc - oxide), IZOx and other materials, as long as the leakage current of the transistor can meet the requirements, which can be adjusted according to the actual situation.
[0140] In some embodiments, the preset first gate insulating layer 140' can be a high - dielectric - constant dielectric layer, that is, a dielectric layer with K≥3.9. The high - dielectric - constant dielectric layer can be used as the gate oxide. The preset first gate insulating layer 140' can be any one or more of silicon oxide, aluminum oxide (Al2O3), hafnium oxide (HfO2).
[0141] In some embodiments, the preset first gate 150' can be made of tungsten, titanium nitride or their composite materials, etc.
[0142] S700: Form a third trench.
[0143] Exemplary steps may include: using wet etching to remove all the materials on the sidewall of the first via K1, and reforming the first via K1, only retaining the materials within the second trench T2; at each conductive layer 30, continue to etch transversely in a direction parallel to the substrate to remove part of the preset first semiconductor layer 130' and the preset first gate insulating layer 140' within the second trench T2 to form a third trench T3 (subsequently used to form a gate isolation layer), and within each first via K1, form a plurality of third trenches T3, as Figure 9A and Figure 9B shown. Figure 9A A schematic cross - sectional view perpendicular to the substrate taken along the section line aa' of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided by some embodiments of the present application; Figure 9B A schematic cross - sectional view perpendicular to the substrate taken along the section line cc' of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided by some embodiments of the present application.
[0144] S800: Remove the parasitic MOS of the write transistor and form the first gate of the write transistor.
[0145] Exemplary steps may include: filling the third trench T3 of each conductive layer with an insulating material and etching away the excess insulating material to make the sidewalls of the conductive layer 30 and the insulating layer 20 flush, forming the gate isolation layer 153, and then forming the first semiconductor layer 130 and the first gate insulating layer 140 of the write transistor; filling the first via K1 with a conductive material to form the write line 150, as Figure 10A and Figure 10B shown. Figure 10A FIG. is a schematic cross-sectional view perpendicular to the substrate taken along the section line aa' of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by some embodiments of the present application; Figure 10B FIG. is a schematic cross-sectional view perpendicular to the substrate taken along the section line cc' of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by some embodiments of the present application.
[0146] As Figure 10A shown, the write line 150 has a vertical portion 151 perpendicular to the substrate and an extending portion 152 located on the peripheral side of the vertical portion 151 and extending laterally in a direction parallel to the substrate, and the gate isolation layer 153 is formed. The write transistor forms such a specific structure of the write line and has a gate isolation layer, which makes it easier to remove parasitic MOS.
[0147] In some embodiments, the gate isolation layer 153 may be made of the same material as the insulating layer 20, such as silicon dioxide, but cannot be made of the same material as the first gate insulating layer 140.
[0148] S900: Form a preset third source / drain and a preset second gate insulating layer of the read transistor.
[0149] Exemplary steps may include: in a preset area of the second semiconductor layer of the read transistor, lithographically etching the stacked structure to form a second via K2 that penetrates the stacked structure and terminates at the upper surface of the substrate 10; sequentially depositing an insulating layer film and a conductive film on the bottom wall and side wall of the second via K2 to form a preset second gate insulating layer 240' of the read transistor and a preset third source / drain 210' covering the preset second gate insulating layer 240', as Figure 11A and Figure 11B shown. Figure 11A FIG. is a schematic cross-sectional view perpendicular to the substrate taken along the section line aa' of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by some embodiments of the present application; Figure 11B FIG. is a schematic cross-sectional view perpendicular to the substrate taken along the section line dd' of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by some embodiments of the present application.
[0150] S1000: Form the third source / drain and the second gate insulating layer of the read transistor.
[0151] Exemplary steps may include: etching (such as dry etching) along the third direction Z to remove part of the materials of the preset second gate insulating layer 240' and the preset third source / drain 210' to form a third through hole K3, so as to expose part of the bottom wall of the third through hole K3, the side walls of the preset third source / drain 210', and part of the preset second gate insulating layer 240' on the bottom wall of the third through hole K3, thereby forming the third source / drain 210 and the second gate insulating layer 240 of the read transistor, as Figure 12A and Figure 12B shown. Figure 12A FIG. is a schematic cross-sectional view perpendicular to the substrate taken along the section line aa' of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided in some embodiments of the present application; Figure 12B FIG. is a schematic cross-sectional view perpendicular to the substrate taken along the section line dd' of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided in some embodiments of the present application.
[0152] S1100: Form the second semiconductor layer of the read transistor.
[0153] Exemplary steps may include: depositing semiconductor material into the third through hole K3 to fill the third through hole K3, thereby forming the second semiconductor layer 230, as Figure 13A and Figure 13B shown. Figure 13A FIG. is a schematic cross-sectional view perpendicular to the substrate taken along the section line aa' of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided in some embodiments of the present application; Figure 13B FIG. is a schematic cross-sectional view perpendicular to the substrate taken along the section line dd' of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided in some embodiments of the present application.
[0154] Figure 13A It shows that the side wall of the second semiconductor layer 230 is in contact with the side wall of the third source / drain 210.
[0155] Some embodiments of the present application further provide an electronic device, including the semiconductor structure provided in some embodiments of the present application as above.
[0156] In some embodiments, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply.
[0157] Although the embodiments disclosed in this application are as above, the content described is only the embodiments adopted for the convenience of understanding this application and is not used to limit this application. Any person skilled in the art within the scope of this application can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application. However, the protection scope of this application shall still be subject to the scope defined by the appended claims.
Claims
1. A semiconductor structure, characterized in that, Comprising: A substrate; At least one memory cell located on the substrate, the memory cell including a write transistor and a read transistor arranged along a first direction, the first direction being parallel to the substrate; The write transistor includes a first gate, a first semiconductor layer insulated from the first gate, and a first source / drain and a second source / drain respectively connected to the first semiconductor layer; The read transistor includes a second gate arranged along the first direction, a third source / drain insulated from the second gate, a second semiconductor layer, and a fourth source / drain, the third source / drain and the fourth source / drain being respectively connected to the second semiconductor layer; The first source / drain of the write transistor is connected to the second gate of the read transistor.
2. The semiconductor structure according to claim 1, wherein The read transistor further includes a second gate insulating layer, the second gate insulating layer being located between the second gate and the third source / drain and separating the second gate from the third source / drain.
3. The semiconductor structure according to claim 2, wherein The second gate insulating layers of a plurality of the read transistors stacked at intervals along a third direction are of an integral structure, the third direction being perpendicular to the substrate.
4. The semiconductor structure according to claim 3, wherein, The third source / drains of a plurality of the read transistors stacked at intervals along the third direction are interconnected and form a read bit line.
5. The semiconductor structure according to claim 3, wherein The second semiconductor layers of a plurality of the read transistors stacked at intervals along the third direction are of an integral structure.
6. The semiconductor structure according to claim 1, wherein The fourth source / drains of a plurality of the read transistors arranged at intervals along a second direction are commonly connected to a read word line extending along the second direction, the second direction being parallel to the substrate and intersecting the first direction.
7. The semiconductor structure according to claim 3, wherein The first gates of a plurality of the write transistors stacked at intervals along the third direction are interconnected and form a write word line.
8. The semiconductor structure according to claim 7, wherein The write word line includes a vertical portion extending along the third direction and an extending portion extending from the vertical portion.
9. The semiconductor structure according to claim 8, wherein, The write transistor further includes a first gate insulating layer, the first gate insulating layer being located between the first semiconductor layer and the extending portion.
10. The semiconductor structure according to claim 8, wherein, The first semiconductor layer at least partially surrounds the write word line.
11. The semiconductor structure according to claim 9, wherein The write transistor further includes a gate isolation layer, the gate isolation layer being located between the vertical portion and the first semiconductor layer and between the vertical portion and the first gate insulating layer in a direction parallel to the substrate.
12. The semiconductor structure according to claim 11, wherein, The gate isolation layer includes a material different from that of the first gate insulating layer.
13. The semiconductor structure according to claim 7, wherein, The first semiconductor layers of different write transistors sharing the same write word line are separated from each other.
14. The semiconductor structure according to claim 6, wherein A plurality of the memory cells arranged along the second direction share a write bit line extending along the second direction.
15. A manufacturing method of a semiconductor structure, characterized in that, Including the following steps: Alternately forming an insulating layer and a conductive layer on the substrate along a third direction perpendicular to the substrate to form a stacked structure; Etching the stacked structure to form, in the conductive layer, one vertical conductive portion extending along a second direction and a plurality of transverse sub-conductive portions extending along a first direction separated by the vertical conductive portion, the first direction intersecting the second direction and both being perpendicular to the third direction; Forming a first through hole penetrating the stacked structure in a write transistor word line preset area of the transverse sub-conductive portion; Form a first semiconductor layer and a write word line of the write transistor in the first through hole; Form a first source / drain and a second source / drain of the write transistor on both sides of the first semiconductor layer along the first direction; In a preset area of the semiconductor layer of the read transistor in the lateral sub-conductive part, form a second through hole penetrating the stacked structure; Deposit an insulating material and a conductive material in sequence in the second through hole; Remove part of the insulating material and the conductive material to form a third through hole, a second gate insulating layer, and a third source / drain; Fill the third through hole with a semiconductor material to form a second semiconductor layer of the read transistor; Connect the first source / drain of the write transistor to the second gate of the read transistor.
16. The manufacturing method according to claim 15, characterized in that, Forming a plurality of lateral sub-conductive parts includes: Form a plurality of first trenches extending in a first direction in the stacked structure to divide the conductive layer in the stacked structure into one vertical conductive part and a plurality of the lateral sub-conductive parts separated by the vertical conductive part; Fill the first trenches with an insulating material.
17. The manufacturing method according to claim 16, characterized in that, Forming a first semiconductor layer and a write word line of the write transistor in the first through hole includes: Form the first through hole; By means of the first through hole, etch the conductive layer in a direction parallel to the substrate at the conductive layer to form a second trench; Deposit a semiconductor material thin film, an insulating layer thin film, and a conductive thin film in sequence along the sidewall of the first through hole and the sidewall of the second trench to form a preset first semiconductor layer, a preset first gate insulating layer, and a preset write word line of the write transistor; Remove all the materials of the preset first semiconductor layer, the preset first gate insulating layer, and the preset write word line located in the first through hole, and only retain the materials of the preset first semiconductor layer, the preset first gate insulating layer, and the preset write word line located in the second trench, and form a first through hole again. The remaining material of the preset write word line in the second trench forms an extending part of the write word line; Remove part of the materials of the preset first semiconductor layer and the preset first gate insulating layer located in the second trench to form a third trench. The remaining material of the preset first semiconductor layer in the second trench forms the first semiconductor layer, and the remaining material of the preset first gate insulating layer in the second trench forms a first gate insulating layer; Fill the third trench with an insulating material to form a gate isolation layer; Fill the first through hole with a conductive thin film again to form a vertical part of the write word line of the write transistor.
18. An electronic device, characterized in that, Including the semiconductor structure according to any one of claims 1-14.