Two layout optimization schemes of bidirectional compact low-leakage SCR device for integrated circuit ESD protection
By optimizing the layout of BLVSCR devices and adding trigger channels and drain channels, the problems of high trigger voltage and reduced overcurrent capability in ESD protection in traditional SCR devices are solved, and high opening speed and conduction uniformity are achieved, which is suitable for ESD protection of low-voltage integrated circuits.
Patent Information
- Application Number
- CN202411878838.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-19
- Publication Date
- 2025-06-24
AI Technical Summary
Traditional SCR devices have problems with excessive trigger voltage and reduced overcurrent capability in ESD protection applications, resulting in deterioration of device turn-on speed and conduction uniformity.
By optimizing the layout of the bidirectional low voltage thyristor rectifier (BLVSCR), more trigger channels and drain channels are added to ensure the device's high opening speed and conduction uniformity in high current conditions.
It realizes the reduction of leakage current without increasing the layout area, and ensures the high robustness, high opening speed and conduction uniformity of the device. It is suitable for ESD protection of a variety of low-voltage integrated circuits.
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Abstract
Description
Technical Field
[0001] The present invention belongs to the field of design of electrostatic discharge (ESD) protection devices for low-voltage integrated circuits (Integrated Circuits, abbreviated as IC), and specifically relates to two structural layout optimizations for the ESD protection device BLVSCR. Background Art
[0002] Electrostatic discharge (ESD) refers to the process in which a conductive path is formed between two objects with different electric potentials and charge transfer occurs when the induced electric field strength between them is greater than the dielectric breakdown electric field between the two objects. ESD damage to integrated circuits has characteristics such as concealment, latency, randomness, and complexity. With the development of semiconductor process technology, IC failures and damages caused by it have become an increasingly serious problem. Research investigations show that approximately 58% of electronic component failures are caused by electrical stress and ESD. Therefore, the research and development of highly robust ESD protection devices that can pass high currents without affecting the turn-on speed and conduction uniformity is of extremely important economic and social significance for building full-chip electrostatic protection under various integrated circuit advanced processes.
[0003] In a specific semiconductor process, an ESD protection device needs to meet a certain ESD design window during operation, that is, the safe operating range of the device should be less than the minimum breakdown voltage of the protected circuit and greater than the operating voltage of the protected circuit. A silicon controlled rectifier (SCR) is a commonly used type of ESD protection device, which has advantages such as low off-state leakage current, high area utilization rate, and high robustness. Therefore, SCR and its improved structures are widely used in the field of integrated circuit ESD protection design. For ESD protection devices with hysteresis characteristics, the magnitudes of the trigger voltage and the holding voltage should be within the ESD design window, and at the same time, the ESD protection device is required to have strong over-current capabilities.
[0004] Traditional SCR devices still have some problems in ESD protection applications, such as too high trigger voltage, and the reduction of the device's over-current capability with the decrease of size. In order to improve the over-current capability of the device, the size of the active region of the device is usually increased, which inevitably causes the deterioration of the device's turn-on speed and conduction uniformity. Therefore, it is very necessary to invent an ESD protection device with high turn-on speed, good conduction uniformity, and high over-current capability. The purpose of this invention is to optimize the layout of the bidirectional low-voltage silicon controlled rectifier (BLVSCR) so that it can better meet the ESD protection requirements.
[0005] A bidirectional ESD protection device BLVSCR with hysteresis characteristics, having the characteristics of high robustness, simple structure, high area utilization, etc., is very suitable for ESD protection in chips. The structure of the device is as follows Figure 1 shown, including: A P-type silicon substrate (101), on which a first N-type doped region A (201) and a first N-type doped region B (202) are formed; a second N-type doped region A (211) is formed on the right side of the first N-type doped region A (201); a second N-type doped region B (212) is formed on the left side of the first N-type doped region B (202); a first P-type doped region A (221) is formed on the second N-type doped region A (211); a first P-type doped region B (222) is formed on the second N-type doped region B (212); On the left side of the first N-type doped region A (201), a first P-type heavily doped region (301) and a first N-type heavily doped region (311) are sequentially formed; a second P-type heavily doped region (302) and a second N-type heavily doped region (312) are formed on the first P-type doped region A (221); a third P-type heavily doped region (303) and a third N-type heavily doped region (313) are formed on the right side of the first N-type doped region B (202); a fourth N-type heavily doped region (314) and a fourth P-type heavily doped region (304) are formed on the first P-type doped region B (222); The first P-type heavily doped region (301) is connected to the fourth N-type heavily doped region (314), defined as the T1 port; the first N-type heavily doped region (311) is connected to the fourth P-type heavily doped region (304); the second P-type heavily doped region (302) is connected to the third N-type heavily doped region (313); the second N-type heavily doped region (312) is connected to the third P-type heavily doped region (303), defined as the T2 port; Shallow trench isolation is respectively provided between the first P-type heavily doped region and the first N-type heavily doped region, between the second P-type heavily doped region and the second N-type heavily doped region, between the third P-type heavily doped region and the third N-type heavily doped region, and between the fourth P-type heavily doped region and the fourth N-type heavily doped region.
[0006] The device contains parasitic PNP transistors Q p1 、Q p2 ; parasitic NPN transistors Q n1 、Q n2 ; The first parasitic PNP transistor Q p1 , including a first P-type heavily doped region (301), a first N-type doped region A (201), and a first P-type doped region A (221); the second parasitic PNP transistor Q p2, including a first P-type doped region B (222), a first N-type doped region B (202), and a third P-type heavily doped region (303); the first parasitic NPN transistor Q n1 , including a first N-type doped region A (201), a first P-type doped region A (221), and a second N-type heavily doped region (312); the second parasitic NPN transistor Q n2 , including a fourth N-type heavily doped region (314), a first P-type doped region B (222), and a first N-type doped region B (202).
[0007] Meanwhile, the base of Qp1 in the forward SCR path is connected to the base of Qn2 in the reverse SCR path, and the base of Qn1 in the forward SCR path is connected to the base of Qp2 in the reverse SCR path. Therefore, there are diode-assisted trigger paths P1 and P2 in the device. The diode-assisted trigger path P1 is composed of three diodes D1, D2, and D3 connected in series. D1 is composed of a first P-type heavily doped region (301) and a first N-type doped region A (201); D2 is composed of a first P-type doped region B (222), a second N-type doped region B (212), and a first N-type doped region B (202); D3 is composed of a second P-type heavily doped region (302), a first P-type doped region A (221), and a second N-type heavily doped region (312). The diode-assisted trigger path P2 is composed of three diodes D4, D5, and D6 connected in series. D4 is composed of a third P-type heavily doped region (303) and a first N-type doped region B (202); D5 is composed of a first P-type doped region A (221), a second N-type doped region A (211), and a first N-type doped region A (201); D6 is composed of a first P-type doped region B (222) and a fourth N-type heavily doped region (314).
[0008] The working principle of the device: When an ESD event reaches the TI port of the device and the ESD voltage is greater than the BV p1 (the avalanche breakdown voltage of the collector junction of the bipolar transistor in the common-emitter configuration) of the parasitic PNP transistor Q in the device CEO , Q p1 turns on, and a current will flow from T1 to T2 successively through the first P-type heavily doped region (301), the first N-type doped region A (201), the second N-type doped region A (211), the first P-type doped region A (221), and the second N-type heavily doped region (312). As the current increases, the voltage drop of the first P-type doped region A (221) increases, causing the emitter junction voltage of Q n1 to increase, and Q n1 turns on. The collector current of Q n1 increases, the emitter junction voltage of Q p1 increases, and the parasitic NPN transistor Qn1 and the parasitic PNP transistor Q p1 couple to form positive feedback, and thus the SCR channel is turned on.
[0009] When an ESD event reaches the T2 port of the device and the ESD voltage is greater than the breakdown voltage BV p1 (common-emitter collector junction avalanche breakdown voltage of the bipolar transistor) of the parasitic PNP transistor Q CEO in the device, Q p2 turns on, and current will flow from T2 to T1 successively through the third P-type heavily doped region (303), the first N-type doped region B (202), the second N-type doped region B (212), the first P-type doped region B (222), and the fourth N-type heavily doped region (314). As the current increases, the voltage drop across the first P-type doped region B (222) increases, causing the emitter junction voltage of Q n2 to increase, and Q n2 turns on. The collector current of Q n2 increases, the emitter junction voltage of Q p2 increases, and a positive feedback is formed between the parasitic NPN transistor Q n2 and the parasitic PNP transistor Q p2 to turn on the SCR channel.
[0010] The auxiliary trigger paths P1 and P2 are respectively composed of three parasitic diodes in series, which can control the conduction voltage at about 2.1V. At the same time, this structure can further reduce the leakage current without increasing the layout area.
[0011] The BLVSCR effectively controls the trigger voltage through the auxiliary trigger of the parasitic diode path and reduces the leakage current at the same time. If the device is used for ESD protection of high-current situations, the device size needs to be increased, which will lead to a decrease in the device turn-on speed and deterioration of the conduction uniformity.
[0012] Therefore, the present invention proposes a method for optimizing the layout of a bidirectional low-voltage SCR device for ESD protection of low-voltage integrated circuits, enabling it to pass high currents and ensuring the device turn-on speed and conduction uniformity, and can be used to achieve better ESD protection for input / output ports (Input / Output, abbreviated as I / O) and the power supply domain. Summary of the Invention
[0013] The object of the present invention is to propose two bidirectional low-voltage SCR devices for ESD protection of low-voltage integrated circuits that can pass high currents and ensure the device turn-on speed and conduction uniformity. The devices are based on the BLVSCR structure and are optimized in layout design, making the devices have characteristics such as high robustness, high turn-on speed, and high conduction uniformity, and are applicable to ESD protection of various low-voltage integrated circuits.
[0014] The present invention optimizes the Bidirectional Low-Voltage Silicon Controlled Rectifier (BLVSCR). Specifically, two optimizations for the layout of the BLVSCR are provided, enabling the device to pass a large current and ensuring the device's turn-on speed and conduction uniformity. It can be used to implement ESD protection for the Input / Output (I / O) and power domains. The device of the present invention has characteristics such as high robustness, high turn-on speed, and high conduction uniformity, and is applicable to ESD protection of various low-voltage integrated circuits.
[0015] The technical solution adopted by the present invention is as follows: 1. A layout layout optimization for improving the performance of the BLVSCR device, including: The device is a 4*4 array, and the repeating unit is characterized in that: The unit includes a P-type silicon substrate (101), on which a first N-type doped region A (201) and a first N-type doped region B (202) are formed; a second N-type doped region A (211) is formed on the right side of the first N-type doped region A (201); a second N-type doped region B (212) is formed on the left side of the first N-type doped region B (202); a first P-type doped region A (221) is formed on the second N-type doped region A (211); a first P-type doped region B (222) is formed on the second N-type doped region B (212); On the left side of the first N-type doped region A (201), a first P-type heavily doped region (301) and a first N-type heavily doped region (311) are sequentially formed; on the first P-type doped region A (221), a second P-type heavily doped region (302) and a second N-type heavily doped region (312) are formed; on the right side of the first N-type doped region B (202), a third P-type heavily doped region (303) and a third N-type heavily doped region (313) are formed; on the first P-type doped region B (222), a fourth N-type heavily doped region (314) and a fourth P-type heavily doped region (304) are formed; The first P-type heavily doped region (301) is connected to the fourth N-type heavily doped region (314); the first N-type heavily doped region (311) is connected to the fourth P-type heavily doped region (304); the second P-type heavily doped region (302) is connected to the third N-type heavily doped region (313); the second N-type heavily doped region (312) is connected to the third P-type heavily doped region (303); Shallow trench isolation is respectively provided between the first P-type heavily doped region and the first N-type heavily doped region, between the second P-type heavily doped region and the second N-type heavily doped region, between the third P-type heavily doped region and the third N-type heavily doped region, and between the fourth P-type heavily doped region and the fourth N-type heavily doped region.
[0016] The units are arranged in a 4×4 array to form a device.
[0017] In the device array, in four units of the same column, the connected first P-type heavily doped region (301) and the fourth N-type heavily doped region (314) are connected; the connected first N-type heavily doped region (311) and the fourth P-type heavily doped region (304) are connected; the connected second P-type heavily doped region (302) and the third N-type heavily doped region (313) are connected; the connected second N-type heavily doped region (312) and the third P-type heavily doped region (303) are connected; In the device array, in four units of the same row, the first P-type heavily doped regions (301) are connected and defined as the T1 port; the first N-type heavily doped regions (311) are connected; the second P-type heavily doped regions (302) are connected; the second N-type heavily doped regions (312) are connected and defined as the T2 port; the fourth N-type heavily doped regions (314) are connected and defined as the T1 port; the fourth P-type heavily doped regions (304) are connected; the third N-type heavily doped regions (313) are connected; the third P-type heavily doped regions (303)) are connected and defined as the T2 port.
[0018] 2. A compact layout and layout optimization for improving the performance of a BLVSCR device, including: the device is a 4×4 array, and its repeating unit is characterized in that: The unit includes a P-type silicon substrate (101), on which a first N-type doped region A (201) and a first N-type doped region B (202) are formed; a second N-type doped region A (211) is formed on the first N-type doped region A (201); a second N-type doped region B (212) is formed on the first N-type doped region B (202); a first P-type doped region A (221) is formed on the right side of the second N-type doped region A (211); a first P-type doped region B (222) is formed on the left side of the second N-type doped region B (212); On the left side of the second N-type doped region A (211), a third N-type heavily doped region (311), a first P-type heavily doped region (301), and a fourth N-type heavily doped region (312) are formed in sequence from top to bottom; on the first P-type doped region A (221), a third P-type heavily doped region (313), a first N-type heavily doped region (302), and a fourth P-type heavily doped region (314) are formed in sequence from top to bottom; on the right side of the second N-type doped region B (212), a fifth P-type heavily doped region (315), a second N-type heavily doped region (304), and a sixth P-type heavily doped region (316) are formed in sequence from top to bottom; on the first P-type doped region B (222), a fifth N-type heavily doped region (317), a second P-type heavily doped region (303), and a sixth N-type heavily doped region (318) are formed in sequence from top to bottom.
[0019] The first P-type heavily doped region (301) is connected to the second N-type heavily doped region (304); the fourth N-type heavily doped region (312) is connected to the fifth P-type heavily doped region (315); the fourth P-type heavily doped region (314) is connected to the fifth N-type heavily doped region (317); the first N-type heavily doped region (302) is connected to the second P-type heavily doped region (303).
[0020] Shallow trench isolation is respectively provided between the third N-type heavily doped region (311) and the first P-type heavily doped region (301), between the first P-type heavily doped region (301) and the fourth N-type heavily doped region (312), between the third P-type heavily doped region (313) and the first N-type heavily doped region (302), between the first N-type heavily doped region (302) and the fourth P-type heavily doped region (314), between the third N-type heavily doped region (311) and the third P-type heavily doped region (313), between the first P-type heavily doped region (301) and the first N-type heavily doped region (302), between the fourth N-type heavily doped region (312) and the fourth P-type heavily doped region (314), between the fifth P-type heavily doped region (315) and the second N-type heavily doped region (304), between the second N-type heavily doped region (304) and the sixth P-type heavily doped region (316), between the fifth N-type heavily doped region (317) and the second P-type heavily doped region (303), between the second P-type heavily doped region (303) and the sixth N-type heavily doped region (318), between the fifth P-type heavily doped region (315) and the fifth N-type heavily doped region (317), between the second N-type heavily doped region (304) and the second P-type heavily doped region (303), and between the sixth P-type heavily doped region (316) and the sixth N-type heavily doped region (318).
[0021] The units are arranged in a 4*4 array form to form a device.
[0022] In the device array, all the first P-type heavily doped regions (301) and the second N-type heavily doped regions (304) in four units of the same column are connected; the first N-type heavily doped regions (302) and the second P-type heavily doped regions (303) are connected; the third N-type heavily doped regions (311), the fourth N-type heavily doped regions (312), the fifth P-type heavily doped regions (315), and the sixth P-type heavily doped regions (316) are connected; the third P-type heavily doped regions (313), the fourth P-type heavily doped regions (314), the fifth N-type heavily doped regions (317), and the sixth N-type heavily doped regions (318) are connected.
[0023] In the device array, all the first P-type heavily doped regions (301) in four cells of the same row are connected and defined as the T1 port; all the first N-type heavily doped regions (302) are connected and defined as the T2 port; all the third N-type heavily doped regions (311) are connected; all the fourth N-type heavily doped regions (312) are connected; all the third P-type heavily doped regions (313) are connected; all the fourth P-type heavily doped regions (314) are connected.
[0024] The present invention provides two design schemes for improving the performance of BLVSCR devices to enable them to pass large currents, and at the same time optimizing the layout to ensure the turn-on speed and conduction uniformity of the devices. The devices in the two schemes have the characteristics of high robustness, high turn-on speed, and high conduction uniformity, and can be applied to various low-voltage integrated circuit ESD protections. Compared with traditional BLVSCR devices that increase the current-carrying capacity by increasing the size, the devices have more trigger channels and discharge channels, which can ensure a higher turn-on speed and better uniformity. The second invention scheme not only has a high turn-on speed and uniformity, but also has a more compact layout. When a positive voltage reaches the T1 port, the array cells of the device are almost turned on simultaneously, and at the same time, current can flow in the SCR of any cell, making the conduction efficiency of the device high without affecting the turn-on speed. At the same time, due to the reduction of the size of each cell, the turn-on uniformity is optimized. Therefore, the present invention well realizes the characteristics of high robustness, high turn-on speed, and high conduction uniformity, and can be applied to various low-voltage integrated circuit ESD protections. Brief Description of the Drawings Figure 1 It is a structural diagram of a traditional BLVSCR device and also a structural diagram of a device cell described in Embodiment 1; Figure 2 It is an equivalent circuit diagram of a traditional BLVSCR device, a cell of Embodiment 1, and a cell of Embodiment 2; Figure 3 It is an array diagram of the device structure described in Embodiment 1; Figure 4 It is a cell diagram of the device structure described in Embodiment 2; Figure 5 It is an array diagram of the device structure described in Embodiment 2.
Claims
1. A layout optimization of a bidirectional low-voltage silicon controlled rectifier (BLVSCR) that allows it to pass a large current and ensures the device's turn-on speed and conduction uniformity. The device is a 4*4 array, and its repeating unit is characterized by: The unit comprises a P-type silicon substrate (101), on which a first N-type doping region A (201) and a first N-type doping region B (202) are formed; a second N-type doping region A (211) is formed on the right side of the first N-type doping region A (201); a second N-type doping region B (212) is formed on the left side of the first N-type doping region B (202); a first P-type doping region A (221) is formed on the second N-type doping region A (211); and a first P-type doping region B (222) is formed on the second N-type doping region B (212); A first P-type heavily doped region (301) and a first N-type heavily doped region (311) are sequentially formed on the left side of the first N-type doping region A (201); a second P-type heavily doped region (302) and a second N-type heavily doped region (312) are formed on the first P-type doping region A (221); a third P-type heavily doped region (303) and a third N-type heavily doped region (313) are formed on the right side of the first N-type doping region B (202); and a fourth N-type heavily doped region (314) and a fourth P-type heavily doped region (304) are formed on the first P-type doping region B (222); The first P-type heavily doped region (301) is connected to the fourth N-type heavily doped region (314); the first N-type heavily doped region (311) is connected to the fourth P-type heavily doped region (304); the second P-type heavily doped region (302) is connected to the third N-type heavily doped region (313); the second N-type heavily doped region (312) is connected to the third P-type heavily doped region (303); Shallow trench isolation is respectively provided between the first P-type heavily doped region (301) and the first N-type heavily doped region (311), between the first N-type heavily doped region (311) and the second P-type heavily doped region (302), between the second P-type heavily doped region (302) and the second N-type heavily doped region (312), between the third P-type heavily doped region (303) and the third N-type heavily doped region (313), between the third N-type heavily doped region (313) and the fourth P-type heavily doped region (304), and between the fourth P-type heavily doped region (304) and the fourth N-type heavily doped region (314).
2. The units are arranged in a 4*4 array to form a device.
3. In the device array, in the four units in the same column, the connected first P-type heavily doped region (301) is connected to the fourth N-type heavily doped region (314); the connected first N-type heavily doped region (311) is connected to the fourth P-type heavily doped region (304); the connected second P-type heavily doped region (302) is connected to the third N-type heavily doped region (313); the connected second N-type heavily doped region (312) is connected to the third P-type heavily doped region (303); In the device array, the first P-type heavily doped regions (301) in the four units in the same row are connected and defined as the T1 port; the first N-type heavily doped regions (311) are connected; the second P-type heavily doped regions (302) are connected; the second N-type heavily doped regions (312) are connected and defined as the T2 port; the fourth N-type heavily doped regions (314) are connected and defined as the T1 port; the fourth P-type heavily doped regions (304) are connected; the third N-type heavily doped regions (313) are connected; and the third P-type heavily doped regions (303) are connected and defined as the T2 port.
4. A layout optimization for a bidirectional low-voltage silicon controlled rectifier (BLVSCR), wherein the device has a more compact layout structure while being able to pass a large current and ensure the device turn-on speed and conduction uniformity. The device is a 4*4 array, and its repeating unit is characterized by: The unit comprises a P-type silicon substrate (101), on which a first N-type doping region A (201) and a first N-type doping region B (202) are formed; a second N-type doping region A (211) is formed on the first N-type doping region A (201); a second N-type doping region B (212) is formed on the first N-type doping region B (202); a first P-type doping region A (221) is formed on the right side of the second N-type doping region A (211); and a first P-type doping region B (222) is formed on the left side of the second N-type doping region B (212); The left side of the second N-type doping region A (211) forms, from top to bottom, a third N-type heavily doped region (311), a first P-type heavily doped region (301), and a fourth N-type heavily doped region (312); the first P-type doping region A (221) forms, from top to bottom, a third P-type heavily doped region (313), a first N-type heavily doped region (302), and a fourth P-type heavily doped region (314); the right side of the second N-type doping region B (212) forms, from top to bottom, a fifth P-type heavily doped region (315), a second N-type heavily doped region (304), and a sixth P-type heavily doped region (316); the first P-type doping region B (222) forms, from top to bottom, a fifth N-type heavily doped region (317), a second P-type heavily doped region (303), and a sixth N-type heavily doped region (318).
5. The first P-type heavily doped region (301) is connected to the second N-type heavily doped region (304); the fourth N-type heavily doped region (312) is connected to the fifth P-type heavily doped region (315); the fourth P-type heavily doped region (314) is connected to the fifth N-type heavily doped region (317); and the first N-type heavily doped region (302) is connected to the second P-type heavily doped region (303).
6. Between the third N-type heavily doped region (311) and the first P-type heavily doped region (301), between the first P-type heavily doped region (301) and the fourth N-type heavily doped region (312), between the third P-type heavily doped region (313) and the first N-type heavily doped region (302), between the first N-type heavily doped region (302) and the fourth P-type heavily doped region (314), between the third N-type heavily doped region (311) and the third P-type heavily doped region (313), between the first P-type heavily doped region (301) and the first N-type heavily doped region (302), between the fourth N-type heavily doped region (312) and the fourth P-type heavily doped region (314), and between the fifth P-type heavily doped region (313). Shallow trench isolation is respectively provided between the N-type heavily doped region (315) and the second N-type heavily doped region (304), between the second N-type heavily doped region (304) and the sixth P-type heavily doped region (316), between the fifth N-type heavily doped region (317) and the second P-type heavily doped region (303), between the second P-type heavily doped region (303) and the sixth N-type heavily doped region (318), between the fifth P-type heavily doped region (315) and the fifth N-type heavily doped region (317), between the second N-type heavily doped region (304) and the second P-type heavily doped region (303), and between the sixth P-type heavily doped region (316) and the sixth N-type heavily doped region (318).
7. The units are arranged in a 4*4 array to form a device.
8. In the device array, all the first P-type heavily doped regions (301) and the second N-type heavily doped regions (304) in the same column of four units are connected; the first N-type heavily doped regions (302) and the second P-type heavily doped regions (303) are connected; the third N-type heavily doped regions (311), the fourth N-type heavily doped regions (312), the fifth P-type heavily doped regions (315), and the sixth P-type heavily doped regions (316) are connected; the third P-type heavily doped regions (313), the fourth P-type heavily doped regions (314), the fifth N-type heavily doped regions (317), and the sixth N-type heavily doped regions (318) are connected.
9. In the device array, all the first P-type heavily doped regions (301) in the four units in the same row are connected, defined as T1 port; all the first N-type heavily doped regions (302) are connected, defined as T2 port; all the third N-type heavily doped regions (311) are connected; all the fourth N-type heavily doped regions (312) are connected; all the third P-type heavily doped regions (313) are connected; and all the fourth P-type heavily doped regions (314) are connected.