Preparation method of solar cell and solar cell

Abstract

The invention relates to the technical field of photovoltaic cells, and provides a preparation method of a solar cell and the solar cell. The preparation method of the solar cell comprises the steps that a silicon substrate is provided, the silicon substrate is provided with a first surface, and the first surface comprises a plurality of first areas arranged at intervals and second areas located between every two adjacent first areas; forming a silica dielectric layer on the second region; a tunneling oxide layer and a doped polycrystalline silicon layer are sequentially formed on the first surface, the tunneling oxide layer covers the first area and the silica dielectric layer, and the doped polycrystalline silicon layer covers the tunneling oxide layer; and patterning the doped polycrystalline silicon layer and the tunneling oxide layer to selectively remove the doped polycrystalline silicon layer and the tunneling oxide layer on the second region. According to the invention, the problem that the passivation effect of a high-efficiency battery adopting a local contact technology is poor is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic cells, and in particular, to a method for preparing a solar cell and a solar cell. Background Art

[0002] Currently, the solar cell industry has generally paid attention to and developed next-generation battery technologies. Among them, N-type silicon substrate batteries characterized by passivated contact technology have attracted people's attention. In order to commercialize the batteries with passivated contact technology, a large amount of research has been carried out on the preparation technology of the passivated contact structure. The core of the passivated contact structure is to introduce an ultrathin tunneling oxide (SiO2) layer and a doped polysilicon (Poly-Si) layer on the back of the battery.

[0003] The non-metal contact area of a solar cell usually does not cover polysilicon, that is, the solar cell has local contacts or finger contacts. A solar cell with local contacts forms metal-polysilicon contacts only in a local area (finger pattern) of the entire back surface, and the remaining areas are passivated.

[0004] However, currently, the high-efficiency batteries using the above local contact technology have the problem of poor passivation effect. Summary of the Invention

[0005] The main object of the present invention is to provide a method for preparing a solar cell and a solar cell, so as to solve the problem of poor passivation effect of high-efficiency batteries using local contact technology in the prior art.

[0006] To achieve the above object, according to one aspect of the present invention, a method for preparing a solar cell is provided. The method for preparing a solar cell includes: providing a silicon substrate, the silicon substrate having a first surface, the first surface including a plurality of first regions arranged at intervals and a second region located between two adjacent first regions; forming a silicon oxide dielectric layer on the second region; sequentially forming a tunneling oxide layer and a doped polysilicon layer on the first surface, the tunneling oxide layer covering the first regions and the silicon oxide dielectric layer, and the doped polysilicon layer covering the tunneling oxide layer; patterning the doped polysilicon layer and the tunneling oxide layer to selectively remove the doped polysilicon layer and the tunneling oxide layer on the second region.

[0007] Optionally, after patterning the doped polysilicon layer and the tunneling oxide layer, the method for preparing a solar cell further includes: removing the silicon oxide dielectric layer by wet etching to expose the second region; forming a back surface passivation layer on the second region.

[0008] Optionally, the step of forming a silicon oxide dielectric layer on the second region includes: performing a first laser treatment on the second region to cause the silicon in the second region of the silicon substrate to react with air and form a silicon oxide dielectric layer.

[0009] Optionally, the laser power of the first laser treatment is 5 - 20 W.

[0010] Optionally, the linear velocity of the first laser treatment is 67000 - 73000 mm / s.

[0011] Optionally, the steps of sequentially forming a tunneling oxide layer and a doped polysilicon layer on the first surface include: forming a tunneling oxide layer on the first surface so that the tunneling oxide layer covers the first region and the silicon oxide dielectric layer; forming an intrinsic amorphous silicon layer on the side of the tunneling oxide layer facing away from the silicon substrate; performing a diffusion treatment on the intrinsic amorphous silicon layer to convert the intrinsic amorphous silicon layer into a doped polysilicon layer, and forming a doped silicon glass on the side of the doped polysilicon layer facing away from the tunneling oxide layer.

[0012] Optionally, the steps of patterning the doped polysilicon layer and the tunneling oxide layer include: performing a second laser treatment on the portion of the doped silicon glass located on the second region to remove the portion of the doped silicon glass located on the second region; using wet etching to remove the portion of the doped polysilicon layer located on the second region and the portion of the tunneling oxide layer located on the second region.

[0013] Optionally, the thickness of the silicon oxide dielectric layer is 8 - 10 nm.

[0014] Optionally, before forming the silicon oxide dielectric layer on the second region, the method for manufacturing a solar cell further includes: polishing the first surface.

[0015] According to another aspect of the present invention, there is provided a solar cell, which is formed by using the manufacturing method of any one of the above - mentioned solar cells.

[0016] Applying the technical solution of the present invention, a preparation method of a solar cell is provided. The preparation method of the solar cell includes: providing a silicon substrate, the silicon substrate having a first surface, the first surface including a plurality of first regions arranged at intervals and a second region located between two adjacent first regions; forming a silicon oxide dielectric layer on the second region; sequentially forming a tunneling oxide layer and a doped polysilicon layer on the first surface, the tunneling oxide layer covering the first region and the silicon oxide dielectric layer, and the doped polysilicon layer covering the tunneling oxide layer; patterning the doped polysilicon layer and the tunneling oxide layer to selectively remove the doped polysilicon layer and the tunneling oxide layer on the second region. The beneficial effects brought by this application are as follows: After selectively removing the doped polysilicon layer and the tunneling oxide layer on the second region, the remaining tunneling oxide layer and doped polysilicon layer on the first region together constitute a passivation contact structure. The synergistic effect of the tunneling barrier layer and the doped polysilicon significantly improves the surface passivation effect of the silicon substrate. Among them, the tunneling oxide layer enhances the charge transport characteristics on the surface of the silicon substrate by reducing non-radiative recombination, improves the surface passivation effect of the silicon substrate, and effectively improves the surface loading rate; the doped polysilicon layer provides an excellent charge transport channel, promoting the smooth flow of carriers. It should be noted that before forming the above-mentioned tunneling oxide layer and doped polysilicon layer, a silicon oxide dielectric layer is first formed on the second region, so that the silicon oxide dielectric layer is located between the silicon substrate and the tunneling oxide layer in the thickness direction of the silicon substrate. Thus, the above-mentioned silicon oxide dielectric layer effectively acts as a mask during the subsequent patterning process of the doped polysilicon layer and the tunneling oxide layer, effectively isolating the influence of the patterning of the doped polysilicon layer and the tunneling oxide layer on the silicon substrate, strengthening the anti-damage ability of the second region of the silicon substrate, maintaining the surface integrity and quality of the second region, and further reducing the non-radiative recombination on the surface of the silicon substrate and improving the passivation effect. In summary, through this application, the problem of poor passivation effect of high-efficiency cells using local contact technology in the prior art is solved. Description of the Drawings

[0017] The specification drawings forming a part of this application are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0018] Figure 1 A flowchart showing a preparation method of a solar cell according to an embodiment of the present invention is shown;

[0019] Figure 2 A structural diagram showing the formation of a silicon oxide dielectric layer by performing a first laser treatment on a second region in a preparation method of a solar cell according to an embodiment of the present invention is shown;

[0020] Figure 3 Shown in Figure 2Based on the shown structure, a schematic diagram of the structure of the tunneling oxide layer, doped polysilicon layer, and doped silicon glass layer is formed;

[0021] Figure 4 It shows that on the basis of Figure 3 the shown structure, a schematic diagram of the structure after the second laser treatment of the doped silicon glass layer;

[0022] Figure 5 It shows that on the basis of Figure 4 the shown structure, a schematic diagram of the solar cell formed after patterning the doped polysilicon layer and the tunneling oxide layer;

[0023] Figure 6 It shows that on the basis of Figure 5 the shown structure, a schematic diagram of the structure after removing the silicon oxide dielectric layer;

[0024] Figure 7 It shows a schematic diagram of the structure of a TOPCon cell according to an embodiment of the present invention;

[0025] Figure 8 It shows a schematic diagram of the structure of a BC cell according to an embodiment of the present invention.

[0026] Among them, the above-mentioned drawings include the following reference numerals:

[0027] 10, silicon substrate; 101, first region; 102, second region; 200, first laser; 20, silicon oxide dielectric layer; 30, tunneling oxide layer; 40, doped polysilicon layer; 500, second laser; 50, doped silicon glass; 60, passivated contact structure.

[0028] 110, first silicon substrate; 111, emitter; 112, first tunneling oxide layer; 113, first doped polysilicon layer; 114, first passivated contact structure; 115, first front passivation layer; 116, first back passivation layer; 117, first front metal electrode; 118, first back metal electrode.

[0029] 120, second silicon substrate; 121, second front passivation layer; 122, second tunneling oxide layer; 123, second doped polysilicon layer; 124, second passivated contact structure; 125, third tunneling oxide layer; 126, third doped polysilicon layer; 127, third passivated contact structure; 128, second back passivation layer; 129, second back metal electrode; 130, third back metal electrode. Detailed implementation manners

[0030] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the drawings and in combination with the embodiments.

[0031] It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs.

[0032] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly dictates otherwise, the singular forms are also intended to include the plural forms. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they specify the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0033] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so as to implement the embodiments of the present invention described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0034] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element can be directly on the other element or there can also be an intermediate element. Moreover, in the description and claims, when an element is described as "connected" to another element, the element can be "directly connected" to the other element or "connected" to the other element through a third element.

[0035] The present application will be further described in detail below in conjunction with specific embodiments, and these embodiments should not be construed as limiting the scope claimed by the present application.

[0036] As introduced in the background art, the passivation effect of high-efficiency batteries using local contact technology in the prior art is poor.

[0037] In the current field of photovoltaic cell manufacturing, especially for high-efficiency cells using local contact technology, the preparation process of traditional solar cells can cause damage to the silicon substrate. Therefore, in order to solve the problem of poor passivation effect of high-efficiency cells using local contact technology, the present application proposes a method for preparing a solar cell, the method for preparing a solar cell comprising: providing a silicon substrate having a first surface, the first surface including a plurality of first regions arranged at intervals and a second region located between two adjacent first regions; forming a silicon oxide dielectric layer on the second region; sequentially forming a tunneling oxide layer and a doped polysilicon layer on the first surface, the tunneling oxide layer covering the first regions and the silicon oxide dielectric layer, and the doped polysilicon layer covering the tunneling oxide layer; patterning the doped polysilicon layer and the tunneling oxide layer to selectively remove the doped polysilicon layer and the tunneling oxide layer on the second region.

[0038] Wherein, after selectively removing the doped polysilicon layer and the tunneling oxide layer on the second region, the remaining tunneling oxide layer and doped polysilicon layer on the first region together constitute a passivated contact structure, and the synergistic effect of the tunneling barrier layer and the doped polysilicon significantly improves the surface passivation effect of the silicon substrate. Further, the tunneling oxide layer enhances the charge transport characteristics on the surface of the silicon substrate by reducing non-radiative recombination, improves the surface passivation effect of the silicon substrate, and effectively improves the surface loading rate; the doped polysilicon layer provides an excellent charge transport channel, facilitating the smooth flow of carriers. It should be noted that before forming the above-mentioned tunneling oxide layer and doped polysilicon layer, the present application first forms a silicon oxide dielectric layer on the second region, so that the silicon oxide dielectric layer is located between the silicon substrate and the tunneling oxide layer in the thickness direction of the silicon substrate. Thus, the silicon oxide dielectric layer effectively acts as a mask during the subsequent patterning process of the doped polysilicon layer and the tunneling oxide layer, effectively isolating the influence of the patterning of the doped polysilicon layer and the tunneling oxide layer on the silicon substrate, strengthening the anti-damage ability of the second region of the silicon substrate, maintaining the surface integrity and quality of the second region, and further reducing non-radiative recombination on the surface of the silicon substrate and improving the passivation effect. In summary, through the present application, the problem of poor passivation effect of high-efficiency cells using local contact technology in the prior art is solved.

[0039] Exemplary embodiments of a method for preparing a solar cell according to the present application will be described in more detail below. However, these exemplary embodiments can be implemented in many different forms and should not be construed as being limited only to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of the present application is thorough and complete, and the concept of these exemplary embodiments is fully conveyed to those of ordinary skill in the art.

[0040] Figure 1 It is a flowchart of a method for preparing a solar cell provided by an embodiment of the present application. Figures 2 to 6Schematic diagram of a preparation process for a solar cell provided by an embodiment of the present application. As Figure 1 shown, a preparation method for a solar cell provided by the present application includes:

[0041] Step S1: Provide a silicon substrate 10. The silicon substrate 10 has a first surface, and the first surface includes a plurality of first regions 101 arranged at intervals and a second region 102 located between two adjacent first regions 101. As Figures 2 to 6 shown;

[0042] The silicon substrate 10 can include an N-type silicon substrate or a P-type silicon substrate according to the doping type, and can include, but is not limited to, a single-crystalline silicon substrate or a polycrystalline silicon substrate according to the crystal structure. Therefore, the above-mentioned silicon substrate 10 can include, but is not limited to, any one of an N-type single-crystalline silicon substrate, an N-type polycrystalline silicon substrate, a P-type single-crystalline silicon substrate, and a P-type polycrystalline silicon substrate.

[0043] Specifically, when the silicon substrate 10 is an N-type silicon substrate, the doping element in the N-type silicon substrate can be one or more of phosphorus, arsenic, and antimony; when the silicon substrate 10 is a P-type silicon substrate, the doping element in the P-type silicon substrate can be one or more of boron, gallium, aluminum, and indium.

[0044] The first surface can be a specific surface of the silicon substrate 10. For a photovoltaic cell, the above-mentioned first surface can be the front or back surface for receiving sunlight.

[0045] The first surface can include a plurality of first regions 101 and one second region 102, and the second region 102 is located between two adjacent first regions 101; or, the first surface can include a plurality of first regions 101 and a plurality of second regions 102, and there is one second region 102 between two adjacent first regions 101.

[0046] It should be noted here that the first region 101 and the second region 102 are obtained by artificially dividing the first surface. In some embodiments, the above-mentioned first region 101 can also be named a contact region, and the second region 102 can also be named a non-contact region.

[0047] Step S2: Form a silicon oxide dielectric layer 20 on the second region 102. As Figure 2 shown;

[0048] The formation of the above-mentioned silicon oxide dielectric layer 20 (SiO x ) only occurs on the second region 102, rather than covering the entire surface of the silicon substrate 10.

[0049] Optionally, the formation of the silicon oxide dielectric layer 20 can include, but is not limited to, being achieved by laser local oxidation or deposition processes. It can be understood that the localization in laser local oxidation refers to a specified region, that is, the second region 102.

[0050] When the silicon oxide dielectric layer 20 is formed by laser local oxidation, the silicon oxide dielectric layer 20 can be formed on the second region 102 by laser irradiating the second region 102; when the silicon oxide dielectric layer 20 is formed by a deposition process, a mask that covers the first region 101 and exposes the second region 102 can be provided on the first surface, so that the silicon oxide dielectric layer 20 can be formed on the second region 102.

[0051] Step S3, a tunneling oxide layer 30 and a doped polysilicon layer 40 are sequentially formed on the first surface. The tunneling oxide layer 30 covers the first region 101 and the silicon oxide dielectric layer 20, and the doped polysilicon layer 40 covers the tunneling oxide layer 30, as Figure 3 and Figure 4 shown;

[0052] The tunneling oxide layer 30 is an ultra-thin oxide layer, and its thickness in the direction perpendicular to the first surface can be 0.5 - 2 nm.

[0053] The doped polysilicon layer 40 can be deposited by low-pressure chemical vapor deposition (LPCVD). Optionally, the thickness of the doped polysilicon layer 40 in the direction perpendicular to the first surface is 70 - 150 nm.

[0054] The above-mentioned tunneling oxide layer 30 can be formed on the first surface of the silicon substrate 10 by thermal oxidation or chemical oxidation. As an insulating but penetrable barrier, it allows carriers (electrons or holes) to tunnel between the polysilicon and the silicon substrate 10, while preventing the direct flow of current, and can effectively isolate the defects on the surface of the silicon substrate 10, thereby optimizing the surface recombination situation of the silicon substrate 10. It should be noted here that since the silicon oxide dielectric layer 20 is pre-formed on the second region 102, the tunneling oxide layer 30 formed on the first surface covers not only the multiple first regions 101 on the first surface but also the silicon oxide dielectric layer 20, so that the above-mentioned silicon oxide dielectric layer 20 serves as a protective layer between the silicon substrate 10 and the tunneling oxide layer 30.

[0055] The doped polysilicon layer 40 is formed on the tunneling oxide layer 30. As the name implies, specific impurities (such as boron or phosphorus) are doped into the doped polysilicon layer 40. Exemplarily, when the doped impurity is boron, it is P-type doping; when the doped impurity is phosphorus, it is N-type doping. Therefore, the above-mentioned doped polysilicon layer 40 can be divided into an N-type doped polysilicon layer and a P-type doped polysilicon layer according to the doping type. Optionally, the doping concentration of the doped impurity (such as boron or phosphorus) in the doped polysilicon layer 40 is e19 - e21 cm -3 .

[0056] In some alternative embodiments, for a TOPCon cell, when the silicon substrate 10 is an N-type silicon substrate as described above, the doped polysilicon layer 40 formed on the N-type silicon substrate 10 is an N-type doped polysilicon layer; when the silicon substrate 10 is a P-type silicon substrate, the doped polysilicon layer 40 formed on the P-type silicon substrate 10 is a P-type doped polysilicon layer.

[0057] Step S4: Pattern the doped polysilicon layer 40 and the tunneling oxide layer 30 to selectively remove the doped polysilicon layer 40 and the tunneling oxide layer 30 on the second region 102, as Figure 5 .

[0058] It can be understood that, as Figure 5 shown, the above patterning can remove the part of the doped polysilicon layer 40 located on the second region 102 and the part of the tunneling oxide layer 30 located on the second region 102, and the remaining tunneling oxide layer 30 and doped polysilicon layer 40 located on the first region 101 form a passivation contact structure 60.

[0059] In some embodiments, the process of patterning the doped polysilicon layer 40 and the tunneling oxide layer 30 can be achieved by wet etching, and the chemical solution used in this wet etching is an alkaline chemical solution. Optionally, before performing the wet etching, a patterning mask can be formed on the side of the doped polysilicon layer 40 away from the tunneling oxide layer 30 through photolithography or laser technology, so that the wet etching only acts on the area to be removed through the chemical solution (etching solution).

[0060] It should be emphasized here that the silicon oxide dielectric layer 20 has high chemical stability to the alkaline chemical solution. Therefore, in the step of patterning the doped polysilicon layer 40 and the tunneling oxide layer 30 using the alkaline chemical solution, the silicon oxide dielectric layer 20 can be used as a mask material to protect the silicon substrate 10 under the doped silicon oxide dielectric layer 20.

[0061] This also means that after the above step S4, the silicon oxide dielectric layer 20 formed in step S2 remains on the second region 102, as Figure 5 shown. In some alternative embodiments, after patterning the doped polysilicon layer 40 and the tunneling oxide layer 30, the method for manufacturing a solar cell further includes: removing the silicon oxide dielectric layer 20 by wet etching to expose the second region 102, as Figure 6 shown; forming a back passivation layer on the second region 102.

[0062] Among them, the material of the back passivation layer can be selected from any one or more of aluminum oxide, titanium dioxide, silicon nitride, and silicon oxynitride.

[0063] In the above-described embodiments, due to the low cost of wet etching, the allowability of batch processing, and the high selectivity of the chemical solution for wet etching to the silicon oxide dielectric layer 20, wet etching can be used to etch the silicon oxide dielectric layer 20 at low cost and efficiently without affecting the silicon substrate 10 below the silicon oxide dielectric layer 20. Further, by forming a back passivation layer on the second region 102, the material of the back passivation layer can be in direct contact with the surface of the silicon substrate 10. On this basis, based on the material characteristics of the back passivation layer, the material of the back passivation layer can passivate the dangling bonds on the surface of the silicon substrate 10, effectively improving the carrier lifetime, and thus further improving the passivation effect on the surface of the silicon substrate 10.

[0064] In addition, it should be noted that the silicon oxide dielectric layer 20 is more easily etched away in an acidic environment. Therefore, in the step of removing the silicon oxide dielectric layer 20 by wet etching, the chemical solution used for the wet etching can be an acidic chemical solution. In addition, since silicon exhibits high chemical stability in an acidic environment, the surface integrity of the second region 102 can be maintained while removing the silicon oxide dielectric layer 20.

[0065] In some alternative embodiments, as Figure 2 shown, the step of forming the silicon oxide dielectric layer 20 on the second region 102 includes: performing a first laser treatment on the second region 102 to cause the silicon in the silicon substrate 10 located in the second region 102 to react with air and form the silicon oxide dielectric layer 20.

[0066] It can be understood that the laser has a high energy density and good focusing ability. When the laser beam is focused on a specific region and reaches a specific power, the above-mentioned specific region can be locally heated to initiate a chemical reaction. Thus, during the first laser treatment of the second region 102, when the second region 102 of the silicon substrate 10 is heated by the laser emitted by the first laser 200, the high temperature causes the silicon to chemically react with the oxygen in the air, and thus the silicon oxide dielectric layer 20 is generated. Exemplarily, the above-mentioned silicon oxide dielectric layer 20 is silicon dioxide.

[0067] In addition, in order to keep the surface integrity of the silicon substrate 10 during the first laser treatment, the energy density of the laser during the first laser treatment can be lower than the ablation threshold of the silicon substrate 10. The ablation threshold refers to the minimum laser energy density required to initiate material removal per unit area.

[0068] In the above-described embodiments, when performing the first laser treatment on the second region 102, the first laser treatment can more directly and precisely focus on the second region 102, so that on the basis of causing the silicon in the silicon substrate 10 located in the second region 102 to react with air and form the silicon oxide dielectric layer 20, the process flow for realizing local oxidation can be simplified.

[0069] Exemplarily, the type of laser in the first laser treatment process may be 355 nm ultraviolet picosecond laser.

[0070] The laser power and the linear velocity are key parameters directly affecting the energy density applied to the silicon substrate 10. Thus, when the energy density of the laser in the first laser treatment process is greater than the ablation threshold of the silicon substrate 10, in order to further reasonably control the energy density of the laser in the first laser treatment process, it can also be achieved by reasonably controlling the laser power and the linear velocity of the first laser treatment.

[0071] Among them, the laser power is a measure of the energy released by the laser beam per unit time. Further, an appropriate laser power can accelerate the oxidation reaction and increase the thickness of the silicon oxide dielectric layer 20 formed per unit time. Therefore, in order to help the silicon oxide dielectric layer 20 reach an ideal film thickness as a mask material in a short time and improve the efficiency and output of the production line, in some embodiments, the laser power of the first laser treatment may be greater than or equal to 5 W; and, an appropriate laser power can also directly affect the quality of subsequent processes. Thus, in order to enhance the process controllability of the growing silicon oxide dielectric layer 20 on the basis of accelerating its growth, so that the silicon oxide dielectric layer 20 can effectively serve as a mask material and further ensure the surface integrity of the silicon substrate 10, the laser power of the first laser treatment may be less than or equal to 20 W. In summary, the laser power of the above-mentioned first laser treatment may be 5 - 20 W.

[0072] In addition, the linear velocity is the speed at which the laser beam moves relative to the silicon substrate 10. In some embodiments, the linear velocity of the first laser treatment may be greater than or equal to 67000 mm / s. It can be understood that the linear velocity of the first laser treatment is relatively high in this range, thus further ensuring that the energy density of the laser in the first laser treatment process can be lower than the ablation threshold of the silicon substrate 10 to ensure the surface integrity of the silicon substrate 10; while a linear velocity less than 73000 mm / s can enhance the growth controllability of the silicon oxide dielectric layer 20, making the formed silicon oxide dielectric layer 20 thick and uniform enough, so that the silicon oxide dielectric layer 20 can effectively serve as a mask material and further ensure the surface integrity of the silicon substrate 10. In summary, the linear velocity of the first laser treatment may be 67000 - 73000 mm / s. In some embodiments, the linear velocity of the first laser treatment may be 700000 mm / s.

[0073] In some alternative embodiments, such as Figures 2 to 5As shown, the thickness of the silicon oxide dielectric layer 20 is 8 - 10 nm. In the above-described embodiments, the silicon oxide dielectric layer 20 with a thickness greater than or equal to 8 nm can effectively block the alkaline chemical solution during the patterning of the doped polysilicon layer 40 and the tunneling oxide layer 30, and the silicon oxide dielectric layer 20 with a thickness less than or equal to 10 nm can be more easily removed in the subsequent removal process (using wet etching to remove the silicon oxide dielectric layer 20 to expose the second region 102). In some embodiments, the thickness of the silicon oxide dielectric layer can be 9 nm.

[0074] In some alternative embodiments, as Figure 3 shown, the steps of sequentially forming the tunneling oxide layer 30 and the doped polysilicon layer 40 on the first surface include: forming the tunneling oxide layer 30 on the first surface so that the tunneling oxide layer 30 covers the first region 101 and the silicon oxide dielectric layer 20; forming an intrinsic amorphous silicon layer (not shown in the figure) on the side of the tunneling oxide layer 30 facing away from the silicon substrate 10; performing a diffusion treatment on the intrinsic amorphous silicon layer to convert the intrinsic amorphous silicon layer into the doped polysilicon layer 40, and forming a doped silicon glass 50 on the side of the doped polysilicon layer 40 facing away from the tunneling oxide layer 30.

[0075] In the above-described embodiments, since the tunneling oxide layer 30 has been formed on the silicon substrate 10 before the formation of the intrinsic amorphous silicon layer, on the one hand, the tunneling oxide layer 30 is beneficial to preventing the doped atoms from diffusing into the silicon substrate 10; on the other hand, the tunneling oxide layer 30 is beneficial to reducing the recombination of electrons and holes, improving the surface passivation effect of the silicon substrate 10. Further, during the diffusion treatment of the intrinsic amorphous silicon layer, the doped atoms obtain energy and can combine with the amorphous silicon atoms inside the intrinsic amorphous silicon layer to convert the intrinsic amorphous silicon layer into the doped polysilicon layer 40. Moreover, the oxide containing the doped atoms generated during the diffusion process can also react with silicon atoms to form the doped silicon glass 50, and the doped silicon glass 50 can serve as a mask for the patterned doped polysilicon layer 40 and the tunneling oxide layer 30, capable of protecting the part of the doped polysilicon layer 40 located on the first region 101 and the part of the tunneling oxide layer 30 located on the first region 101 from damage, thereby reducing the surface recombination of the doped polysilicon layer 40 and enhancing the passivation effect of the doped polysilicon layer 40 on the silicon substrate 10.

[0076] Exemplarily, when the above-described doped atoms are phosphorus atoms, the above-described oxide containing the doped atoms can be phosphorus pentoxide (P2O5), and the above-described doped silicon glass 50 can be phosphosilicate glass (PSG); when the above-described doped atoms are boron atoms, the above-described oxide containing the doped atoms can be boron oxide, and the above-described doped silicon glass 50 can be borosilicate glass (BSG).

[0077] In some alternative embodiments, as Figure 4 and Figure 5As shown, when a doped silicon glass 50 is formed on a side of the doped polysilicon layer 40 facing away from the tunneling oxide layer 30, in order to remove the portion of the doped polysilicon layer 40 located on the second region 102 and the portion of the tunneling oxide layer 30 located on the second region 102, the doped silicon glass 50 can be first patterned so that the doped silicon glass 50 serves as a mask for patterning the doped polysilicon layer 40 and the tunneling oxide layer 30. Further, the step of patterning the doped polysilicon layer 40 and the tunneling oxide layer 30 may include: performing a second laser treatment on the portion of the doped silicon glass 50 located on the second region 102 to remove the portion of the doped silicon glass 50 located on the second region 102; using wet etching to remove the portion of the doped polysilicon layer 40 located on the second region 102 and the portion of the tunneling oxide layer 30 located on the second region 102. It can be understood that after removing the portion of the doped polysilicon layer 40 located on the second region 102 and the portion of the tunneling oxide layer 30 located on the second region 102, the remaining portion of the doped polysilicon layer 40 located on the first region 101 and the portion of the tunneling oxide layer 30 located on the first region 101 can be a passivation contact structure 60. It can be understood that the laser in the second laser treatment process can be emitted by a second laser 500, and the second laser 500 and the first laser 200 can be the same or different. By using the second laser treatment to pattern the doped silicon glass 50, it can be compatible with the first laser treatment for forming the silicon oxide dielectric layer 20 in the above process, thereby simplifying the process flow, reducing the equipment cost, and also providing process flexibility.

[0078] In some alternative embodiments, the laser power of the second laser treatment is 70 - 90 W.

[0079] In the above embodiments, in order to ensure that the portion of the doped silicon glass 50 located on the second region 102 is completely removed and to increase the removal speed, the laser power of the second laser treatment can be set to be greater than or equal to 70 W; further, by setting the laser power of the second laser treatment to be less than or equal to 90 W, it can contribute to the integrity of the portion of the doped silicon glass 50 other than the portion located on the second region 102.

[0080] Exemplarily, the laser type in the second laser treatment process can be green femtosecond.

[0081] In some alternative embodiments, before forming the silicon oxide dielectric layer 20 on the second region 102, the method for manufacturing a solar cell further includes: performing a polishing treatment on the first surface.

[0082] In the above embodiments, the polishing treatment can significantly reduce the dangling bonds on the surface of the silicon substrate 10, thereby helping to reduce surface recombination. On this basis, after the step of removing the silicon oxide dielectric layer 20, the tight contact between the back surface passivation layer formed on the second region 102 in the first surface and the polished surface can more effectively passivate these dangling bonds, form a high-quality interface, thereby further reducing the surface recombination rate, and thus effectively improving the surface passivation effect of the silicon substrate 10.

[0083] In some embodiments, when the above solar cell is a tunnel oxide passivated contact (TOPCon) cell, a method for manufacturing a TOPCon cell is provided. The manufacturing method includes:

[0084] S100. Provide a first silicon substrate, the first silicon substrate having opposite front and back surfaces, the back surface including a plurality of first regions and a second region located between two adjacent first regions;

[0085] S101. Form an emitter on the front surface of the first silicon substrate;

[0086] S102. Perform a first laser treatment on the second region of the back surface of the first silicon substrate, so that the silicon in the second region of the first silicon substrate reacts with air to form a first silicon oxide dielectric layer;

[0087] S103. Form a first tunnel oxide layer on the back surface of the first silicon substrate, so that the first tunnel oxide layer covers the first region and the first silicon oxide dielectric layer;

[0088] S104. Form a first intrinsic amorphous silicon layer on the side of the first tunnel oxide layer facing away from the first silicon substrate;

[0089] S105. Perform a diffusion treatment on the first intrinsic amorphous silicon layer to convert the first intrinsic amorphous silicon layer into a first doped polysilicon layer, and form a first doped silicon glass on the side of the first doped polysilicon layer facing away from the first tunnel oxide layer;

[0090] S106. Perform a second laser treatment on the part of the first doped silicon glass located on the second region to remove the part of the first doped silicon glass located on the second region;

[0091] S107. Use a first wet etching to remove the part of the first doped polysilicon layer located on the second region and the part of the first tunnel oxide layer located on the second region. The remaining parts of the first doped polysilicon layer and the first tunnel oxide layer located on the first region form a first passivated contact structure;

[0092] S108. Use a second wet etching to remove the first silicon oxide dielectric layer to expose the second region;

[0093] S109. Remove the part of the first doped silicon glass layer located on the first region, and form a first back passivation layer on the side of the first doped polysilicon layer facing away from the first silicon substrate, so that the first back passivation layer covers the first passivated contact structure and the second region on the back of the first silicon substrate;

[0094] S110. Form a first back metal electrode on the first region, which penetrates the first back passivation layer and is in contact with the first doped polysilicon layer;

[0095] S111. Form a first front passivation layer on the side of the emitter facing away from the first silicon substrate;

[0096] S112. Form a front metal electrode on the front of the first silicon substrate, which penetrates the first front passivation layer and is in contact with the emitter.

[0097] In some other embodiments, when the above solar cell is a back contact (BC) cell, a preparation method of the BC cell is provided. The preparation method includes:

[0098] S200. Provide a second silicon substrate, the second silicon substrate has opposite front and back sides, the back side includes a plurality of first regions, second regions located between two adjacent first regions, and spacer regions located between adjacent first regions and second regions;

[0099] S201. Form a second front passivation layer on the front of the second silicon substrate;

[0100] S202. Perform a first laser treatment on the second regions and spacer regions on the back of the second silicon substrate, so that the silicon in the second regions and spacer regions of the second silicon substrate reacts with air and forms a second silicon oxide dielectric layer;

[0101] S203. Form a second tunneling oxide layer on the back of the second silicon substrate, so that the second tunneling oxide layer covers the first regions and the second silicon oxide dielectric layer;

[0102] S204. Form a second intrinsic amorphous silicon layer on the side of the second tunneling oxide layer facing away from the second silicon substrate;

[0103] S205. Perform a diffusion treatment on the second intrinsic amorphous silicon layer to convert the second intrinsic amorphous silicon layer into a second doped polysilicon layer, and form a second doped silicon glass on the side of the second doped polysilicon layer facing away from the second tunneling oxide layer;

[0104] S206. Perform a second laser treatment on the part of the second doped silicon glass located on the second regions and spacer regions to remove the part of the second doped silicon glass located on the second regions and spacer regions;

[0105] S207. Use the first wet etching to remove the portions of the second doped polysilicon layer located on the second region and the spacer region, and the portions of the second tunneling oxide layer located on the second region and the spacer region. The remaining portions of the second doped polysilicon layer and the second tunneling oxide layer located on the first region form the second passivation contact structure;

[0106] S208. Use the second wet etching to remove the second silicon oxide dielectric layer, so that the second region and the spacer region are exposed;

[0107] S209. Perform the first laser treatment on the spacer region on the back of the second silicon substrate again, so that the silicon in the spacer region of the second silicon substrate reacts with air to form the third silicon oxide dielectric layer;

[0108] S210. Form a third tunneling oxide layer on the back of the second silicon substrate, so that the third tunneling oxide layer covers the second region, the third silicon oxide dielectric layer, and the second passivation contact structure;

[0109] S211. Form a third intrinsic amorphous silicon layer on the side of the third tunneling oxide layer facing away from the second silicon substrate;

[0110] S212. Perform a diffusion treatment on the third intrinsic amorphous silicon layer to convert the third intrinsic amorphous silicon layer into a third doped polysilicon layer, and form a third doped silicon glass on the side of the third doped polysilicon layer facing away from the third tunneling oxide layer;

[0111] S213. Perform the second laser treatment on the portions of the third doped silicon glass located on the second passivation contact structure and the spacer region to remove the portions of the third doped silicon glass located on the second passivation contact structure and the spacer region;

[0112] S214. Use the first wet etching to remove the portions of the third doped polysilicon layer located on the second passivation contact structure and the spacer region, and the portions of the third tunneling oxide layer located on the second passivation contact structure and the spacer region. The remaining portions of the third doped polysilicon layer and the third tunneling oxide layer located on the second region form the third passivation contact structure;

[0113] S215. Use the second wet etching to remove the third silicon oxide dielectric layer, so that the spacer region is exposed;

[0114] S216. Remove the portion of the second doped silicon glass layer located on the first region, and form a second back passivation layer on the sides of the second doped polysilicon layer and the third doped polysilicon layer facing away from the second silicon substrate, so that the second back passivation layer covers the second passivation contact structure, the third passivation contact structure, and the spacer region on the back of the second silicon substrate;

[0115] S217. Form a second back metal electrode on the first region, which penetrates the second back passivation layer and is in contact with the second doped polysilicon layer, and form a third back metal electrode on the second region, which penetrates the second back passivation layer and is in contact with the third doped polysilicon layer.

[0116] According to another aspect of the present application, a solar cell is provided, which is formed by using any one of the preparation methods of the solar cell.

[0117] In some embodiments, compared with the solar cells prepared in the prior art without the step of forming a silicon oxide dielectric layer on the second region, the solar cells of the present solution are improved in terms of photoelectric conversion efficiency, open circuit voltage, short circuit current, fill factor and band gap. Among them, the improvement range of the photoelectric conversion efficiency can satisfy 0 < Δeta ≤ 0.05%, the improvement range of the open circuit voltage can satisfy 0 < Δvoc ≤ 0.0004 mV, the improvement range of the short circuit current can satisfy 0 < Δisc ≤ 0.004 mA, and the improvement range of the fill factor can satisfy 0 < Δff ≤ 0.09.

[0118] Exemplarily, the above solar cell is a TOPCon cell or a back contact cell.

[0119] In some embodiments, as Figure 7 shown, when the solar cell is a TOPCon cell, the TOPCon cell may include, but is not limited to, a first silicon substrate 110, an emitter 111, a first passivated contact structure 114, a first front passivation layer 115, a first back passivation layer 116, a first front metal electrode 117 and a first back metal electrode 118. Among them, the first silicon substrate 110 has opposite front and back surfaces, the back surface includes a plurality of spaced first regions and a second region located between two adjacent first regions, the first passivated contact structure 114 includes a stacked first tunneling oxide layer 112 and a first doped polysilicon layer 113, the first passivated contact structure 114 is located on the above first region, the emitter 111 is located on the front surface of the first silicon substrate 110, the first front passivation layer 115 is located on the side of the emitter 111 away from the first silicon substrate 110, the first back passivation layer 116 includes a part covering the side of the first passivated contact structure 114 away from the first silicon substrate 110 and a part covering the second region of the back surface of the first silicon substrate 110, the first back metal electrode 118 is located on the first region and penetrates the first back passivation layer 116 to be in contact with the first doped polysilicon layer 113, and the first front metal electrode 117 is located on the front surface of the first silicon substrate 110 and penetrates the first front passivation layer 115 to be in contact with the emitter 111.

[0120] In other embodiments, as Figure 8As shown, in the case where the solar cell is a back-contact cell, the above-mentioned back-contact cell may include, but is not limited to, a second silicon substrate 120, a second passivated contact structure 124, a third passivated contact structure 127, a second front passivation layer 121, a second back passivation layer 128, a second back metal electrode 129, and a third back metal electrode 130. Among them, the second silicon substrate 120 has opposite front and back surfaces. The back surface includes a plurality of first regions arranged at intervals and a second region located between two adjacent first regions. There is a spacing region between the adjacent first region and the second region. The second passivated contact structure 124 is located on the first region, and the second passivated contact structure 124 includes a second tunneling oxide layer 122 and a second doped polysilicon layer 123 arranged in a stacked manner. The third passivated contact structure 127 is located on the second region, and the third passivated contact structure 127 includes a third tunneling oxide layer 125 and a third doped polysilicon layer 126 arranged in a stacked manner. The second front passivation layer 121 is located on the front surface of the second silicon substrate 120. The second back passivation layer 128 includes a portion covering the side of the second passivated contact structure 124 facing away from the second silicon substrate 120, a portion covering the side of the third passivated contact structure 127 facing away from the second silicon substrate 120, and the spacing region on the back surface of the second silicon substrate 120 located between the adjacent first region and the second region. The second back metal electrode 129 is located on the first region and is in contact with the second doped polysilicon layer 123 through the second back passivation layer 128. The third back metal electrode 130 is located on the second region and is in contact with the third doped polysilicon layer 126 through the second back passivation layer 128.

[0121] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0122] 1. Applying the technical solution of the present invention, a preparation method of a solar cell is provided. The preparation method of the solar cell includes: providing a silicon substrate, the silicon substrate having a first surface, the first surface including a plurality of first regions arranged at intervals and a second region located between two adjacent first regions; forming a silicon oxide dielectric layer on the second region; sequentially forming a tunneling oxide layer and a doped polysilicon layer on the first surface, the tunneling oxide layer covering the first regions and the silicon oxide dielectric layer, and the doped polysilicon layer covering the tunneling oxide layer; patterning the doped polysilicon layer and the tunneling oxide layer to selectively remove the doped polysilicon layer and the tunneling oxide layer on the second region. The beneficial effects brought by this application are as follows: After selectively removing the doped polysilicon layer and the tunneling oxide layer on the second region, the remaining tunneling oxide layer and doped polysilicon layer on the first region together constitute a passivation contact structure. The synergistic effect of the tunneling barrier layer and the doped polysilicon significantly improves the surface passivation effect of the silicon substrate. Among them, the tunneling oxide layer enhances the charge transport characteristics of the silicon substrate surface by reducing non-radiative recombination, improves the surface passivation effect of the silicon substrate, and effectively improves the surface loading rate; the doped polysilicon layer provides an excellent charge transport channel, promoting the smooth flow of carriers. It should be noted that before forming the above-mentioned tunneling oxide layer and doped polysilicon layer, a silicon oxide dielectric layer is first formed on the second region, so that the silicon oxide dielectric layer is located between the silicon substrate and the tunneling oxide layer in the thickness direction of the silicon substrate. Thus, the above-mentioned silicon oxide dielectric layer effectively acts as a mask during the subsequent patterning process of the doped polysilicon layer and the tunneling oxide layer, effectively isolating the influence of the patterning of the doped polysilicon layer and the tunneling oxide layer on the silicon substrate, strengthening the anti-damage ability of the second region of the silicon substrate, maintaining the surface integrity and quality of the second region, and further reducing the non-radiative recombination on the silicon substrate surface and improving the passivation effect. In summary, through this application, the problem of poor passivation effect of high-efficiency cells using local contact technology in the prior art is solved.

[0123] 2. Applying the technical solution of the present invention, a solar cell is provided. Since this solar cell is prepared by using the above-mentioned preparation method of the solar cell, compared with a traditional solar cell prepared without using the preparation method of the solar cell of this application, the second region of the silicon substrate of the solar cell of this application can have good surface integrity and quality, which improves the non-radiative recombination phenomenon on the silicon substrate surface of the solar cell, improves the passivation efficiency, and solves the problem of poor passivation effect of high-efficiency cells using local contact technology in the prior art.

[0124] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for preparing a solar cell, characterized in that, The preparation method of the solar cell includes: providing a silicon substrate having a first surface, the first surface including a plurality of first regions arranged at intervals and a second region located between two adjacent first regions; forming a silicon oxide dielectric layer on the second region; sequentially forming a tunneling oxide layer and a doped polysilicon layer on the first surface, the tunneling oxide layer covering the first region and the silicon oxide dielectric layer, and the doped polysilicon layer covering the tunneling oxide layer; patterning the doped polysilicon layer and the tunneling oxide layer to selectively remove the doped polysilicon layer and the tunneling oxide layer on the second region.

2. The manufacturing method of the solar cell according to claim 1, characterized in that After patterning the doped polysilicon layer and the tunneling oxide layer, the preparation method of the solar cell further includes: removing the silicon oxide dielectric layer by wet etching to expose the second region; forming a back passivation layer on the second region.

3. The manufacturing method of the solar cell according to claim 1, characterized in that, The step of forming a silicon oxide dielectric layer on the second region includes: performing a first laser treatment on the second region to cause the silicon in the silicon substrate located in the second region to react with air and form the silicon oxide dielectric layer.

4. The manufacturing method of the solar cell according to claim 3, characterized in that The laser power of the first laser treatment is 5 - 20 W.

5. The manufacturing method of the solar cell according to claim 3, wherein, The linear velocity of the first laser treatment is 67000 - 73000 mm / s.

6. The method for preparing a solar cell according to claim 1, wherein The step of sequentially forming a tunneling oxide layer and a doped polysilicon layer on the first surface includes: forming the tunneling oxide layer on the first surface so that the tunneling oxide layer covers the first region and the silicon oxide dielectric layer; forming an intrinsic amorphous silicon layer on the side of the tunneling oxide layer facing away from the silicon substrate; performing a diffusion treatment on the intrinsic amorphous silicon layer to convert the intrinsic amorphous silicon layer into the doped polysilicon layer and form a doped silicon glass on the side of the doped polysilicon layer facing away from the tunneling oxide layer.

7. The method for preparing a solar cell according to claim 6, wherein The step of patterning the doped polysilicon layer and the tunneling oxide layer includes: performing a second laser treatment on the portion of the doped silicon glass located on the second region to remove the portion of the doped silicon glass located on the second region; removing the portion of the doped polysilicon layer located on the second region and the portion of the tunneling oxide layer located on the second region by wet etching.

8. The method for preparing a solar cell according to any one of claims 1 to 7, characterized in that, The thickness of the silicon oxide dielectric layer is 8 - 10 nm.

9. The manufacturing method of the solar cell according to any one of claims 1 to 7, characterized in that, Before forming the silicon oxide dielectric layer on the second region, the preparation method of the solar cell further includes: polishing the first surface.

10. A solar cell, characterized in that, The solar cell is prepared by using the preparation method of the solar cell according to any one of claims 1 to 9.

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