Solar cell and preparation method thereof

Abstract

The invention discloses a solar cell and a preparation method thereof, and belongs to the field of photovoltaic technology. According to the solar cell, a silicon substrate is provided with a front surface and a back surface which are oppositely arranged, a first area and a second area which are arranged in a staggered mode and are free of intervals are arranged in the first direction, and the thickness of the silicon substrate located in the first area is larger than that of the silicon substrate located in the second area; the first doped structure is arranged on the back surface and located in the first region, and comprises a first tunneling layer and a first doped crystalline silicon layer which are stacked in sequence; the second doping structure is arranged on the back surface and located in the second region; the surface of the first tunneling layer facing the silicon substrate is spaced apart from the surface of the second doping structure away from the silicon substrate along the second direction. According to the solar cell, the Gap region does not need to be etched by laser, the area of the photoelectric conversion region can be increased, the patterning precision requirement is reduced, the problem of offset short circuit of metallization printing is solved, meanwhile, effective spacing of different doping structures is achieved, and short circuit is effectively prevented.

Description

Technical Field

[0001] The present application belongs to the field of photovoltaic technology, and in particular relates to a solar cell and a method for preparing the same. Background Art

[0002] Back contact (BC) type cells have the P-type doping structure (called the P region), the N-type doping structure (referred to as the N region) and the electrodes all located on the back surface, leaving the front surface free of electrode shading, which greatly improves the absorption of sunlight and has a higher cell efficiency.

[0003] Existing BC batteries generally adopt a design with an isolation area (Gap area) at the junction of the P area and the N area to prevent the P area and the N area from contacting and causing short circuit failure. The Gap area is mainly prepared by laser technology, and the graphic accuracy requirements are high, which affects the alignment of the subsequent metallization process and easily causes battery performance degradation; if there is a connectivity defect in the Gap area, it will also cause the battery to short-circuit and fail. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a solar cell and a method for preparing the same, which can reduce the requirements for patterning accuracy, improve the problem of metallization printing offset short circuit, achieve effective spacing of different doping structures, and prevent short circuit.

[0005] In a first aspect, the present application provides a solar cell, comprising: A silicon substrate having a front surface and a back surface arranged opposite to each other, and having first regions and second regions arranged in a staggered manner without any gap along a first direction, wherein the first direction is a direction parallel to the plane where the silicon substrate is located, and the thickness of the silicon substrate located in the first region is greater than the thickness of the silicon substrate located in the second region; A first doping structure, provided on the back surface and located in the first region, comprises a first tunneling layer and a first doped crystalline silicon layer stacked in sequence, wherein the first tunneling layer is in contact with the silicon substrate; A second doping structure, disposed on the back surface and located in the second region; Among them, a side of the first tunneling layer facing the silicon substrate is spaced apart from a side of the second doping structure facing away from the silicon substrate along a second direction, and the second direction is a direction perpendicular to the plane where the silicon substrate is located; the doping types of the first doping structure and the second doping structure are opposite.

[0006] According to the solar cell of the present application, by arranging a first region and a second region that are staggeredly arranged and have no gap along a first direction, and respectively arranging two doping structures with opposite doping types, laser etching of the Gap region is not required, the area of the optoelectronic conversion region can be increased, the requirements for patterning accuracy can be reduced, the problem of metalization printing offset short circuit can be improved, the thickness of the silicon substrate in the first region is greater than the thickness of the silicon substrate in the second region, and the first tunneling layer at the thicker part separates the first doped crystalline silicon layer and the second doping structure along a second direction, realizing effective separation of different doping structures and effectively preventing short circuit.

[0007] According to an embodiment of the present application, the second doping structure includes a second tunneling layer and a second doped crystalline silicon layer stacked in sequence, and the second tunneling layer is in contact with the silicon substrate; One side of the first tunneling layer facing the silicon substrate is spaced apart from one side of the second doped crystalline silicon layer facing away from the silicon substrate along the second direction.

[0008] According to an embodiment of the present application, the distance between one side of the first tunneling layer facing the silicon substrate and one side of the second doped crystalline silicon layer facing away from the silicon substrate along the second direction is 10 μm - 15 μm.

[0009] According to an embodiment of the present application, the first tunneling layer and the second tunneling layer are integrally provided.

[0010] According to an embodiment of the present application, the second doping structure is a second diffusion layer formed by diffusing a doping source from the back surface to the front surface of the silicon substrate along the second direction.

[0011] According to an embodiment of the present application, the distance between one side of the first tunneling layer facing the silicon substrate and one side of the second diffusion layer facing away from the front surface along the second direction is 10 μm - 15 μm.

[0012] According to an embodiment of the present application, the area of the first region is greater than or equal to the area of the second region.

[0013] In a second aspect, the present application provides a method for manufacturing a solar cell, the method comprising: Providing a silicon substrate having a front surface and a back surface arranged opposite to each other, the silicon substrate being provided with a first region and a second region that are staggeredly arranged and have no gap along a first direction, and the first direction being a direction parallel to the plane where the silicon substrate is located; Forming a first doping structure on the back surface, the first doping structure including a first tunneling layer and a first doped crystalline silicon layer stacked in sequence, and the first tunneling layer is in contact with the silicon substrate; Remove the first doping structure and part of the silicon substrate in the second region of the back surface, and form a second doping structure with a doping type opposite to that of the first doping structure in the second region. A side of the first tunneling layer facing the silicon substrate is spaced apart from a side of the second doping structure facing away from the silicon substrate in a second direction, and the second direction is a direction perpendicular to the plane where the silicon substrate is located.

[0014] According to the method for manufacturing a solar cell of the present application, by arranging first regions and second regions that are alternately arranged and have no gaps in a first direction, two doping structures with opposite doping types are prepared on the back surface of the silicon substrate. Without laser etching of the Gap region, the area of the optoelectronic conversion region can be increased, the requirement for patterning accuracy can be reduced, and the problem of metalization printing offset short circuit can be improved. The thickness of the silicon substrate in the first region is greater than the thickness of the silicon substrate in the second region. The first tunneling layer at the thicker part separates the first doped crystalline silicon layer and the second doping structure in the second direction, realizing effective separation of different doping structures. The process is simple and short circuit can be effectively prevented.

[0015] According to an embodiment of the present application, the second doping structure includes a second tunneling layer and a second doped crystalline silicon layer stacked in sequence, and the second tunneling layer is in contact with the silicon substrate; Forming a first doping structure on the back surface includes: Form a first tunneling layer, the first doped crystalline silicon layer, and a first mask layer stacked in sequence, and the first mask layer is in contact with a side of the first doped crystalline silicon layer facing away from the first tunneling layer; Remove the first doping structure and part of the silicon substrate in the second region of the back surface, and form a second doping structure with a doping type opposite to that of the first doping structure in the second region, including: Use a laser to remove the first mask layer in the second region of the back surface; Etch the first doped crystalline silicon layer, the first tunneling layer, and part of the silicon substrate in the second region; Form a second tunneling layer, a second doped crystalline silicon layer, and a second mask layer stacked in sequence on the back surface, and the second mask layer is in contact with a side of the second doped crystalline silicon layer facing away from the second tunneling layer; Use a laser to remove the second mask layer in the first region of the back surface; Etch the second doped crystalline silicon layer and the second tunneling layer in the first region; Etch the first mask layer in the first region and the second mask layer in the second region.

[0016] According to one embodiment of the present application, etching the first doped crystalline silicon layer, the first tunneling layer, and a portion of the silicon substrate in the second region includes: Etching the first doped crystalline silicon layer and the first tunneling layer in the second region; The silicon substrate is etched 13 μm-18 μm from the back surface to the front surface along the second direction, so that the distance between the first tunneling layer facing the silicon substrate and the second doped crystalline silicon layer facing away from the silicon substrate along the second direction is 10 μm-15 μm.

[0017] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 This is one of the structural schematic diagrams of the solar cell provided in the embodiment of the present application; Figure 2 This is the second structural schematic diagram of the solar cell provided in the embodiment of the present application; Figure 3 This is the third structural schematic diagram of the solar cell provided in the embodiment of the present application; Figure 4 is a schematic diagram of a process for preparing a solar cell provided in an embodiment of the present application; Figure 5 This is one of the schematic diagrams of the intermediate structure of the solar cell provided in the embodiment of the present application; Figure 6 This is the second schematic diagram of the intermediate structure of the solar cell provided in the embodiment of the present application; Figure 7 This is the third schematic diagram of the intermediate structure of the solar cell provided in the embodiment of the present application; Figure 8 This is the fourth schematic diagram of the intermediate structure of the solar cell provided in the embodiment of the present application; Figure 9 This is the fifth schematic diagram of the intermediate structure of the solar cell provided in the embodiment of the present application; Figure 10 This is the sixth schematic diagram of the intermediate structure of the solar cell provided in the embodiments of the present application.

[0019] Reference numerals: Silicon substrate 100, first region 110, second region 120, The first doping structure 210, the first tunneling layer 211, the first doped crystalline silicon layer 212, the first mask layer 213, The second doping structure 220, the second tunneling layer 221, the second doped crystalline silicon layer 222, the second mask layer 223, the second diffusion layer 224, The passivation layer 310, the antireflection layer 320, the first electrode structure 410, the second electrode structure 420. Detailed implementation manners

[0020] The embodiments of the present application will be described in detail below. The examples of the embodiments are shown in the drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application and should not be construed as a limitation to the present application.

[0021] Reference will be made below Figures 1 - 10 to describe the solar cell of the embodiments of the present application and the preparation method of the solar cell.

[0022] As Figure 1 shown, the solar cell includes a silicon substrate 100, a first doping structure 210, and a second doping structure 220.

[0023] Among them, the silicon substrate 100 has a front surface and a back surface which are oppositely arranged. The front surface refers to the light-receiving surface of the solar cell facing the light source, and the back surface refers to the backlight surface of the solar cell.

[0024] In actual implementation, the silicon substrate 100 can be an N-type silicon wafer or a P-type silicon wafer.

[0025] In this embodiment, the first doping structure 210 and the second doping structure 220 are disposed on the back surface of the silicon substrate 100.

[0026] The silicon substrate 100 is provided with first regions 110 and second regions 120 which are alternately arranged and have no gap along a first direction D1. The first doping structure 210 is disposed on the back surface and located in the first regions 110, and the second doping structure 220 is disposed on the back surface and located in the second regions 120.

[0027] Among them, the first direction D1 is a direction parallel to the plane where the silicon substrate 100 is located.

[0028] It can be understood that the doping types of the first doping structure 210 and the second doping structure 220 are opposite. One of the first doping structure 210 and the second doping structure 220 forms a hole-dominated conductive region (P region) responsible for collecting photo-generated holes and transporting them to the corresponding electrode, and the other forms an electron-dominated conductive region (N region) for collecting photo-generated electrons and transporting them to the corresponding electrode. The efficient separation and collection of photo-generated carriers are achieved through doping structures with different doping types.

[0029] For example, the first doping structure 210 can be a P region doped with boron as a doping source, and the second doping structure 220 can be an N region doped with phosphorus as a doping source.

[0030] For another example, the first doping structure 210 can be an N region doped with phosphorus as a doping source, and the second doping structure 220 can be a P region doped with boron as a doping source.

[0031] In this embodiment, the first doping structure 210 is disposed in the first region 110, the second doping structure 220 is disposed in the second region 120, and the first region 110 and the second region 120 are arranged alternately along the first direction D1. The directional migration of photo-generated carriers is achieved through the built-in electric field to form a photo-generated current.

[0032] It can be understood that the photo-generated current formed by the first doping structure 210 and the second doping structure 220 is collected by the metal electrodes. The first electrode structure 410 is in contact with the first doping structure 210, and the second electrode structure 420 is in contact with the second doping structure 220 to achieve the selective separation of electrons and holes and export the photo-generated current.

[0033] Among them, the first electrode structure 410 and the second electrode structure 420 can be grid line structures such as fine grids and main grids.

[0034] In actual implementation, the solar cell can also be provided with structures such as a passivation layer 310 and an antireflection layer 320 to reduce carrier recombination and increase light absorption. On the back surface, the first electrode structure 410 penetrates the passivation layer 310 and the antireflection layer 320 to contact the first doping structure 210, and the second electrode structure 420 penetrates the passivation layer 310 and the antireflection layer 320 to contact the second doping structure 220.

[0035] Among them, the passivation layer 310 can be prepared from aluminum oxide (Al2O3), the thickness of the passivation layer 310 can be 2 nm - 10 nm, the antireflection layer 320 can be a single-layer structure or a multi-layer structure of a silicon nitride (SiNx) layer, a silicon oxide (SiOx) layer, and a silicon oxynitride (SiOxNy) layer, and the thickness of the antireflection layer 320 can be 10 nm - 100 nm.

[0036] It should be noted that there is no gap between the adjacent first region 110 and the second region 120, and the first region 110 and the second region 120 are adjacent, that is, there is no isolation region (i.e., the Gap region in the related art) between the first region 110 and the second region 120.

[0037] In this embodiment, the thickness of the silicon substrate 100 in the first region 110 is greater than the thickness of the silicon substrate 100 in the second region 120, that is, the silicon substrate 100 in the first region 110 is thicker than the silicon substrate 100 in the second region 120. The first doping structure 210 formed in the first region 110 and the second doping structure 220 formed in the second region 120 form a height difference in the second direction D2. The first region 110 of the solar cell is thicker than the second region 120.

[0038] Wherein, the second direction D2 is a direction perpendicular to the plane where the silicon substrate 100 is located.

[0039] In actual implementation, the second direction D2 can also be referred to as the thickness direction of the silicon substrate 100, and the first direction D1 can be perpendicular to the second direction D2. It should be noted that the "perpendicular" here includes not only the absolute 90-degree perpendicular, but also other approximately perpendicular situations close to 90 degrees.

[0040] In this embodiment, the first doping structure 210 includes a first tunneling layer 211 and a first doped crystalline silicon layer 212 stacked in sequence, and the first tunneling layer 211 is in contact with the silicon substrate 100.

[0041] It can be understood that the first tunneling layer 211 and the first doped crystalline silicon layer 212 can form a passivation contact structure, which helps to reduce the recombination of carriers and reduce the contact recombination loss.

[0042] Wherein, the first tunneling layer 211 is a hierarchical structure in contact with the silicon substrate 100, which can realize the selective transport of carriers, isolate the metal electrode from the silicon substrate 100, and reduce the carrier recombination loss.

[0043] In actual implementation, the first tunneling layer 211 can be prepared by using silicon oxide (SiO2).

[0044] In this embodiment, one side of the first tunneling layer 211 facing the silicon substrate 100 is spaced apart from one side of the second doping structure 220 facing away from the silicon substrate 100 in the second direction D2, that is, the first doping structure 210 and the second doping structure 220 are spaced apart in the second direction D2. The first tunneling layer 211 can space the first doped crystalline silicon layer 212 and the second doping structure 220 to prevent short circuits caused by the contact of doping structures of different doping types, and realize the efficient separation and collection of photo-generated carriers.

[0045] A specific embodiment is described below.

[0046] like Figure 1 As shown, the solar cell includes a silicon substrate 100, a first doping structure 210 and a second doping structure 220. The first doping structure 210 and the second doping structure 220 are arranged on the back surface of the silicon substrate 100, and a first region 110 and a second region 120 are arranged alternately and without intervals along a first direction D1. The first doping structure 210 is arranged on the back surface and located in the first region 110, and the second doping structure 220 is arranged on the back surface and located in the second region 120.

[0047] There is no gap between the adjacent first region 110 and the second region 120, which can effectively increase the photoelectric conversion area of ​​the solar cell. The battery preparation process does not require laser etching of the Gap area, which can reduce the graphic accuracy requirements and improve the offset short circuit problem caused by excessively high accuracy requirements in the subsequent metallization printing process.

[0048] The thickness of the silicon substrate 100 located in the first area 110 is greater than the thickness of the silicon substrate 100 located in the second area 120. The first doped structure 210 includes a first tunneling layer 211 and a first doped crystalline silicon layer 212 stacked in sequence. The side of the first tunneling layer 211 facing the silicon substrate 100 is separated from the side of the second doped structure 220 facing away from the silicon substrate 100 along the second direction D2.

[0049] Along the first direction D1, the first region 110 and the second region 120 are arranged alternately without any gap, which effectively increases the photoelectric conversion area of ​​the solar cell and reduces the manufacturing precision requirements. Along the second direction D2, the first tunneling layer 211 separates the first doped crystalline silicon layer 212 and the second doped structure 220, which can prevent the doped structures of different doping types from contacting each other and causing a short circuit.

[0050] In related technologies, BC batteries generally adopt a design in which an isolation area (Gap area) is set at the junction of the P area and the N area through laser grooving. The laser process requires high graphic accuracy, which affects the alignment of the subsequent metallization process and can easily cause battery performance degradation. If there are connectivity defects in the Gap area, it will also cause the battery to short-circuit and fail. In addition, the Gap area cannot generate photogenerated carriers. The existence of the Gap area leads to a reduction in the effective area of ​​the battery, limiting the photoelectric conversion efficiency.

[0051] In the embodiment of the present application, by designing the first region 110 and the second region 120 which are staggered and arranged without gaps along the first direction D1, the first doping structure 210 and the second doping structure 220 are arranged, and the adjacent first region 110 and the second region 120 are without gaps, the photoelectric conversion area of ​​the solar cell can be effectively increased, and the photoelectric conversion efficiency can be improved. The cell preparation process does not require laser etching of the Gap area, which can reduce the graphic accuracy requirements, and improve the offset short circuit problem caused by excessively high accuracy requirements in the subsequent metallization printing process. The thickness of the silicon substrate 100 located in the first region 110 is greater than the thickness of the silicon substrate 100 located in the second region 120, forming a significantly different thickness distribution in the solar cell, and the first doped crystalline silicon layer 212 and the second doping structure 220 are separated along the second direction D2 in conjunction with the first tunneling layer 211 located at the thicker part of the cell, effectively preventing the doping structures of different doping types from contacting and causing a short circuit.

[0052] According to the solar cell provided in the embodiment of the present application, by arranging the first region 110 and the second region 120 which are staggered and have no gap along the first direction D1, two doping structures with opposite doping types are arranged respectively, and there is no need to laser etch the Gap region, so the area of ​​the photoelectric conversion region can be increased, and the requirements for patterning accuracy can be reduced, and the problem of metallization printing offset short circuit can be improved. The thickness of the silicon substrate 100 located in the first region 110 is greater than the thickness of the silicon substrate 100 located in the second region 120. The first tunneling layer 211 located in the thicker part separates the first doped crystalline silicon layer 212 and the second doping structure 220 along the second direction D2, so as to realize the effective spacing of different doping structures and effectively prevent short circuit.

[0053] In the embodiment of the present application, the second doping structure 220 has a doping type opposite to that of the first doping structure 210. The first doping structure 210 includes a first tunneling layer 211 and a first doped crystalline silicon layer 212 stacked in sequence. The hierarchical structure of the second doping structure 220 may be the same as the hierarchical structure of the first doping structure 210, or the hierarchical structure of the second doping structure 220 may be different from the hierarchical structure of the first doping structure 210.

[0054] In some embodiments, Figure 2 As shown, the second doped structure 220 includes a second tunneling layer 221 and a second doped crystalline silicon layer 222 stacked in sequence, and the second tunneling layer 221 is in contact with the silicon substrate 100; the first tunneling layer 211 is spaced apart from the second doped crystalline silicon layer 222 along the second direction D2 on the side facing the silicon substrate 100.

[0055] In this embodiment, the hierarchical structures of the second doping structure 220 and the first doping structure 210 are both a tunneling layer and a doped polycrystalline silicon layer stacked in sequence. Among them, the second tunneling layer 221 can also be prepared using silicon dioxide (SiO2), and the doping types of the first doped polycrystalline silicon layer 212 and the second doped polycrystalline silicon layer 222 are opposite.

[0056] In actual implementation, the first doped polycrystalline silicon layer 212 and the second doped polycrystalline silicon layer 222 can be obtained by doping a doping source in a microcrystalline silicon layer, an amorphous silicon layer, or a polycrystalline silicon layer.

[0057] For example, the first doped polycrystalline silicon layer 212 can be a polycrystalline silicon layer with boron as the doping source, which can be called P-poly. The first doping structure 210 forms the P region of the solar cell. The second doped polycrystalline silicon layer 222 can be a polycrystalline silicon layer with phosphorus as the doping source, which can be called N-poly. The second doping structure 220 forms the N region of the solar cell.

[0058] It should be noted that the second doping structure 220 and the first doping structure 210 adopting the same hierarchical structure can make parameters such as the doping concentration and junction depth of the P region and the N region consistent, reduce the electrical performance fluctuations of different conductive regions, improve the photoelectric conversion efficiency of the solar cell, and in addition, the passivation structure formed by the tunneling layer and the doped polycrystalline silicon layer stacked in sequence can also reduce the recombination loss of the solar cell. Moreover, the same hierarchical structure can use the same preparation process during preparation to reduce equipment switching and process adjustment, and reduce production complexity and production cost.

[0059] In some embodiments, the distance between the side of the first tunneling layer 211 facing the silicon substrate 100 and the side of the second doped polycrystalline silicon layer 222 facing away from the silicon substrate 100 along the second direction D2 is 10 μm - 15 μm.

[0060] It can be understood that for the first doping structure 210 and the second doping structure 220 adopting a tunneling layer and a doped polycrystalline silicon layer stacked in sequence, the first tunneling layer 211 is located in the thicker first region 110 of the silicon substrate 100, and the second doped polycrystalline silicon layer 222 is located in the thinner second region 120 of the silicon substrate 100. The side of the first tunneling layer 211 facing the silicon substrate 100 and the side of the second doped polycrystalline silicon layer 222 facing away from the silicon substrate 100 are spaced apart along the second direction D2. The first tunneling layer 211 can achieve effective isolation between the first doped polycrystalline silicon layer 212 and the second doping in the second direction D2.

[0061] In this embodiment, as Figure 2As shown, the distance H1 along the second direction D2 between the side of the first tunneling layer 211 facing the silicon substrate 100 and the side of the second doped crystalline silicon layer 222 facing away from the silicon substrate 100 is 10 μm - 15 μm. The side of the first tunneling layer 211 facing the silicon substrate 100 is in contact with the silicon substrate 100, that is, the first doped crystalline silicon layer 212 and the second doped crystalline silicon layer 222 are spaced apart by a 10 μm - 15 μm thick silicon substrate 100 and the first tunneling layer 211 in the second direction D2.

[0062] It should be noted that for the first region 110 and the second region 120 without a gap along the first direction D1, a silicon substrate 100 with a thickness of 10 μm - 15 μm and the first tunneling layer 211 located at the thicker part are provided in the second direction D2 to isolate the first doped crystalline silicon layer 212 and the second doped crystalline silicon layer 222. While increasing the area of the optoelectronic conversion region of the solar cell, it effectively prevents short circuits caused by the contact of doping structures of different doping types.

[0063] In some embodiments, the first tunneling layer 211 and the second tunneling layer 221 are integrally provided.

[0064] In actual implementation, a groove can be first formed in the silicon substrate 100. The groove corresponds to the second region 120. A tunneling layer is prepared. The one located in the groove can be called the second tunneling layer 221, and the one located outside the groove can be called the first tunneling layer 211.

[0065] In this embodiment, the first tunneling layer 211 and the second tunneling layer 221 are integrally provided. For the sidewall of the silicon substrate 100 at the connection of the first region 110 and the second region 120, a tunneling layer with a tunneling effect is also covered, effectively reducing the recombination probability of carriers.

[0066] In other embodiments, as Figure 3 shown, the second doping structure 220 can be a second diffusion layer 224 formed by diffusing a doping source from the back surface to the front surface of the silicon substrate 100 along the second direction D2.

[0067] In this embodiment, by using a doping source to diffuse in the thickness direction from the back surface to the front surface of the silicon substrate 100, the second diffusion layer 224 is prepared. The diffusion can achieve uniform doping. The equipment is simple and the process is mature. During the preparation process, parameters such as diffusion time, temperature, and gas flow can be controlled to control the doping depth and concentration distribution.

[0068] In actual implementation, the preparation of the first doping structure 210 can be completed on the silicon substrate 100 first, then the first doping region in the second region 120 is removed, and a part of the silicon substrate 100 in the second region 120 is removed, so that the thickness of the silicon substrate 100 in the first region 110 is greater than the thickness of the silicon substrate 100 in the second region 120. Then, a doping source is used to diffuse in the second region 120 along the thickness direction to prepare the second diffusion layer 224. When preparing the first doping structure 210, a first mask layer 213 can be prepared on the side of the first doped crystalline silicon layer 212 facing away from the first tunneling layer 211 to prevent the first doping structure 210 from being affected during the subsequent preparation of the second doping structure 220. At the same time, the first tunneling layer 211 separates the second diffusion layer 224 and the first doped crystalline silicon layer 212 in the second direction D2, which can also prevent the diffusion process from affecting the first doped crystalline silicon layer 212.

[0069] In some embodiments, the distance between the side of the first tunneling layer 211 facing the silicon substrate 100 and the side of the second diffusion layer 224 facing away from the front surface in the second direction D2 is 10 μm - 15 μm.

[0070] In this embodiment, as Figure 3 shown, the distance H2 between the side of the first tunneling layer 211 facing the silicon substrate 100 and the side of the second diffusion layer 224 facing away from the front surface in the second direction D2 is 10 μm - 15 μm. The side of the first tunneling layer 211 facing the silicon substrate 100 contacts the silicon substrate 100, that is, the first doped crystalline silicon layer 212 and the second diffusion layer 224 are separated by a 10 μm - 15 μm thick silicon substrate 100 and the first tunneling layer 211 in the second direction D2.

[0071] It can be understood that for the first region 110 and the second region 120 without a gap along the first direction D1, a 10 μm - 15 μm thick silicon substrate 100 and the first tunneling layer 211 located at the thicker part are provided in the second direction D2 to isolate the first doped crystalline silicon layer 212 and the second diffusion layer 224. While increasing the area of the photovoltaic conversion region of the solar cell, it effectively prevents short - circuit caused by the contact of doping structures of different doping types.

[0072] In actual implementation, when diffusing in the second region 120 to prepare the second diffusion layer 224, even if the doping source diffuses to the boundary of the first region 110, there is a silicon substrate 100 with a sufficient thickness (10 μm - 15 μm) and the first tunneling layer 211 in the first region 110 for isolation. Without the premise of laser - etching the Gap region, it can effectively prevent short - circuit caused by the contact of doping structures of different doping types.

[0073] In some embodiments, the area of the first region 110 is greater than or equal to the area of the second region 120.

[0074] In this embodiment, the total area of the first region 110 in the solar cell may be greater than or equal to the total area of the second region 120, or the area of a single first region 110 may be greater than or equal to the area of a single second region 120.

[0075] In actual implementation, the area ratio of the first region 110 and the second region 120 can be designed by comprehensively considering the electrical performance, optical loss, and process feasibility of the solar cell, etc.

[0076] It should be noted that the area of the first region 110 can match the number of carriers collected by the first doping structure 210 in the first region 110, and the area of the second region 120 can match the number of carriers collected by the second doping structure 220 in the second region 120.

[0077] For example, the first doping structure 210 can be a P region doped with boron as a doping source, and the second doping structure 220 can be an N region doped with phosphorus as a doping source. The area of the first region 110 can be set to be larger than the area of the second region 120, and the slightly larger P region area is used to balance the hole collection efficiency.

[0078] The embodiment of the present application also provides a preparation method of a solar cell, and this preparation method can be used to prepare the solar cell as described above.

[0079] As Figure 4 shown, the preparation method of this solar cell includes: step 510, step 520, and step 530.

[0080] Step 510: Provide a silicon substrate 100.

[0081] Wherein, the silicon substrate 100 has a positive surface and a back surface arranged oppositely, and the silicon substrate 100 is provided with first regions 110 and second regions 120 that are arranged in a staggered manner and have no interval along a first direction D1, and the first direction D1 is a direction parallel to the plane where the silicon substrate 100 is located.

[0082] In actual implementation, the silicon substrate 100 can be an N-type silicon wafer or a P-type silicon wafer.

[0083] In this step, pretreatment processes such as cleaning and texturing of the silicon substrate 100 can be performed to improve the subsequent process quality and cell performance.

[0084] For example, the silicon substrate 100 is an N-type silicon wafer with a resistivity of 0.3 Ω·cm - 7 Ω·cm. The N-type silicon wafer is placed in an alkaline polishing trough machine, and the original silicon wafer is polished on both sides by alkaline etching to form a tower base.

[0085] Among them, the size of the tower base can be 10μm - 20μm, the treatment time in the alkali tank can be set to 50s - 500s, the treatment temperature can be set to 50°C - 90°C, the alkali concentration is set to 0.5% - 2%, and the additive concentration is set to 0.5% - 1%.

[0086] Step 520: Form a first doping structure 210 on the back surface.

[0087] Among them, the first doping structure 210 includes a first tunneling layer 211 and a first doped polysilicon layer 212 stacked in sequence, and the first tunneling layer 211 is in contact with the silicon substrate 100.

[0088] In this step, the first tunneling layer 211 and the first doped polysilicon layer 212 are stacked in sequence over the entire range of the back surface of the silicon substrate 100 (including the first region 110 and the second region 120) to form the first doping structure 210.

[0089] Taking the polysilicon layer P-poly with boron as the doping source in the first doped polysilicon layer 212 as an example.

[0090] Adopt the method of low-pressure chemical vapor deposition (LPCVD) plus tube diffusion to form the first tunneling layer 211 and the boron-doped first doped polysilicon layer 212.

[0091] In this embodiment, boron trichloride (BCl3) or boron tribromide (BBr3) can be used as the boron doping source, the diffusion temperature is controlled at 900°C - 1100°C, the sheet resistance is controlled at 50Ω / sq - 400Ω / sq, the thickness of the first doped polysilicon layer 212 can be 100nm - 400nm, and the surface concentration can be 1E18cm -3 -1E20cm -3 .

[0092] It can be understood that during the preparation process, a first mask layer 213 can be formed on the surface of the first doped polysilicon layer 212 (i.e., the side of the first doped polysilicon layer 212 facing away from the first tunneling layer 211) to protect the doped polysilicon layer through the mask layer.

[0093] Step 530: Remove the first doping structure 210 and part of the silicon substrate 100 in the second region 120 of the back surface, and form a second doping structure 220 with a doping type opposite to that of the first doping structure 210 in the second region 120.

[0094] Among them, the side of the first tunneling layer 211 facing the silicon substrate 100 and the side of the second doping structure 220 facing away from the silicon substrate 100 are spaced apart along the second direction D2, and the second direction D2 is the direction perpendicular to the plane where the silicon substrate 100 is located.

[0095] In this step, the first doping structure 210 in the second region 120 of the back surface is removed, and then a part of the silicon substrate 100 in the second region 120 is removed, so that the thickness of the silicon substrate 100 in the first region 110 is greater than the thickness of the silicon substrate 100 in the second region 120. Then, a second doping structure 220 with a doping type opposite to that of the first doping structure 210 is formed in the second region 120.

[0096] It can be understood that when removing the first doping structure 210 and a part of the silicon substrate 100 in the second region 120, the first doping structure 210 in the first region 110 is retained.

[0097] In actual implementation, the first doping structure 210 and a part of the silicon substrate 100 in the second region 120 can be removed by means such as laser, alkali etching, and acid etching.

[0098] In this embodiment, the second doping structure 220 is prepared in the second region 120. One side of the first tunneling layer 211 of the first region 110 facing the silicon substrate 100 is spaced apart from one side of the second doping structure 220 of the second region 120 along the second direction D2. That is, the first doping structure 210 and the second doping structure 220 are spaced apart along the second direction D2. The first tunneling layer 211 can space the first doped crystalline silicon layer 212 and the second doping structure 220, preventing the contact of doping structures with different doping types from causing a short circuit and realizing the efficient separation and collection of photo-generated carriers.

[0099] It can be understood that after the preparation of the second doping structure 220, structures such as a passivation layer 310 and an antireflection layer 320 can be prepared, and electrodes can also be prepared by screen printing. The first doping structure 210 corresponds to the first electrode structure 410, the second doping structure 220 corresponds to the second electrode structure 420, and the first electrode structure 410 and the second electrode structure 420 can be grid line structures such as fine grids and main grids.

[0100] According to the preparation method of the solar cell provided by the embodiment of the present application, by arranging the first region 110 and the second region 120 in a staggered and non-spaced manner along the first direction D1, two doping structures with opposite doping types are prepared on the back surface of the silicon substrate 100. Without laser etching the Gap region, the area of the optoelectronic conversion region can be increased, the requirement for patterning accuracy can be reduced, the problem of metalization printing offset short circuit can be improved. The thickness of the silicon substrate 100 in the first region 110 is greater than the thickness of the silicon substrate 100 in the second region 120. The first tunneling layer 211 at the thicker part spaces the first doped crystalline silicon layer 212 and the second doping structure 220 along the second direction D2, realizing the effective spacing of different doping structures. The process is simple and can effectively prevent short circuits.

[0101] In the embodiment of the present application, the second doping structure 220 has a doping type opposite to that of the first doping structure 210. The first doping structure 210 includes a first tunneling layer 211 and a first doped crystalline silicon layer 212 stacked in sequence. The hierarchical structure of the second doping structure 220 may be the same as the hierarchical structure of the first doping structure 210, or the hierarchical structure of the second doping structure 220 may be different from the hierarchical structure of the first doping structure 210.

[0102] In some embodiments, Figure 2 As shown, the second doped structure 220 includes a second tunneling layer 221 and a second doped crystalline silicon layer 222 stacked in sequence, and the second tunneling layer 221 is in contact with the silicon substrate 100; the first tunneling layer 211 is spaced apart from the second doped crystalline silicon layer 222 along the second direction D2 on the side facing the silicon substrate 100.

[0103] In other embodiments, Figure 3 As shown, the second doping structure 220 may be a second diffusion layer 224 formed by diffusion of a doping source along a second direction D2 from a back surface to a front surface of the silicon substrate 100 .

[0104] A specific preparation process of the second doping structure 220 is introduced below.

[0105] The second doping structure 220 includes a second tunneling layer 221 and a second doped crystalline silicon layer 222 which are stacked in sequence, and the second tunneling layer 221 is in contact with the silicon substrate 100 .

[0106] In some embodiments, forming a first doping structure 210 on the back surface includes: A first tunneling layer 211, a first doped crystalline silicon layer 212 and a first mask layer 213 are sequentially stacked, and the first mask layer 213 is in contact with a surface of the first doped crystalline silicon layer 212 that is away from the first tunneling layer 211; The first doping structure 210 and a portion of the silicon substrate 100 in the second region 120 of the back surface are removed, and a second doping structure 220 having a doping type opposite to that of the first doping structure 210 is formed in the second region 120, including: Using laser to remove the first mask layer 213 in the second area 120 of the back surface; Etching the first doped crystalline silicon layer 212 , the first tunneling layer 211 and a portion of the silicon substrate 100 in the second region 120 ; A second tunneling layer 221, a second doped crystalline silicon layer 222 and a second mask layer 223 are sequentially stacked on the back surface, and the second mask layer 223 is in contact with a side of the second doped crystalline silicon layer 222 away from the second tunneling layer 221; Using laser to remove the second mask layer 223 in the first area 110 of the back surface; Etch the second doped polysilicon layer 222 and the second tunneling layer 221 in the first region 110; Etch the first mask layer 213 in the first region 110 and the second mask layer 223 in the second region 120.

[0107] It should be noted that the first mask layer 213 can protect the first doped polysilicon layer 212, and the second mask layer 223 can protect the second doped polysilicon layer 222.

[0108] As Figure 5 shown, when preparing the first doped structure 210, a first tunneling layer 211, a first doped polysilicon layer 212, and a first mask layer 213 are sequentially formed on the back surface (including the first region 110 and the second region 120). As Figure 6 shown, the first mask layer 213 in the second region 120 is removed by laser, and the first mask layer 213 in the first region 110 is retained to protect the first doped polysilicon layer 212 in the first region 110.

[0109] As Figure 7 shown, the first doped polysilicon layer 212, the first tunneling layer 211, and a part of the silicon substrate 100 in the second region 120 are etched. Under the protection of the first mask layer 213, the first doped polysilicon layer 212 and the first tunneling layer 211 in the first region 110 are retained.

[0110] In actual implementation, the first doped polysilicon layer 212, the first tunneling layer 211, and a part of the silicon substrate 100 in the second region 120 can be removed by wet etching.

[0111] In this embodiment, after removing the first doped structure 210 and a part of the silicon substrate 100 in the second region 120 on the back surface, as Figure 8 shown, a second tunneling layer 221, a second doped polysilicon layer 222, and a second mask layer 223 are sequentially formed on the back surface (including the first region 110 and the second region 120).

[0112] As Figure 9 shown, the second mask layer 223 in the first region 110 on the back surface is removed by laser to remove the second doped polysilicon layer 222 and the second tunneling layer 221 in the first region 110.

[0113] In actual implementation, the second doped polysilicon layer 222 and the second tunneling layer 221 in the first region 110 can be removed by wet etching. At this time, the second doped polysilicon layer 222 in the second region 120 is protected by the second mask layer 223.

[0114] As Figure 10As shown, after removing the second doped polysilicon layer 222 and the second tunneling layer 221 in the first region 110, the first mask layer 213 in the first region 110 and the second mask layer 223 in the second region 120 can be removed by pickling, facilitating the subsequent preparation of the passivation layer 310, the antireflection layer 320, and the electrodes.

[0115] In some embodiments, as Figure 2 shown, the distance H1 along the second direction D2 between the side of the first tunneling layer 211 facing the silicon substrate 100 and the side of the second doped polysilicon layer 222 facing away from the silicon substrate 100 can be 10 μm - 15 μm. The side of the first tunneling layer 211 facing the silicon substrate 100 contacts the silicon substrate 100, that is, the first doped polysilicon layer 212 and the second doped polysilicon layer 222 are spaced apart by a 10 μm - 15 μm thick silicon substrate 100 and the first tunneling layer 211 in the second direction D2.

[0116] It should be noted that for the first region 110 and the second region 120 without a gap along the first direction D1, a silicon substrate 100 with a thickness of 10 μm - 15 μm and the first tunneling layer 211 at the thicker part are provided in the second direction D2 to isolate the first doped polysilicon layer 212 and the second doped polysilicon layer 222. While increasing the area of the optoelectronic conversion region of the solar cell, it effectively prevents short - circuit caused by the contact of doping structures of different doping types.

[0117] In some embodiments, etching the first doped polysilicon layer 212, the first tunneling layer 211, and a part of the silicon substrate 100 in the second region 120 includes: etching the first doped polysilicon layer 212 and the first tunneling layer 211 in the second region 120; etching 13 μm - 18 μm of the silicon substrate 100 from the back surface to the front surface along the second direction D2, so that the distance along the second direction D2 between the side of the first tunneling layer 211 facing the silicon substrate 100 and the side of the second doped polysilicon layer 222 facing away from the silicon substrate 100 is 10 μm - 15 μm.

[0118] In this embodiment, after removing the first doped polysilicon layer 212 and the first tunneling layer 211 in the second region 120, as Figure 7 shown, when etching a part of the silicon substrate 100 in the second region 120, the silicon substrate 100 with a distance H3 = 13 μm - 18 μm can be etched from the back surface to the front surface along the second direction D2 (i.e., the thickness direction of the silicon substrate 100). After preparing the second doping structure 220, as Figure 10 shown, the distance H1 along the second direction D2 between the side of the first tunneling layer 211 facing the silicon substrate 100 and the side of the second doped polysilicon layer 222 facing away from the silicon substrate 100 is 10 μm - 15 μm.

[0119] It can be understood that H3>H1. After preparing the second doped crystalline silicon layer 222 and the second tunneling layer 221, the distance between the side of the first tunneling layer 211 facing the silicon substrate 100 and the side of the second doped crystalline silicon layer 222 away from the silicon substrate 100 along the second direction D2 is maintained at 10μm-15μm. The first doped crystalline silicon layer 212 and the second doped crystalline silicon layer 222 are effectively isolated by the silicon substrate 100 with a thickness of 10μm-15μm and the first tunneling layer 211 located in a thicker position. There is no need to laser etch the Gap area, which can prevent the doping structures of different doping types from contacting and causing a short circuit.

[0120] A specific embodiment is described below.

[0121] An N-type silicon wafer with a resistivity of 3Ω·cm is selected as the silicon substrate 100, and the original silicon wafer is double-sided polished by alkaline etching to form a tower base. The tower base size is 15μm, the alkaline bath treatment time can be set to 300s, the treatment temperature can be set to 70°C, the alkali concentration is set to 1%, and the additive concentration is set to 0.5%.

[0122] The silicon substrate 100 has a front surface and a back surface opposite to each other. The silicon substrate 100 has first regions 110 and second regions 120 arranged alternately and without intervals along a first direction D1. The first direction D1 is a direction parallel to the plane where the silicon substrate 100 is located.

[0123] like Figure 5 As shown, by LPCVD plus tubular diffusion, boron trichloride (BCl3) or boron tribromide (BBr3) is used as a boron doping source, the diffusion temperature is controlled at 980°C, and the square resistance is controlled at 200Ω / sq. A first tunneling layer 211, a first doped crystalline silicon layer 212, and a first mask layer 213 are stacked in sequence on the entire range of the back surface of the silicon substrate 100 (including the first region 110 and the second region 120). The first doped crystalline silicon layer 212 can be called P-poly, and the first mask layer 213 is borosilicate glass (BSG).

[0124] In this embodiment, the BSG thickness may be 80 nm, the first tunneling layer 211 thickness may be 1.5 nm, the P-poly thickness may be 250 nm, and the surface concentration may be 1E19 cm -3 .

[0125] like Figure 6 As shown, laser is used to remove the BSG in the second area 120. For ultraviolet picosecond laser, the process parameters may include: spot power 15W, spot size 100μm, frequency 500kHz, and scanning speed 60000mm / s; for green light picosecond laser, the process parameters may include: spot power 30W, spot size 100μm, frequency 500kHz, and scanning speed 50000mm / s.

[0126] Using a single-sided chain device, hydrofluoric acid is used to remove the BSG on the front surface, and then enter the tank machine to remove the P-poly diffused around the front surface and the P-poly in the second back surface region 120. As Figure 7 shown, further etching is performed on the silicon substrate 100 in the second back surface region 120, and the depth of the silicon substrate 100 in the second back surface region 120 is 15 μm.

[0127] Alkaline polishing is performed on the front surface and the back surface. The base size of the pyramid in the second back surface region 120 is 25 μm, and the P-poly and BSG in the first region 110 are retained.

[0128] As Figure 8 shown, by means of LPCVD plus tube diffusion, a second tunneling layer 221, a second doped polycrystalline silicon layer 222, and a second mask layer 223 are sequentially formed in the entire range of the back surface of the silicon substrate 100 (including the first region 110 and the second region 120) using a phosphorus doping source. The second doped polycrystalline silicon layer 222 can be called N-poly, and the second mask layer 223 is phosphosilicate glass (PSG).

[0129] In this embodiment, the thickness of the PSG can be 40 nm, the thickness of the second tunneling layer 221 can be 1.5 nm, the thickness of the N-poly can be 150 nm, and the surface concentration can be 5E20 cm -3 .

[0130] As Figure 9 shown, laser film opening is performed on the first region 110 of the back surface according to the patterning to remove the PSG and expose the N-poly stacked on the P region. The laser process parameters can refer to the process parameters for removing the BSG.

[0131] The chain machine removes the PSG plated around the front surface, and then enters the tank machine to remove the N-poly plated around the front surface and the N-poly in the first back surface region 110. Alkaline combined with additives is used to texture the front surface. The pyramid size is 2 μm, the time in the texturing tank is 400 s, the temperature is 80 °C, the alkali concentration is 1%, and the additive concentration is 0.8%.

[0132] As Figure 10 shown, hydrofluoric acid is used to remove the PSG in the N region and the BSG in the P region on the back surface and perform RCA cleaning. At this time, a vertical height difference H1 = 12 μm will be formed between the N region and the P region, that is, the distance between the side of the first tunneling layer 211 facing the silicon substrate 100 and the side of the second doped polycrystalline silicon layer 222 facing away from the silicon substrate 100 along the second direction D2 is 10 μm - 15 μm.

[0133] A passivation layer 310 of Al2O3 is formed on the front and back surfaces by atomic layer deposition (ALD), and the thickness of the passivation layer 310 is 3 nm. Then, an antireflection layer 320 is deposited on the front and back surfaces by plasma-enhanced chemical vapor deposition (PECVD). The antireflection layer 320 can be a laminated film of one or more of silicon nitride, silicon oxynitride, and silicon oxide, and the thickness of the antireflection layer 320 is 80 nm.

[0134] The electrodes of the main grid and the secondary grid on the back surface are prepared by screen printing, and the printing paste sintering is optimized by laser-assisted sintering technology to obtain the Figure 2 solar cell as shown.

[0135] In the embodiments of the present application, the Gap region structure on the back surface of the solar cell is removed, and the first region 110 and the second region 120 are arranged in a staggered manner along the first direction D1 without a gap, increasing the areas of the N region and the P region on the back surface. The laser etching of the Gap region is not required during the battery preparation process, which can reduce the difficulty of laser patterning and metallization. The thickness of the silicon substrate 100 in the first region 110 is greater than the thickness of the silicon substrate 100 in the second region 120, forming an obvious thickness distribution in the solar cell. The first tunneling layer 211 located at the thicker part of the battery separates the first doped crystalline silicon layer 212 and the second doping structure 220 along the second direction D2, effectively preventing the contact of doping structures of different doping types from causing a short circuit. The preparation process flow of the solar cell is simple and is conducive to large-scale production.

[0136] The terms "first", "second", etc. in the description and claims of the present application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are usually of the same type and do not limit the number of objects. For example, the first object can be one or multiple. In addition, "and / or" in the description and claims means at least one of the connected objects, and the character " / " generally indicates an "or" relationship between the associated objects before and after.

[0137] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "thickness", "upper", "lower", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0138] In the description of the present application, the "first feature" and the "second feature" may include one or more of such features.

[0139] In the description of the present application, the meaning of "a plurality of" is two or more.

[0140] In the description of the present application, the first feature being "on" or "under" the second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact through additional features therebetween.

[0141] In the description of the present application, the first feature being "on", "above", and "over" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature has a higher horizontal height than the second feature.

[0142] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.

[0143] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the claims and their equivalents.

Claims

1. A solar cell, characterized in that, Comprising: A silicon substrate having a front surface and a back surface disposed opposite to each other, with a first region and a second region arranged in an interleaved manner and without gaps along a first direction, the first direction being parallel to the plane of the silicon substrate, and the thickness of the silicon substrate in the first region being greater than the thickness of the silicon substrate in the second region; A first doping structure disposed on the back surface and located in the first region, comprising a first tunneling layer and a first doped polysilicon layer stacked in sequence, and the first tunneling layer is in contact with the silicon substrate; A second doping structure disposed on the back surface and located in the second region; Wherein, one side of the first tunneling layer facing the silicon substrate and one side of the second doping structure facing away from the silicon substrate are spaced apart along a second direction, the second direction being perpendicular to the plane of the silicon substrate; the doping types of the first doping structure and the second doping structure are opposite.

2. The solar cell according to claim 1, characterized in that, The second doping structure comprises a second tunneling layer and a second doped polysilicon layer stacked in sequence, and the second tunneling layer is in contact with the silicon substrate; One side of the first tunneling layer facing the silicon substrate and one side of the second doped polysilicon layer facing away from the silicon substrate are spaced apart along the second direction.

3. The solar cell according to claim 2, characterized in that, The distance between one side of the first tunneling layer facing the silicon substrate and one side of the second doped polysilicon layer facing away from the silicon substrate along the second direction is 10 μm - 15 μm.

4. The solar cell according to claim 2, characterized in that, The first tunneling layer and the second tunneling layer are integrally provided.

5. The solar cell according to claim 1, characterized in that, The second doping structure is a second diffusion layer formed by diffusing a doping source from the back surface of the silicon substrate towards the front surface along the second direction.

6. The solar cell according to claim 5, characterized in that, The distance between one side of the first tunneling layer facing the silicon substrate and one side of the second diffusion layer facing away from the front surface along the second direction is 10 μm - 15 μm.

7. The solar cell according to any one of claims 1-5, characterized in that, The area of the first region is greater than or equal to the area of the second region.

8. A method for preparing a solar cell, characterized in that, Comprising: Providing a silicon substrate having a front surface and a back surface disposed opposite to each other, the silicon substrate being provided with a first region and a second region arranged in an interleaved manner and without gaps along a first direction, the first direction being parallel to the plane of the silicon substrate; Forming a first doping structure on the back surface, the first doping structure comprising a first tunneling layer and a first doped polysilicon layer stacked in sequence, and the first tunneling layer is in contact with the silicon substrate; Removing the first doping structure and a part of the silicon substrate in the second region of the back surface, and forming a second doping structure with a doping type opposite to that of the first doping structure in the second region, and one side of the first tunneling layer facing the silicon substrate and one side of the second doping structure facing away from the silicon substrate are spaced apart along a second direction, the second direction being perpendicular to the plane of the silicon substrate.

9. The method for preparing a solar cell according to claim 8, characterized in that, The second doping structure comprises a second tunneling layer and a second doped polysilicon layer stacked in sequence, and the second tunneling layer is in contact with the silicon substrate; Forming a first doping structure on the back surface, comprising: Forming the first tunneling layer, the first doped polysilicon layer and a first mask layer stacked in sequence, and the first mask layer is in contact with one side of the first doped polysilicon layer facing away from the first tunneling layer; Removing the first doping structure and a part of the silicon substrate in the second region of the back surface, and forming a second doping structure with a doping type opposite to that of the first doping structure in the second region, includes: Removing the first mask layer in the second region of the back surface by using a laser; Etching the first doped crystalline silicon layer, the first tunneling layer and a part of the silicon substrate in the second region; Forming a second tunneling layer, a second doped crystalline silicon layer and a second mask layer stacked in sequence on the back surface, where the second mask layer contacts a surface of the second doped crystalline silicon layer facing away from the second tunneling layer; Removing the second mask layer in the first region of the back surface by using a laser; Etching the second doped crystalline silicon layer and the second tunneling layer in the first region; Etching the first mask layer in the first region and the second mask layer in the second region.

10. The method for manufacturing a solar cell according to claim 9, wherein Etching the first doped crystalline silicon layer, the first tunneling layer and a part of the silicon substrate in the second region includes: Etching the first doped crystalline silicon layer and the first tunneling layer in the second region; Etching 13μm - 18μm of the silicon substrate from the back surface to the front surface along the second direction, so that the distance along the second direction between a surface of the first tunneling layer facing the silicon substrate and a surface of the second doped crystalline silicon layer facing away from the silicon substrate is 10μm - 15μm.

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