Solar cell, manufacturing method thereof and photovoltaic module

Abstract

The embodiment of the invention relates to the technical field of solar cells, and provides a solar cell piece and a manufacturing method thereof, and a photovoltaic module, the solar cell piece comprises a substrate, the substrate comprises a first surface and a second surface which are opposite, the first surface comprises first areas and second areas which are alternately arranged, the first areas are provided with textured structures, and the second areas are provided with textured structures. The second area is a polished surface; the first region is provided with a tunneling layer, a doped conductive layer and a functional layer which are arranged in sequence, and the functional layer is also located in the second region and is in contact with the polished surface; and a first electrode on the first region, the first electrode being in electrical contact with the doped conductive layer. According to the invention, the contact area of the first electrode and the doped conductive layer is increased, the filling factor is further improved, an excellent passivation effect is realized, and the photoelectric conversion efficiency of the solar cell is remarkably improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of solar cells, and particularly to a solar cell chip, a manufacturing method thereof, and a photovoltaic module. Background Art

[0002] With the increasing depletion of fossil energy, solar energy, as a clean and renewable alternative energy, has received more and more extensive attention and applications. As a device for converting solar energy into electrical energy, the performance of a solar cell is directly related to the energy utilization efficiency and the overall power generation cost.

[0003] The working principle of a solar cell is based on the photovoltaic effect of semiconductor materials. That is, under illumination conditions, electron-hole pairs (carriers) are generated inside the semiconductor, separated under the action of the built-in electric field, and led out through electrodes to form a current, thereby realizing the conversion of photoelectric energy. Summary of the Invention

[0004] Embodiments of the present disclosure provide a solar cell chip, a manufacturing method thereof, and a photovoltaic module, which are beneficial to improving the photoelectric conversion efficiency of the solar cell chip.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a solar cell chip, including: a substrate, the substrate includes opposite first and second surfaces, the first surface includes alternately arranged first and second regions, the first region has a textured surface structure, and the second region is a polished surface; a tunneling layer, a doped conductive layer, and a functional layer are sequentially arranged on the first region, and the functional layer is also located on the second region; wherein, the functional layer located on the second region is in contact with the polished surface; a first electrode, located on the first region, and the first electrode is in electrical contact with the doped conductive layer.

[0006] In some embodiments, the textured surface structure is a smooth pyramid textured surface structure.

[0007] In some embodiments, the radius of curvature of the edges of the pyramid texture is 100 nm to 300 nm.

[0008] In some embodiments, the functional layer includes: a passivation layer, the passivation layer is located on the surface of the doped conductive layer and is also located on the polished surface; an antireflection layer, the antireflection layer is located on the surface of the passivation layer.

[0009] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a method for manufacturing a solar cell, including: providing a substrate, the substrate including opposite first and second surfaces, the first surface including alternately arranged first and second regions; performing a texturing process on the substrate to form a textured structure on the first surface; sequentially forming a tunneling layer and a doped conductive layer on the surface of the textured structure; removing the tunneling layer and the doped conductive layer on the second region until the textured structure on the second region is exposed, and retaining the tunneling layer and the doped conductive layer on the first region; performing a polishing process on the second region to remove the textured structure on the second region and obtain a polished surface; forming a functional layer on the surface of the doped conductive layer and the polished surface; forming a first electrode, the first electrode being in electrical contact with the doped conductive layer.

[0010] In some embodiments, removing the tunneling layer and the doped conductive layer on the second region includes: using a laser ablation process to remove the tunneling layer and the doped conductive layer on the second region.

[0011] In some embodiments, the process parameters of the laser ablation process include: the wavelength of the laser is 355 nm to 532 nm, the power density is 2 J / cm² to 5 J / cm², and the spot size is 100 μm to 200 μm.

[0012] In some embodiments, in the process step of sequentially forming a tunneling layer and a doped conductive layer on the surface of the textured structure, it further includes: forming a first doping source layer on the surface of the doped conductive layer; the manufacturing method further includes: in the same process step, removing the first doping source layer located on the second region and the tunneling layer and the doped conductive layer on the second region; and after the polishing process, removing the first doping source layer located on the first region.

[0013] In some embodiments, the first doping source layer is further formed on the second surface, and the tunneling layer and the doped conductive layer are further formed on the second surface, and the tunneling layer and the doped conductive layer located on the second surface are between the second surface and the first doping source layer; the manufacturing method further includes: after removing the tunneling layer and the doped conductive layer on the second region and before the polishing process, removing the first doping source layer on the second surface to expose the doped conductive layer on the second surface; in the process step of performing the polishing process, the tunneling layer and the doped conductive layer on the second surface are also removed.

[0014] In some embodiments, before forming the tunneling layer and the doped conductive layer, a second doping source layer is further formed on the textured structure; the manufacturing method further includes: removing the second doping source layer on the first surface; performing a rounding process on the textured structure on the first surface to increase the corner curvature radius of the textured structure.

[0015] In some embodiments, the process parameters of the rounding treatment include: providing an etching solution to the textured structure, and the etching solution etches the textured structure; wherein, the etching solution is an aqueous solution of hydrofluoric acid and nitric acid, and the volume ratio of hydrofluoric acid, nitric acid and water is 1:(2-4):(9-11), the process temperature is 25°C to 40°C, and the process duration is 60 s to 180 s; or, the etching solution is an aqueous solution of ozone and hydrofluoric acid, the concentration of ozone is 20 ppm to 100 ppm, the mass percentage of hydrofluoric acid is 0.1% to 1%, the process temperature is 20°C to 30°C, and the process duration is 60 s to 180 s.

[0016] According to some embodiments of the present application, on the other hand, an embodiment of the present application further provides a photovoltaic module, including: a battery string, which is formed by connecting a plurality of solar cells as described in the above embodiments, or, a solar cell formed by the manufacturing method of the solar cells as described in the above embodiments; an encapsulation adhesive film, which is used to cover the surface of the battery string; a cover plate, which is used to cover the surface of the encapsulation adhesive film away from the battery string.

[0017] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages: The solar cell provided by the embodiment of the present disclosure includes a substrate, the substrate includes opposite first and second surfaces, the first surface includes alternately arranged first and second regions, the first region has a textured structure, and a tunneling layer and a doped conductive layer are sequentially covered on the first region, which is beneficial to increasing the contact area between the first electrode and the doped conductive layer, improving the carrier transport channel, reducing the contact resistance, and thus improving the fill factor; the second region is a polished surface, the functional layer is in contact with the polished surface and is also located on the surface of the doped conductive layer. Since the second region is a polished surface, it is beneficial to increasing the absorption of long-wavelength light in the second region and reducing the generation of dangling bonds in the second region. The direct contact between the functional layer and the polished surface is beneficial to achieving an excellent passivation effect. In addition, there is no tunneling layer and doped conductive layer on the second region to reduce the parasitic absorption phenomenon and increase the short-circuit current density. Therefore, the photoelectric conversion efficiency of the solar cell provided by the embodiment of the present disclosure can be improved. Description of the Drawings

[0018] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute a limitation on the embodiments, unless otherwise stated, the figures in the drawings do not constitute a proportional limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1 It is a schematic structural diagram of a traditional solar cell; Figure 2 It is a schematic structural diagram of a solar cell provided by an embodiment of the present application; Figure 3 It is a schematic structural diagram of another solar cell provided by an embodiment of the present application; Figure 4 It is a schematic structural diagram of yet another solar cell provided by an embodiment of the present application; Figure 5 It is a schematic diagram of the substrate structure corresponding to the step of providing a substrate in the manufacturing method of the solar cell provided by an embodiment of the present application; Figure 6 It is for Figure 5 the schematic structural diagram after texturing the substrate shown; Figure 7 It is for Figure 6 the schematic structural diagram after forming a tunneling layer and a doped conductive layer on the structure shown; Figure 8 It is for Figure 7 the schematic structural diagram after removing the tunneling layer and the doped conductive layer on the second region from the structure shown; Figure 9 It is for Figure 8 the schematic structural diagram after polishing the second region on the structure shown; Figure 10 It is for Figure 9 a schematic structural diagram after forming a functional layer on the structure shown; Figure 11 It is for Figure 10 the schematic structural diagram after forming a first electrode and a second electrode on the structure shown; Figure 12 It is for Figure 9 another schematic structural diagram after forming a functional layer, a first electrode and a second electrode on the structure shown; Figure 13 It is a partial three - dimensional schematic structural diagram of a photovoltaic module provided by an embodiment of the present application; Figure 14 It is for Figure 13 a schematic cross - sectional structural diagram along the cross - section direction NN1.

[0020] Explanation of reference numerals: Substrate 11, back surface 12, front surface 13, tunneling layer 14, doped conductive layer 15, functional layer 16, back electrode 17 and front electrode 18; Solar cell 100, substrate 110, first surface 101, second surface 102, first region Ⅰ, second region Ⅱ, textured structure 111, polished surface 121, first electrode 131, second electrode 112, tunneling layer 103, doped conductive layer 104, functional layer 105, passivation layer 115, antireflection layer 125, encapsulation film 201, cover plate 202 and conductive strip 203. Detailed implementation

[0021] Figure 1 It is a schematic structural diagram of a traditional solar cell. Exemplarily, the manufacturing method of a traditional solar cell includes: Provide a substrate 11, which includes a back surface 12 and a front surface 13.

[0022] Texturize the substrate 11 to form a textured structure on both the front surface 13 and the back surface 12 of the substrate 11.

[0023] Perform boron diffusion on the front surface 13 to form a P-type emitter. In this process, BSG (Boron Silicate Glass) is formed simultaneously.

[0024] Remove the BSG on the back surface 12 and form a polished surface through polishing. During the process of boron diffusion on the front surface 13, boron atoms will not only diffuse to the front surface 13, but also to the back surface 12 and the edge of the substrate 11, that is, a layer of BSG will also be formed on the back surface 12 of the substrate 11. To ensure the performance of the solar cell, it is usually necessary to remove the BSG on the front surface 13 and the back surface 12.

[0025] Sequentially form a tunneling layer 14 and a doped conductive layer 15 on the back surface 12. The specific steps of forming the doped conductive layer 15 include depositing a layer of polysilicon on the tunneling oxide layer and doping it by phosphorus diffusion or ion implantation, and forming PSG (Phospho Silicate Glass) after phosphorus diffusion.

[0026] Remove the PSG on the front surface 13 and the tunneling layer 14 and the doped conductive layer 15 on the front surface 13. During the process of phosphorus doping on the back surface 12, phosphorus diffusion will reach the front surface 13 of the substrate 11, thereby forming PSG on the front surface 13. To ensure the battery performance, it is usually necessary to remove the PSG on the front surface 13 and the back surface 12.

[0027] Form a functional layer 16 on both the front surface 13 and the back surface 12. Specifically, form the functional layer 16 on the surface of the doped conductive layer 15 and the textured structure.

[0028] Form electrodes on the front surface 13 and the back surface 12. The back electrode 17 is in electrical contact with the doped conductive layer 15, and the front electrode 18 is in direct contact with the emitter.

[0029] Reference Figure 1 For Figure 1 , the back surface 12 structure of the solar cell chip mostly adopts a full-coverage structure of a polished surface, a tunneling layer 14, and a doped conductive layer 15. First of all, although the back surface 12 structure of the solar cell chip adopting a polished surface can effectively reduce the surface recombination rate and provide a good passivation effect, due to its smooth surface characteristics, the contact area between the substrate 11 and the electrode is small, resulting in a high contact resistance. The high contact resistance will increase the energy loss during the current transmission process, thereby reducing the fill factor and further affecting the overall conversion efficiency of the solar cell chip. In addition, the full coverage of the tunneling layer 14 and the doped conductive layer 15 on the back surface 12 of the solar cell chip will cause a significant parasitic absorption phenomenon, that is, part of the incident light is absorbed by the doped conductive layer 15 and cannot be effectively transmitted to the substrate 11, thereby reducing the number of available photons and significantly affecting the performance of the solar cell chip, and further reducing the overall conversion efficiency of the solar cell chip.

[0030] To solve or improve at least the above technical problems, the present disclosure provides a solar cell chip, a manufacturing method thereof, and a photovoltaic module. The solar cell chip includes a substrate, and the first surface of the substrate is divided into alternately arranged first regions and second regions. Among them, the first region adopts a textured surface structure to increase the contact area between the first electrode and the doped conductive layer, thereby improving the fill factor and current collection efficiency; the second region is a polished surface with a smooth surface, which can achieve excellent passivation effect and effectively reduce the surface recombination rate. In terms of the layer structure design, a tunneling layer and a doped conductive layer are sequentially arranged in the first region to achieve good carrier selective transmission and interface passivation; the tunneling layer and the doped conductive layer are not arranged in the second region, avoiding the parasitic absorption phenomenon and retaining good optical performance and passivation effect. In addition, a functional layer is further deposited on the doped conductive layer and the polished surface, thereby significantly improving the overall photoelectric conversion efficiency of the solar cell chip.

[0031] In the description of the embodiments of the present application, technical terms such as "first" and "second" are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity, specific order or primary-secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "a plurality" is more than two, unless otherwise specifically defined. Similarly, "a plurality of groups" means two or more groups (including two groups), and "a plurality of pieces" means two or more pieces (including two pieces).

[0032] References to "embodiments" in this disclosure mean that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive of other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0033] In the description of the embodiments of the present application, the term "and / or" is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: the existence of A, the simultaneous existence of A and B, and the existence of B. Additionally, the character " / " in this disclosure generally represents an "or" relationship between the associated objects before and after.

[0034] In the description of the embodiments of the present application, the orientation or positional relationship indicated by technical terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. This is only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation on the embodiments of the present application. For example, if the device or element in the drawing is inverted, then the element described as "below" or "beneath" or "under" or "at the bottom" of other elements or features will be oriented "above" or "at the top" of the other elements or features. Thus, the term "below" can cover both the upper and lower orientations depending on the context in which the term is used, which will be obvious to those of ordinary skill in the art. The material can be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptors used herein can be interpreted accordingly.

[0035] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "joined", "fixed", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can also be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0036] In the accompanying drawings corresponding to the embodiments of the present application, for better understanding and convenience of description, the thickness and area of the layers are enlarged. In addition, when it is described that a component is "substantially" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a partial edge of the entire surface.

[0037] In the description of the embodiments of the present application, when a certain component "comprises" another component, unless otherwise specified, other components are not excluded, and other components may further be included. That the second component is formed or disposed above or on the first component, or, is formed or disposed on the surface of the first component, or, is formed or disposed on one side of the first component, may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components may be provided between the first component and the second component such that the first component and the second component may not be in direct contact. For simplicity and clarity, various components may be drawn at arbitrary scales. In the drawings, some layers / components may be omitted for simplicity. Unless otherwise specified, that the second component is formed or disposed on the surface of the first component means that the first component and the second component are in direct contact. Among them, the above-mentioned "component" may refer to a layer, a film, a region, a part, a structure, etc.

[0038] The terms used in the description of the various embodiments herein are only for describing specific embodiments and are not intended to be limiting. As used in the description of the various embodiments and the appended claims, "the component" is also intended to include the plural form unless the context clearly indicates otherwise. Among them, the component includes components such as a layer, a film, a region, or a plate.

[0039] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are presented for the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0040] Figures 2 to 4 It is a schematic structural diagram of a solar cell provided for the embodiments of the present disclosure.

[0041] Reference Figures 2 to 4, a solar cell 100, comprising: a substrate 110 and a first electrode 131; the substrate 110 includes opposite first and second surfaces 101 and 102, the first surface 101 includes alternately arranged first regions Ⅰ and second regions Ⅱ, the first regions Ⅰ have a textured surface structure 111, and the second regions Ⅱ are polished surfaces 121. A tunneling layer 103, a doped conductive layer 104, and a functional layer 105 are sequentially disposed on the first regions Ⅰ, and the functional layer 105 is also located on the second regions Ⅱ; wherein, the functional layer 105 located on the second regions Ⅱ is in contact with the polished surface 121; the first electrode 131 is located on the first regions Ⅰ, and the first electrode 131 is in electrical contact with the doped conductive layer 104.

[0042] In some embodiments, the solar cell is a single-sided cell, then the second surface 102 of the substrate 110 can be used as the light-receiving surface for receiving incident light, and the first surface 101 is used as the backlight surface. In some embodiments, the solar cell is a double-sided cell, then both the second surface 102 and the first surface 101 of the substrate 110 can be used as the light-receiving surfaces and can be used to receive incident light. It can be understood that the backlight surface referred to in the embodiments of the present application can also receive incident light, but the degree of receiving incident light is weaker than that of the light-receiving surface, so it is defined as the backlight surface.

[0043] In some embodiments, a texturing process can be performed on at least one of the second surface 102 or the first surface 101 of the substrate 110 to form a textured surface on at least one of the second surface 102 or the first surface 101 of the substrate 110. In this way, the absorption and utilization rate of incident light by the second surface 102 and the first surface 101 of the substrate 110 can be enhanced. In some embodiments, the textured surface can be a pyramid textured surface. As a common textured surface, the pyramid textured surface not only reduces the reflectivity of the substrate surface, but also forms a light trap, enhances the absorption effect of the substrate on incident light, and improves the photoelectric conversion efficiency of the solar cell.

[0044] Specifically, if the solar cell is a single-sided cell, a textured surface can be formed on the light-receiving surface of the substrate 110, for example, it can be a pyramid textured surface, and the backlight surface of the substrate can be a polished surface, that is, the backlight surface of the substrate is flatter than the light-receiving surface. It should be noted that for a single-sided cell, a textured surface can also be formed on both the light-receiving surface and the backlight surface of the substrate 110.

[0045] If the solar cell is a double-sided cell, a textured surface can be formed on both the light-receiving surface and the backlight surface of the substrate 110.

[0046] For those skilled in the art, the first surface 101 can be divided into a first region Ⅰ and a second region II. Among them, the first region Ⅰ is generally used to refer to the relative region where the first electrode 131 is formed in the subsequent metallization process, and the second region II is generally used to refer to other regions except the first region I. The first region Ⅰ adopts a textured surface structure design, aiming to significantly improve the contact performance between the first electrode and the doped conductive layer, thereby effectively reducing the contact resistance. This optimization not only improves the current transmission efficiency but also enhances the fill factor, thus improving the overall conversion efficiency of the solar cell. The second region II adopts a polished surface design, which can provide excellent passivation effects and significantly reduce the surface recombination rate. This design helps to improve the photoelectric conversion efficiency and ensure that more photo-generated carriers are effectively collected. This partition design not only ensures the good contact performance of the first region Ⅰ but also achieves an efficient passivation effect in the second region II, thereby improving the performance of the solar cell as a whole.

[0047] Reference Figure 2 , in some embodiments, since the first region Ⅰ adopts a textured surface structure and the tunneling layer 103 and the doped conductive layer 104 are usually thin, the tunneling layer 103 and the doped conductive layer 104 formed on the first region Ⅰ are also conformal to the textured surface structure. The textured surface structure increases the contact area between the first electrode 131 and the doped conductive layer 104 through its microscopic pyramid shape or random texture, significantly improving the contact performance between the first electrode 131 and the doped conductive layer 104, and thus improving the light conversion efficiency.

[0048] The second region II does not have the tunneling layer 103 and the doped conductive layer 104 to reduce the parasitic absorption effect of the second region II on carrier transport, so that more photons can be transmitted to the substrate 110, thereby increasing the short-circuit current.

[0049] The tunneling layer 103 is arranged in the first region Ⅰ of the substrate 110, so that the tunneling layer 103 has a chemical passivation effect on the first region Ⅰ of the substrate 110. Specifically, by saturating the dangling bonds in the first region Ⅰ of the substrate 110, the density of defect states in the first region Ⅰ of the substrate 110 is reduced, and the recombination centers on the surface of the substrate 110 are reduced to lower the carrier recombination rate.

[0050] In some embodiments, the material of the tunneling layer 103 can include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or magnesium fluoride.

[0051] The doped conductive layer 104 is located above the tunneling layer 103. The concentration of the doping element in the doped conductive layer 104 is greater than that of the doping element in the substrate 110, so as to form a sufficiently high potential barrier in the first region Ⅰ, which can induce the band bending of the material of the substrate, realize the aggregation of majority carriers (also known as majority carriers) and the depletion of minority carriers (also known as minority carriers) in the first region Ⅰ, and reduce the carrier recombination in the first region Ⅰ. The doped conductive layer 104 also has a field passivation effect. Specifically, the doped conductive layer 104 forms an electrostatic field pointing into the interior of the substrate 110 in the first region Ⅰ, causing the minority carriers to escape from the interface, thereby reducing the minority carrier concentration, reducing the carrier recombination rate at the interface of the first region Ⅰ, and thus increasing the open-circuit voltage, short-circuit current and fill factor of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.

[0052] The material of the doped conductive layer 104 may include at least one of amorphous silicon, polycrystalline silicon or silicon carbide.

[0053] The doped conductive layer 104 may be doped with the same type of doping element as the substrate 110. For example, if the doping element type of the substrate 110 is P-type, the doping element type in the doped conductive layer 104 may also be P-type; if the doping element type of the substrate 110 is N-type, the doping element type in the doped conductive layer 104 may also be N-type.

[0054] It can be seen from this that the tunneling layer 103 and the doped conductive layer 104 provide good surface passivation for the first region Ⅰ. The tunneling layer can allow the majority carriers to tunnel into the doped conductive layer 104 while blocking the recombination of minority carriers, enabling the majority carriers to be laterally transported in the doped conductive layer 104 and collected by the metal electrode, thereby greatly reducing the metal contact recombination current and improving the open-circuit voltage and short-circuit current of the solar cell.

[0055] In the embodiments of the present disclosure, both the first region Ⅰ and the second region Ⅱ have a functional layer 105. Specifically, in the first region Ⅰ, the functional layer 105 is located above the doped conductive layer 104. Refer to Figure 2 , in some embodiments, the functional layer 105 located above the doped conductive layer 104 is also a textured structure. In the second region Ⅱ, the functional layer 105 is located on the polished surface 121 and is in direct contact with the polished surface 121. The functional layer 105 can provide good passivation for the first surface 101. For example, it can chemically passivate the dangling bonds on the first surface 101 well, saturate the dangling bonds on the first surface 101, reduce the density of defect states on the first surface 101, and inhibit the carrier recombination on the first surface 101.

[0056] The material of the functional layer 105 may be one of silicon oxide, aluminum oxide, silicon nitride or silicon oxynitride.

[0057] The functional layer 105 can be a single-layer structure or a multi-layer structure. For a multi-layer structure, the materials of different layers can be different from each other, or the materials of some layers can be the same and different from those of other layers. For example, the functional layer 105 can be a laminated structure of a silicon nitride layer and an aluminum oxide layer.

[0058] The first electrode 131 is located on the first region Ⅰ and is in electrical contact with the doped conductive layer 104. Refer to Figure 2 , in some embodiments, since the doped conductive layer 104 has a matte surface structure, the contact surface between the first electrode 131 and the doped conductive layer 104 is also matte. Since the first region Ⅰ adopts the matte surface structure 111, the contact area between the first electrode 131 and the doped conductive layer 104 is increased, thereby reducing the contact resistance and improving the current transmission efficiency. The second electrode 112 is located on the second surface 102 and is in electrical contact with the emitter.

[0059] The substrate 110 is the core part of the solar cell chip and is used to absorb light energy and generate photo-generated carriers (electrons and holes). In some embodiments, the material of the substrate 110 can be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, such as silicon or germanium. Among them, the elemental semiconductor material can be in single crystal state, polycrystalline state, amorphous state or microcrystalline state (the state with both single crystal state and amorphous state is called microcrystalline state). For example, silicon can be at least one of single crystal silicon, polycrystalline silicon, amorphous silicon or microcrystalline silicon, and the material of the substrate 110 can include at least one of single crystal silicon, polycrystalline silicon, amorphous silicon or microcrystalline silicon.

[0060] In some embodiments, the material of the substrate 110 can also be a compound semiconductor material. Common compound semiconductor materials include but are not limited to silicon germanide, silicon carbide, gallium arsenide, indium gallium, perovskite, cadmium telluride, copper indium selenide, etc. The material can also be silicon carbide, organic material or multi-element compound. The multi-element compound can include but is not limited to perovskite, gallium arsenide, cadmium telluride, copper indium selenide, etc.

[0061] The substrate 110 can also be a sapphire substrate, a substrate on insulator or a germanium substrate on insulator.

[0062] The substrate 110 can be an N-type semiconductor substrate or a P-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type doping element, and the N-type doping element can be any one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb) or arsenic (As). The P-type semiconductor substrate is doped with a P-type element, and the P-type doping element can be any one of group III elements such as boron (B), aluminum (Al), gallium (Ga) or indium (In).

[0063] The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0064] Reference Figure 3 In some embodiments, the suede structure is a smooth pyramid suede structure.

[0065] Although the pyramid structure can improve the contact performance, due to its sharp corners, it is easy to cause uneven thickness of the tunneling layer 103 and the doped conductive layer 104 during the deposition process. In particular, insufficient coverage may occur at the corners. And in subsequent high-temperature processes (such as annealing, sintering, etc.), these sharp corners are prone to cracking or deformation, thus destroying the original good passivation effect and increasing the surface recombination rate.

[0066] Different from the traditional sharp pyramid structure, the smooth pyramid suede structure has a smoother surface morphology, reducing the presence of sharp corners. This design not only retains the advantages of the suede structure but also avoids the problems caused by sharp corners. Since the surface of the pyramid suede is smoother, the tunneling layer 103 and the doped conductive layer 104 can be uniformly deposited on the entire surface, reducing the thickness non-uniformity caused by corners and ensuring a better passivation effect. Moreover, the smooth surface morphology exhibits higher mechanical stability in high-temperature processes and is not easily cracked or deformed, thus maintaining the integrity of the passivation effect.

[0067] In the embodiments of the present disclosure, the first region I adopts a smooth pyramid suede structure, and the tunneling layer 103 and the doped conductive layer 104 are sequentially arranged on the smooth pyramid suede structure, which can ensure the uniformity and integrity of these tunneling layer 103 and doped conductive layer 104, further enhancing the passivation effect and the conductive performance.

[0068] In some embodiments, the radius of curvature of the corners of the pyramid suede is 100 nm to 300 nm.

[0069] The radius of curvature of the corners is used to describe the degree of bending of the corners of the pyramid suede. In the embodiments of the present disclosure, the originally sharp corners of the pyramid suede structure become smooth after treatment, and the radius of the best-fitting circle of these smooth corners ranges from 100 nm to 300 nm. For example, it can be specifically 100 nm, 150 nm, 200 nm, 250 nm, or 300 nm.

[0070] If the radius of curvature is less than 100 nm, the edges and corners are too sharp to solve the problems of uneven deposition of the tunneling layer 103 and the doped conductive layer 104 and vulnerability in high-temperature processes. If the radius of curvature is greater than 300 nm, although the edges and corners can be further smoothed, the original structure of the pyramid texture may be overly changed, affecting its original optical properties (such as light trapping ability). Therefore, by controlling the radius of curvature of the edges and corners within the range of 100 nm to 300 nm, the problems of uneven deposition of the tunneling layer 103 and the doped conductive layer 104 and vulnerability in high-temperature processes can be solved, and the original optical properties of the pyramid texture can be ensured to be unaffected.

[0071] In some embodiments, the range of 100 nm to 300 nm is further subdivided into three sub-intervals: 100 nm to 150 nm, 150 nm to 250 nm, and 250 nm to 300 nm.

[0072] Specifically, when the radius of curvature of the edges and corners of the pyramid texture is between 100 nm and 150 nm, the edges and corners are relatively smooth but still retain a certain sharpness. Compared with the case where the radius of curvature is less than 100 nm, this degree of smoothness improves the uniformity and integrity of the deposition of the tunneling layer 103 and the doped conductive layer 104, reducing the risk of local fracture. When the radius of curvature of the edges and corners of the pyramid texture is between 150 nm and 250 nm, the edges and corners are relatively smooth, significantly reducing the sharp parts. At this degree of smoothness, the deposition uniformity of the tunneling layer 103 and the doped conductive layer 104 is optimal: the smooth edges and corners ensure the uniform deposition of the tunneling layer 103 and the doped conductive layer 104, avoiding the problems of uneven thickness and local fracture of the tunneling layer 103 and the doped conductive layer 104. When the radius of curvature of the edges and corners of the pyramid texture is between 250 nm and 300 nm, the edges and corners are very smooth, almost eliminating the sharp edges. At this degree of smoothness of the edges and corners, while ensuring good deposition uniformity of the tunneling layer 103 and the doped conductive layer 104, it will not overly change the original structure of the pyramid texture and affect its original optical properties.

[0073] Reference Figure 4 Referring to

[0074] Although the doped conductive layer 104 itself provides a certain degree of passivation effect through the field effect, the introduction of the passivation layer 115 can further reduce the defects and dangling bonds at the interface and improve the passivation effect. The passivation layer 115 can also protect the doped conductive layer 104 from contamination or damage in subsequent processes.

[0075] Although the polished surface 121 provides a good surface quality, there may still be a small number of surface defects. The passivation layer 115 can reduce these defects through a chemical passivation mechanism, further reducing the surface recombination rate.

[0076] By adjusting its refractive index and thickness, the antireflection layer 125 enables incident light to enter the interior of the solar cell to the greatest extent rather than being reflected, which can significantly improve the utilization rate of light, thereby enhancing the short-circuit current and the overall conversion efficiency of the solar cell.

[0077] The antireflection layer 125 is usually made of materials with specific refractive indices, which can form a matching optical interface with air and the underlying passivation layer 115, thus reducing the reflection loss at the interface. For example, the antireflection layer materials include silicon nitride (SiNx), silicon oxynitride, or silicon oxide, whose refractive indices are between that of air and silicon, and can effectively reduce the reflection loss at the interface.

[0078] Reference Figures 2 to 4 , the second surface 102 has a textured surface structure, a functional layer 105 is provided on the surface of the textured surface structure, and a second electrode 112 is formed on the second surface 102. The second electrode 112 is in electrical contact with the emitter.

[0079] The second surface 102 adopts a textured surface structure, which is beneficial to enhancing the absorption and utilization rate of incident light by the second surface 102. In some embodiments, the textured surface structure can be a pyramid textured surface. The pyramid texture not only reduces the reflectivity of the second surface 102 but also forms a light trap, enhancing the absorption effect of the second surface 102 on incident light and improving the photoelectric conversion efficiency of the solar cell. The functional layer 105 covers the textured surface structure. The functional layer 105 can play a good passivation role on the second surface 102.

[0080] In the solar cell provided by the embodiment of the present application, the first surface 101 of the substrate 110 includes alternately arranged first regions Ⅰ and second regions Ⅱ. The first regions Ⅰ adopt a matte structure 111, and a tunneling layer 103 and a doped conductive layer 104 are sequentially covered on the first regions Ⅰ, which is beneficial to increasing the contact area between the first electrode 131 and the doped conductive layer 104, improving the carrier transport channel, reducing the contact resistance, and further increasing the fill factor. The second regions Ⅱ are polished surfaces 121, and the functional layer 105 is in contact with the polished surfaces 121 and is also located on the surface of the doped conductive layer 104. Since the second regions Ⅱ are polished surfaces 121, it is beneficial to increase the absorption of light in the long wavelength band by the second regions Ⅱ and reduce the generation of dangling bonds in the second regions Ⅱ. The direct contact between the functional layer 105 and the polished surfaces 121 is beneficial to achieving an excellent passivation effect. In addition, there are no tunneling layer 103 and doped conductive layer 104 on the second regions Ⅱ to reduce the parasitic absorption phenomenon and increase the short-circuit current density. Therefore, the photoelectric conversion efficiency of the solar cell provided by the embodiment of the present disclosure can be improved.

[0081] Correspondingly, another embodiment of the present application further provides a manufacturing method of a solar cell, which can be used to manufacture the solar cell provided by the above embodiment. The manufacturing method of the solar cell provided by another embodiment of the present application will be described in detail below with reference to the accompanying drawings. For the same or corresponding parts as those in the previous embodiment, reference may be made to the corresponding description of the previous embodiment, and details will not be described in detail below.

[0082] The manufacturing method of the solar cell provided by the embodiment of the present application includes: providing a substrate, the substrate includes opposite first and second surfaces, and the first surface includes alternately arranged first and second regions; performing a texturing process on the substrate to form a matte structure on the first surface; sequentially forming a tunneling layer and a doped conductive layer on the surface of the matte structure; removing the tunneling layer and the doped conductive layer on the second region until the matte structure on the second region is exposed, and retaining the tunneling layer and the doped conductive layer on the first region; performing a polishing process on the second region to remove the matte structure on the second region and obtain a polished surface; forming a functional layer on the surface of the doped conductive layer and the polished surface; forming a first electrode, and the first electrode is in electrical contact with the doped conductive layer.

[0083] Refer to Figure 5 , provide a substrate 110, the substrate 110 includes opposite first and second surfaces 101 and 102, and the first surface 101 of the substrate 110 includes alternately arranged first regions Ⅰ and second regions Ⅱ.

[0084] Refer to Figure 6 , perform a texturing process on the substrate 110 to form a matte structure 111 on the first surface 101, and at the same time form a matte structure 111 on the second surface 102.

[0085] In some embodiments, a textured structure 111 can be formed on the surface of the substrate 110 by double-sided alkaline solution texturing. For example, the substrate is etched with an alkaline solution having a concentration of 1.5 wt% to 3 wt% in a temperature range of 60 °C to 90 °C. Commonly used alkaline solutions include sodium hydroxide or potassium hydroxide to form a double-sided pyramid textured structure with a height of 1 μm to 5 μm. The reflectivity of the textured structure of the pyramid is ≤ 10%, which can effectively scatter incident light, thereby reducing surface reflection and significantly improving the light absorption efficiency.

[0086] Reference Figure 7 , a tunneling layer 103 and a doped conductive layer 104 are sequentially formed on the surface of the textured structure. That is, a tunneling layer 103 is formed on the surface of the textured structure, and then a doped conductive layer 104 is formed on the tunneling layer 103.

[0087] In some embodiments, a 1 nm to 2 nm thick silicon oxide layer can be formed as the tunneling layer 103 on the first surface 101 in a temperature range of 500 °C to 700 °C by Low Pressure Chemical Vapor Deposition (LPCVD) technology; then a 100 nm to 150 nm thick phosphorus-doped amorphous silicon layer (doping concentration of 1×10^19 atoms / cm³ to 5×10^20 atoms / cm³) is deposited on the silicon oxide layer as the doped conductive layer 104; and an annealing treatment is performed in a nitrogen atmosphere at 700 °C to 800 °C for 10 min to 30 min to convert the amorphous silicon layer into a polycrystalline silicon layer, improving its crystallinity and electrical properties.

[0088] In some embodiments, in the process steps of sequentially forming the tunneling layer 103 and the doped conductive layer 104 on the surface of the textured structure 111, it further includes: forming a first doping source layer on the surface of the doped conductive layer 104.

[0089] Exemplarily, the first doping source layer is PSG. PSG is a silicon glass containing phosphorus elements and is usually formed on the surface of the doped conductive layer 104 by Chemical Vapor Deposition (CVD) or other methods. PSG can be used as a diffusion source for phosphorus. During subsequent high-temperature annealing, phosphorus atoms will diffuse into the substrate to form an n+ doped region, thereby enhancing the field effect passivation effect. PSG itself also has a certain passivation ability, which can further reduce surface defects and dangling bonds and lower the surface recombination rate. PSG can also be used as a protective layer to prevent contamination or damage to the doped conductive layer 104 during subsequent processes.

[0090] Reference Figure 8, the tunneling layer 103 and the doped conductive layer 104 on the second region II are removed until the suede structure 111 on the second region II is exposed, and the tunneling layer 103 and the doped conductive layer 104 on the first region I are retained.

[0091] In some embodiments, the manufacturing method further includes: in the same process step, removing the first doping source layer on the second region II, as well as the tunneling layer 103 and the doped conductive layer 104 on the second region II.

[0092] Reference Figure 9 , the second region II is polished to remove the suede structure 111 on the second region II and obtain a polished surface 121.

[0093] Optionally, the substrate 110 can be polished in an alkali solution with a concentration of 1 wt% to 5 wt% at a temperature in the range of 60 °C to 75 °C for 1 min to 5 min to obtain the polished surface 121, reduce reflection loss and improve light absorption efficiency.

[0094] In some embodiments, after the polishing process, the first doping source layer on the first region I is removed.

[0095] Reference Figure 10 , a functional layer 105 is formed on the surface of the doped conductive layer 104 and the polished surface 121, and the functional layer 105 is also formed on the second surface 102.

[0096] Reference Figure 11 , a first electrode 131 is formed, and the first electrode 131 is in electrical contact with the doped conductive layer 104; a second electrode 112 is formed on the second surface 102, and the second electrode 112 is in electrical contact with the emitter. Optionally, the first electrode 131 and the second electrode 112 are formed by double-sided screen printing technology and high-temperature sintering. For example, silver paste is precisely printed on the first surface 101 and the first region I using screen printing technology, and the printed silver paste is sintered at a temperature of 500 °C to 900 °C to cure the silver paste printed on the substrate 110 and form a good ohmic contact with the substrate 110.

[0097] Reference Figure 12 , in some embodiments, the functional layer 105 includes a passivation layer 115 and an antireflection layer 125, and the antireflection layer 125 is located on the surface of the passivation layer 115.

[0098] Optionally, using Atomic Layer Deposition (ALD) technology, an alumina layer with a thickness of 5 nm to 12 nm is deposited on the first surface 101 and the second surface 102 as the passivation layer 115. The passivation layer 115 can significantly reduce the surface recombination rate and increase the open-circuit voltage of the solar cell. And using Tubular Plasma Enhanced Chemical Vapor Deposition (Tube PECVD) technology, a silicon nitride or silicon oxynitride layer with a thickness of 80 nm to 100 nm is deposited on the first surface 101 and the second surface 102 as the antireflection layer 125. The antireflection layer 125 reduces the reflection loss of light and increases the light absorption efficiency by optimizing the thickness and refractive index. In addition, the passivation layer 115 and the antireflection layer 125 also provide an additional surface passivation effect, further improving the overall performance of the solar cell.

[0099] In some embodiments, removing the tunneling layer 103 and the doped conductive layer 104 on the second region includes: using a laser ablation process to remove the tunneling layer 103 and the doped conductive layer 104 on the second region.

[0100] Laser ablation can very precisely remove the material in the specified area without affecting the surrounding structures. Using the laser ablation process can remove the tunneling layer 103 and the doped conductive layer 104 on the second region II while retaining the tunneling layer 103 and the doped conductive layer 104 on the first region I. And laser ablation is a non-contact processing method that can remove the target material without damaging the substrate. This helps to maintain the integrity and performance of the substrate.

[0101] In some embodiments, the process parameters of the laser ablation process include: the wavelength of the laser is 355 nm to 532 nm, for example, specifically it can be 355 nm or 532 nm; the power density is 2 J / cm² to 5 J / cm², for example, specifically it can be 2 J / cm², 3 J / cm², 4 J / cm² or 5 J / cm²; this power density range can ensure effective material removal while preventing problems such as overburning, microcracks or interface damage caused by excessive energy, thereby improving the edge quality and structural integrity of the ablation area. The spot size is 100 μm to 200 μm, for example, specifically it can be 100 μm, 120 μm, 170 μm or 180 μm.

[0102] Reference Figure 7, in some embodiments, the first doping source layer is further formed on the second surface 102, and the tunneling layer 103 and the doped conductive layer 104 are further formed on the second surface 102. The tunneling layer 103 and the doped conductive layer 104 on the second surface 102 are located between the second surface 102 and the first doping source layer, that is, the first doping source layer further covers the second surface 102.

[0103] In some embodiments, the manufacturing method further includes: after removing the tunneling layer 103 and the doped conductive layer 104 on the second region II and before the polishing process, removing the first doping source layer on the second surface 102 to expose the doped conductive layer 104 on the second surface 102; for example, using a hydrofluoric acid solution with a mass percentage of 5% - 10% to remove the first doping source layer on the second surface 102. In the process step of the polishing process, the tunneling layer 103 and the doped conductive layer 104 on the second surface 102 are also removed.

[0104] During the polishing process, the first doping source layer on the first region I serves to protect the tunneling layer 103 and the doped conductive layer 104 on the first region I. Due to the presence of the first doping source layer on the first region I, the tunneling layer 103 and the doped conductive layer 104 on the first region I will not be removed during the polishing process.

[0105] In some embodiments, before forming the tunneling layer 103 and the doped conductive layer 104, a second doping source layer is further formed on the textured structure 111; the manufacturing method further includes: removing the second doping source layer on the first surface 101; performing a rounding process on the textured structure 111 on the first surface 101 to increase the corner curvature radius of the textured structure 111.

[0106] Before forming the tunneling layer 103 and the doped conductive layer 104 on the first surface 101, it is necessary to perform a rounding process on the textured structure 111 on the first surface 101 to improve the deposition uniformity and integrity of the subsequent tunneling layer 103 and doped conductive layer 104.

[0107] In some embodiments, the process parameters of the rounding treatment include: providing an etching solution to the textured structure 111, and the etching solution etches the textured structure 111; wherein, the etching solution is an aqueous solution of hydrofluoric acid and nitric acid, and the volume ratio of hydrofluoric acid, nitric acid and water is 1:(2-4):(9-11), for example, the volume ratio of hydrofluoric acid, nitric acid and water can specifically be 1:3:10; the process temperature is 25°C - 40°C, for example, it can specifically be 25°C, 30°C, 35°C or 40°C; the process duration is 60s - 180s, for example, it can specifically be 60s, 100s, 150s or 180s; or, the etching solution is an aqueous solution of ozone and hydrofluoric acid, the concentration of ozone is 20ppm - 100ppm, for example, it can specifically be 20ppm, 50ppm, 70ppm or 100ppm; the mass percentage of hydrofluoric acid is 0.1% - 1%, for example, it can specifically be 0.1%, 0.3%, 0.7% or 1%; the process temperature is 20°C - 30°C, for example, it can specifically be 20°C, 23°C, 27°C or 30°C; the process duration is 60s - 180s, for example, it can specifically be 60s, 100s, 150s or 180s.

[0108] The above-mentioned etching solution can selectively remove the high points or sharp parts in the textured structure 111, achieve a smooth transition on the surface, and thus effectively improve the deposition uniformity and integrity of the subsequent tunneling layer 103 and doped conductive layer 104.

[0109] In the manufacturing method of the solar cell provided by the embodiment of the present application, a first region Ⅰ and a second region Ⅱ are alternately arranged on the first surface 101 of the substrate 110. The first region Ⅰ adopts the textured structure 111, and a tunneling layer 103, a doped conductive layer 104 and a functional layer 105 are sequentially formed on the first region Ⅰ, which is beneficial to increasing the contact area between the first electrode 131 and the doped conductive layer 104, improving the carrier transport channel, reducing the contact resistance, and further increasing the fill factor. The second region Ⅱ is polished to remove the textured structure 111 on the second region Ⅱ and obtain a polished surface 121, and the functional layer 105 is formed on the polished surface 121, which is beneficial to increasing the absorption of light in the long wavelength band by the second region Ⅱ and reducing the generation of dangling bonds in the second region Ⅱ. The direct contact between the functional layer 105 and the polished surface 121 is beneficial to achieving an excellent passivation effect. Removing the tunneling layer 103 and the doped conductive layer 104 on the second region Ⅱ can effectively reduce the parasitic absorption phenomenon, increase the short-circuit current density, and significantly improve the photoelectric conversion efficiency of the solar cell chip.

[0110] According to some embodiments of the present application, on the other hand, an embodiment of the present application further provides a photovoltaic module, including a plurality of solar cells as described in the above embodiments, or a plurality of solar cells manufactured by the manufacturing method of the solar cells in the above embodiments. The following will describe in detail the photovoltaic module provided by another embodiment of the present application. For the same or corresponding parts as the previous embodiment, reference may be made to the corresponding description of the previous embodiment, and the following will not be elaborated in detail.

[0111] Figure 13 FIG. 4 is a partial three-dimensional structural schematic diagram of the photovoltaic module provided by the embodiment of the present application; Figure 14 is Figure 13 a schematic cross-sectional structural diagram along the cross-sectional direction NN1.

[0112] Referring to Figure 13 and Figure 14 , the photovoltaic module provided by the embodiment of the present application includes: a battery string, an encapsulation adhesive film 201, and a cover plate 202.

[0113] The battery string is formed by connecting a plurality of solar cells as described in the above embodiments, or is formed by connecting a plurality of solar cells manufactured by the manufacturing method of the solar cells in the above embodiments.

[0114] It should be noted that the solar cells are electrically connected to form a plurality of battery strings, and the plurality of battery strings are electrically connected in series and / or in parallel. Since the solar cell includes a segmented cell, and the segmented cell is formed by dividing a whole solar cell, thus, by means of the current drop of the segmented cell, the power loss of the photovoltaic module can be improved, so as to improve the photoelectric conversion efficiency of the photovoltaic module.

[0115] In one or more embodiments, referring to Figure 14 as shown, the plurality of battery strings can be electrically connected through a conductive strip 203. Figure 14 Only a positional relationship between the solar cells is schematically shown, that is, the arrangement directions of the electrodes with the same polarity of the solar cells are the same, or in other words, the electrodes with the positive polarity of each solar cell are arranged on the same side, so that the conductive strip is respectively connected to different sides of two adjacent solar cells. In some embodiments, the solar cells can also be arranged such that the electrodes with different polarities face the same side, that is, the electrodes of adjacent solar cells are sequentially arranged in the order of the first polarity, the second polarity, and the first polarity, then the conductive strip connects two adjacent cells on the same side.

[0116] In one or more embodiments, there is no gap between the solar cells, that is, the solar cells overlap each other.

[0117] Referring to Figure 14, the encapsulation film 201 is used to cover the surface of the battery string.

[0118] In one or more embodiments, the encapsulation film includes a first encapsulation layer and a second encapsulation layer. The first encapsulation layer covers one of the front or back sides of the solar cell, and the second encapsulation layer covers the other of the front or back sides of the solar cell. Specifically, at least one of the first encapsulation layer or the second encapsulation layer can be an organic encapsulation film such as a polyvinyl butyral (PVB) film, an ethylene-vinyl acetate copolymer (EVA) film, a polyethylene octene copolymer elastomer (POE) film, or a polyethylene terephthalate (PET) film.

[0119] In some cases, there is a dividing line between the first encapsulation layer and the second encapsulation layer before lamination. After the lamination process, there will no longer be the concept of the first encapsulation layer and the second encapsulation layer in the formed photovoltaic module, that is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film.

[0120] Reference Figure 14 , the cover plate 202 is used to cover the surface of the encapsulation film 201 away from the battery string.

[0121] In one or more embodiments, the cover plate can be a cover plate with a light-transmitting function such as a glass cover plate or a plastic cover plate. Specifically, the surface of the cover plate facing the encapsulation film can be a concave-convex surface, so as to increase the utilization rate of incident light. The cover plate includes a first cover plate and a second cover plate. The first cover plate is opposite to the first encapsulation layer, and the second cover plate is opposite to the second encapsulation layer.

[0122] In one or more embodiments, reference Figure 13 As shown, the solar cells 100 in the battery string are arranged along the direction U, and the main grids of two adjacent solar cells 100 in the battery string are staggered in the direction Y. For the photovoltaic module, by setting the main grids of two adjacent solar cells 100 in the battery string to be staggered in the direction Y, different potentials of the photovoltaic module can be tested, thereby improving the reliability of the test results.

[0123] In one or more embodiments, the photovoltaic cell includes, but is not limited to, a PERC cell (Passivated Emitter Rear Cell), an IBC cell (Interdigitated Back Contact), a TOPCon cell (Tunnel Oxide Passivated Contact), a HIT / HJT cell (Heterojunction Technology), a thin-film solar cell, or any combination thereof. Among them, the thin-film solar cell includes, but is not limited to, a perovskite thin-film solar cell, a copper indium selenide thin-film solar cell, a gallium arsenide thin-film solar cell, and a cadmium sulfide thin-film solar cell. The tandem cell includes, but is not limited to, a perovskite cell stacked with a crystalline silicon cell, a perovskite cell stacked with a perovskite cell, and a perovskite cell stacked with a thin-film cell.

[0124] In the photovoltaic module provided by the embodiment of the present application, the first surface 101 of the substrate 110 of the solar cell chip includes alternately arranged first regions I and second regions II. The first regions I adopt a matte structure 111, and a tunneling layer 103 and a doped conductive layer 104 are sequentially covered on the first regions I, which is beneficial to increasing the contact area between the first electrode 131 and the doped conductive layer 104, improving the carrier transport channel, reducing the contact resistance, and thus increasing the fill factor. The second regions II are polished surfaces 121, and the functional layer 105 is in contact with the polished surfaces 121 and is also located on the surface of the doped conductive layer 104. Since the second regions II are polished surfaces 121, it is beneficial to increasing the absorption of light in the long wavelength band by the second regions II and reducing the generation of dangling bonds in the second regions II. The direct contact between the functional layer 105 and the polished surfaces 121 is beneficial to achieving an excellent passivation effect. In addition, there are no tunneling layer 103 and doped conductive layer 104 on the second regions II to reduce the parasitic absorption phenomenon and increase the short-circuit current density. Therefore, the photoelectric conversion efficiency of the solar cell chip provided by the embodiment of the present disclosure can be improved.

[0125] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the scope defined by the claims.

Claims

1. A solar cell, characterized in that: include: A substrate, the substrate comprising a first surface and a second surface opposite to each other, the first surface comprising first areas and second areas arranged alternately, the first areas having a suede structure, and the second areas being a polished surface; The first region has a tunneling layer, a doped conductive layer and a functional layer arranged in sequence, and the functional layer is also located in the second region; wherein the functional layer located in the second region is in contact with the polishing surface; A first electrode is located on the first region, and the first electrode is in electrical contact with the doped conductive layer.

2. The solar cell according to claim 1, characterized in that: The suede structure is a smooth pyramid suede structure.

3. The solar cell according to claim 2, characterized in that: The angular curvature radius of the pyramid velvet surface is 100nm-300nm.

4. The solar cell according to claim 1, characterized in that: The functional layer comprises: A passivation layer, the passivation layer is located on the surface of the doped conductive layer and also on the polishing surface; An anti-reflection layer is located on the surface of the passivation layer.

5. A method for manufacturing a solar cell, characterized in that: include: Providing a substrate, the substrate comprising a first surface and a second surface opposite to each other, the first surface comprising first areas and second areas arranged alternately; Performing a velvet treatment on the substrate to form a velvet structure on the first surface; sequentially forming a tunneling layer and a doped conductive layer on the surface of the velvet structure; removing the tunneling layer and the doped conductive layer on the second region until the suede structure on the second region is exposed, and retaining the tunneling layer and the doped conductive layer on the first region; Polishing the second region to remove the suede structure on the second region and obtain a polished surface; forming a functional layer on the surface of the doped conductive layer and the polished surface; A first electrode is formed, the first electrode being in electrical contact with the doped conductive layer.

6. The method for manufacturing a solar cell according to claim 5, characterized in that: The removing the tunneling layer and the doped conductive layer on the second region comprises: The tunneling layer and the doped conductive layer on the second region are removed by laser ablation.

7. The method for manufacturing a solar cell according to claim 6, characterized in that: The process parameters of the laser ablation process include: the laser wavelength is 355nm~532nm, the power density is 2J / cm²~5J / cm², and the spot size is 100μm~200μm.

8. The method for manufacturing a solar cell according to any one of claims 5 to 7, characterized in that: The process step of sequentially forming the tunneling layer and the doped conductive layer on the surface of the textured structure further includes: forming a first doping source layer on the surface of the doped conductive layer; The manufacturing method further comprises: In the same process step, removing the first doping source layer located on the second region and the tunneling layer and the doped conductive layer on the second region; After the polishing process, the first doping source layer located on the first region is removed.

9. The method for manufacturing a solar cell according to claim 8, characterized in that: The first doping source layer is also formed on the second surface, and the tunneling layer and the doped conductive layer are also formed on the second surface, and the tunneling layer and the doped conductive layer located on the second surface are located between the second surface and the first doping source layer; The manufacturing method further comprises: After removing the tunneling layer and the doped conductive layer on the second region and before performing the polishing process, removing the first doping source layer on the second surface to expose the doped conductive layer on the second surface; In the process step of performing the polishing treatment, the tunneling layer and the doped conductive layer on the second surface are also removed.

10. The method for manufacturing a solar cell according to claim 5, characterized in that: Before forming the tunneling layer and the doped conductive layer, a second doping source layer is formed on the textured structure; the manufacturing method further includes: removing the second doping source layer on the first surface; The suede structure on the first surface is rounded to increase the radius of curvature of the corners of the suede structure.

11. The method for manufacturing a solar cell according to claim 10, characterized in that: The process parameters of the rounding treatment include: Providing an etching solution to the velvet structure, wherein the etching solution etches the velvet structure; Wherein, the etching solution is an aqueous solution of hydrofluoric acid and nitric acid, the volume ratio of hydrofluoric acid, nitric acid and water is 1: (2-4): (9-11), the process temperature is 25°C-40°C, and the process time is 60s-180s; or, The etching solution is an aqueous solution of ozone and hydrofluoric acid, the concentration of ozone is 20ppm~100ppm, the mass percentage of hydrofluoric acid is 0.1%~1%, the process temperature is 20℃~30℃, and the process time is 60s~180s.

12. A photovoltaic module, characterized in that: include: A battery string, formed by connecting a plurality of solar cells according to any one of claims 1 to 4, or by connecting solar cells manufactured by the method for manufacturing a solar cell according to any one of claims 5 to 11; A packaging film, used to cover the surface of the battery string; The cover plate is used to cover the surface of the packaging film away from the battery string.

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