Light emitting diode and preparation method thereof
By designing the design of opening isolation grooves on the epitaxial structure of the light emitting diode and the edge of the passivation layer, the problem of decomposition of the first passivation layer and the second passivation layer in the laser stripping process is solved, and the huge transfer accuracy is improved.
Patent Information
- Application Number
- CN202510164618.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-14
- Publication Date
- 2025-06-24
AI Technical Summary
When large amount transfer is performed by laser peeling and other processes, the first passivation layer and the second passivation layer are easily decomposed, resulting in a decrease in the accuracy of large amount transfer.
A light emitting diode is designed, and its epitaxial structure is in a step structure. The transparent conductive layer is located on the top surface of the step structure. The first passivation layer and the second passivation layer are covered on the transparent conductive layer and the metal reflective layer. An isolation groove is opened at its edge. The angle between the side wall and the bottom of the isolation groove is greater than or equal to 90 degrees.
By avoiding laser irradiation at the isolation groove, decomposition of the first passivation layer and the second passivation layer is prevented, thereby improving the huge transfer accuracy.
Smart Images
Figure CN120201826A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of light-emitting devices, and particularly to a light-emitting diode and a method for manufacturing the same. Background Art
[0002] A light-emitting diode (LED) is a semiconductor device that can emit light.
[0003] Related technologies provide a light-emitting diode. The structure of the light-emitting diode includes an epitaxial structure, a transparent conductive layer, a first passivation layer, a metal reflective layer, and a second passivation layer. The transparent conductive layer is located on the epitaxial structure. The first passivation layer covers the transparent conductive layer and the epitaxial structure. The metal reflective layer is located on the first passivation layer. The second passivation layer covers the metal reflective layer and the first passivation layer.
[0004] In related technologies, the above-structured LED can be applied to a Micro LED. When the above-structured Micro LED is subjected to mass transfer using processes such as laser lift-off, the laser will cause the first passivation layer and the second passivation layer to decompose, thereby resulting in a decrease in the mass transfer accuracy. Summary of the Invention
[0005] Embodiments of the present disclosure provide a light-emitting diode and a method for manufacturing the same, which can avoid the decomposition of the first passivation layer and the second passivation layer during processes such as laser lift-off, and thereby improve the problem of decreased mass transfer accuracy. The technical solutions are as follows:
[0006] On the one hand, a light-emitting diode is provided. The light-emitting diode includes:
[0007] An epitaxial structure, a transparent conductive layer, a first passivation layer, a metal reflective layer, and a second passivation layer;
[0008] The epitaxial structure has a stepped structure. The transparent conductive layer is located on the stepped top surface of the stepped structure. The first passivation layer covers the transparent conductive layer and the stepped structure. The metal reflective layer is located on the first passivation layer on the stepped top surface. The second passivation layer covers the metal reflective layer and the first passivation layer. Isolation grooves are formed at the edges of the second passivation layer, the first passivation layer, and the epitaxial structure. The included angle between the side wall and the bottom of the isolation groove is greater than or equal to 90 degrees.
[0009] Optionally, the width of the isolation groove is 2 to 100 μm.
[0010] Optionally, the distance between the edge of the metal reflective layer and the side wall of the isolation groove is 1.5 to 5 μm.
[0011] Optionally, the first passivation layer and the second passivation layer are respectively DBR layers;
[0012] The thicknesses of the first passivation layer and the second passivation layer are respectively 6,000 to 17,000 angstroms.
[0013] Optionally, the metal reflective layer is a stack of Ti, Al, Ti, Pt, Ti or a stack of Al, Ti, Pt, Ti or a stack of Ag, Ni, TiW.
[0014] On the other hand, a method for manufacturing a light-emitting diode is provided, and the method includes:
[0015] Fabricating an epitaxial structure, and the epitaxial structure has a stepped structure;
[0016] Fabricating a transparent conductive layer on the surface of the epitaxial structure, and the transparent conductive layer is located on the top surface of the step of the stepped structure;
[0017] Fabricating a first passivation layer, and the first passivation layer covers the transparent conductive layer and the stepped structure;
[0018] Fabricating a metal reflective layer, and the metal reflective layer is located on the first passivation layer on the top surface of the step;
[0019] Fabricating a second passivation layer, and the second passivation layer covers the first passivation layer and the metal reflective layer;
[0020] Fabricating isolation grooves, and the isolation grooves are formed at the edges of the second passivation layer, the first passivation layer and the epitaxial structure, and the included angle between the side wall and the bottom of the isolation groove is greater than or equal to 90 degrees.
[0021] Optionally, the fabricating of the isolation grooves includes:
[0022] Etching the first passivation layer and the second passivation layer with a first etching gas to form the part of the isolation groove located in the first passivation layer and the second passivation layer;
[0023] Etching the epitaxial structure with a second etching gas to form the part of the isolation groove located in the epitaxial structure.
[0024] Optionally, the etching of the first passivation layer and the second passivation layer with the first etching gas includes:
[0025] Using CF4 as the first etching gas to perform ICP etching on the first passivation layer and the second passivation layer.
[0026] Optionally, the etching of the epitaxial structure with the second etching gas includes:
[0027] Using a mixed gas of Cl2, BCl2 and HBr as the second etching gas to perform ICP etching on the epitaxial structure.
[0028] Optionally, the width of the isolation groove is 2 to 100 μm.
[0029] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure are as follows:
[0030] In the embodiments of the present disclosure, isolation grooves are provided at the edges of the second passivation layer, the first passivation layer, and the epitaxial structure. When subsequent processes such as laser lift-off are used for mass transfer, since there is no first passivation layer and second passivation layer at the isolation grooves, the laser will not irradiate the first passivation layer and the second passivation layer, and the decomposition of the first passivation layer and the second passivation layer will not be caused, improving the mass transfer accuracy. Description of the Drawings
[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for description in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0032] Figure 1 It is a schematic structural diagram of a light-emitting diode provided by an embodiment of the present disclosure;
[0033] Figure 2 It is a schematic structural diagram of a light-emitting diode provided by an embodiment of the present disclosure;
[0034] Figure 3 It is a flowchart of a method for manufacturing a light-emitting diode provided by an embodiment of the present disclosure;
[0035] Figure 4 It is a flowchart of a method for manufacturing a light-emitting diode provided by an embodiment of the present disclosure;
[0036] Figure 5 It is a flowchart of a method for manufacturing a light-emitting diode provided by an embodiment of the present disclosure.
[0037] The reference numerals are as follows:
[0038] 10: Epitaxial structure; 20: Electrode structure;
[0039] 101: Substrate; 102: First semiconductor layer; 103: Active layer; 104: Second semiconductor layer; 105: Transparent conductive layer; 106: First passivation layer; 107: Metal reflection layer; 108: Second passivation layer; 109: First electrode; 110: Second electrode; 111: Bonding layer; 112: Temporary substrate; 113: Third passivation layer;
[0040] 201: Step structure; 2011: Step top surface; 2012: Step bottom surface;
[0041] 301: First through-hole; 302: Second through-hole;
[0042] 1001: Isolation groove. Specific embodiments
[0043] To make the objectives, technical solutions, and advantages of the present disclosure clearer, the following will further describe the embodiments of the present disclosure in detail with reference to the accompanying drawings.
[0044] Figure 1 Schematic diagram of the structure of a light-emitting diode provided in an embodiment of the present disclosure. Refer to Figure 1 The light-emitting diode includes: an epitaxial structure 10, a transparent conductive layer 105, a first passivation layer 106, a metal reflection layer 107, and a second passivation layer 108.
[0045] Among them, the epitaxial structure 10 has a stepped structure 201. The transparent conductive layer 105 is located on the stepped top surface 2011 of the stepped structure 201. The first passivation layer 106 covers the transparent conductive layer 105 and the stepped structure 201. The metal reflection layer 107 is located on the first passivation layer 106 on the stepped top surface 2011. The second passivation layer 108 covers the metal reflection layer 107 and the first passivation layer 106. Isolation grooves 1001 are provided at the edges of the second passivation layer, the first passivation layer, and the epitaxial structure 10. The included angle a between the side wall and the bottom of the isolation groove 1001 is greater than or equal to 90 degrees.
[0046] In the embodiment of the present disclosure, isolation grooves are provided at the edges of the second passivation layer, the first passivation layer, and the epitaxial structure. During subsequent mass transfer using processes such as laser lift-off, since there is no first passivation layer and second passivation layer at the isolation grooves, the laser will not irradiate the first passivation layer and the second passivation layer, and the decomposition of the first passivation layer and the second passivation layer will not occur, improving the mass transfer accuracy.
[0047] In the embodiment of the present disclosure, the width of the isolation groove 1001 can be 2 to 100 μm.
[0048] Exemplarily, the width of the isolation groove 1001 is 10 μm.
[0049] In this implementation manner, with the isolation groove having the above width, on the one hand, it is beneficial to divide the light-emitting diode into individual chips, and on the other hand, it will not affect the light emission of the light-emitting diode due to the too large size of the isolation groove.
[0050] In the embodiment of the present disclosure, the distance between the edge of the metal reflection layer 107 and the side wall of the isolation groove 1001 is 1.5 to 5 μm.
[0051] In this implementation, the edge of the metal reflective layer and the sidewall of the isolation groove adopt the above-mentioned spacing, and the second passivation layer can completely cover the metal reflective layer, improving the reflectivity of the light-emitting diode.
[0052] Exemplarily, the spacing between the edge of the metal reflective layer 107 and the sidewall of the isolation groove 1001 is 3 μm.
[0053] In the embodiments of the present disclosure, the first passivation layer 106 and the second passivation layer 108 can be Distributed Bragg Reflector (DBR) layers respectively, and the DBR layer is a stack composed of alternately arranged SiO2 and Ti3O5 cycles.
[0054] In this implementation, the first passivation layer and the second passivation layer are DBR layers, and the DBR layer has a high reflectivity, which can reduce the loss of light and improve the brightness of the light-emitting diode.
[0055] Exemplarily, the first passivation layer 106 and the second passivation layer 108 are DBR layers.
[0056] In the embodiments of the present disclosure, the cycle of alternation of SiO2 and Ti3O5 in the first passivation layer 106 and the second passivation layer 108 can be 5 to 15 cycles.
[0057] Exemplarily, the cycle of alternation of SiO2 and Ti3O5 in the first passivation layer 106 and the second passivation layer 108 is 10 cycles.
[0058] In the embodiments of the present disclosure, when the first passivation layer 106 and the second passivation layer 108 are DBR layers, the thicknesses of the first passivation layer 106 and the second passivation layer 108 are respectively 500 to 20000 angstroms.
[0059] In this implementation, by using the first passivation layer and the second passivation layer with the above thicknesses, the reflectivity of the light-emitting diode can be improved, and using this thickness will not be too thick to cause the isolation groove to be too deep, increasing the difficulty of subsequent processes such as laser lift-off during mass transfer.
[0060] Exemplarily, when the first passivation layer 106 and the second passivation layer 108 are DBR layers, the thicknesses of the first passivation layer 106 and the second passivation layer 108 are respectively 10000 angstroms.
[0061] In other examples, the first passivation layer 106 and the second passivation layer 108 can also be SiO2 layers or Ti3O5 layers.
[0062] In the embodiments of the present disclosure, when the first passivation layer 106 and the second passivation layer 108 are SiO2 layers, the thicknesses of the first passivation layer 106 and the second passivation layer 108 can be 500 to 10000 angstroms.
[0063] Exemplarily, when the first passivation layer 106 and the second passivation layer 108 are SiO2 layers, the thicknesses of the first passivation layer 106 and the second passivation layer 108 are 5000 angstroms.
[0064] In an embodiment of the present disclosure, when the first passivation layer 106 and the second passivation layer 108 are Ti3O5 layers, the thicknesses of the first passivation layer 106 and the second passivation layer 108 can be 200 - 1800 angstroms.
[0065] Exemplarily, when the first passivation layer 106 and the second passivation layer 108 are Ti3O5 layers, the thicknesses of the first passivation layer 106 and the second passivation layer 108 are 1000 angstroms.
[0066] In an embodiment of the present disclosure, the metal reflection layer 107 can be a Ti, Al, Ti, Pt, Ti stack or an Al, Ti, Pt, Ti stack or an Ag, Ni, TiW stack.
[0067] In this implementation, the Ti layer provides high hardness and wear resistance, the Al layer provides good electrical conductivity and corrosion resistance, the Pt and Ti layers enhance the structural stability and reflection performance, the Ag layer provides a high reflectivity, the Ni layer can improve the adhesion between the film layers, and the TiW layer serves as a protective layer to prevent metal migration and improve corrosion resistance. The metal reflection layer made of the above - mentioned combined stack can achieve high reflectivity, high stability and corrosion resistance, improving the overall performance and reliability of the device.
[0068] In an embodiment of the present disclosure, the thickness of a single layer of Al or Ag in the metal reflection layer 107 can be 500 - 2000 angstroms, and the thicknesses of the remaining layers can be 5 - 2000 angstroms.
[0069] Exemplarily, the thickness of a single layer of Al or Ag is 1500 angstroms, and the thicknesses of the remaining layers are 1000 angstroms.
[0070] In an embodiment of the present disclosure, the transparent conductive layer 105 can be an indium tin oxide (ITO) layer. ITO has good transparency and electrical conductivity, allowing light to pass through while conducting current to form an electrical connection.
[0071] In an embodiment of the present disclosure, the above - mentioned light - emitting diode may further include: a substrate 101 and an electrode structure 20.
[0072] Exemplarily, the epitaxial structure 10 includes a first semiconductor layer 102, an active layer 103, and a second semiconductor layer 104. The bottom surface 2012 of the step is located in the first semiconductor layer 102.
[0073] Exemplarily, the electrode structure 20 includes a first electrode 109 and a second electrode 110.
[0074] Among them, the first semiconductor layer 102, the active layer 103, and the second semiconductor layer 104 are stacked on the substrate 101 in sequence.
[0075] Among them, the first passivation layer 106, the metal reflective layer 107, and the second passivation layer 108 open a first through hole 301 at the top surface 2011 of the step, the first passivation layer 106 and the second passivation layer 108 open a second through hole 302 at the bottom surface 2012 of the step, the first electrode 109 is connected to the transparent conductive layer 105 through the first through hole 301 at the top surface 2011 of the step, and the second electrode 110 is connected to the epitaxial structure 10 (the first semiconductor layer 102) through the second through hole 302 at the bottom surface 2012 of the step.
[0076] In the embodiment of the present disclosure, the substrate 101 can be any one of substrates such as a sapphire patterned substrate, an Si substrate, and an SiC substrate, and the embodiment of the present disclosure does not limit the material of the substrate 101.
[0077] Exemplarily, the substrate 101 is a sapphire patterned substrate.
[0078] In the embodiment of the present disclosure, the first semiconductor layer 102 can be an N-type semiconductor layer, and the second semiconductor layer 104 can be a P-type semiconductor layer.
[0079] For example, the first semiconductor layer 102 can be an N-type GaN layer, and the second semiconductor layer 104 can be a P-type GaN layer.
[0080] In other embodiments, the first semiconductor layer 102 can be a P-type semiconductor layer, and the second semiconductor layer 104 can be an N-type semiconductor layer.
[0081] In the embodiment of the present disclosure, the active layer 103 can be a multi-quantum well layer. For example, the multi-quantum well layer can be an InGaN / GaN multi-quantum well structure.
[0082] In the embodiment of the present disclosure, the first electrode 109 and the second electrode 110 can be a combination of one or more of metals or alloy layers such as Cr, Al, AlCu, Ti, Ni, Pt, and Au.
[0083] Exemplarily, the first electrode 109 and the second electrode 110 are a stack of Cr, Al, AlCu, Ti, Ni, Pt, and Au.
[0084] Figure 2 It is a schematic structural diagram of a light-emitting diode provided by an embodiment of the present disclosure. Refer to Figure 2 , this light-emitting diode may further include: a bonding layer 111, a temporary substrate 112, and a third passivation layer 113.
[0085] Among them, the bonding layer 111 covers the electrode structure 20 and the second passivation layer 108. The electrode structure 20 and the second passivation layer 108 are connected to the temporary substrate 112 through the bonding layer 111, and the third passivation layer 113 is on the bottom surface of the first semiconductor layer 102.
[0086] In an embodiment of the present disclosure, one side of the first semiconductor layer 102 covering the third passivation layer 113 is roughened.
[0087] In an embodiment of the present disclosure, isolation grooves are also formed in the third passivation layer 113.
[0088] In an embodiment of the present disclosure, the bonding layer 111 can be glue.
[0089] In an embodiment of the present disclosure, the temporary substrate 112 can be any one of substrates such as a sapphire patterned substrate, an Si substrate, and an SiC substrate. The present disclosure does not limit the material of the temporary substrate 112.
[0090] Exemplarily, the temporary substrate 112 is a sapphire patterned substrate.
[0091] In an embodiment of the present disclosure, the third passivation layer 113 can be a silicon dioxide layer or a titanium dioxide layer.
[0092] It should be noted that in an embodiment of the present disclosure, structures can be selectively added or reduced on the basis of the above-mentioned light-emitting diode structure, and the present disclosure does not limit this.
[0093] Figure 3 It is a flowchart of a method for manufacturing a light-emitting diode provided by an embodiment of the present disclosure. Refer to Figure 3 , and the method steps include:
[0094] S11. Fabricate an epitaxial structure, and the epitaxial structure has a stepped structure.
[0095] S12. Fabricate a transparent conductive layer on the surface of the epitaxial structure, and the transparent conductive layer is located on the top surface of the step of the stepped structure.
[0096] S13. Fabricate a first passivation layer, and the first passivation layer covers the transparent conductive layer and the stepped structure.
[0097] S14. Fabricate a metal reflective layer, and the metal reflective layer is on the first passivation layer on the top surface of the step.
[0098] S15. Fabricate a second passivation layer, and the second passivation layer covers the first passivation layer and the metal reflective layer.
[0099] S16. Fabricate isolation grooves, and the isolation grooves are formed at the edges of the second passivation layer, the first passivation layer, and the epitaxial structure, and the included angle between the side wall and the bottom of the isolation groove is greater than or equal to 90 degrees.
[0100] In the embodiment of the present disclosure, isolation grooves are formed at the edges of the second passivation layer, the first passivation layer, and the epitaxial structure. When subsequent processes such as laser lift-off are used for mass transfer, since there is no first passivation layer and second passivation layer at the isolation grooves, the laser will not irradiate the first passivation layer and the second passivation layer, and the decomposition of the first passivation layer and the second passivation layer will not be caused, thereby improving the mass transfer accuracy.
[0101] Figure 4 It is a flowchart of a method for manufacturing a light-emitting diode provided by an embodiment of the present disclosure. Refer to Figure 4 The method steps include:
[0102] S21. A first semiconductor layer, an active layer, and a second semiconductor layer are sequentially formed on a substrate, and the second semiconductor layer, the active layer, and the first semiconductor layer constitute an epitaxial structure.
[0103] Among them, the substrate can be any one of substrates such as a sapphire patterned substrate, an Si substrate, and an SiC substrate.
[0104] In one example, step S21 includes:
[0105] The first step is to fabricate the first semiconductor layer.
[0106] In the embodiment of the present disclosure, the first semiconductor layer is an N-type GaN layer.
[0107] The second step is to fabricate the active layer.
[0108] In the embodiment of the present disclosure, the active layer is a multi-quantum well layer. For example, the multi-quantum well layer can be an InGaN / GaN multi-quantum well structure.
[0109] The third step is to fabricate the second semiconductor layer.
[0110] In the embodiment of the present disclosure, the second semiconductor layer is a P-type GaN layer.
[0111] In the embodiment of the present disclosure, the first semiconductor layer, the active layer, and the second semiconductor layer are sequentially stacked on the substrate.
[0112] S22. The epitaxial structure is patterned to form a step structure. The step structure has a step top surface and a step bottom surface. The step bottom surface of the step structure is located within the epitaxial structure, and the step top surface of the step structure is located on the second semiconductor layer.
[0113] In the embodiment of the present disclosure, the epitaxial structure is patterned by inductively coupled plasma (ICP) etching.
[0114] S23. Fabricate a transparent conductive layer on the surface of the epitaxial structure, and the transparent conductive layer is located on the top surface of the step structure.
[0115] In one example, step S23 includes:
[0116] First step, fabricate a transparent conductive thin film on the surface of the epitaxial structure.
[0117] Second step, perform patterning on the transparent conductive thin film to form a transparent conductive layer.
[0118] In the embodiments of the present disclosure, the transparent conductive layer can be an indium tin oxide (ITO) layer. ITO has good transparency and conductivity. It allows light to pass through while also conducting current to form an electrical connection.
[0119] S24. Fabricate a first passivation layer on the transparent conductive layer, and the first passivation layer covers the transparent conductive layer and the step structure.
[0120] In the embodiments of the present disclosure, the first passivation layer can be a Distributed Bragg Reflector (DBR) layer. The DBR layer is a stack formed by alternating SiO2 and Ti3O5 periodically.
[0121] Exemplarily, the first passivation layer is a DBR layer.
[0122] In this implementation, the first passivation layer is a DBR layer. The DBR layer has a high reflectivity, which can reduce light loss and improve the brightness of the light-emitting diode.
[0123] In the embodiments of the present disclosure, the period of alternation between SiO2 and Ti3O5 in the first passivation layer can be 5 to 15 periods.
[0124] Exemplarily, the period of alternation between SiO2 and Ti3O5 in the first passivation layer can be 10 periods.
[0125] In the embodiments of the present disclosure, when the first passivation layer is a DBR layer, the thickness of the first passivation layer can be 6000 to 17000 angstroms.
[0126] In this implementation, by using the first passivation layer with the above thickness, the reflectivity of the light-emitting diode can be improved, and using this thickness will not be too thick to cause the isolation groove to be too deep, increasing the difficulty of subsequent processes such as laser lift-off for mass transfer.
[0127] Exemplarily, when the first passivation layer is a DBR layer, the thickness of the first passivation layer is 10000 angstroms.
[0128] In the embodiments of the present disclosure, the first passivation layer can also be a SiO2 layer or a Ti3O5 layer.
[0129] In an embodiment of the present disclosure, when the first passivation layer is a SiO2 layer, the first passivation layer with a thickness of 500 - 10000 angstroms is deposited under the condition that the temperature is 240 - 300 °C.
[0130] Exemplarily, when the first passivation layer is a SiO2 layer, the first passivation layer with a thickness of 5000 angstroms is deposited under the condition that the temperature is 260 °C.
[0131] In an embodiment of the present disclosure, when the first passivation layer is a Ti3O5 layer, the first passivation layer with a thickness of 200 - 1800 angstroms is deposited under the condition that the temperature is 200 - 350 °C.
[0132] Exemplarily, when the first passivation layer is a Ti3O5 layer, the first passivation layer with a thickness of 1000 angstroms is deposited under the condition that the temperature is 300 °C.
[0133] S25. Fabricate a metal reflection layer, and the metal reflection layer is located on the first passivation layer on the top surface of the step.
[0134] In an embodiment of the present disclosure, an electron beam evaporation or magnetron sputtering deposition device is used to fabricate the metal reflection layer.
[0135] Exemplarily, an electron beam evaporation device is used to fabricate the metal reflection layer.
[0136] In an embodiment of the present disclosure, the metal reflection layer can be a Ti, Al, Ti, Pt, Ti stack or an Al, Ti, Pt, Ti stack or an Ag, Ni, TiW stack.
[0137] In this implementation, the Ti layer provides high hardness and wear resistance, the Al layer provides good electrical conductivity and corrosion resistance, the Pt and Ti layers enhance the structural stability and reflection performance, the Ag layer provides a high reflectivity, the Ni layer can improve the adhesion between the film layers, and the TiW layer acts as a protective layer to prevent metal migration and improve corrosion resistance. The metal reflection layer fabricated by the above combined stack can achieve high reflectivity, high stability and corrosion resistance, and improve the overall performance and reliability of the device.
[0138] In an embodiment of the present disclosure, the thickness of a single layer of Al or Ag in the metal reflection layer can be 500 - 2000 angstroms, and the thickness of the remaining layers can be 5 - 2000 angstroms.
[0139] Exemplarily, the thickness of a single layer of Al or Ag is 1500 angstroms, and the thickness of the remaining layers is 1000 angstroms.
[0140] S26. Fabricate a second passivation layer, and the second passivation layer covers the first passivation layer and the metal reflection layer.
[0141] In an embodiment of the present disclosure, the second passivation layer can be a DBR layer, and the DBR layer is a stack composed of alternating SiO2 and Ti3O5 periods.
[0142] Exemplarily, the second passivation layer is a DBR layer.
[0143] In an embodiment of the present disclosure, the second passivation layer is a DBR layer, and the DBR layer has a high reflectivity, which can reduce the loss of light and improve the brightness of the light-emitting diode.
[0144] In an embodiment of the present disclosure, the period of alternation of SiO2 and Ti3O5 in the second passivation layer can be 5 to 15 periods.
[0145] Exemplarily, the period of alternation of SiO2 and Ti3O5 in the second passivation layer can be 10 periods.
[0146] In an embodiment of the present disclosure, when the second passivation layer is a DBR layer, the thickness of the second passivation layer can be 6000 to 17000 angstroms.
[0147] In this implementation manner, by using the second passivation layer with the above thickness, the reflectivity of the light-emitting diode can be improved, and using this thickness will not be too thick to cause the isolation groove to be too deep, resulting in an increase in the difficulty of subsequent processes such as laser lift-off during mass transfer.
[0148] Exemplarily, when the second passivation layer is a DBR layer, the thickness of the second passivation layer is 10000 angstroms.
[0149] In an embodiment of the present disclosure, the second passivation layer can also be a SiO2 layer or a Ti3O5 layer.
[0150] In an embodiment of the present disclosure, when the second passivation layer is a SiO2 layer, a second passivation layer with a thickness of 500 to 10000 angstroms is deposited under the condition that the temperature is 240 to 300 °C.
[0151] Exemplarily, when the second passivation layer is a SiO2 layer, a second passivation layer with a thickness of 5000 angstroms is deposited under the condition that the temperature is 260 °C.
[0152] In an embodiment of the present disclosure, when the second passivation layer is a Ti3O5 layer, a second passivation layer with a thickness of 200 to 1800 angstroms is deposited under the condition that the temperature is 200 to 350 °C.
[0153] Exemplarily, when the second passivation layer is a Ti3O5 layer, a second passivation layer with a thickness of 1000 angstroms is deposited under the condition that the temperature is 300 °C.
[0154] S27. Etch the isolation groove, and the isolation groove is opened at the edges of the second passivation layer, the first passivation layer, and the epitaxial structure.
[0155] In one example, step S27 includes:
[0156] In the first step, a first etch gas is used to etch the first passivation layer and the second passivation layer, forming the part of the isolation trench located in the first passivation layer and the second passivation layer.
[0157] In an embodiment of the present disclosure, CF4 is used as the first etch gas to perform ICP etching on the first passivation layer and the second passivation layer.
[0158] In this implementation manner, using CF4 as the first etch gas for etching can react quickly with SiO2 and Ti3O5 in the DBR to accelerate the etching rate.
[0159] In the second step, a second etch gas is used to etch the epitaxial structure, forming the part of the isolation trench located in the epitaxial structure.
[0160] In an embodiment of the present disclosure, a mixed gas of Cl2, BCl2, and HBr is used as the second etch gas to perform ICP etching on the epitaxial structure.
[0161] In this implementation manner, using a mixed gas of Cl2, BCl2, and HBr as the second etch gas can precisely control the etching process by adjusting the gas ratio, reduce etching damage, and improve the device performance and stability.
[0162] In an embodiment of the present disclosure, the width of the isolation trench can be 2 - 100 μm.
[0163] Exemplarily, the width of the isolation trench is 10 μm.
[0164] In this implementation manner, using an isolation trench with the above width is beneficial for splitting the light-emitting diode into individual chips on the one hand, and on the other hand, it will not affect the light emission of the light-emitting diode due to the too large size of the isolation trench.
[0165] S28. Fabricate an electrode structure, and the electrode structure passes through the first passivation layer, the metal reflection layer, and the second passivation layer to be connected to the epitaxial structure.
[0166] In one example, step S28 includes:
[0167] In the second step, perform patterning on the first passivation layer, the metal reflection layer, and the second passivation layer, open a first through hole at the top surface of the step, and open a second through hole at the bottom surface of the step.
[0168] In an embodiment of the present disclosure, the first through hole and the second through hole are opened by a wet etching or dry etching method.
[0169] In the third step, fabricate a first electrode and a second electrode. The first electrode is connected to the current spreading layer through the first through hole at the top surface of the step, and the second electrode is connected to the epitaxial structure through the second through hole at the bottom surface of the step.
[0170] In an embodiment of the present disclosure, the first electrode and the second electrode may be one or a combination of metals or alloy layers such as Cr, Al, AlCu, Ti, Ni, Pt, and Au.
[0171] Exemplarily, the first electrode and the second electrode are a stack of Cr, Al, AlCu, Ti, Ni, Pt, and Au.
[0172] Figure 5 It is a flowchart of a method for manufacturing a light-emitting diode provided by an embodiment of the present disclosure. Refer to Figure 5 , and the steps of the method include:
[0173] S31. Form a first semiconductor layer, an active layer, and a second semiconductor layer on a substrate in sequence, and the second semiconductor layer, the active layer, and the first semiconductor layer constitute an epitaxial structure.
[0174] This step can refer to S21 and will not be elaborated here.
[0175] S32. Pattern the epitaxial structure to form a step structure, which has a step top surface and a step bottom surface. The step bottom surface of the step structure is located within the epitaxial structure, and the step top surface of the step structure is located on the second semiconductor layer.
[0176] This step can refer to S22 and will not be elaborated here.
[0177] S33. Fabricate a transparent conductive layer on the surface of the epitaxial structure, and the transparent conductive layer is located on the step top surface of the step structure.
[0178] This step can refer to S23 and will not be elaborated here.
[0179] S34. Fabricate a first passivation layer on the transparent conductive layer, and the first passivation layer covers the transparent conductive layer and the step structure.
[0180] This step can refer to S24 and will not be elaborated here.
[0181] S35. Fabricate a metal reflective layer, and the metal reflective layer is located on the first passivation layer on the step top surface.
[0182] This step can refer to S25 and will not be elaborated here.
[0183] S36. Fabricate a second passivation layer, and the second passivation layer covers the first passivation layer and the metal reflective layer.
[0184] This step can refer to S26 and will not be elaborated here.
[0185] S37. Fabricate an electrode structure, and the electrode structure passes through the first passivation layer, the metal reflective layer, and the second passivation layer to connect with the epitaxial structure.
[0186] This step can refer to S28 and will not be elaborated here.
[0187] S38. Flip the structure on the substrate to the temporary substrate through the bonding layer, and the bonding layer covers the electrode structure and the second passivation layer.
[0188] In the embodiments of the present disclosure, the bonding layer can be glue.
[0189] In the embodiments of the present disclosure, the temporary substrate can be any one of substrates such as a sapphire patterned substrate, an Si substrate, and an SiC substrate, and the embodiments of the present disclosure do not limit the material of the temporary substrate.
[0190] Exemplarily, the temporary substrate is a sapphire patterned substrate.
[0191] S39. Process the epitaxial structure.
[0192] In the embodiments of the present disclosure, the first semiconductor is processed with a KOH or TMAH solution, which can make the surface of the first semiconductor layer obtain a suitable rough texture and have an enhanced light extraction effect.
[0193] In the embodiments of the present disclosure, in an environment with a temperature of 25 to 80 °C, an aqueous solution of KOH or TMAH with a mass fraction of 0.5 to 50% is used to treat the surface of the first semiconductor for 60 to 1800 s.
[0194] Exemplarily, in an environment with a temperature of 40 °C, an aqueous solution of KOH or TMAH with a mass fraction of 25% is used to treat the surface of the first semiconductor for 900 s.
[0195] In another example, a crystal layer is fabricated on the surface of the first semiconductor, which can make the surface of the first semiconductor layer obtain a suitable rough texture and have an enhanced light extraction effect.
[0196] In the embodiments of the present disclosure, the crystal layer can be a silicon dioxide layer or a titanium dioxide layer.
[0197] In another example, after the processing of the epitaxial structure is completed, a third passivation layer can also be deposited on the processed surface.
[0198] Exemplarily, a third passivation layer with a thickness of 300 to 12000 angstroms is deposited using a Physical Vapor Deposition (PVD) device under the condition of a temperature of 50 to 150 °C.
[0199] Exemplarily, the third passivation layer can be SiO2, Al2O3 or Si x N y layer.
[0200] Exemplarily, Six N y In the layer, x can be 3 and y can be 4.
[0201] S40, etch isolation grooves, which are opened at the edges of the third passivation layer, the epitaxial structure, the second passivation layer, and the first passivation layer.
[0202] In one example, step S40 includes: First, use a second etch gas to etch the third passivation layer and the epitaxial structure to form the part of the isolation groove located in the epitaxial structure.
[0203] In the embodiments of the present disclosure, a mixed gas of Cl2, BCl2, and HBr is used as the second etch gas to perform ICP etching on the epitaxial structure.
[0204] In this implementation manner, using a mixed gas of Cl2, BCl2, and HBr as the second etch gas can precisely control the etching process by adjusting the gas ratio, reduce etching damage, and improve the device performance and stability.
[0205] Second, use a first etch gas to etch the first passivation layer and the second passivation layer to form the part of the isolation groove located in the first passivation layer and the second passivation layer.
[0206] In the embodiments of the present disclosure, CF4 is used as the first etch gas to perform ICP etching on the first passivation layer and the second passivation layer.
[0207] In this implementation manner, using CF4 as the first etch gas for etching can react quickly with SiO2 and Ti3O5 in the DBR to accelerate the etching rate.
[0208] In the embodiments of the present disclosure, the width of the isolation groove can be 2 - 100 μm.
[0209] Exemplarily, the width of the isolation groove is 10 μm.
[0210] In this implementation manner, using the isolation groove with the above width is beneficial to divide the light-emitting diode into individual chips on the one hand, and on the other hand, it will not affect the light emission of the light-emitting diode because the size of the isolation groove is too large.
[0211] The above are only optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. A light emitting diode, characterized in that: The light emitting diode comprises: an epitaxial structure (10), a transparent conductive layer (105), a first passivation layer (106), a metal reflective layer (107) and a second passivation layer (108); The epitaxial structure (10) is in the form of a step structure (201); the transparent conductive layer (105) is located on a step top surface (2011) of the step structure (201); the first passivation layer (106) covers the transparent conductive layer (105) and the step structure (201); the metal reflective layer (107) is located on the first passivation layer (106) on the step top surface (2011); the second passivation layer (108) covers the metal reflective layer (107) and the first passivation layer (106); the second passivation layer (108), the first passivation layer (106) and the edges of the epitaxial structure (10) are provided with an isolation groove (1001); and the angle (a) between the side wall and the bottom of the isolation groove (1001) is greater than or equal to 90 degrees.
2. The light emitting diode according to claim 1, characterized in that: The width of the isolation groove (1001) is 2-100 μm.
3. The light emitting diode according to claim 1, characterized in that: The distance between the edge of the metal reflective layer (107) and the side wall of the isolation groove (1001) is 1.5 to 5 μm.
4. The light emitting diode according to any one of claims 1 to 3, characterized in that: The first passivation layer (106) and the second passivation layer (108) are respectively DBR layers; The thickness of the first passivation layer (106) and the second passivation layer (108) are respectively 600 to 17000 angstroms.
5. The light emitting diode according to any one of claims 1 to 3, characterized in that: The metal reflective layer (107) is a stack of Ti, Al, Ti, Pt, Ti or a stack of Al, Ti, Pt, Ti or a stack of Ag, Ni, TiW.
6. A method for preparing a light emitting diode, characterized in that: The method comprises: Manufacturing an epitaxial structure, wherein the epitaxial structure is a step structure; Making a transparent conductive layer on the surface of the epitaxial structure, wherein the transparent conductive layer is located on the top surface of the step of the step structure; Manufacturing a first passivation layer, wherein the first passivation layer covers the transparent conductive layer and the step structure; Manufacturing a metal reflective layer, wherein the metal reflective layer is located on the first passivation layer on the top surface of the step; Manufacturing a second passivation layer, wherein the second passivation layer covers the first passivation layer and the metal reflective layer; An isolation groove is manufactured, wherein the isolation groove is opened at the edge of the second passivation layer, the first passivation layer and the epitaxial structure, and the angle between the side wall and the bottom of the isolation groove is greater than or equal to 90 degrees.
7. The method for preparing a light emitting diode according to claim 6, characterized in that: The method of making the isolation groove comprises: Etching the first passivation layer and the second passivation layer using a first etching gas to form a portion of the isolation groove located in the first passivation layer and the second passivation layer; The epitaxial structure is etched using a second etching gas to form a portion of the isolation groove located in the epitaxial structure.
8. The method for preparing a light emitting diode according to claim 7, characterized in that: The etching of the first passivation layer and the second passivation layer by using a first etching gas comprises: CF4 is used as the first etching gas to perform ICP etching on the first passivation layer and the second passivation layer.
9. The method for preparing a light emitting diode according to claim 7, characterized in that: The step of etching the epitaxial structure using a second etching gas comprises: A mixed gas of Cl2, BCl2 and HBr is used as the second etching gas to perform ICP etching on the epitaxial structure.
10. The method according to any one of claims 6 to 9, characterized in that: The width of the isolation groove is 2-100 μm.