Semiconductor structure, preparation method thereof and electronic equipment

Abstract

The invention relates to a semiconductor structure, a preparation method thereof and electronic equipment, relates to the technical field of semiconductors, and is used for improving the storage capacity of a memory. The preparation method of the semiconductor structure comprises the following steps: providing a substrate, and alternately forming a plurality of conductive material layers and a plurality of insulating material layers on the substrate along a direction vertical to the substrate; the conductive material layer and the insulating material layer are etched, so that a first electrode of the capacitor is formed on the edge of at least one side, parallel to the first direction of the substrate, of each conductive material layer, the first electrode is exposed, and the first electrode comprises at least two first sub-electrodes which are separated from each other; forming a dielectric layer covering the first sub-electrodes and a second electrode covering the dielectric layer, and enabling at least one part of the second electrode to be located between the at least two first sub-electrodes; the capacitor also includes a dielectric layer and a second electrode.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a semiconductor structure, a preparation method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are increasingly reduced, and the types and quantities of devices included in a single chip increase accordingly, making any minor difference in the process production likely to affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's law came out, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the needs of current products. Summary of the Invention

[0004] Based on this, embodiments of the present disclosure provide a semiconductor structure, a preparation method thereof, and an electronic device, which are beneficial to effectively improving the capacitance value without increasing or reducing the size of the capacitor, thereby improving the storage capacity of the memory and the electronic device.

[0005] According to some embodiments, on the one hand, the present disclosure provides a preparation method of a semiconductor structure, including the following steps.

[0006] Provide a substrate, and alternately form a plurality of conductive material layers and a plurality of insulating material layers on the substrate along a direction perpendicular to the substrate.

[0007] Etch the conductive material layer and the insulating material layer to respectively form a first electrode of a capacitor at the edges of each conductive material layer in a first direction parallel to the substrate, and expose the first electrode; wherein, the first electrode includes at least two first sub-electrodes separated from each other.

[0008] Form a dielectric layer covering the first sub-electrode and a second electrode covering the dielectric layer, such that at least a part of the second electrode is located between the at least two first sub-electrodes; the capacitor further includes the dielectric layer and the second electrode.

[0009] In some embodiments of the present disclosure, the first electrode includes two first sub-electrodes arranged in a second direction parallel to the substrate; both the first direction and the second direction are parallel to the substrate and intersect.

[0010] In some embodiments of the present disclosure, the first sub-electrode includes a bottom surface close to the substrate, a top surface far from the substrate, and a side surface connecting the top surface and the bottom surface; the side surfaces of the two first sub-electrodes facing away from each other are parallel to each other.

[0011] In some embodiments of the present disclosure, the two first sub - electrodes have equal dimensions in the direction perpendicular to the substrate, which is the first dimension; the distance between the sides of the two first sub - electrodes facing away from each other is the second dimension; wherein, the ratio of the first dimension to the second dimension is greater than 1.1.

[0012] In some embodiments of the present disclosure, etching the conductive material layer and the insulating material layer to respectively form the first electrode of the capacitor at the edges of each conductive material layer in the first direction parallel to the substrate and exposing the first electrode includes the following steps.

[0013] Performing a single patterning process on the multi - layer conductive material layer and the multi - layer insulating material layer to form an etching structure; any conductive material layer in the etching structure includes: a first conductive structure extending in the second direction, a plurality of second conductive structures extending in the first direction and connected to the first conductive structure, and a first electrode connected to the end of the second conductive structure away from the first conductive structure.

[0014] Forming an isolation material layer in the etching region of the multi - layer conductive material layer and the multi - layer insulating material layer.

[0015] Etching the isolation material layer in the direction perpendicular to the substrate and etching the insulating material layer between the first electrodes adjacent in the direction perpendicular to the substrate in the direction parallel to the substrate to expose the first electrode.

[0016] In some other embodiments of the present disclosure, the first electrode includes two first sub - electrodes and two second sub - electrodes, and the second sub - electrodes connect the two first sub - electrodes. Etching the conductive material layer and the insulating material layer to respectively form the first electrode of the capacitor at the edges of each conductive material layer in the first direction parallel to the substrate and exposing the first electrode includes the following steps.

[0017] Performing a single patterning process on the multi - layer conductive material layer and the multi - layer insulating material layer to form an etching structure; any conductive material layer in the etching structure includes: a first conductive structure extending in the second direction, and a plurality of initial second conductive structures extending in the first direction and connected to the first conductive structure.

[0018] Forming an isolation material layer in the etching region of the multi - layer conductive material layer and the multi - layer insulating material layer and exposing the end face of the initial second conductive structure away from the first conductive structure.

[0019] Based on the exposed end face of the initial second conductive structure, etching the initial second conductive structure in the direction parallel to the substrate to form a second conductive structure and a first electrode receiving groove at one end of the second conductive structure away from the first conductive structure.

[0020] Forming a first electrode on the groove wall of the first electrode receiving groove.

[0021] Etch the isolation material layer along the direction perpendicular to the substrate, and etch the insulating material layer between the first electrodes adjacent in the direction perpendicular to the substrate along the direction parallel to the substrate to expose the first electrodes.

[0022] In some embodiments of the present disclosure, forming the first electrode on the sidewall of the first electrode receiving groove includes the following steps.

[0023] Conformally form a first electrode material layer in the first electrode receiving groove and on the sidewalls of the insulating material layer and the isolation material layer.

[0024] Remove the first electrode material layer on the sidewalls of both the insulating material layer and the isolation material layer, so that the first electrode material layer remaining in the first electrode receiving groove constitutes the first electrode.

[0025] In some embodiments of the present disclosure, two first sub-electrodes and two second sub-electrodes in the first electrode are connected to each other to form a ring structure. Forming the dielectric layer covering the first sub-electrode and the second electrode covering the dielectric layer includes the following steps.

[0026] Form a dielectric layer on the inner surface of the ring, the outer surface of the ring and the end surface far from the second conductive structure of the ring structure.

[0027] Form an inner electrode covering the dielectric layer inside the ring of the ring structure, and form an outer electrode covering the dielectric layer and connected to the inner electrode outside the ring of the ring structure; the second electrode includes the inner electrode and the outer electrode.

[0028] In some embodiments of the present disclosure, the isolation material layer is etched by a dry etching process, and the insulating material layer between the first electrodes adjacent in the direction perpendicular to the substrate is etched by a wet etching process.

[0029] In some embodiments of the present disclosure, the isolation material layer and the insulating material layer are made of the same material.

[0030] According to some embodiments, another aspect of the present disclosure provides a semiconductor structure, including a substrate and one or more memory cells disposed on the substrate; the memory cell includes a capacitor and a transistor; wherein, the capacitor includes: a first electrode, a dielectric layer and a second electrode; the first electrode includes at least two first sub-electrodes separated from each other; the at least two first sub-electrodes are respectively connected to the same transistor; the second electrode covers the first sub-electrode, and at least a part of the second electrode is located between the at least two first sub-electrodes; the dielectric layer is located between the first sub-electrode and the second electrode.

[0031] In some embodiments of the present disclosure, the first electrode includes two first sub-electrodes arranged in a second direction parallel to the substrate.

[0032] In some embodiments of the present disclosure, the first sub - electrode includes a bottom surface close to the substrate, a top surface far from the substrate, and a side surface connecting the top surface and the bottom surface; the side surfaces of the two first sub - electrodes facing away from each other are parallel to each other.

[0033] In some embodiments of the present disclosure, the two first sub - electrodes have equal dimensions in the direction perpendicular to the substrate, which is the first dimension; the distance between the side surfaces of the two first sub - electrodes facing away from each other is the second dimension; wherein, the ratio of the first dimension to the second dimension is greater than 1.1.

[0034] In some embodiments of the present disclosure, the first electrode further includes at least one second sub - electrode connecting the two first sub - electrodes.

[0035] In some embodiments of the present disclosure, the first electrode includes two second sub - electrodes arranged in the direction perpendicular to the substrate.

[0036] In some embodiments of the present disclosure, the two first sub - electrodes and the two second sub - electrodes are interconnected to form an annular structure.

[0037] In some embodiments of the present disclosure, the second electrode includes an inner electrode located inside the ring of the annular structure and an outer electrode located outside the ring of the annular structure and connected to the inner electrode.

[0038] In some embodiments of the present disclosure, the first electrode further includes an interconnecting portion; the interconnecting portion is respectively connected to the first sub - electrode and the second sub - electrode.

[0039] According to some embodiments, on the other hand, the present disclosure provides an electronic device including the semiconductor structure as described above.

[0040] The embodiments of the present disclosure may / at least have the following advantages:

[0041] In the embodiments of the present disclosure, the structure of the first electrode in the capacitor is optimized, such that the first electrode includes at least two separated first sub - electrodes. Thus, the surface area of the first electrode can be effectively increased based on the exposed surfaces of the at least two first sub - electrodes. After sequentially coating the dielectric layer and the second electrode, it is ensured that the first electrode and the second electrode in the capacitor can have a large facing area. Furthermore, the capacitance value can be effectively increased without increasing the size of the capacitor or reducing the size of the capacitor, so as to improve the storage capacity of the memory and the electronic device. Moreover, the preparation method provided by the embodiments of the present disclosure is simple and easy to implement, and is also conducive to effectively improving the production efficiency and production yield of the memory and the electronic device. Description of the Drawings

[0042] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0043] Figure 1 It is a flowchart of a method for fabricating a semiconductor structure provided in some embodiments;

[0044] Figure 2 Figures (a) and (b) in [reference] are respectively schematic structural diagrams of a first electrode in a semiconductor structure provided in some embodiments;

[0045] Figure 3 It is a flowchart of a step S200 provided in some embodiments;

[0046] Figure 4 It is a schematic cross-sectional view perpendicular to the substrate of the structure obtained after alternately forming a multi-layer conductive material layer and a multi-layer insulating material layer in some embodiments;

[0047] Figure 5 It is a schematic diagram of the structure obtained after forming an etching structure in some embodiments; wherein, Figure 5 Figure (a) in [reference] is a schematic cross-sectional view parallel to the substrate of the shown structure along the C-C direction in Figure (b), Figure 5 Figure (b) in [reference] is a schematic cross-sectional view perpendicular to the substrate of the shown structure along the A-A direction in Figure (a);

[0048] Figure 6 It is a schematic diagram of the structure obtained after forming an isolation material layer in some embodiments; wherein, Figure 6 Figure (a) in [reference] is a schematic cross-sectional view parallel to the substrate of the shown structure along the C-C direction in Figure (c), Figure 6 Figure (b) in [reference] is a schematic cross-sectional view perpendicular to the substrate of the shown structure along the A-A direction in Figure (a), Figure 6 Figure (c) in [reference] is a schematic cross-sectional view perpendicular to the substrate of the shown structure along the B-B direction in Figure (a);

[0049] Figure 7 It is a schematic diagram of the structure obtained after exposing the first electrode in some embodiments; wherein, Figure 7 Figure (a) in [reference] is a top view of the shown structure, Figure 7 Figure (b) in [reference] is a schematic cross-sectional view perpendicular to the substrate of the shown structure along the A-A direction in Figure (a);

[0050] Figure 8Schematic diagram of the structure obtained after forming the second electrode in some embodiments; wherein, Figure 8 In FIG. (a), it is a schematic cross-sectional view parallel to the substrate along the C-C direction in FIG. (c) of the shown structure, Figure 8 In FIG. (b), it is a schematic cross-sectional view perpendicular to the substrate along the A-A direction in FIG. (a) of the shown structure, Figure 8 In FIG. (c), it is a schematic cross-sectional view perpendicular to the substrate along the B-B direction in FIG. (a) of the shown structure;

[0051] Figure 9 is Figure 8 a top view schematic diagram of the shown structure;

[0052] Figure 10 Flowchart of another step S200 provided in some embodiments;

[0053] Figure 11 Flowchart of a step S240 provided in some embodiments;

[0054] Figure 12 Flowchart of a step S300 provided in some embodiments;

[0055] Figure 13 Schematic diagram of the structure obtained after forming the etching structure in some embodiments; wherein, Figure 13 In FIG. (a), it is a top view schematic diagram of the shown structure, Figure 13 In FIG. (b), it is a schematic cross-sectional view perpendicular to the substrate along the A-A direction in FIG. (a) of the shown structure, Figure 13 In FIG. (c), it is a schematic cross-sectional view perpendicular to the substrate along the B-B direction in FIG. (a) of the shown structure;

[0056] Figure 14 Schematic diagram of the structure obtained after forming the isolation material layer in some embodiments; wherein, Figure 14 In FIG. (a), it is a top view schematic diagram of the shown structure, Figure 14 In FIG. (b), it is a schematic cross-sectional view perpendicular to the substrate along the A-A direction in FIG. (a) of the shown structure, Figure 14 In FIG. (c), it is a schematic cross-sectional view perpendicular to the substrate along the B-B direction in FIG. (a) of the shown structure;

[0057] Figure 15 Schematic diagram of the structure obtained after forming the first electrode accommodating groove in some embodiments; wherein, Figure 15 In FIG. (a), it is a top view schematic diagram of the shown structure, Figure 15 In FIG. (b), it is a schematic cross-sectional view perpendicular to the substrate along the A-A direction in FIG. (a) of the shown structure, Figure 15Figure (c) in [reference] is a schematic cross-sectional view perpendicular to the substrate along the B-B direction in Figure (a) of the shown structure;

[0058] Figure 16 is a schematic view of the structure obtained after forming the first electrode material layer in some embodiments; wherein, Figure 16 Figure (a) in [reference] is a schematic cross-sectional view parallel to the substrate along the C-C direction in Figure (c) of the shown structure, Figure 16 Figure (b) in [reference] is a schematic cross-sectional view perpendicular to the substrate along the A-A direction in Figure (a) of the shown structure, Figure 16 Figure (c) in [reference] is a schematic cross-sectional view perpendicular to the substrate along the B-B direction in Figure (a) of the shown structure;

[0059] Figure 17 is a schematic view of the structure obtained after forming the first electrode in some embodiments; wherein, Figure 17 Figure (a) in [reference] is a schematic cross-sectional view perpendicular to the substrate along the C-C direction in Figure (b) of the shown structure, Figure 17 Figure (b) in [reference] is a schematic cross-sectional view perpendicular to the substrate along the B-B direction in Figure (a) of the shown structure;

[0060] Figure 18 is a schematic view of the structure obtained after exposing the first electrode in some embodiments; wherein, Figure 18 Figure (a) in [reference] is a schematic cross-sectional view parallel to the substrate along the C-C direction in Figure (c) of the shown structure, Figure 18 Figure (b) in [reference] is a schematic cross-sectional view perpendicular to the substrate along the A-A direction in Figure (a) of the shown structure, Figure 18 Figure (c) in [reference] is a schematic cross-sectional view perpendicular to the substrate along the B-B direction in Figure (a) of the shown structure;

[0061] Figure 19 is a schematic view of the structure obtained after forming the second electrode in some embodiments; wherein, Figure 19 Figure (a) in [reference] is a top view of the shown structure, Figure 19 Figure (b) in [reference] is a schematic cross-sectional view perpendicular to the substrate along the A-A direction in Figure (a) of the shown structure, Figure 19 Figure (c) in [reference] is a schematic cross-sectional view perpendicular to the substrate along the B-B direction in Figure (a) of the shown structure;

[0062] Figure 20 is a schematic view of the structure obtained after forming the etching holes in some embodiments; wherein, Figure 20 Figure (a) in [reference] is a top view of the shown structure, Figure 20 Figure (b) in [reference] is a schematic cross-sectional view perpendicular to the substrate along the B-B direction in Figure (a) of the shown structure,Figure 20 Figure (c) in [reference] is a schematic cross-sectional view perpendicular to the substrate along the D-D direction in Figure (a);

[0063] Figure 21 It is a schematic diagram of the structure obtained after forming a transistor accommodation groove in some embodiments; among them, Figure 21 Figure (a) in [reference] is a top view of the shown structure, Figure 21 Figure (b) in [reference] is a schematic cross-sectional view perpendicular to the substrate along the B-B direction in Figure (a) of the shown structure, Figure 21 Figure (c) in [reference] is a schematic cross-sectional view perpendicular to the substrate along the D-D direction in Figure (a) of the shown structure;

[0064] Figure 22 It is a schematic diagram of the structure obtained after forming a gate material layer in some embodiments; among them, Figure 22 Figure (a) in [reference] is a top view of the shown structure, Figure 22 Figure (b) in [reference] is a schematic cross-sectional view perpendicular to the substrate along the B-B direction in Figure (a) of the shown structure, Figure 22 Figure (c) in [reference] is a schematic cross-sectional view perpendicular to the substrate along the D-D direction in Figure (a) of the shown structure;

[0065] Figure 23 It is a schematic diagram of the structure obtained after forming a transistor in some embodiments; among them, Figure 23 Figure (a) in [reference] is a top view of the shown structure, Figure 23 Figure (b) in [reference] is a schematic cross-sectional view perpendicular to the substrate along the B-B direction in Figure (a) of the shown structure, Figure 23 Figure (c) in [reference] is a schematic cross-sectional view perpendicular to the substrate along the D-D direction in Figure (a) of the shown structure;

[0066] Figure 24 It is a schematic diagram of the structure obtained after forming a word line in some embodiments; among them, Figure 24 Figure (a) in [reference] is a top view of the shown structure, Figure 24 Figure (b) in [reference] is a schematic cross-sectional view perpendicular to the substrate along the B-B direction in Figure (a) of the shown structure, Figure 24 Figure (c) in [reference] is a schematic cross-sectional view perpendicular to the substrate along the D-D direction in Figure (a) of the shown structure.

[0067] Note:

[0068] 1 - Substrate, L1 - Conductive material layer, L2 - Insulating material layer, L11 - First conductive structure, L12 - Second conductive structure, L12a - Initial second conductive structure, 20 - Isolation material layer, 2 - Isolation structure, 3 - Capacitor, 31 - First electrode, 311 - First sub - electrode, 312 - Second sub - electrode, 310 - First electrode material layer, 313 - Interconnection part, 32 - Dielectric layer, 33 - Second electrode, 331 - Inner electrode, 332 - Outer electrode, 4 - Transistor, 41 - Semiconductor layer, 410 - Semiconductor material layer, 42 - Gate dielectric layer, 420 - Gate dielectric material layer, 43 - Gate, 430 - Gate material layer, 5 - Insulating layer, WL - Word line, G1 - First trench, G2 - Second trench, G3 - First electrode accommodation groove, G4 - Transistor accommodation groove, H - Etching hole. Detailed implementation manners

[0069] For the convenience of understanding the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present disclosure is more thorough and comprehensive.

[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present disclosure belongs. The terms used in the description of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0071] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0072] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "overlying", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that spatial relationship terms include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the figures is flipped, an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can include both an upper and a lower orientation. In addition, the device may also have additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0073] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / include" or "has" etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the associated listed items.

[0074] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present disclosure, and such variations in the illustrated shapes can be expected due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present disclosure.

[0075] Embodiments of the present disclosure provide a semiconductor structure, a method for preparing the same, and an electronic device, which are beneficial to effectively increasing the capacitance value without increasing or reducing the size of the capacitor, thereby improving the storage capacity of the memory and the electronic device.

[0076] In some embodiments, referring to Figure 1 , embodiments of the present disclosure provide a method for preparing a semiconductor structure, including the following steps S100 to S300.

[0077] S100, providing a substrate, and alternately forming a plurality of conductive material layers and a plurality of insulating material layers on the substrate along a direction perpendicular to the substrate.

[0078] S200, etch the conductive material layer and the insulating material layer to form the first electrodes of the capacitor at the edges of the conductive material layers in the first direction parallel to the substrate respectively, and expose the first electrodes; wherein, the first electrodes include at least two first sub-electrodes separated from each other.

[0079] S300, form a dielectric layer covering the first sub-electrodes and a second electrode covering the dielectric layer, such that at least a part of the second electrode is located between the at least two first sub-electrodes; the capacitor further includes a dielectric layer and a second electrode.

[0080] It should be added that the first electrodes formed in step S200 may specifically include, but are not limited to, the following embodiments. In a possible embodiment, please refer to Figure 2 Figure (a) in, the first electrode 31 includes two first sub-electrodes 311 separated from each other. In another possible embodiment, please refer to Figure 2 Figure (b) in, the first electrode 31 includes two first sub-electrodes 311 separated from each other, and at least one second sub-electrode 312 connecting the two first sub-electrodes 311.

[0081] Exemplarily, the first electrode 31 includes two second sub-electrodes 312, and the two second sub-electrodes 312 are arranged in the direction perpendicular to the substrate (for example, the Z direction).

[0082] Exemplarily, the two first sub-electrodes 311 and the two second sub-electrodes 312 are connected to each other to form an annular structure.

[0083] Exemplarily, the second electrode includes an inner electrode located inside the ring of the annular structure and an outer electrode located outside the ring of the annular structure and connected to the inner electrode.

[0084] Exemplarily, the first electrode further includes an interconnecting portion; the interconnecting portion is respectively connected to the first sub-electrodes 311 and the second sub-electrodes 312.

[0085] Thus, the embodiments of the present disclosure optimize the structure of the first electrodes in the capacitor, such that the first electrodes include at least two first sub-electrodes separated from each other, so that the surface area of the first electrodes can be effectively increased based on the exposed surfaces of the at least two first sub-electrodes. After sequentially covering the dielectric layer and the second electrode, it is ensured that the first electrodes and the second electrodes in the capacitor can have a relatively large facing area, and thus the capacitance value can be effectively improved without increasing the size of the capacitor or reducing the size of the capacitor, so as to improve the storage capacity of the memory and the electronic device, and save the array area of the memory cell array, thereby facilitating the reduction of production costs and contributing to the realization of high-level multi-layer integration.

[0086] In addition, the preparation method provided by the embodiments of the present disclosure is simple and easy to implement, and is also conducive to effectively improving the production efficiency and production yield of the memory and electronic devices.

[0087] It is worth mentioning that in some embodiments of the present disclosure, please continue to refer to Figure 2 Figures (a) and (b) in. The first electrode 31 includes two first sub-electrodes 311 arranged in a second direction parallel to the substrate; both the first direction and the second direction are parallel to the substrate and intersect. The first sub-electrode 311 includes a bottom surface close to the substrate, a top surface far from the substrate, and a side surface connecting the top surface and the bottom surface; the side surfaces of the two first sub-electrodes 311 facing away from each other are parallel to each other. The dimensions of the two first sub-electrodes 311 in the direction perpendicular to the substrate (for example, the Z direction) are equal, which is the first dimension D1; the distance between the side surfaces of the two first sub-electrodes 311 facing away from each other is the second dimension D2; wherein, the ratio of the first dimension D1 to the second dimension D2 is greater than 1.1. More preferably, the ratio of the first dimension D1 to the second dimension D2 is greater than 1.4; in other words, the ratio of the second dimension D2 to the first dimension D1 will be less than another target threshold, such as: 0.91; more preferably, the ratio of the second dimension D2 to the first dimension D1 < 0.72, but is not limited thereto.

[0088] Here, it can be understood that compared with the first electrode 31 adopting an integral structure with a cross-sectional size of the first dimension D1×the second dimension D2 and the same extension length, in the case where the ratio of the first dimension D1 to the second dimension D2 is greater than 1.1, the first electrode 31 of the capacitor adopting the foregoing structure in the embodiments of the present disclosure can greatly increase the surface area of the first electrode 31. For example, it can increase by nearly at least one-third of the area of the integral structure, and even increase by nearly twice the area of the integral structure.

[0089] Combined with the different structures of the foregoing first electrode 31, some possible implementations of each first electrode 31 and the corresponding capacitor formation steps are illustrated in some embodiments of the present disclosure, but are not limited thereto.

[0090] In some embodiments of the present disclosure, please understand in combination with Figure 2 Figure (a) in. The first electrode 31 includes two first sub-electrodes 311 oppositely arranged in a direction parallel to the substrate (for example, the X direction). That is, in the embodiments of the present disclosure, the central axis of the first electrode 31 of the capacitor in its extending direction (for example, the Y direction) is separated from the middle, forming sub-electrodes 311 located on the left and right sides of the central axis respectively, so as to obtain a double-sided capacitor without changing the original spatial dimensions.

[0091] Correspondingly, please refer to Figure 3, in step S200, the conductive material layer and the insulating material layer are etched to form the first electrodes of the capacitors at the edges of the respective conductive material layers in the first direction parallel to the substrate, and the first electrodes are exposed, including the following steps S210 to S230.

[0092] S210, perform a patterning process on the multi-layer conductive material layer and the multi-layer insulating material layer to form an etching structure; any conductive material layer in the etching structure includes: a first conductive structure extending in the second direction, a plurality of second conductive structures extending in the first direction and connected to the first conductive structure, and a first electrode connected to the end of the second conductive structure far from the first conductive structure.

[0093] Here, both the second direction and the first direction are parallel to the substrate and intersect, for example, orthogonally.

[0094] S220, form an isolation material layer in the etching regions of the multi-layer conductive material layer and the multi-layer insulating material layer.

[0095] S230, etch the isolation material layer in the direction perpendicular to the substrate, and etch the insulating material layer between the first electrodes adjacent in the direction perpendicular to the substrate in the direction parallel to the substrate to expose the first electrodes.

[0096] Exemplarily, please refer to Figures 4 - 9 , the above method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure is described in detail below.

[0097] In step S100, please refer to Figure 4 , provide a substrate 1, and alternately form a multi-layer conductive material layer L1 and a multi-layer insulating material layer L2 on the substrate 1 in the direction perpendicular to the substrate (for example, the Z direction).

[0098] Here, the number of stacked layers of the conductive material layer L1 is related to the number of stacked layers of the capacitor to be formed. The insulating material layer L2 is used to insulate adjacent conductive material layers L1 and the top conductive material layer L1 and the bottom conductive material layer L1. The alternating stacking of the foregoing multi-layer conductive material layer L1 and multi-layer insulating material layer L2 can start with the insulating material layer L2 and end with the insulating material layer L2.

[0099] Exemplarily, the substrate 1 can be composed of a semiconductor material, an insulating material, a conductive material, or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbide (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate 1 can be a layered substrate including a stack such as Si and SiGe, a stack of Si and SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0100] Exemplarily, the conductive material layer L1 includes, but is not limited to, a single layer or a stack of metal materials. For example, it can be a stack of a titanium nitride (TiN) layer and a tungsten (W) layer.

[0101] Exemplarily, the insulating material layer L2 includes, but is not limited to, an oxide layer, such as a silicon dioxide (SiO2) layer.

[0102] Exemplarily, the formation processes of the conductive material layer L1 and the insulating material layer L2 include, but are not limited to, chemical vapor deposition processes.

[0103] In step S210, please refer to Figure 5 Figures (a) and (b) therein for understanding. A patterning process is performed on the multi-layer conductive material layer L1 and the multi-layer insulating material layer L2 to form an etching structure. Any one of the conductive material layers L1 in the etching structure includes: a first conductive structure L11 extending along a second direction (e.g., the X direction), a plurality of second conductive structures L12 extending along a first direction (e.g., the Y direction) and connected to the first conductive structure L11, and a first electrode 31 connected to the end of the second conductive structure L12 away from the first conductive structure L11. The second direction (e.g., the X direction) and the first direction (e.g., the Y direction) are both parallel to the substrate 1 and intersect, for example, orthogonally. The two first sub-electrodes 311 of the first electrode 31 are opposite to each other in the second direction (e.g., the X direction).

[0104] Here, the first conductive structure L11, the second conductive structure L12, and the first electrode 31 can be integrally formed. The etching pattern for forming the etching structure can be directly etched on the side of the end of the second conductive structure L12 away from the first conductive structure L11 to obtain two first sub-electrodes 311 of the first electrode 31 that are oppositely arranged in the second direction (e.g., the X direction). Moreover, there is a first trench G1 between the second conductive structures L12 that are adjacent to each other and on the same side of the first conductive structure L11, and there is a second trench G2 between the two first sub-electrodes 311 in the same first electrode 31. It can be seen that in the embodiments of the present disclosure, the preparation method of the first electrode 31 is simple, and the two first sub-electrodes 311 of the first electrode 31 can be directly obtained while forming the etching structure through a single patterning process. Moreover, when the ratio of the aforementioned first dimension D1 to the second dimension D2 is greater than 1.1, the embodiments of the present disclosure can effectively increase the capacitance value of the capacitor by increasing the facing area between the first electrode 31 and the second electrode.

[0105] Exemplarily, the first conductive structure L11 includes but is not limited to bit lines. Moreover, each second conductive structure L12 integrally connected to the first conductive structure L11 can be used to define the region where the transistor in the memory cell is to be formed.

[0106] It should be added that before performing a single patterning process on the multi-layer conductive material layer L1 and the multi-layer insulating material layer L2 to form the etching structure, a hard mask layer (Mask) covering the top insulating material layer L2 can be formed first, and the aforementioned patterning process can be performed based on the mask patterns in the hard mask layer for defining the bit line pattern and the device active region pattern.

[0107] Exemplarily, the patterning process for forming the etching structure includes but is not limited to a dry etching process.

[0108] In step S220, please refer to Figure 6 Figures (a), (b), and (c) to understand that an isolation material layer 20 is formed in the etching region of the multi-layer conductive material layer and the multi-layer insulating material layer.

[0109] Here, the etching region of the multi-layer conductive material layer and the multi-layer insulating material layer refers to the region where the materials are correspondingly removed when forming the etching structure in the aforementioned step S210, and at least includes the aforementioned first trench G1 and second trench G2 to form a flat appearance.

[0110] Exemplarily, the material of the isolation material layer 20 is the same as that of the insulating material layer L2, for example, both are silicon oxide (SiO2).

[0111] In step S230, please refer to Figure 7Referring to FIGS. (a) and (b) therein, the isolation material layer 20 is etched along the direction perpendicular to the substrate (e.g., the Z direction), and the insulating material layer L2 between the first electrodes 31 adjacent in the direction perpendicular to the substrate (e.g., the Z direction) is etched along the direction parallel to the substrate (e.g., the second direction X direction) to expose the first electrodes 31.

[0112] Here, after the first electrodes 31 are exposed, the remaining isolation material layer 20 constitutes the isolation structure 2.

[0113] Exemplarily, the isolation material layer 20 is etched using a dry etching process.

[0114] Exemplarily, the insulating material layer L2 between the first electrodes 31 adjacent in the direction perpendicular to the substrate (e.g., the Z direction) is etched using a wet etching process.

[0115] In step S300, please refer to Figure 8 FIGS. (a), (b), (c) therein and Figure 9 understand that a dielectric layer 32 covering the first sub-electrodes 311 and a second electrode 33 covering the dielectric layer 32 are formed, such that at least a part of the second electrode 33 is located between the at least two first sub-electrodes 311. The capacitor further includes the dielectric layer 32 and the second electrode 33.

[0116] Exemplarily, the second electrode 33 overlaps with the first sub-electrodes 311 both in the direction parallel to the substrate 1 and in the direction perpendicular to the substrate 1.

[0117] Exemplarily, the formation process of the dielectric layer 32 includes but is not limited to an atomic layer deposition process.

[0118] Exemplarily, the material of the dielectric layer 32 includes but is not limited to a high-K (HK) dielectric material. K is the dielectric constant, and the HK dielectric material refers to a dielectric material having a high dielectric constant K, and the high dielectric constant K is, for example, greater than 3.9.

[0119] Exemplarily, the formation process of the dielectric layer 32 includes but is not limited to an atomic layer deposition process.

[0120] Exemplarily, the second electrode 33 is formed of a conductor material with better conductivity, including but not limited to polysilicon, tungsten, titanium nitride, etc.

[0121] In some embodiments of the present disclosure, please refer to Figure 2 FIG. (b) therein to understand that the first electrode 31 includes two first sub-electrodes 311 and two second sub-electrodes 312, and the second sub-electrodes 312 connect the two first sub-electrodes 311. Correspondingly, please refer to Figure 10, in step S200, the conductive material layer and the insulating material layer are etched to form the first electrodes of the capacitors at the edges of the respective conductive material layers in the first direction parallel to the substrate, and the first electrodes are exposed, including the following steps S210’ to S250’.

[0122] S210’, perform a single patterning process on the multi-layer conductive material layer and the multi-layer insulating material layer to form an etching structure; any conductive material layer in the etching structure includes: a first conductive structure extending in the second direction, and a plurality of initial second conductive structures extending in the first direction and connected to the first conductive structure.

[0123] Here, both the second direction and the first direction are parallel to the substrate and intersect.

[0124] S220’, form an isolation material layer in the etching region of the multi-layer conductive material layer and the multi-layer insulating material layer, and expose the end faces of the initial second conductive structures away from the first conductive structure.

[0125] S230’, based on the exposed end faces of the initial second conductive structures, etch the initial second conductive structures in a direction parallel to the substrate to form second conductive structures and first electrode receiving grooves at the ends of the second conductive structures away from the first conductive structure.

[0126] S240’, form a first electrode on the side walls of the first electrode receiving grooves.

[0127] S250’, etch the isolation material layer in a direction perpendicular to the substrate, and etch the insulating material layer between the first electrodes adjacent in the direction perpendicular to the substrate in a direction parallel to the substrate to expose the first electrodes.

[0128] Thus, in the embodiments of the present disclosure, by etching the initial second conductive structures in a direction parallel to the substrate, first electrode receiving grooves can be formed, and a first electrode can be conformally formed on the side walls of the first electrode receiving grooves, so that the first electrode is in a hollow ring shape or a hollow cylinder shape, effectively increasing the facing area of the electrodes in the capacitor without changing the original spatial dimensions. For example, the increase in the facing area can be nearly doubled.

[0129] On this basis, in some embodiments of the present disclosure, please refer to Figure 11 , in step S240’, forming a first electrode on the side walls of the first electrode receiving grooves includes the following steps S241’ to S242’.

[0130] S241’, conformally form a first electrode material layer in the first electrode receiving grooves and on the side walls of the insulating material layer and the isolation material layer.

[0131] S242’, removing the first electrode material layer on the sidewalls of both the insulating material layer and the isolation material layer, such that the first electrode material layer remaining in the first electrode receiving groove forms the first electrode.

[0132] In some embodiments of the present disclosure, please continue to refer to Figure 2 Figure (b) in, two first sub - electrodes 311 and two second sub - electrodes 312 in the first electrode 31 are interconnected to form an annular structure. Correspondingly, please refer to Figure 12 , in step S300, forming a dielectric layer covering the first electrode and a second electrode covering the dielectric layer, including the following steps S310 and S320.

[0133] S310, forming a dielectric layer on the inner surface of the ring, the outer surface of the ring and the end face away from the second conductive structure of the annular structure.

[0134] S320, forming an inner electrode covering the dielectric layer inside the ring of the annular structure, and forming an outer electrode covering the dielectric layer and connected to the inner electrode outside the ring of the annular structure; the second electrode includes the inner electrode and the outer electrode.

[0135] Exemplarily, please refer to Figures 13 - 19 , the above - mentioned preparation method of another semiconductor structure provided by the embodiments of the present disclosure is described in detail below.

[0136] After performing step S100, in step S210’, please refer to Figure 13 Figures (a), (b) and (c) in, performing a single patterning process on the multi - layer conductive material layer L1 and the multi - layer insulating material layer L2 to form an etching structure; any conductive material layer L1 in the etching structure includes: a first conductive structure L11 extending along the second direction (e.g., the X direction), and a plurality of initial second conductive structures L12a extending along the first direction (e.g., the Y direction) and connected to the first conductive structure L11.

[0137] Here, the second direction (e.g., the X direction) and the first direction (e.g., the Y direction) are both parallel to the substrate 1 and intersect, for example, orthogonally.

[0138] In step S220’, please refer to Figure 14 Figures (a), (b) and (c) in, forming an isolation material layer 20 in the etching region of the multi - layer conductive material layer L1 and the multi - layer insulating material layer L2, and exposing the end face of the initial second conductive structure L12a away from the first conductive structure L11.

[0139] Here, it can be understood that in order to expose the end face of the initial second conductive structure L12a away from the first conductive structure L11, the isolation material layer 20 is not formed in all the etching regions of each conductive material layer L1 and each insulating material layer L2; for example Figure 14As shown in Figure (a) therein, the sidewall of the isolation material layer 20 can be flush with the end face of the initial second conductive structure L12a away from the first conductive structure L11 and perpendicular to the substrate 1.

[0140] In step S230’, please refer to Figure 15 Figures (a), (b) and (c) therein. Based on the exposed end face of the initial second conductive structure L12a, etch the initial second conductive structure L12a along the direction parallel to the substrate (e.g., the first direction Y) to form the second conductive structure L12 and the first electrode accommodating groove G3 located at one end of the second conductive structure L12 away from the first conductive structure L11.

[0141] Here, the etching dimension of the initial second conductive structure L12a in the first direction Y is the extension length of the first electrode 31 to be formed in the first electrode accommodating groove G3.

[0142] Exemplarily, the etching process of the initial second conductive structure L12a includes but is not limited to the wet etching process.

[0143] In step S240’, please refer to Figure 16 Figures (a), (b) and (c) therein and Figure 17 Figures (a) and (b) therein. Form the first electrode 31 on the groove wall of the first electrode accommodating groove G3.

[0144] Exemplarily, step S240’ may include S241’ to S242’.

[0145] In step S241’, as Figure 16 shown in Figures (a), (b) and (c) therein, conformally form the first electrode material layer 310 in the first electrode accommodating groove G3 and on the sidewalls of the insulating material layer L2 and the isolation material layer 20.

[0146] Here, conformally forming means that: the first electrode material layer 310 is a thin layer structure, and the surface of the first electrode material layer 310 mimics the groove wall morphology of the first electrode accommodating groove G3 and the sidewall morphologies of the insulating material layer L2 and the isolation material layer 20, so that the surface morphology of the first electrode material layer 310 is consistent with the groove wall morphology of the first electrode accommodating groove G3 and the sidewall morphologies of the insulating material layer L2 and the isolation material layer 20.

[0147] Exemplarily, the first electrode material layer 310 is formed by a deposition process, such as including but not limited to the Atomic Layer Deposition (ALD) process.

[0148] Exemplarily, the material of the first electrode material layer 310 includes, but is not limited to, one or more of titanium nitride (TiN), tungsten (W), indium tin oxide (ITO), or polysilicon (poly).

[0149] In step S242’, as Figure 17 shown in FIGS. (a) and (b) of , the first electrode material layer 310 on the sidewalls of both the insulating material layer L2 and the isolation material layer 20 is removed, so that the first electrode material layer 310 remaining in the first electrode receiving groove G3 forms the first electrode 31.

[0150] Here, by removing the first electrode material layer 310 on the sidewalls of both the insulating material layer L2 and the isolation material layer 20, the interconnection between adjacent first electrodes 31 can be effectively blocked to ensure that the first electrodes 31 of each capacitor 3 can work independently.

[0151] Exemplarily, two first sub - electrodes 311 and two second sub - electrodes 312 in the first electrode 31 are interconnected to form an annular structure.

[0152] Exemplarily, the first electrode 31 further includes an interconnection portion 313 located at the bottom of the first electrode receiving groove G3 (i.e., the end face of the second conductive structure L12 away from the first conductive structure L11). The interconnection portion 313 is respectively connected to the first sub - electrode 311 and the second sub - electrode 312.

[0153] In step S250’, please refer to Figure 18 FIGS. (a), (b), and (c) of for understanding. The isolation material layer 20 is etched along the direction perpendicular to the substrate (e.g., the Z - direction), and the insulating material layer L2 between the first electrodes 31 adjacent in the direction perpendicular to the substrate (e.g., the Z - direction) is etched along the direction parallel to the substrate (e.g., the second direction X - direction) to expose the first electrode 31.

[0154] Here, after the first electrode 31 is exposed, the remaining isolation material layer 20 forms the isolation structure 2.

[0155] Exemplarily, the isolation material layer 20 is etched using a dry etching process.

[0156] Exemplarily, the insulating material layer L2 between the first electrodes 31 adjacent in the direction perpendicular to the substrate (e.g., the Z - direction) is etched using a wet etching process.

[0157] In some embodiments of the present disclosure, as Figure 18 shown in FIG. (b) of , two first sub - electrodes 311 and two second sub - electrodes 312 in the first electrode 31 are interconnected to form an annular structure. Correspondingly, please refer to Figure 19Understand from FIGS. (a), (b) and (c) that in step S300, a dielectric layer 32 covering the first electrode 31 is formed, and a second electrode 33 covering the dielectric layer 32 is formed.

[0158] Here, for the formation processes and formation materials of the dielectric layer 32 and the second electrode 33, reference can be made to the relevant descriptions in some of the foregoing embodiments.

[0159] Exemplarily, step S300 may include steps S310 and S320.

[0160] In step S310, please refer to FIGS. (a), (b) and (c) Figure 18 and FIGS. (a), (b) and (c) Figure 19 to understand that the dielectric layer 32 is formed on the inner surface of the ring, the outer surface of the ring and the end face away from the second conductive structure L12 of the annular structure.

[0161] In step S320, please refer to FIGS. (a), (b) and (c) Figure 19 to understand that an inner electrode 331 covering the dielectric layer 32 is formed inside the ring of the annular structure, and an outer electrode 332 covering the dielectric layer 32 and connected to the inner electrode 331 is formed outside the ring of the annular structure.

[0162] It is worth mentioning that each storage unit of the memory, in addition to including a capacitor, further includes a transistor electrically connected to the capacitor correspondingly. It can be understood that after the capacitor is formed, regardless of the structure of the first electrode in the capacitor, the transistor can be fabricated using the same process. In the following some embodiments, taking the storage unit having a 1T1C structure as an example, the fabrication process of a kind of transistor in the semiconductor structure is exemplified, but the structure and fabrication process of the transistor in the storage unit are not limited thereto, and there may be other possible implementation manners according to requirements. The embodiments of the present disclosure do not limit this.

[0163] Please refer to Figure 20 FIGS. (a), (b) and (c) to etch the second conductive structure L12 and the insulating material layer L2 along the direction perpendicular to the substrate (for example, the Z direction) to form an etching hole H penetrating through the second conductive structure L12 and the insulating material layer L2.

[0164] Exemplarily, the cross-sectional shape of the etching hole H includes but is not limited to a circle, an ellipse or a rectangle, etc. And, the maximum dimension of the etching hole H in the X direction is smaller than the dimension of the second conductive structure L12 in the X direction.

[0165] Exemplarily, the formation process of the etching hole H includes but is not limited to a dry etching process.

[0166] Please refer to Figure 21In FIGS. (a), (b), and (c), along the direction parallel to the substrate (e.g., including the X direction and the Y direction) of the etching holes H, the second conductive structure L12 is etched to form the transistor accommodating groove G4. Here, the etching size of the second conductive structure L12 needs to be precisely controlled to balance the process window and the process implementation difficulty. For example, after etching the second conductive structure L12 to form the transistor accommodating groove G4, the maximum size of the transistor accommodating groove G4 in the X direction is equal to the size of the second conductive structure L12 in the X direction, so as to effectively isolate the second conductive structure L12 and expose the side wall of the corresponding isolation structure 2 within the transistor accommodating groove G4.

[0167] For example, the forming process of the transistor accommodating groove G4 includes but is not limited to the wet etching process. And when the material of the second conductive structure L12 is metal and the material of the insulating material layer L2 is oxide, an acid solution with a relatively high etching selectivity ratio for metal and oxide is selected as the etching solution for wet etching the second conductive structure L12, which can effectively avoid etching loss of the insulating material layer L2 while etching the second conductive structure L12.

[0168] Please refer to Figure 22 In FIGS. (a), (b), and (c), a semiconductor material layer 410, a gate dielectric material layer 420, and a gate material layer 430 are conformally covered in sequence within the etching holes H and the transistor accommodating groove G4.

[0169] Here, the semiconductor material layer 410 conformally covers the inner walls of the etching holes H and the transistor accommodating groove G4, and the gate dielectric material layer 420 conformally covers the semiconductor material layer 410. And after the semiconductor material layer 410 and the gate dielectric material layer 420 are formed in sequence, the hole size reserved for the corresponding transistor accommodating groove G4 (i.e., the transistor channel region) needs to be larger than the hole size reserved for the corresponding insulating material layer L2 (i.e., the parasitic MOS region) (the difference between the two is related to the etching size of the aforementioned second conductive structure L12), so as to ensure that the deposition thickness of the gate material layer 430 formed in the transistor channel region is greater than the deposition thickness of the gate material layer 430 formed in the parasitic MOS region.

[0170] For example, the forming processes of the semiconductor material layer 410, the gate dielectric material layer 420, and the gate material layer 430 include but are not limited to the atomic layer deposition process.

[0171] For example, the material of the semiconductor material layer 410 includes but is not limited to metal oxides. The material of the metal oxide can be, for example, Indium Gallium Zinc Oxide (IGZO), or it can also be ITO, IWO, ZnO x , InO x , In2O3, InWO, SnO2, TiOx 、InSnO x 、Zn x O y N z 、Mg x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、Zr x In y Zn z O a 、Hf x In y Zn z O a 、Sn x In y Zn z O a 、Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn z O a 、Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a 、InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide) or IZO x and other materials (where the subscripts x, y, z, a, and d are respectively used to indicate the number of atoms of the corresponding elements in the corresponding chemical formula), as long as the leakage current of the transistor can meet the requirements, and specific adjustments can be made according to the actual situation.

[0172] Exemplarily, the material of the gate dielectric layer 420 includes but is not limited to HK materials, such as alumina (Al2O3).

[0173] Exemplarily, the gate material layer 430 includes but is not limited to a metal gate material layer, such as an indium tin oxide (ITO) layer doped with tin, a stack of TiN and W, an aluminum-doped zinc oxide (AZO) layer, or an indium-doped zinc oxide (IZO) layer, etc.

[0174] It is worth mentioning that the film thickness of the aforementioned formed gate material layer 430 can be determined according to the process dimensions. Moreover, the gate material layer 430 can also serve as a protective layer (also referred to as a sacrificial layer) for the semiconductor material layer 410 when etching the semiconductor material layer 410 and the gate dielectric material layer 420 in the parasitic MOS region subsequently. Thus, without the need to be removed after serving as an etching protective layer, the gate material layer 430 can be directly matched with subsequent processes to achieve its electrical connection with the word line.

[0175] Please refer to Figure 23 Figures (a), (b), and (c) therein. First, dry-etch (anisotropic etch) the gate material layer 430 to expose the sidewalls of the gate dielectric material layer 420 in the parasitic MOS region, and make the gate material layer 430 remaining in the transistor accommodation groove G4 form the gate 43 (or protective layer or sacrificial layer) of the transistor 4. That is: as Figure 23 shown in Figures (b) and (c) therein, the gate material layer 430 on the sidewalls of the parasitic MOS region will be completely etched, and the gate material layer 430 on the inner sidewalls of the transistor accommodation groove G4 is basically all retained.

[0176] Please continue to refer to Figure 23 Figures (a), (b), and (c) therein. Then, adopt a wet-etch (isotropic etch) process to sequentially remove the semiconductor material layer 410 and the gate dielectric material layer 420 in the parasitic MOS region, and make the semiconductor material layer 410 remaining in the transistor accommodation groove G4 form the semiconductor layer 41 of the transistor 4, and make the gate dielectric material layer 420 remaining in the transistor accommodation groove G4 form the gate dielectric layer 42 of the transistor 4.

[0177] Exemplarily, the gate material layer 430 is an ITO layer, the semiconductor material layer 410 is an IGZO layer, the gate dielectric material layer 420 is an Al2O3 layer, and the wet-etching solution for the semiconductor material layer 410 and the gate dielectric material layer 420 can be a dilute hydrochloric acid (HCl) solution that has a relatively high etching selectivity for both IGZO and Al2O3 with respect to ITO, or strong acids such as acetic acid or perchloric acid can also be used. Thus, the wet-etching solution can first react with the exposed gate dielectric material layer 420 in the parasitic MOS region to remove the gate dielectric material layer 420 in the parasitic MOS region and expose the semiconductor material layer 410 in the parasitic MOS region, and then react with the exposed semiconductor material layer 410 in the parasitic MOS region to remove the semiconductor material layer 410 in the parasitic MOS region.

[0178] It can be understood that at room temperature conditions (such as 20°C to 30°C), dilute HCl with a mass percentage in the range of 1% to 20% has a very slow etching rate for the ITO layer, while the etching rate for the IGZO layer is extremely fast; for example, the etching selectivity of dilute HCl for IGZO / ITO can be as high as 1000 to ensure that the IGZO layer / Al2O3 layer on the sidewalls of the parasitic MOS region can be completely etched away.

[0179] In addition, in order to prevent short - circuiting of the subsequent word line WL and the semiconductor layer 41 due to over - etching of the semiconductor material layer 410 and the gate dielectric material layer 420 in the transistor accommodation groove G4 during the above - mentioned wet etching, please refer to Figure 24 Figures (a), (b), and (c) therein. Before forming the word line WL, an insulating layer 5 can be formed on the sidewalls of the parasitic MOS region and the exposed surfaces of the semiconductor layer 41 and the gate dielectric layer 42 in the transistor accommodation groove G4 first, and then the word line WL covering the insulating layer 5 and electrically connected to the gate 43 is formed.

[0180] Exemplarily, the insulating layer 5 can be obtained by first forming an insulating material layer and then dry - etching to remove the insulating material layer on the sidewalls of the gate 43.

[0181] Exemplarily, the material of the insulating layer 5 includes but is not limited to HK materials, such as aluminum oxide (Al2O3).

[0182] Exemplarily, the word line WL and the gate material layer 430 are made of the same material.

[0183] Some embodiments of the present disclosure also provide a semiconductor structure, including a substrate and one or more memory cells disposed on the substrate. The memory cell includes a capacitor and a transistor, and the capacitor can be prepared by using the preparation method of the semiconductor structure described in any of the above - mentioned embodiments. The semiconductor structure also has all the technical advantages of the foregoing preparation method.

[0184] Exemplarily, please refer to Figure 8 Figures (a), (b), and (c) therein and Figure 18 Figures (a), (b), and (c) therein. The capacitor 3 includes: a first electrode 31, a dielectric layer 32, and a second electrode 33. The first electrode 31 includes at least two first sub - electrodes 311 separated from each other; the at least two first sub - electrodes 311 are respectively connected to the same transistor 4. The second electrode 33 covers the first sub - electrodes 311, and at least a part of the second electrode 33 is located between the at least two first sub - electrodes 311. The dielectric layer 32 is located between the first sub - electrodes 311 and the second electrode 33.

[0185] It can be understood that Figure 8 andFigure 18 No transistor 4 has been formed within the semiconductor structure shown. Therefore, Figure 8 and Figure 18 the area where transistor 4 is to be formed in is marked with a dashed box to clearly show the distribution position and connection relationship between the first electrode 31 and transistor 4.

[0186] In some embodiments of the present disclosure, the first electrode 31 includes two first sub - electrodes 311 arranged in a second direction (e.g., the X - direction) parallel to the substrate 1. In this way, it is convenient for manufacturing and is conducive to improving production efficiency.

[0187] Exemplarily, please refer to Figure 2 figures (a) and (b) in to understand that the first electrode 31 includes two first sub - electrodes 311 arranged in a second direction parallel to the substrate; the first sub - electrode 311 includes a bottom surface close to the substrate, a top surface far from the substrate, and a side surface connecting the top surface and the bottom surface; the side surfaces of the two first sub - electrodes 311 facing away from each other are parallel to each other; the dimensions of the two first sub - electrodes 311 in the direction perpendicular to the substrate (e.g., the Z - direction) are equal, which is the first dimension D1. The distance between the side surfaces of the two first sub - electrodes 311 facing away from each other is the second dimension D2. Among them, the ratio of the first dimension D1 to the second dimension D2 is greater than 1.1. More preferably, the ratio of the first dimension D1 to the second dimension D2 is greater than 1.4; in other words, the ratio of the second dimension D2 to the first dimension D1 is less than another target threshold, such as: 0.91; more preferably, the ratio of the second dimension D2 to the first dimension D1 < 0.72, but not limited thereto.

[0188] Here, it can be understood that compared with the first electrode 31 adopting an integral structure with a cross - sectional size of D1×D2 and the same extension length, when the ratio of the first dimension D1 to the second dimension D2 is greater than the target threshold, the first electrode 31 of the capacitor adopting the aforementioned structure in the embodiments of the present disclosure can greatly increase the surface area of the first electrode 31. For example, it can increase the area by at least one - third of the overall structure, and even increase the area by nearly twice the overall structure.

[0189] Exemplarily, please refer to Figure 18 figures (b) and (c) in and Figure 19As understood from FIGS. (b) and (c), the first electrode 31 includes two first sub - electrodes 311 separated from each other, and at least one second sub - electrode 312 connecting the two first sub - electrodes 311. For example, the first electrode 31 includes two second sub - electrodes 312, and the two second sub - electrodes 312 are arranged in a direction perpendicular to the substrate (e.g., the Z - direction). For example, the two first sub - electrodes 311 and the two second sub - electrodes 312 are connected to each other to form an annular structure. For example, the second electrode 33 includes an inner electrode 331 located inside the ring of the annular structure, and an outer electrode 332 located outside the ring of the annular structure and connected to the inner electrode 331.

[0190] Exemplarily, the first electrode 31 further includes an interconnecting portion 313 located on the end face of the second conductive structure L12 away from the first conductive structure L11 to connect the first sub - electrode 311 and the second sub - electrode 312 respectively. By providing the interconnecting portion 313 in the first electrode 31 in the embodiments of the present disclosure, it is beneficial to further increase the facing area between the first electrode 31 and the second electrode 33 through the interconnecting portion 313, thereby further increasing the capacitance value of the capacitor 3.

[0191] Thus, in the memory provided by the embodiments of the present disclosure, the first electrode 31 of the capacitor 3 can have various possible implementations to effectively increase the capacitance value without increasing the size of the capacitor or reducing the size of the capacitor.

[0192] It should be added that the storage units in some of the above - mentioned embodiments can be understood as storage units in a logic circuit. For example, a single - transistor single - capacitor (1T1C) or a dual - transistor single - capacitor (2T1C) is used as a storage unit, without limiting the wiring characteristics or the characteristics of the shape and structure of the storage unit.

[0193] In some embodiments, please refer to Figure 24 FIGS. (a), (b), and (c). The storage unit U adopts a 1T1C structure, that is, it includes a capacitor 3 and a transistor 4, and multiple storage units U are sequentially stacked in a three - dimensional space. Among them, the first conductive structure L11 integrally connected to the second conductive structure L12 is a bit line. The word line WL penetrates through each second conductive structure L12 and the corresponding insulating material layer L2 in a direction perpendicular to the substrate (e.g., the Z - direction). The transistor 4 includes a gate 43, a gate dielectric layer 42, and a semiconductor layer 41 sequentially surrounding the side wall of the word line WL; and the gate 43, the gate dielectric layer 42, and the semiconductor layer 41 are all located in a transistor accommodation groove G4 formed in the second conductive structure L12. The two parts of the second conductive structure L12 separated by the transistor accommodation groove G4 are connected by the semiconductor layer 41, and the semiconductor layer 41 constitutes the channel region of the transistor 4.

[0194] Here, it should be added that please continue to refer to Figure 24Understand with reference to FIGS. (a), (b), and (c) herein and in combination with the manufacturing process of the transistor 4 in some of the foregoing embodiments. The memory further includes an insulating layer 5 disposed between the word line WL and the gate dielectric layer 42 and between the word line WL and the semiconductor layer 41.

[0195] Exemplarily, the insulating layer 5 may also be located between the word line WL and the insulating material layer L2.

[0196] In the embodiments of the present disclosure, the capacitor 3 adopts the foregoing structure, and the semiconductor layer 41 in the transistor 4 is made of metal oxide, such as IGZO or ITO, IWO, ZnO x , InO x , In2O3, InWO, SnO2, TiO x , InSnO x , Zn x O y , N z , Mg x , Zn y O z , In x , Zn y O z , In x , Ga y , Zn z O a , Zr x , In y , Zn z O a , Hf x , In y , Zn z O a , Sn x , In y , Zn z O a , Al x , Sn y , In z , Zn a O d , Si x , In y , Zn z O a , Zn x , Sn y O z , Al x , Zn y , Sn z O a , Ga x , Zn y , Sn z O a , Zr x , Zny Sn z O a 、InGaSiO, IAZO, IGO, IZO (indium - zinc - oxide), IZO x etc., which is also conducive to further improving the charge data retention ability and data sensing and reading ability of the storage unit.

[0197] Some embodiments of the present disclosure also provide an electronic device, such as a data storage device, a photocopier, a network device, a household appliance, an instrument, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal, etc., which are devices with data storage functions. The electronic device may include the semiconductor structure described in some of the foregoing embodiments. The technical advantages possessed by the foregoing semiconductor structure are also possessed by the electronic device, and will not be elaborated here.

[0198] In some embodiments, the electronic device includes a housing, a circuit board disposed in the housing, and a semiconductor structure integrated on the circuit board. The structure of the semiconductor structure may refer to the relevant descriptions in some of the foregoing embodiments. The electronic device may also include other necessary elements or components, which are not limited in the embodiments of the present disclosure.

[0199] In some embodiments, an external control device such as a processor or an actuator coupled to the semiconductor structure may also be integrated on the circuit board. For example, the electronic device further includes a processor integrated on the circuit board. The processor is coupled to the semiconductor structure, and the processor can control the read and write operations of the semiconductor structure.

[0200] The technical features of the above - described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above - described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0201] The above - described embodiments only represent several implementation manners of the present disclosure, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure should be subject to the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that, Including: Providing a substrate, and alternately forming a plurality of conductive material layers and a plurality of insulating material layers on the substrate along a direction perpendicular to the substrate; Etching the conductive material layer and the insulating material layer to respectively form a first electrode of a capacitor at an edge of each of the conductive material layers in a first direction parallel to the substrate, and exposing the first electrode; wherein, the first electrode includes at least two first sub-electrodes separated from each other; Forming a dielectric layer covering the first sub-electrodes, and a second electrode covering the dielectric layer, such that at least a part of the second electrode is located between the at least two first sub-electrodes; the capacitor further includes the dielectric layer and the second electrode.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein, The first electrode includes two of the first sub-electrodes arranged in a second direction parallel to the substrate; the first direction and the second direction are both parallel to the substrate and intersect.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein, Each of the first sub-electrodes includes a bottom surface close to the substrate and a top surface away from the substrate, and a side surface connecting the top surface and the bottom surface; the side surfaces of the two first sub-electrodes facing away from each other are parallel to each other.

4. The semiconductor structure according to claim 3, wherein The two first sub-electrodes have equal dimensions in a direction perpendicular to the substrate, which is a first dimension; The distance between the side surfaces of the two first sub-electrodes facing away from each other is a second dimension; wherein, the ratio of the first dimension to the second dimension is greater than 1.

1.

5. The method for manufacturing a semiconductor structure according to claim 2, wherein, The etching of the conductive material layer and the insulating material layer to respectively form a first electrode of a capacitor at an edge of each of the conductive material layers in a first direction parallel to the substrate, and exposing the first electrode, includes: Performing a single patterning process on the plurality of conductive material layers and the plurality of insulating material layers to form an etching structure; any one of the conductive material layers in the etching structure includes: a first conductive structure extending along the second direction, a plurality of second conductive structures extending along the first direction and connected to the first conductive structure, and the first electrode connected to an end of the second conductive structure away from the first conductive structure; Forming an isolation material layer in an etching region of the plurality of conductive material layers and the plurality of insulating material layers; Etching the isolation material layer along a direction perpendicular to the substrate, and etching the insulating material layer between the first electrodes adjacent in the direction perpendicular to the substrate along a direction parallel to the substrate to expose the first electrode.

6. The method for preparing a semiconductor structure according to claim 2, wherein, The first electrode includes two of the first sub-electrodes and two second sub-electrodes, the second sub-electrodes connecting the two first sub-electrodes; the etching of the conductive material layer and the insulating material layer to respectively form a first electrode of a capacitor at an edge of each of the conductive material layers in a first direction parallel to the substrate, and exposing the first electrode, includes: Perform a patterning process on the multi-layer conductive material layer and the multi-layer insulating material layer to form an etching structure; any one of the conductive material layers in the etching structure includes: a first conductive structure extending along the second direction, and a plurality of initial second conductive structures extending along the first direction and connected to the first conductive structure; Form an isolation material layer in the etching region of the multi-layer conductive material layer and the multi-layer insulating material layer, and expose the end face of the initial second conductive structure away from the first conductive structure; Based on the exposed end face of the initial second conductive structure, etch the initial second conductive structure along the direction parallel to the substrate to form a second conductive structure and a first electrode accommodating groove at one end of the second conductive structure away from the first conductive structure; Form the first electrode on the groove wall of the first electrode accommodating groove; Etch the isolation material layer along the direction perpendicular to the substrate, and etch the insulating material layer between the first electrodes adjacent in the direction perpendicular to the substrate along the direction parallel to the substrate to expose the first electrode.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein, The forming the first electrode on the groove wall of the first electrode accommodating groove includes: Conformally form a first electrode material layer in the first electrode accommodating groove and on the side walls of the insulating material layer and the isolation material layer; Remove the first electrode material layer on the side walls of both the insulating material layer and the isolation material layer, so that the first electrode material layer remaining in the first electrode accommodating groove constitutes the first electrode.

8. The method for preparing a semiconductor structure according to claim 6, wherein Two of the first sub-electrodes and two of the second sub-electrodes in the first electrode are connected to each other to form a ring structure; The forming the dielectric layer covering the first sub-electrode and the second electrode covering the dielectric layer includes: Form the dielectric layer on the inner surface, outer surface of the ring of the ring structure and the end face away from the second conductive structure; Form an inner electrode covering the dielectric layer inside the ring of the ring structure, and form an outer electrode covering the dielectric layer and connected to the inner electrode outside the ring of the ring structure; the second electrode includes the inner electrode and the outer electrode.

9. The method for preparing a semiconductor structure according to claim 6, wherein The isolation material layer is etched by a dry etching process, and the insulating material layer between the first electrodes adjacent in the direction perpendicular to the substrate is etched by a wet etching process.

10. The method for manufacturing a semiconductor structure according to claim 6, wherein, The isolation material layer and the insulating material layer are made of the same material.

11. A semiconductor structure, characterized in that, Includes: A substrate and one or more memory cells provided on the substrate; The memory cell includes a capacitor and a transistor; wherein, the capacitor includes: A first electrode including at least two first sub-electrodes separated from each other; the at least two first sub-electrodes are respectively connected to the same transistor; A second electrode covering the first sub-electrode, and at least a part of the second electrode is located between the at least two first sub-electrodes; A dielectric layer located between the first sub-electrode and the second electrode.

12. The semiconductor structure according to claim 11, wherein, The first electrode includes two first sub-electrodes arranged in the second direction parallel to the substrate.

13. The semiconductor structure according to claim 12, wherein The first sub - electrode includes a bottom surface close to the substrate, a top surface far from the substrate, and a side surface connecting the top surface and the bottom surface; the side surfaces of the two first sub - electrodes facing away from each other are parallel to each other.

14. The semiconductor structure according to claim 13, wherein The two first sub - electrodes have equal dimensions in the direction perpendicular to the substrate, which is the first dimension; The distance between the side surfaces of the two first sub - electrodes facing away from each other is the second dimension; wherein, the ratio of the first dimension to the second dimension is greater than 1.

1.

15. The semiconductor structure according to claim 11, wherein The first electrode further includes at least one second sub - electrode connecting the two first sub - electrodes.

16. The semiconductor structure according to claim 15, wherein The first electrode includes two second sub - electrodes, and the two second sub - electrodes are arranged in the direction perpendicular to the substrate.

17. The semiconductor structure according to claim 16, wherein, The two first sub - electrodes and the two second sub - electrodes are connected to each other to form a ring structure.

18. The semiconductor structure according to claim 17, wherein, The second electrode includes an inner electrode located inside the ring of the ring structure, and an outer electrode located outside the ring of the ring structure and connected to the inner electrode.

19. The semiconductor structure according to claim 15, wherein, The first electrode further includes an interconnecting portion; The interconnecting portion is respectively connected to the first sub - electrode and the second sub - electrode.

20. An electronic device, comprising the semiconductor structure according to any one of claims 11 - 19.

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