Power consumption control in memory system

Abstract

A method for reducing power consumption in a memory system includes determining, by a controller of the memory system and based on a plurality of commands received by the memory system during a first time period, that a condition is satisfied (602); in response to determining that the condition is satisfied, a frequency or voltage applied to one or more processors of the controller is reduced by the controller (604).

Description

Technical Field

[0001] The present disclosure relates to a memory device, a memory system, and a method for power consumption control in a flash memory. Background Art

[0002] A flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. The flash memory includes a NOR flash memory and a NAND flash memory. Various operations, such as a programming (writing) or reading operation, can be performed by the flash memory. Operations performed by the flash memory may affect the power consumption of the flash memory. Summary of the Invention

[0003] The present disclosure relates to a memory system, a method, and a controller for reducing power consumption in a memory system. An exemplary method includes: determining, by a controller of a memory system and based on a plurality of commands received by the memory system during a first time period, that a condition is satisfied. In response to determining that the condition is satisfied, reducing, by the controller, a frequency or a voltage applied to one or more processors of the controller.

[0004] Although generally described as computer-implemented software embodied on a tangible medium that processes and transforms the corresponding data, some or all aspects in various aspects may be computer-implemented methods, or may be further included in a corresponding system or other device for performing the described functionality. Details of these aspects and other aspects and embodiments of the present disclosure are set forth in the drawings and the following description. Other features, objects, and advantages of the present disclosure will be apparent from the description, the drawings, and the claims. Brief Description of the Drawings

[0005] Figure 1 A block diagram of an exemplary system having a memory device in accordance with some aspects of the present disclosure is shown.

[0006] Figure 2 A schematic diagram of an exemplary memory system in accordance with some aspects of the present disclosure is shown.

[0007] Figure 3 A schematic diagram of an exemplary memory controller coupled to a power management controller in accordance with some aspects of the present disclosure is shown.

[0008] Figure 4 A schematic diagram of an exemplary workflow for changing a core frequency or a core voltage of a processor of a memory controller in a memory system in accordance with some aspects of the present disclosure is shown.

[0009] Figure 5Shows an example of the change in power consumption associated with different memory device operations after a change in core frequency and core voltage according to some aspects of the present disclosure.

[0010] Figure 6 Shows an example of a flowchart of a method for reducing power consumption in a memory system according to some aspects of the present disclosure.

[0011] Like reference numerals and names in the various figures indicate like elements. Detailed Description

[0012] This specification relates to a memory system, a method, and a controller for reducing power consumption in a memory system. In some cases, a memory device (e.g., a NAND flash memory device) in a memory system may perform operations including sequential read and sequential write of data. The sequential read and write operations of the memory device are operations in which data is read from or written to the memory device sequentially. The power consumption of the memory system caused by the sequential read or sequential write operation of the memory device in the memory system may increase as the speed of the sequential read or sequential write operation increases. To avoid excessive power consumption during the sequential read or sequential write operation, a memory controller that controls the memory device in the memory system may change the core frequency or core voltage applied to the processor of the memory controller to reduce the power consumption of the memory system while maintaining a high speed of the sequential read or sequential write operation. Changing the core frequency or core voltage may also help avoid an excessive temperature of the memory device during the sequential read or sequential write operation.

[0013] Figure 1 Shows a block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game controller, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device. As Figure 1 shown, the system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to or receive data from the memory device 104.

[0014] Memory device 104 can be any memory device disclosed in the present disclosure. According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108, and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in a low-duty-cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in a high-duty-cycle environment, such as a Solid State Drive (SSD) or an Embedded Multimedia Card (eMMC), which is used as a data storage device for mobile devices such as smart phones, tablets, laptop computers, etc. and enterprise storage arrays. Memory controller 106 can be configured to control the operations of memory device 104 (e.g., read operations, erase operations, and program operations). Memory controller 106 can also be configured to manage various functions regarding data stored in or to be stored in memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, memory controller 106 is further configured to process error correction codes (ECC) regarding data read from or written to memory device 104. Memory controller 106 can also perform any other appropriate functions, such as formatting memory device 104.

[0015] Memory controller 106 can communicate with an external device (e.g., host 108) according to a specific communication protocol. For example, memory controller 106 can communicate with an external device through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, High-Speed PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0016] The memory controller 106 and one or more memory devices 104 may be integrated into various types of storage devices, such as being included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products. In some embodiments, the memory system 102 may be implemented and packaged into an SSD, such as a client SSD or an enterprise SSD. The client SSD may be used in electronic devices, such as personal computers, digital cameras, smart phones, mobile devices, etc. The enterprise SSD may be used in an enterprise environment, such as a data center or a server.

[0017] Figure 2 A schematic diagram of an exemplary memory system 200 is shown. The memory system 200 includes a memory controller 202, a volatile memory device 206, non-volatile memory devices 208, 210, and 212, and a power management controller 204. Figure 3 The memory controller 202 is described in more detail herein. The memory controller 202 is coupled to the volatile memory device 206, the non-volatile memory devices 208, 210, and 212, and the power management controller 204. In some embodiments, the volatile memory device 206 may be used to cache data accessible by the memory controller 202. In some embodiments, the memory device 206 may be a non-volatile memory device.

[0018] In some embodiments, the memory controller 202 controls operations performed by the non-volatile memory devices 208, 210, and 212. Exemplary operations may include sequential read operations, sequential write operations, idle operations, and other operations. Other operations may include random read operations and random write operations. The memory controller 202 may change the core frequency or core voltage applied to the processor in the memory controller 202. Figure 4 An exemplary workflow for changing the core frequency or core voltage of the processor of the memory controller in the memory system is shown.

[0019] In some embodiments, the memory controller 202 may send a command to the power management controller 204 such that the power management controller 204 may change the core voltage applied to the processor in the memory controller 202.

[0020] Figure 3 A schematic diagram 300 of an exemplary memory controller coupled to a power management controller is shown. The memory controller 302 may correspond to Figure 2The memory controller 202 therein. The memory controller 302 includes tightly coupled memories 304 and 312, a main CPU 306, other CPUs 314, a shared memory 316, and a phase-locked loop (PLL) frequency adjustment module 308. The main CPU 306 and other CPUs 314 are processors in the memory controller 302 for supporting the operation of the memory device controlled by the memory controller 302. The other CPUs 314 may include one or more auxiliary CPUs controlled by the main CPU 306. The memory controller 302 is coupled to a power management controller 310. The tightly coupled memory 304 is coupled to the main CPU 306, and the tightly coupled memory 312 is coupled to the other CPUs 314. The tightly coupled memory 304 includes a command sequence mode determination module 318, a frequency and voltage change module 320, and a CPU synchronization module 322. The tightly coupled memory 312 includes a CPU synchronization module 324 and a command group counter module 326.

[0021] In some embodiments, the command sequence mode determination module 318 may determine the command sequence mode associated with the main CPU 306. The command sequence mode may include a sequential read mode, a sequential write mode, an idle mode, and other modes. In the sequential read mode, the main CPU 306 supports the sequential read operation of the memory device controlled by the memory controller 302. In the sequential write mode, the main CPU 306 supports the sequential write operation of the memory device controlled by the memory controller 302. In the idle mode, the main CPU 306 supports the idle operation of the memory device controlled by the memory controller 302, where the main CPU 306 does not receive commands from the host or receives a small number of commands from the host. In other modes, the main CPU 306 supports other operations of the memory device controlled by the memory controller 302. Examples of other operations may include random read and random write operations.

[0022] In some embodiments, the frequency and voltage change module 320 may change the core frequency or core voltage applied to the main CPU 306 and other CPUs 314. The CPU synchronization module 322 may perform a synchronization operation on the main CPU 306, where the main CPU 306 completes its current command and waits for the main CPU 306 and other CPUs 314 to complete the core frequency change or core voltage change before continuing to process new commands or tasks.

[0023] In some embodiments, the CPU synchronization module 324 may perform a synchronization operation on the other CPUs 314, where the other CPUs 314 complete their current commands and wait for the main CPU 306 and other CPUs 314 to complete the core frequency change or core voltage change before continuing to process new commands or tasks.

[0024] In some embodiments, the command group counter module 326 can count and monitor the number of commands associated with each command sequence pattern and received by the memory controller 302 during a specific time period. The main CPU 306 can use the monitored number of commands associated with each command sequence pattern to determine when to change the core frequency or core voltage applied to the main CPU 306 and other CPUs 314.

[0025] In some embodiments, the main CPU 306 can control the PLL frequency adjustment module 308 coupled to the main CPU 306 to change the core frequency applied to the main CPU 306 and other CPUs 314. The shared memory 316 is coupled to both the main CPU 306 and other CPUs 314 to store data shared between the main CPU 306 and other CPUs 314.

[0026] In some embodiments, the main CPU 306 can control the power management controller 310 coupled to the main CPU 306 to change the core voltage applied to the main CPU 306 and other CPUs 314. The power management controller 310 can correspond to Figure 2 the power management controller 204 in. The main CPU 306 can send commands to the power management controller 310 such that the power management controller 310 can change the core voltage applied to the main CPU 306 and other CPUs 314.

[0027] Figure 4 An exemplary workflow 400 for changing the core frequency or core voltage of a processor of a memory controller in a memory system is shown.

[0028] At 402, the main processor of the memory controller in the memory system determines that the condition is met to change the core frequency or core voltage applied to one or more processors of the memory controller. In some embodiments, the memory controller (e.g., Figure 3 the memory controller 302 in) can be a system on chip (SOC). The one or more processors can include a main processor (e.g., Figure 3 the main CPU 306 in) and one or more auxiliary processors (e.g., Figure 3 the other CPUs 314 in).

[0029] In some embodiments, to determine whether a condition is met, the main processor first monitors, respectively, the number of commands for sequential reads (e.g., sequential read commands having a command size of 128 KB) received by the memory controller during a time period (e.g., a first time period), and the number of commands for sequential writes (e.g., sequential write commands having a command size of 128 KB) received by it. For example, the time period can be one second.

[0030] In some embodiments, if the monitored number of sequential read commands received by the memory controller during the time period is greater than a read threshold, the main processor determines that the condition is met, thereby changing the core frequency or core voltage of one or more processors applied to the memory controller. The core frequency or core voltage can be respectively reduced to a target frequency or a target voltage to reduce the power consumption associated with the read and / or write operations of the memory device controlled by the memory controller.

[0031] In some embodiments, if the monitored number of sequential write commands received by the memory controller during the time period is greater than a write threshold, the main processor determines that the condition is met, thereby changing the core frequency or core voltage of one or more processors applied to the memory controller. The core frequency or core voltage can be respectively reduced to a target frequency or a target voltage to reduce the power consumption associated with the read and / or write operations of the memory device controlled by the memory controller.

[0032] In some embodiments, if the monitored number of combined sequential write commands and sequential read commands received by the memory controller during the time period is greater than a total threshold, the main processor determines that the condition is met, thereby changing the core frequency or core voltage of one or more processors applied to the memory controller. The core frequency or core voltage can be respectively reduced to a target frequency or a target voltage to reduce the power consumption associated with the read and / or write operations of the memory device controlled by the memory controller.

[0033] In some embodiments, the read threshold, write threshold, or total threshold can be predetermined based on the read or write performance that the main processor can support without causing excessive power consumption of the memory system. For example, the core frequency applied to the main CPU is 800 MHz, and the read performance that the main processor can support is 30% of the maximum read speed of 14 GB per second. Then the read threshold can be set to 14 GB * 0.3 / (128 * 1024), which is approximately 32,000 commands in one second. As another example, the write performance that the main processor can support is 30% of the maximum write speed of 10 GB per second. Then the write threshold can be set to 10 GB * 0.3 / (128 * 1024), which is approximately 23,000 commands in one second.

[0034] In some embodiments, to avoid an excessive number of frequency changes or voltage changes during a specific time period, the main processor may also monitor the latency period (e.g., the second time period) as an additional condition for determining whether to change the core frequency or the core voltage. For example, if a time period equal to the latency period has not elapsed since the core frequency or the core voltage was last changed, the main processor will not change the core frequency or the core voltage even if the conditions have been met. If the conditions are met after a time period equal to the latency period has elapsed since the core frequency or the core voltage was last changed, the main processor may change the core frequency or the core voltage.

[0035] In some embodiments, the main processor may also check the garbage collection status of each memory device controlled by the memory controller as another condition for determining whether to change the core frequency or the core voltage. For example, during the garbage collection process of the memory device controlled by the memory controller, the main processor may increase the core frequency or the core voltage regardless of whether the other conditions described above are met. As another example, if no memory device controlled by the memory controller is in the garbage collection state, the main processor may determine whether to change the core frequency or the core voltage based on the other conditions described above.

[0036] In some embodiments, if the main processor determines that the memory device controlled by the memory controller is not in any of the sequential read mode, the sequential write mode, or the garbage collection mode, the main processor does not change the core frequency or the core voltage.

[0037] At 404, after determining that the conditions for changing the core frequency or the core voltage are met, the main processor changes the core frequency to the target frequency or changes the core voltage to the target voltage. In some embodiments, the target frequency and the target voltage may be predetermined based on testing and calculations. For example, the target frequency may be predetermined such that the read and write performance of the memory device (e.g., SSD) controlled by the memory controller is not affected by the target frequency. The target frequency may be a frequency lower than the core frequency. In another example, the target voltage may be predetermined such that the target voltage can support the stability of the memory device controlled by the memory controller.

[0038] Table 1 below includes examples of the target frequency and the target voltage for different input / output (I / O) command sequence cases. The exemplary target frequency and target voltage may be further adjusted based on testing of the read and write performance of the memory device controlled by the memory controller.

[0039] Table 1

[0040]

[0041]

[0042] In some embodiments, to change the core frequency to a target frequency or change the core voltage to a target voltage, first, each processor in one or more processors may perform a synchronization operation. During the synchronization operation, each processor may first complete the processing of its current command and then wait for the process of changing the frequency and voltage of the processor to complete. This waiting state of each processor in one or more processors may be a common designated state. The code for each processor to perform the synchronization operation may be stored in a tightly coupled memory, e.g., Figure 3 the tightly coupled memory 304 for the main CPU 306 or the tightly coupled memory 312 for other CPUs 314 in

[0043] In some embodiments, after each CPU finishes processing its current command during the synchronization operation, the main processor may change the core frequency to a target frequency by modifying a phase-locked loop (PLL) register (e.g., Figure 3 the PLL frequency adjustment module 308 in ). The target frequency may be lower than the core frequency to reduce the power consumption associated with read and / or write operations of the memory device controlled by the memory controller.

[0044] In some embodiments, after reducing the core frequency, to change the voltage, the main processor may change the core voltage to a target voltage by sending a corresponding command to a power management integrated circuit (PMIC). The target voltage may be lower than the core voltage to reduce the power consumption associated with read and / or write operations of the memory device controlled by the memory controller.

[0045] In some embodiments, after the main processor changes both the core frequency and the core voltage, each CPU may exit the synchronization function and then continue to process new tasks.

[0046] Figure 5Shows an example of the change in power consumption associated with different memory device operations after a change in core frequency and core voltage. For the sequential read operation in the example, the SOC core voltage changes from 0.8V to 0.78V, the SOC core frequency changes from 1200MHz to 800MHz, and thus, the SOC power consumption changes from 18W to 16W. For the sequential write operation in the example, the SOC core voltage changes from 0.8V to 0.78V, the SOC core frequency changes from 1200MHz to 800MHz, and thus, the SOC power consumption changes from 24W to 22W. For the idle operation in the example, the SOC core voltage changes from 0.8V to 0.76V, the SOC core frequency changes from 1200MHz to 400MHz, and thus, the SOC power consumption changes from 6W to 4W. For other operations in the example, the SOC core voltage and SOC core frequency do not change, and thus, the SOC power consumption does not change.

[0047] Figure 6 Shows an example 600 of a flowchart of a method for reducing power consumption in a memory system according to some aspects of the present disclosure. At 602, a controller of the memory system determines that a condition is satisfied based on a plurality of commands received by the memory system during a first time period.

[0048] At 604, in response to determining that the condition is satisfied, the controller reduces the frequency or voltage applied to one or more processors of the controller.

[0049] Certain aspects of the subject matter described herein may be implemented as a memory system. The memory system includes a memory device and a controller coupled to the memory device and configured to perform operations including: determining that a condition is satisfied based on a plurality of commands received by the memory system during a first time period; and in response to determining that the condition is satisfied, reducing the frequency or voltage applied to one or more processors of the controller.

[0050] The memory system may include one or more of the following features.

[0051] In some embodiments, the plurality of commands includes at least one of a sequential write command or a sequential read command.

[0052] In some embodiments, the operations further include: determining that a second time period has elapsed since the last time the frequency or voltage applied to one or more processors of the controller was reduced, and reducing the frequency or voltage applied to one or more processors of the controller includes: in response to determining that the condition is satisfied and that a second time period has elapsed since the last time the frequency or voltage applied to one or more processors of the controller was reduced, reducing the frequency or voltage applied to one or more processors of the controller.

[0053] In some embodiments, reducing the frequency or voltage applied to one or more processors of a controller includes: reducing the frequency applied to one or more processors of the controller, and subsequently reducing the voltage applied to one or more processors of the controller.

[0054] In some embodiments, a first time period immediately precedes the moment of reducing the frequency or voltage applied to one or more processors of the controller.

[0055] In some embodiments, the memory system is in a sequential write mode, a sequential read mode, or an idle mode.

[0056] In some embodiments, before reducing the frequency or voltage applied to one or more processors of the controller, the operation further includes: in response to determining that a condition is met, completing all current tasks of the one or more processors, and synchronizing each of the one or more processors to a common specified state.

[0057] In some embodiments, after reducing the frequency or voltage applied to one or more processors of the controller, the operation further includes: executing new tasks on the one or more processors.

[0058] In some embodiments, reducing the frequency applied to one or more processors includes: using a phase-locked loop (PLL) register in the controller to reduce the frequency applied to one or more processors.

[0059] In some embodiments, the one or more processors include a main processor and one or more auxiliary processors, the memory system further includes a power management integrated circuit (PMIC) coupled to the controller, and reducing the voltage applied to the one or more processors includes: determining, by the main processor, one or more commands based on a plurality of parameters monitored by the one or more processors, and sending, by the main processor, the one or more commands to the PMIC to reduce the voltage applied to the one or more processors.

[0060] In some embodiments, before reducing the frequency or voltage applied to one or more processors of the controller, the operation further includes: determining that the memory system is not in a garbage collection mode, and reducing the frequency or voltage applied to one or more processors of the controller includes: in response to determining that a condition is met and the memory system is not in a garbage collection mode, reducing the frequency or voltage applied to one or more processors of the controller.

[0061] In some embodiments, the condition includes: the number of a plurality of commands received by the memory system during the first time period is greater than a threshold, the ratio of the threshold to the first time period is greater than or equal to 32000, and the first time period is longer than or equal to one second.

[0062] Certain aspects of the subject matter described herein can be implemented as a method. The method includes: determining, by a controller of a memory system and based on a plurality of commands received by the memory system during a first time period, that a condition is satisfied; and in response to determining that the condition is satisfied, reducing a frequency or voltage applied to one or more processors of the controller.

[0063] The method can include one or more of the following features.

[0064] In some embodiments, the plurality of commands includes at least one of a sequential write command or a sequential read command.

[0065] In some embodiments, the method further includes: determining that a second time period has elapsed since the last reduction of the frequency or voltage applied to one or more processors of the controller, and reducing the frequency or voltage applied to one or more processors of the controller includes: in response to determining that the condition is satisfied and that a second time period has elapsed since the last reduction of the frequency or voltage applied to one or more processors of the controller, reducing the frequency or voltage applied to one or more processors of the controller.

[0066] In some embodiments, reducing the frequency or voltage applied to one or more processors of the controller includes: reducing the frequency applied to one or more processors of the controller, and then reducing the voltage applied to one or more processors of the controller.

[0067] In some embodiments, before reducing the frequency or voltage applied to one or more processors of the controller, the method further includes: in response to determining that the condition is satisfied, completing all current tasks of one or more processors, and synchronizing each of the one or more processors to a common designated state.

[0068] In some embodiments, after reducing the frequency or voltage applied to one or more processors of the controller, the method further includes: performing new tasks on one or more processors.

[0069] In some embodiments, reducing the frequency applied to one or more processors includes: using a phase-locked loop (PLL) register in the controller to reduce the frequency applied to one or more processors.

[0070] In some embodiments, one or more processors include a main processor and one or more auxiliary processors, the memory system further includes a power management integrated circuit (PMIC) coupled to the controller, and reducing the voltage applied to the one or more processors includes: determining, by the main processor, one or more commands based on a plurality of parameters monitored by the one or more processors, and sending, by the main processor, the one or more commands to the PMIC to reduce the voltage applied to the one or more processors.

[0071] In some embodiments, before reducing the frequency or voltage applied to one or more processors of the controller, the method further includes: determining that the memory system is not in a garbage collection mode, and reducing the frequency or voltage applied to one or more processors of the controller includes: reducing the frequency or voltage applied to one or more processors of the controller in response to determining that a condition is satisfied and the memory system is not in a garbage collection mode.

[0072] In some embodiments, the condition includes: the number of a plurality of commands received by the memory system during a first time period is greater than a threshold, the ratio of the threshold to the first time period is greater than or equal to 32000, and the first time period is longer than or equal to one second.

[0073] Certain aspects of the subject matter described herein can be implemented as a controller of a memory system. The controller is configured to perform operations that include: determining, by the controller and based on a plurality of commands received by the memory system during a first time period, that a condition is satisfied; and reducing, in response to determining that the condition is satisfied, the frequency or voltage applied to one or more processors of the controller.

[0074] Although this specification contains many specific implementation details, these details should not be construed as limitations on the scope of the claims, but rather as descriptions of features that may be specific to particular embodiments. In the context of separate embodiments, certain features described in this specification can also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented separately or in any sub-combination in multiple embodiments. Additionally, although the foregoing features may be described as acting in certain combinations and even initially claimed as such, one or more features from the claimed combination can in some cases be deleted from the combination, and the claimed combination can be directed to a sub-combination or a variation of the sub-combination.

[0075] As used in this disclosure, unless the context clearly indicates otherwise, the term "a" or "the" is used to include one or more than one. Unless otherwise indicated, the term "or" is used to mean non-exclusive "or". The statement "at least one of A and B" has the same meaning as "A, B, or A and B". In addition, the wording or terms adopted in this disclosure but not otherwise defined are for descriptive purposes only and not for purposes of limitation. Any use of section headings is intended to assist in reading the document and should not be construed as limiting; information related to a section heading may appear within or outside of that particular section.

[0076] As used in this disclosure, the terms "about" or "approximately" may permit a degree of variability in a value or range, e.g., within 10%, within 5%, or within 1% of the stated value or the stated limits of a range.

[0077] As used in this disclosure, the term "substantially" means most or majority, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0078] Values expressed in a range format should be interpreted in a flexible manner to include not only the numerical values explicitly recited as the limits of the range, but also all individual numerical values or sub-ranges subsumed within that range as if each numerical value and sub-range were explicitly recited. For example, a range of "0.1% to about 5%" or "0.1% to 5%" should be interpreted to include from about 0.1% to about 5%, as well as the individual values (e.g., 1%, 2%, 3%, and 4%) and sub-ranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) subsumed within the indicated range. Unless otherwise indicated, the statement "X to Y" has the same meaning as "about X to about Y". Similarly, unless otherwise indicated, the statement "X, Y, or Z" has the same meaning as "about X, about Y, or about Z".

[0079] Specific embodiments of the subject matter have been described. As will be apparent to those skilled in the art, other embodiments, alternatives, and permutations of the described embodiments are within the scope of the following claims. Although the operations are described in a specific order in the figures and claims, to achieve the desired results, it is not required to perform the operations in the specific order shown or in a sequential order, or to perform all of the operations shown (some operations may be considered optional). In some cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and is performed when deemed appropriate.

[0080] Furthermore, the separation or integration of the various system modules and components in the previously described embodiments is not necessary in all embodiments, and the described components and systems can generally be integrated together or packaged into multiple products.

[0081] Accordingly, the previously described exemplary embodiments do not limit or restrict the present disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of the present disclosure.

Claims

1. A memory system, comprising: A memory device; And A controller coupled to the memory device and configured to perform operations, the operations including: Determining that a condition is met based on a plurality of commands received by the memory system during a first time period; And In response to determining that the condition is met, reducing the frequency or voltage applied to one or more processors of the controller.

2. The memory system according to claim 1, wherein, The plurality of commands includes at least one of a sequential write command or a sequential read command.

3. The memory system according to claim 1 or 2, wherein, The operations further include: Determining that a second time period has elapsed since the last reduction of the frequency or voltage applied to the one or more processors of the controller; and Wherein, reducing the frequency or voltage applied to the one or more processors of the controller includes: In response to determining that the condition is met and that the second time period has elapsed since the last reduction of the frequency or voltage applied to the one or more processors of the controller, reducing the frequency or voltage applied to the one or more processors of the controller.

4. The memory system according to any one of claims 1 to 3, wherein, Reducing the frequency or voltage applied to the one or more processors of the controller includes: reducing the frequency applied to the one or more processors of the controller, and then reducing the voltage applied to the one or more processors of the controller.

5. The memory system according to any one of claims 1 to 4, wherein, The first time period is immediately before the moment of reducing the frequency or voltage applied to the one or more processors of the controller.

6. The memory system according to any one of claims 1 to 5, wherein, The memory system is in a sequential write mode, a sequential read mode, or an idle mode.

7. The memory system according to any one of claims 1 to 6, wherein, Before reducing the frequency or voltage applied to the one or more processors of the controller, the operations further include: In response to determining that the condition is met: Completing all current tasks of the one or more processors; and Synchronizing each of the one or more processors to a common designated state.

8. The memory system according to any one of claims 1 to 7, wherein, After reducing the frequency or voltage applied to the one or more processors of the controller, the operations further include: Performing new tasks on the one or more processors.

9. The memory system according to any one of claims 1 to 8, wherein Reducing the frequency applied to the one or more processors includes: using a phase-locked loop (PLL) register in the controller to reduce the frequency applied to the one or more processors.

10. The memory system according to any one of claims 1 to 9, wherein, The one or more processors include a main processor and one or more auxiliary processors, the memory system further includes a power management integrated circuit (PMIC) coupled to the controller, and wherein, reducing the voltage applied to the one or more processors includes: Determining, by the main processor, one or more commands based on a plurality of parameters monitored by the one or more processors; and Sending, by the main processor, the one or more commands to the PMIC to reduce the voltage applied to the one or more processors.

11. The memory system according to any one of claims 1 to 10, wherein, Before reducing the frequency or voltage applied to the one or more processors of the controller, the operations further include: Determining that the memory system is not in a garbage collection mode; and Wherein, reducing the frequency or voltage applied to the one or more processors of the controller includes: Reducing the frequency or voltage applied to the one or more processors of the controller in response to determining that the condition is satisfied and the memory system is not in a garbage collection mode.

12. The memory system according to any one of claims 1 to 11, wherein, The condition includes: the number of the plurality of commands received by the memory system during the first time period is more than a threshold, the ratio of the threshold to the first time period is greater than or equal to 32000, and the first time period is longer than or equal to one second.

13. A method, comprising: Determining, by a controller of a memory system and based on a plurality of commands received by the memory system during a first time period, that a condition is satisfied; And Reducing, by the controller, the frequency or voltage applied to one or more processors of the controller in response to determining that the condition is satisfied.

14. The method according to claim 13, wherein, The plurality of commands includes at least one of a sequential write command or a sequential read command.

15. The method according to claim 13 or 14, further comprising: Determining that a second time period has elapsed since the last reduction of the frequency or voltage applied to the one or more processors of the controller; And Wherein, reducing the frequency or voltage applied to the one or more processors of the controller includes: Reducing the frequency or voltage applied to the one or more processors of the controller in response to determining that the condition is satisfied and that the second time period has elapsed since the last reduction of the frequency or voltage applied to the one or more processors of the controller.

16. The method according to any one of claims 13 to 15, wherein, Reducing the frequency or voltage applied to the one or more processors of the controller includes: reducing the frequency applied to the one or more processors of the controller, and then reducing the voltage applied to the one or more processors of the controller.

17. The method according to any one of claims 13 to 16, wherein Before reducing the frequency or voltage applied to the one or more processors of the controller, the method further comprises: In response to determining that the condition is satisfied: Completing all current tasks of the one or more processors; and Synchronizing each of the one or more processors to a common designated state.

18. The method according to any one of claims 13 to 17, wherein After reducing the frequency or voltage applied to the one or more processors of the controller, the method further comprises: Executing new tasks on the one or more processors.

19. The method according to any one of claims 13 to 18, wherein, Reducing the frequency applied to the one or more processors includes: using a phase-locked loop (PLL) register in the controller to reduce the frequency applied to the one or more processors.

20. The method according to any one of claims 13 to 19, wherein, The one or more processors include a main processor and one or more auxiliary processors, the memory system further includes a power management integrated circuit (PMIC) coupled to the controller, and wherein, reducing the voltage applied to the one or more processors includes: Determining, by the main processor, one or more commands based on a plurality of parameters monitored by the one or more processors; and The one or more commands are sent by the main processor to the PMIC to reduce the voltage applied to the one or more processors.

21. The method according to any one of claims 13 to 20, wherein, Before reducing the frequency or the voltage applied to the one or more processors of the controller, the method further comprises: determining that the memory system is not in a garbage collection mode; and wherein reducing the frequency or the voltage applied to the one or more processors of the controller comprises: reducing the frequency or the voltage applied to the one or more processors of the controller in response to determining that the condition is met and the memory system is not in a garbage collection mode.

22. The method according to any one of claims 13 to 21, wherein, The condition includes: the number of the plurality of commands received by the memory system during the first time period is more than a threshold, the ratio of the threshold to the first time period is greater than or equal to 32000, and the first time period is longer than or equal to one second.

23. A controller of a memory system, wherein, The controller is configured to perform operations, the operations including: determining by the controller and based on the plurality of commands received by the memory system during a first time period that the condition is met; and reducing, in response to determining that the condition is met, the frequency or the voltage applied to one or more processors of the controller by the controller.

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