Dicing tape and dicing die bonding film

Abstract

The invention relates to a dicing tape and a dicing die bonding film. The dicing tape according to the present invention is obtained by laminating an adhesive layer on a base material layer, and the tensile storage modulus at-5 DEG C of the dicing tape is 100 MPa or more.

Description

[0001] This application is a divisional application of a Chinese patent application with an application date of June 3, 2020, an application number of 202010496602.6, and an invention title of "Cutting Tape and Cutting Chip Bonding Film".

[0002] Cross-reference to related applications

[0003] This application claims the priority of Japanese Patent Application No. 2019-110200, which is incorporated herein by reference in its entirety. Technical field

[0004] The present invention relates to a cutting tape and a cutting chip bonding film. Background art

[0005] As is well known, in the past, in the manufacture of semiconductor devices, a cutting tape and a cutting chip bonding film have been used to obtain semiconductor chips for chip bonding.

[0006] The above-mentioned cutting tape is composed of a base material layer laminated with an adhesive layer, and the above-mentioned cutting chip bonding film is composed of a chip bonding layer laminated peelably on the adhesive layer of the cutting tape.

[0007] Also known is a method of obtaining a semiconductor chip (Die) for chip bonding using the above-mentioned cutting chip bonding film, which employs a method having the following steps: a semi-cutting step of forming grooves in a semiconductor wafer and then grinding the semiconductor wafer to make it thinner in order to process the semiconductor wafer into chips (Dies) by cutting; a back grinding step of grinding the semiconductor wafer after the semi-cutting step to make it thinner; a mounting step of attaching one surface (for example, the surface opposite to the circuit surface) of the semiconductor wafer after the back grinding step to the chip bonding layer to fix the semiconductor wafer to the cutting tape; a spreading step of expanding the distance between the semi-cut semiconductor chips; a notch maintaining step of maintaining the distance between the semiconductor chips; a picking step of peeling between the chip bonding layer and the adhesive layer and taking out the semiconductor chip in a state where the chip bonding layer is attached; and a chip bonding step of bonding the semiconductor chip in a state where the chip bonding layer is attached to an adherend (for example, a mounting substrate, etc.).

[0008] It should be noted that in the above-mentioned notch maintaining step, hot air (for example, 100 to 130 °C) is directed at the cutting tape to cause the cutting tape to thermally contract and then cooled and cured, thereby maintaining the distance (notch) between adjacent semiconductor chips that have been cut.

[0009] In addition, in the above-mentioned spreading step, the chip bonding layer is cut into a size corresponding to the size of a plurality of singulated semiconductor chips.

[0010] In the method of obtaining a semiconductor chip for chip bonding by using the cutting chip bonding film as described above, Patent Document 1 discloses that: by using a cutting tape having specific physical properties (a cutting tape having an initial elastic modulus at -10°C of 200 MPa or more and 380 MPa or less and a Tanδ (loss modulus / storage modulus) at -10°C of 0.080 or more and 0.3 or less), and performing the above-mentioned expansion process under a low temperature condition of -15 to 5°C, the cutability from the semiconductor wafer to a plurality of semiconductor chips (for example, cutting ease, uniform cutability, etc.) in the above-mentioned expansion process can be improved.

[0011] Prior Art Documents

[0012] Patent Documents

[0013] Patent Document 1: Japanese Patent Application Laid-Open No. 2015-185591 Summary of the Invention

[0014] Problems to be Solved by the Invention

[0015] As described in Patent Document 1, by using a cutting tape having specific physical properties and performing the above-mentioned expansion process under the above-mentioned low temperature condition, the cutability of the semiconductor wafer is improved. However, when cutting the semiconductor wafer into a plurality of semiconductor chips by expansion using the cutting tape and the cutting chip bonding film under a low temperature condition, it is necessary to further improve the cutability of the semiconductor wafer.

[0016] Especially when cutting a semiconductor wafer into a plurality of small semiconductor chips (for example, a semiconductor chip having a size of length 12 mm × width 4 mm × thickness 0.055 mm), it is necessary to further improve the cutability of the semiconductor wafer.

[0017] Therefore, the subject of the present invention is to provide a cutting tape and a cutting chip bonding film capable of further improving the cutability from a semiconductor wafer to a plurality of semiconductor chips based on expansion under a low temperature condition.

[0018] Solutions for Solving the Problems

[0019] The cutting tape of the present invention has an adhesive layer laminated on a base material layer.

[0020] The tensile storage modulus of the cutting tape at -5°C is 100 MPa or more.

[0021] In the above-mentioned cutting tape, preferably:

[0022] The 30% tensile stress at -5°C is 5.5 N / 10 mm or more.

[0023] In the above-mentioned cutting tape, preferably:

[0024] The 30% tensile stress at room temperature is 3.2 N / 10 mm or more.

[0025] In the above-mentioned dicing tape, it is preferable that:

[0026] The ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is 1.7 or more.

[0027] The dicing chip bonding film of the present invention includes:

[0028] A dicing tape having an adhesive layer laminated on a base material layer, and

[0029] A chip bonding layer laminated on the adhesive layer of the above-mentioned dicing tape,

[0030] The tensile storage modulus of the dicing chip bonding film at -5°C is 100 MPa or more. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 : A cross-sectional view showing the configuration of a dicing tape according to an embodiment of the present invention.

[0032] Figure 2 : A cross-sectional view showing the configuration of a dicing chip bonding film according to an embodiment of the present invention.

[0033] Figure 3A : A cross-sectional view schematically showing the state of semi-dicing in a method for manufacturing a semiconductor integrated circuit.

[0034] Figure 3B : A cross-sectional view schematically showing the state of semi-dicing in a method for manufacturing a semiconductor integrated circuit.

[0035] Figure 3C : A cross-sectional view schematically showing the state of back grinding in a method for manufacturing a semiconductor integrated circuit.

[0036] Figure 3D : A cross-sectional view schematically showing the state of back grinding in a method for manufacturing a semiconductor integrated circuit.

[0037] Figure 4A : A cross-sectional view schematically showing the state of an installation process in a method for manufacturing a semiconductor integrated circuit.

[0038] Figure 4B : A cross-sectional view schematically showing the state of an installation process in a method for manufacturing a semiconductor integrated circuit.

[0039] Figure 5A : A cross-sectional view schematically showing the state of an expansion process at low temperature in a method for manufacturing a semiconductor integrated circuit.

[0040] Figure 5B : A cross-sectional view schematically showing the state of an extension process at low temperature in a method for manufacturing a semiconductor integrated circuit.

[0041] Figure 5C : A cross-sectional view schematically showing the state of an extension process at low temperature in a method for manufacturing a semiconductor integrated circuit.

[0042] Figure 6A : A cross-sectional view schematically showing the state of an extension process at normal temperature in a method for manufacturing a semiconductor integrated circuit.

[0043] Figure 6B : A cross-sectional view schematically showing the state of an extension process at normal temperature in a method for manufacturing a semiconductor integrated circuit.

[0044] Figure 7 : A cross-sectional view schematically showing the state of a notch maintaining process in a method for manufacturing a semiconductor integrated circuit.

[0045] Figure 8 : A cross-sectional view schematically showing the state of a pick-up process in a method for manufacturing a semiconductor integrated circuit.

[0046] Explanation of Reference Numerals

[0047] 1 Substrate layer

[0048] 2 Adhesive layer

[0049] 3 Chip bonding layer

[0050] 10 Cutting tape

[0051] 20 Cutting chip bonding film

[0052] 1a First resin layer

[0053] 1b Second resin layer

[0054] 1c Third resin layer

[0055] G Back grinding tape

[0056] H Holder

[0057] J Adsorption jig

[0058] P Pin member

[0059] R Cutting ring

[0060] T Wafer processing tape

[0061] U Lifting member

[0062] W Semiconductor wafer Detailed Embodiment

[0063] An embodiment of the present invention will be described below.

[0064] [Cutting Tape]

[0065] As Figure 1 shown, the cutting tape 10 of this embodiment has an adhesive layer 2 laminated on the base material layer 1, and its tensile storage modulus at -5°C is 100 MPa or more.

[0066] Regarding the reason for improving the cutability of the semiconductor wafer attached to the cutting tape 10 by making the tensile storage modulus of the cutting tape 10 at -5°C 100 MPa or more, it can be considered as follows.

[0067] In order to improve the cutability (such as cut ease, uniform cutability, etc.) of the semiconductor wafer attached to the cutting tape 10, which is cut into a plurality of semiconductor chips by expansion, it is necessary to sufficiently apply a tensile force to the entire cutting tape 10 at the start of cutting the semiconductor wafer.

[0068] Here, it can be considered that when the cutting tape 10 is soft at the start of cutting, that is, when the tensile storage modulus of the cutting tape 10 is small, the tensile force at the start of cutting will be absorbed by the cutting tape 10 as it approaches the central part from the outer edge part of the cutting tape 10, and thus gradually becomes smaller. Therefore, it is considered that it is difficult to sufficiently apply the tensile force at the start of cutting to the entire cutting tape 10.

[0069] On the contrary, the cutting tape 10 of this embodiment has a large tensile storage modulus of 100 MPa or more. Therefore, it is considered that the tensile force at the start of cutting is not easily absorbed by the cutting tape 10 as it approaches the central part from the outer edge part of the cutting tape 10. Therefore, it is possible to sufficiently apply the tensile force at the start of cutting to the entire cutting tape 10. As a result, it is easy to cut the semiconductor wafer into a plurality of semiconductor chips, and it is easy to obtain semiconductor chips that are cut more evenly. That is, the cutability from the semiconductor wafer to a plurality of semiconductor chips can be further improved.

[0070] It should be noted that as described in the embodiment part below, by making the tensile storage modulus of the cutting tape 10 at -5°C 100 MPa or more, it is possible to further improve the cutability, especially when cutting a semiconductor wafer (for example, a semiconductor wafer with a diameter of 200 mm (8 inches)) into small semiconductor chips (for example, with a length of 12 mm × a width of 4 mm × a thickness of 0.55 mm).

[0071] The inventors of the present invention speculate the reason as follows.

[0072] When cutting semiconductor wafers of the same size, the smaller the size of the cut semiconductor chips, the narrower the interval of the grooves (lines) formed in the semiconductor wafer during the half-cutting process. As a result, the number of grooves formed on the semiconductor wafer increases. Consequently, the elongation rate of the grooves in the expansion process decreases.

[0073] Therefore, when cutting a semiconductor wafer into small semiconductor chips in the expansion process, in order to suppress the occurrence of cutting defects, it is necessary to generate high stress at a lower elongation rate.

[0074] Here, the elastic modulus refers to the slope of the stress with respect to the elongation rate (strain) when stretching the base material layer. Therefore, it is considered that a high elastic modulus can generate high stress at a lower elongation rate.

[0075] Moreover, in the expansion process using the cutting tape 10, from the viewpoints of good cutability when cutting a semiconductor wafer into multiple small semiconductor chips and that the tensile force does not cause the cutting tape 10 to break, the method of performing expansion at a temperature of -5°C is optimal. Therefore, it is considered that by setting the tensile storage modulus at -5°C to a relatively high value such as 100 MPa or more, high stress can be generated at a lower elongation rate.

[0076] The inventors et al. speculate that as a result, the cutability when cutting a semiconductor wafer into small semiconductor chips can be further improved.

[0077] The cutting tape 10 of the present embodiment preferably has a tensile storage modulus at -5°C of 400 MPa or less.

[0078] Thereby, a sufficient tensile force is applied to the entire cutting tape 10, and the cutting tape 10 becomes more easily elongated. Therefore, it is possible to suppress the breakage of the cutting tape 10 caused by the tensile force when cutting the semiconductor wafer attached to the cutting tape 10 into semiconductor chips, and further improve the cutability from the semiconductor wafer to multiple semiconductor chips.

[0079] In addition, by making the tensile storage modulus at -5°C 400 MPa or less, in particular, the cutability from the semiconductor wafer to multiple small semiconductor chips can be further improved.

[0080] The tensile storage modulus at -5°C can be obtained as described below.

[0081] Specifically, a cut tape with a length of 40 mm (measured length) and a width of 10 mm is used as a test piece, and a solid viscoelasticity measuring device (e.g., model RSAIII, manufactured by Rheometric Scientific Co., Ltd.) is used to measure the tensile storage modulus of the above test piece in the temperature range of -50 to 100°C under the conditions of a frequency of 1 Hz, a deformation amount of 0.1%, a heating rate of 10°C / minute, and a distance between jigs of 22.5 mm. At this time, it can be obtained by reading the value at -5°C.

[0082] It should be noted that the above measurement is performed by stretching the above test piece along the MD direction (resin flow direction).

[0083] The cut tape 10 of this embodiment preferably has a 30% tensile stress at -5°C of 5.5 N / 10 mm or more.

[0084] The cut tape 10 of this embodiment preferably has a 30% tensile stress at -5°C of 30 N / 10 mm or less.

[0085] Thus, a sufficient tensile force is applied to the entire cut tape 10 during expansion, and the cut tape 10 becomes easier to elongate. Therefore, during the expansion of the cut tape 10 attached to the semiconductor wafer and the cutting of the above semiconductor wafer into semiconductor chips, the rupture of the cut tape caused by expansion can be suppressed, and furthermore, the cutability from the semiconductor wafer to multiple semiconductor chips can be improved.

[0086] In addition, by making the 30% tensile stress at -5°C 30 N / 10 mm or less, the cutability from the semiconductor wafer to multiple small semiconductor chips can be further improved, in particular.

[0087] The cut tape 10 of this embodiment preferably has a 30% tensile stress at room temperature (23°C) of 3.2 N / 10 mm or more.

[0088] The 30% tensile stress at room temperature (23°C) is preferably 30 N / 10 mm or less.

[0089] Thus, a sufficient tensile force is applied to the entire cut tape 10 during expansion, and the cut tape 10 becomes easier to elongate. Therefore, during the expansion of the cut tape 10 attached to the semiconductor wafer and the cutting of the above semiconductor wafer into semiconductor chips, the rupture of the cut tape caused by expansion can be suppressed, and furthermore, the cutability from the semiconductor wafer to multiple semiconductor chips can be improved.

[0090] In addition, by making the 30% tensile stress at room temperature 30 N / 10 mm or less, the cutability from the semiconductor wafer to multiple small semiconductor chips can be further improved, in particular.

[0091] The 30% tensile stress at -5°C and room temperature can be obtained as described below.

[0092] Specifically, it can be obtained as follows: Using a cut tape with a length of 100 mm and a width of 10 mm as a test piece, and using a tensile testing machine (Tensilon universal testing machine, manufactured by Shimadzu Corporation), at the measurement temperatures (-5°C and room temperature (23°C ± 1°C)), under the conditions of a distance between clamps of 50 mm and a tensile speed of 100 mm / minute, stretch the above test piece, and measure the stress when the elongation rate reaches 30% (the distance between clamps is 65 mm).

[0093] It should be noted that the above measurement is performed by stretching the above test piece along the MD direction (resin flow direction).

[0094] The cut tape 10 of this embodiment preferably has a ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature of 1.7 or more.

[0095] The cut tape 10 of this embodiment preferably has a ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature of 3.0 or less.

[0096] Thereby, a sufficient tensile force is applied to the entire cut tape 10 during expansion, and the cut tape 10 becomes more easily stretchable. Therefore, during the expansion of the cut tape 10 attached to the semiconductor wafer and the cutting of the above semiconductor wafer into semiconductor chips, it is possible to suppress the rupture of the cut tape caused by expansion and further improve the cutability from the semiconductor wafer to a plurality of semiconductor chips.

[0097] In addition, by making the ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature 3.0 or less, it is possible to further improve the cutability from the semiconductor wafer to a plurality of small semiconductor chips in particular.

[0098] The substrate layer 1 supports the adhesive layer 2. The substrate layer 1 contains a resin. Examples of the resin contained in the substrate layer 1 include polyolefin, polyester, polyurethane, polycarbonate, polyetheretherketone, polyimide, polyetherimide, polyamide, wholly aromatic polyamide, polyvinyl chloride, polyvinylidene chloride, polyphenylene sulfide, fluororesin, cellulose-based resin, and silicone resin.

[0099] Examples of the polyolefin include homopolymers of α-olefins, copolymers of two or more α-olefins, block polypropylene, random polypropylene, copolymers of one or two or more α-olefins and other vinyl monomers, and the like.

[0100] As a homopolymer of an α-olefin, a homopolymer of an α-olefin having 2 or more and 12 or less carbon atoms is preferred. Examples of such homopolymers include ethylene, propylene, 1-butene, 4-methyl-1-pentene, etc.

[0101] Examples of copolymers of two or more α-olefins include ethylene / propylene copolymers, ethylene / 1-butene copolymers, ethylene / propylene / 1-butene copolymers, ethylene / α-olefin copolymers having 5 or more and 12 or less carbon atoms, propylene / ethylene copolymers, propylene / 1-butene copolymers, propylene / α-olefin copolymers having 5 or more and 12 or less carbon atoms, etc.

[0102] Examples of copolymers of one or two or more α-olefins and other vinyl monomers include ethylene-vinyl acetate copolymers (EVA), etc.

[0103] The polyolefin may be a substance called an α-olefin-based thermoplastic elastomer. Examples of α-olefin-based thermoplastic elastomers include substances composed of a combination of a propylene-ethylene copolymer and a propylene homopolymer, or a propylene-ethylene-α-olefin terpolymer having 4 or more carbon atoms.

[0104] Examples of commercially available products of α-olefin-based thermoplastic elastomers include, for example, Vistamaxx 3980 (manufactured by ExxonMobil Chemical company) as a propylene-based elastomer resin.

[0105] The base material layer 1 may contain one of the above resins or may contain two or more of the above resins.

[0106] It should be noted that when the adhesive layer 2 contains an ultraviolet curable adhesive described later, the base material layer 1 is preferably configured to have ultraviolet transmissivity.

[0107] The base material layer 1 may have a single-layer structure or a laminated structure. The base material layer 1 can be obtained by non-stretching molding or can be obtained by stretching molding, and is preferably obtained by stretching molding. When the base material layer 1 has a laminated structure, the base material layer 1 preferably has a layer containing an elastomer (hereinafter referred to as an elastomer layer) and a layer containing a non-elastomer (hereinafter referred to as a non-elastomer layer).

[0108] By making the base material layer 1 a base material layer having an elastomer layer and a non-elastomer layer, the elastomer layer can function as a stress relaxation layer for relaxing tensile stress. That is, the tensile stress generated in the base material layer 1 can be made small, so that the base material layer 1 can have an appropriate hardness and is relatively easy to stretch.

[0109] Thereby, the cutability from the semiconductor wafer to a plurality of semiconductor chips can be improved.

[0110] In addition, during the expansion in the cutting process, breakage of the base material layer 1 can be suppressed, preventing damage from occurring.

[0111] It should be noted that in this specification, the elastomeric layer refers to a low elastic modulus layer with a tensile storage modulus at room temperature lower than that of the non-elastomeric layer. As the elastomeric layer, those with a tensile storage modulus at room temperature of 10 MPa or more and 100 MPa or less can be cited. As the non-elastomeric layer, those with a tensile storage modulus at room temperature of 200 MPa or more and 500 MPa or less can be cited.

[0112] The elastomeric layer can contain one elastomer or two or more elastomers, and preferably contains an α-olefin-based thermoplastic elastomer.

[0113] The non-elastomeric layer can contain one non-elastomer or two or more non-elastomers, and preferably contains the metallocene PP described later.

[0114] When the base material layer 1 has an elastomeric layer and a non-elastomeric layer, the base material layer 1 preferably forms a three-layer structure with the elastomeric layer as the central layer and non-elastomeric layers on both opposite sides of the central layer (non-elastomeric layer / elastomeric layer / non-elastomeric layer) (refer to Figure 1 ). It should be noted that in Figure 1 , one non-elastomeric layer is represented as the first resin layer 1a, the elastomeric layer is represented as the second resin layer 1b, and the other non-elastomeric layer is represented as the third resin layer 3c.

[0115] In addition, as described above, in the cut maintenance process, hot air (for example, 100 to 130 °C) is directed at the above-mentioned cut chip bonding film maintained in an expanded state at room temperature (for example, 23 °C) to cause the above-mentioned cut chip bonding film to thermally contract and then cool and solidify. Therefore, the outermost layer of the base material layer 1 preferably contains a resin with a melting point close to the temperature of the hot air directed at the cutting tape. Thereby, the outermost layer melted by the directed hot air can be cured more rapidly.

[0116] As a result, in the cut maintenance process, the cut can be maintained more adequately.

[0117] When the base material layer 1 has a laminated structure of an elastomer layer and a non-elastomer layer, the elastomer layer contains an α-olefin-based thermoplastic elastomer, and the non-elastomer layer contains a polyolefin such as the metallocene PP described later, it is preferable that the elastomer layer contains 50% by mass or more and 100% by mass or less of the α-olefin-based thermoplastic elastomer with respect to the total mass of the elastomer forming the elastomer layer, more preferably 70% by mass or more and 100% by mass or less, further preferably 80% by mass or more and 100% by mass or less, particularly preferably 90% by mass or more and 100% by mass or less, and the mode of containing 95% by mass or more and 100% by mass is the best. By containing the α-olefin-based thermoplastic elastomer in the above range, the affinity between the elastomer layer and the non-elastomer layer is improved, so that the base material layer 1 can be extruded and molded relatively easily. In addition, the elastomer layer can function as a stress relaxation layer, so that the semiconductor wafer attached to the cutting tape can be cut efficiently.

[0118] When the base material layer 1 has a laminated structure of an elastomer layer and a non-elastomer layer, the base material layer 1 is preferably obtained by co-extrusion molding, in which the elastomer and the non-elastomer are co-extruded to form a laminated structure of the elastomer layer and the non-elastomer layer. As the co-extrusion molding, any suitable co-extrusion molding commonly performed in the manufacture of films, sheets, etc. can be used. In the co-extrusion molding, from the viewpoint of obtaining the base material layer 1 efficiently and inexpensively, the inflation method or the co-extrusion T-die method is preferably used.

[0119] When the base material layer 1 having a laminated structure is obtained by co-extrusion molding, the above-mentioned elastomer layer and the above-mentioned non-elastomer layer are in contact with each other in a heat-melted state, so it is preferable that the melting point difference between the above-mentioned elastomer and the above-mentioned non-elastomer is small. By making the melting point difference small, it is possible to suppress excessive heat being applied to either the above-mentioned elastomer or the above-mentioned non-elastomer having a low melting point, so it is possible to suppress the case where either the above-mentioned elastomer or the above-mentioned non-elastomer having a low melting point undergoes thermal degradation to generate by-products. In addition, it is also possible to suppress the following situation: the viscosity of either the above-mentioned elastomer or the above-mentioned non-elastomer having a low melting point drops excessively, resulting in poor lamination between the above-mentioned elastomer layer and the above-mentioned non-elastomer layer. The melting point difference between the above-mentioned elastomer and the above-mentioned non-elastomer is preferably 0 °C or more and 70 °C or less, more preferably 0 °C or more and 55 °C or less.

[0120] The melting points of the above-mentioned elastomer and the above-mentioned non-elastomer can be measured by differential scanning calorimetry (DSC) analysis. For example, using a differential scanning calorimeter device (model DSC Q2000 manufactured by TA INSTRUMENTS), it is heated to 200 °C at a heating rate of 5 °C / minute in a nitrogen gas stream, and the peak temperature of the endothermic peak is obtained for measurement.

[0121] The thickness of the base material layer 1 is preferably 55 μm or more and 195 μm or less, more preferably 55 μm or more and 190 μm or less, still more preferably 55 μm or more and 170 μm or less, and most preferably 60 μm or more and 160 μm or less. By setting the thickness of the base material layer 1 within the above range, a dicing tape can be efficiently manufactured, and a semiconductor wafer attached to the dicing tape can be efficiently cut.

[0122] The thickness of the base material layer 1 can be obtained, for example, as follows: Measure the thicknesses of arbitrarily selected 5 points randomly using a direct-reading thickness gauge (model R-205 manufactured by PEACOCK Co., Ltd.), and calculate the arithmetic average of these thicknesses.

[0123] In the base material layer 1 formed by laminating an elastomer layer and a non-elastomer layer, the ratio of the thickness of the non-elastomer layer to the thickness of the elastomer layer is preferably 1 / 25 or more and 1 / 3 or less, more preferably 1 / 25 or more and 1 / 3.5 or less, still more preferably 1 / 25 or more and 1 / 4 or less, particularly preferably 1 / 22 or more and 1 / 4 or less, and most preferably 1 / 20 or more and 1 / 4 or less. By setting the ratio of the thickness of the non-elastomer layer to the thickness of the elastomer layer within the above range, a semiconductor wafer attached to the dicing tape can be cut more efficiently.

[0124] The elastomer layer may have a single-layer (1-layer) structure or a laminated structure. The elastomer layer preferably has a structure of 1 to 5 layers, more preferably 1 to 3 layers, still more preferably 1 to 2 layers, and most preferably 1 layer. When the elastomer layer has a laminated structure, all layers may contain the same elastomer, or at least 2 layers may contain different elastomers.

[0125] The non-elastomer layer may have a single-layer (1-layer) structure or a laminated structure. The non-elastomer layer preferably has a structure of 1 to 5 layers, more preferably 1 to 3 layers, still more preferably 1 to 2 layers, and most preferably 1 layer. When the non-elastomer layer has a laminated structure, all layers may contain the same non-elastomer, or at least 2 layers may contain different non-elastomers.

[0126] The non-elastomer layer preferably contains a polypropylene resin (hereinafter referred to as metallocene PP) obtained as a polymerization product using a metallocene catalyst as the non-elastomer. Examples of the metallocene PP include propylene / α-olefin copolymers obtained as polymerization products of metallocene catalysts. By making the non-elastomer layer contain metallocene PP, a dicing tape can be efficiently manufactured, and a semiconductor wafer attached to the dicing tape can be efficiently cut.

[0127] It should be noted that examples of commercially available metallocene polypropylene include WINTEC WXK1233 and WINTEC WMX03 (both manufactured by Japan Polypropylene Corporation).

[0128] Here, the metallocene catalyst is a catalyst comprising a transition metal compound of Group 4 of the periodic table (so-called metallocene compound) and a cocatalyst that can react with the metallocene compound to activate the metallocene compound into a stable ionic state. The transition metal compound of Group 4 of the periodic table includes a ligand having a cyclopentadienyl skeleton. The metallocene catalyst optionally includes an organoaluminum compound. The metallocene compound is a crosslinked metallocene compound capable of stereoregular polymerization of propylene.

[0129] Among the propylene / α-olefin copolymers that are polymerization products of the above metallocene catalyst, an atactic propylene / α-olefin copolymer that is a polymerization product of the metallocene catalyst is preferred. Among the atactic propylene / α-olefin copolymers that are polymerization products of the above metallocene catalyst, copolymers selected from the group consisting of an atactic propylene / α-olefin copolymer having 2 carbon atoms as the α-olefin, an atactic propylene / α-olefin copolymer having 4 carbon atoms as the α-olefin, and an atactic propylene / α-olefin copolymer having 5 carbon atoms as the α-olefin in the polymerization product of the metallocene catalyst are preferred. Among these, an atactic propylene / ethylene copolymer that is a polymerization product of the metallocene catalyst is most preferred.

[0130] Regarding the atactic propylene / α-olefin copolymer that is a polymerization product of the above metallocene catalyst, from the viewpoints of coextrusion film-forming property with the above elastomer layer and cuttability of the semiconductor wafer adhered to the cutting tape, those having a melting point of 80°C or higher and 140°C or lower, particularly 100°C or higher and 130°C or lower, are preferred.

[0131] The melting point of the atactic propylene / α-olefin copolymer that is a polymerization product of the above metallocene catalyst can be measured by the above method.

[0132] Here, if the above elastomer layer is disposed on the outermost layer of the base material layer 1, when the base material layer 1 is formed into a roll, the above elastomer layers disposed on the outermost layer are likely to adhere to each other (stick together easily). Therefore, it becomes difficult to unwind the base material layer 1 from the roll. In contrast, a preferred form of the base material layer 1 of the above laminate structure is a non-elastomer layer / elastomer layer / non-elastomer layer, that is, the non-elastomer layer is disposed on the outermost layer. Therefore, the anti-blocking property of the base material layer 1 in this form becomes excellent. Thereby, it is possible to suppress delays in the manufacture of semiconductor devices using the cutting tape 10 due to adhesion.

[0133] The above-mentioned non-elastomer layer preferably contains a resin having a melting point of 100°C or higher and 130°C or lower and a molecular weight dispersity (weight average molecular weight / number average molecular weight) of 5 or less. Examples of such a resin include metallocene PP.

[0134] By making the above-mentioned non-elastomer layer contain the resin as described above, the non-elastomer layer can be cooled and cured more rapidly in the cut maintaining process. Therefore, it is possible to more sufficiently suppress the shrinkage of the base material layer 1 after the cutting tape is thermally shrunk.

[0135] Accordingly, in the cut maintaining process, the cut can be more sufficiently maintained.

[0136] The adhesive layer 2 contains an adhesive. The adhesive layer 2 holds the semiconductor wafer for singulation into semiconductor chips by adhesion.

[0137] Examples of the above-mentioned adhesive include an adhesive that can reduce the adhesive force by an external action during the use of the cutting tape 10 (hereinafter referred to as an adhesive force reducing type adhesive).

[0138] When an adhesive force reducing type adhesive is used as the adhesive, during the use of the cutting tape 10, the adhesive layer 2 can be separately used in a state showing a high adhesive force (hereinafter referred to as a high adhesion state) and a state showing a low adhesive force (hereinafter referred to as a low adhesion state). For example, when the semiconductor wafer attached to the cutting tape 10 is subjected to cutting, the high adhesion state is used to suppress the floating or peeling of the plurality of semiconductor chips singulated by cutting the semiconductor wafer from the adhesive layer 2. In contrast, after cutting the semiconductor wafer, the low adhesion state is used to pick up the plurality of singulated semiconductor chips, so that it is easy to pick up the plurality of semiconductor chips from the adhesive layer 2.

[0139] Examples of the above-mentioned adhesive force reducing type adhesive include, for example, an adhesive that can be cured by irradiating radiation during the use of the cutting tape 10 (hereinafter referred to as a radiation curable adhesive).

[0140] Examples of the above-mentioned radiation curable adhesive include, for example, an adhesive of a type that is cured by irradiating electron beams, ultraviolet rays, α rays, β rays, γ rays, or X rays. Among these, an adhesive cured by irradiating ultraviolet rays (ultraviolet curable adhesive) is preferably used.

[0141] Examples of the above-mentioned radiation curable adhesive include, for example, an additive type radiation curable adhesive that contains a base polymer such as an acrylic polymer and a radiation polymerizable monomer component and a radiation polymerizable oligomer component having a functional group such as a carbon-carbon double bond with radiation polymerizability.

[0142] Examples of the acrylic polymer described above include acrylic polymers containing monomer units derived from (meth)acrylate. Examples of the (meth)acrylate include alkyl (meth)acrylate, cycloalkyl (meth)acrylate, and aryl (meth)acrylate, etc.

[0143] The adhesive layer 2 may contain an external crosslinking agent. Any type of external crosslinking agent can be used as long as it can react with the acrylic polymer as the base polymer to form a crosslinked structure. Examples of such external crosslinking agents include polyisocyanate compounds, epoxy compounds, polyol compounds, aziridine compounds, and melamine-based crosslinking agents, etc.

[0144] Examples of the radiation-polymerizable monomer component described above include urethane (meth)acrylate, trimethylolpropane tri(meth)acrylate, pentaerythritol tri(meth)acrylate, pentaerythritol tetra(meth)acrylate, dipentaerythritol monohydroxy penta(meth)acrylate, dipentaerythritol hexa(meth)acrylate, and 1,4-butanediol di(meth)acrylate, etc. Examples of the radiation-polymerizable oligomer component include various oligomers such as urethane-based, polyether-based, polyester-based, polycarbonate-based, and polybutadiene-based oligomers. The content ratios of the radiation-polymerizable monomer component and the radiation-polymerizable oligomer component in the radiation-curable adhesive can be selected within a range that appropriately reduces the adhesiveness of the adhesive layer 2.

[0145] The radiation-curable adhesive preferably contains a photoinitiator. Examples of the photoinitiator include α-ketol compounds, acetophenone compounds, benzoin ether compounds, ketal compounds, aromatic sulfonyl chloride compounds, photoactive oxime compounds, benzophenone compounds, thioxanthone compounds, camphorquinone, halogenated ketones, acylphosphine oxides, and acylphosphonates, etc.

[0146] In the adhesive layer 2, in addition to the above-mentioned components, a crosslinking accelerator, a tackifier, an antioxidant, a coloring agent such as a pigment or a dye, etc. may also be contained.

[0147] The thickness of the adhesive layer 2 is preferably 1 μm or more and 50 μm or less, more preferably 2 μm or more and 30 μm or less, and further preferably 5 μm or more and 25 μm or less.

[0148] [Dicing Chip Bonding Film]

[0149] After that, refer to Figure 2 The dicing chip bonding film 20 will be described. It should be noted that in the description of the dicing chip bonding film 20, the parts that overlap with the dicing tape 10 will not be described again.

[0150] AsFigure 2 As shown, the dicing chip bonding film 20 of the present embodiment includes a dicing tape 10 having an adhesive layer 2 laminated on a base material layer 1, and a chip bonding layer 3 laminated on the adhesive layer 2 of the dicing tape 10.

[0151] In the dicing chip bonding film 20, a semiconductor wafer is attached to the chip bonding layer 3.

[0152] In the dicing of the semiconductor wafer using the dicing chip bonding film 20, the chip bonding layer 3 is also diced together with the semiconductor wafer. The chip bonding layer 3 is diced into a size corresponding to that of a plurality of singulated semiconductor chips. Thereby, semiconductor chips with the chip bonding layer 3 can be obtained.

[0153] As described above, the tensile storage modulus of the dicing tape 10 of the dicing chip bonding film 20 at -5°C is 100 MPa or more.

[0154] Here, usually, the chip bonding layer 3 of the dicing chip bonding film 20 mostly contains an acrylic resin having a glass transition temperature (Tg) near 0°C. Therefore, setting the temperature of the expansion process to a temperature lower than the Tg of the acrylic resin will cause it to be prone to cracking. On the other hand, if the temperature of the expansion process is excessively lowered, the elastic modulus of the chip bonding layer 3 will increase to an extent that hinders the dicing property of the chip bonding layer 3. Therefore, from the viewpoint of the dicing property of the chip bonding layer 3, the temperature of the expansion process is preferably set to -5°C.

[0155] Therefore, in the expansion process using the dicing chip bonding film 20, from the viewpoints of good dicing property when dicing the semiconductor wafer into a plurality of small semiconductor chips as described above and less likely to occur cracking of the dicing tape 10 due to tensile force, and from the viewpoint of the dicing property of the chip bonding layer 3, it is considered that the best solution is to perform the expansion process at a temperature of -5°C.

[0156] Therefore, it is considered that for the dicing chip bonding film 20, by setting the tensile storage modulus at -5°C to a relatively high value of 100 MPa as well, high stress can be generated at a lower elongation rate.

[0157] It is speculated that as a result, the dicing property when dicing the semiconductor wafer into small semiconductor chips can be further improved.

[0158] As described above, the tensile storage modulus of the dicing tape 10 of the dicing chip bonding film 20 is preferably 400 MPa or less at -5°C.

[0159] In addition, as described above, the cutting tape 10 for cutting the chip bonding film 20 preferably has a 30% tensile stress of 5.5 N / 10 mm or more at -5°C, a 30% tensile stress of 3.2 N / 10 mm at room temperature, and a ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature of 1.7 or more.

[0160] Furthermore, as described above, the cutting tape 10 for cutting the chip bonding film 20 preferably has a 30% tensile stress of 30 N / 10 mm or less at -5°C and a 30% tensile stress of 30 N / 10 mm or less at room temperature.

[0161] The chip bonding layer 3 preferably has thermosetting properties. By including at least one of a thermosetting resin and a thermoplastic resin having a thermosetting functional group in the chip bonding layer 3, thermosetting properties can be imparted to the chip bonding layer 3.

[0162] When the chip bonding layer 3 contains a thermosetting resin, examples of such a thermosetting resin include epoxy resins, phenolic resins, amino resins, unsaturated polyester resins, polyurethane resins, silicone resins, and thermosetting polyimide resins. Among these, epoxy resins are preferably used.

[0163] Examples of epoxy resins include bisphenol A type, bisphenol F type, bisphenol S type, brominated bisphenol A type, hydrogenated bisphenol A type, bisphenol AF type, biphenyl type, naphthalene type, fluorene type, phenol novolak type, o-cresol novolak type, trihydroxyphenylmethane type, tetraphenylethane type, hydantoin type, isocyanuric acid triglycidyl ester type, and glycidylamine type epoxy resins.

[0164] Examples of phenolic resins as curing agents for epoxy resins include novolak type phenolic resins, resol type phenolic resins, and polyoxystyrenes such as poly(p-oxystyrene).

[0165] When the chip bonding layer 3 contains a thermoplastic resin having a thermosetting functional group, examples of such a thermoplastic resin include acrylic resins containing a thermosetting functional group. Examples of acrylic resins among acrylic resins containing a thermosetting functional group include acrylic resins containing monomer units derived from (meth)acrylate.

[0166] For a thermosetting resin having a thermosetting functional group, a curing agent can be selected according to the type of the thermosetting functional group.

[0167] From the viewpoint of allowing the curing reaction of the resin component to proceed sufficiently or increasing the curing reaction rate, the chip bonding layer 3 may also contain a thermosetting catalyst. Examples of thermosetting catalysts include imidazole-based compounds, triphenylphosphine-based compounds, amine-based compounds, and trihaloborane-based compounds.

[0168] The chip bonding layer 3 may contain a thermoplastic resin. The thermoplastic resin functions as a binder. Examples of the thermoplastic resin include natural rubber, butyl rubber, isoprene rubber, chloroprene rubber, ethylene-vinyl acetate copolymer, ethylene-acrylic acid copolymer, ethylene-acrylate copolymer, polybutadiene resin, polycarbonate resin, thermoplastic polyimide resin, polyamide resins such as polyamide 6 and polyamide 6,6, phenoxy resin, acrylic resin, saturated polyester resins such as PET and PBT, polyamideimide resin, fluororesin, etc. The above thermoplastic resin may be used alone or in combination of two or more. From the viewpoint of less ionic impurities and high heat resistance and easy to ensure the connection reliability based on the chip bonding layer, an acrylic resin is preferred as the above thermoplastic resin.

[0169] The above acrylic resin is preferably a polymer containing monomer units derived from (meth)acrylate as the monomer units in the largest mass ratio. Examples of the (meth)acrylate include (meth)acrylic acid alkyl ester, (meth)acrylic acid cycloalkyl ester, and (meth)acrylic acid aryl ester, etc. The above acrylic resin may contain monomer units derived from other components copolymerizable with (meth)acrylate. Examples of the above other components include carboxyl group-containing monomers, acid anhydride monomers, hydroxyl group-containing monomers, glycidyl group-containing monomers, sulfonic acid group-containing monomers, phosphoric acid group-containing monomers, acrylamide, acrylonitrile and other functional group-containing monomers, and various polyfunctional monomers, etc. From the viewpoint of achieving high cohesion of the chip bonding layer, the above acrylic resin is preferably a copolymer of (meth)acrylate (especially (meth)acrylic acid alkyl ester with 4 or less carbon atoms in the alkyl group), carboxyl group-containing monomer, nitrogen atom-containing monomer, polyfunctional monomer (especially polyglycidyl-based polyfunctional monomer), and more preferably a copolymer of ethyl acrylate, butyl acrylate, acrylic acid, acrylonitrile, and (meth)acrylic acid polyglycidyl ester.

[0170] As needed, the chip bonding layer 3 may contain one or two or more other components. Examples of the other components include flame retardants, silane coupling agents, and ion trappers.

[0171] The thickness of the chip bonding layer 3 is preferably 40 μm or more, more preferably 60 μm or more, and further preferably 80 μm or more. In addition, the thickness of the chip bonding layer 3 is preferably 200 μm or less, more preferably 160 μm or less, and further preferably 120 μm or less.

[0172] The diced chip bonding film 20 of the present embodiment can be used, for example, as an auxiliary tool for manufacturing semiconductor integrated circuits. Specific examples of using the diced chip bonding film 20 will be described below.

[0173] Hereinafter, an example of using the substrate layer 1 as a single layer for the dicing chip bonding film 20 will be described.

[0174] A method for manufacturing a semiconductor integrated circuit includes the following steps: a semi-dicing step of forming grooves on a semiconductor wafer to process the semiconductor wafer into chips (Dies) by cutting, and then grinding the semiconductor wafer to reduce its thickness; a back grinding step of grinding the semiconductor wafer after the semi-dicing step to reduce its thickness; a mounting step of attaching one surface (e.g., the surface opposite to the circuit surface) of the semiconductor wafer after the back grinding step to the chip bonding layer 3 to fix the semiconductor wafer to the dicing tape 10; an expanding step of expanding the intervals between the semi-diced semiconductor chips; a notch maintaining step of maintaining the intervals between the semiconductor chips; a picking step of peeling the chip bonding layer 3 from the adhesive layer 2 to take out the semiconductor chip (Die) with the chip bonding layer 3 attached; and a chip bonding step of bonding the semiconductor chip (Die) with the chip bonding layer 3 attached to an adherend. When implementing these steps, the dicing tape (dicing chip bonding film) of the present embodiment is used as a manufacturing auxiliary tool.

[0175] In the semi-dicing step, as Figure 3A and Figure 3B shown, semi-dicing for cutting the semiconductor integrated circuit into small pieces (Dies) is performed. Specifically, a wafer processing tape T is attached to the surface of the semiconductor wafer W opposite to the circuit surface (refer to Figure 3A ). In addition, a dicing ring R is mounted on the wafer processing tape T (refer to Figure 3A ). Grooves for dicing are formed in the state where the wafer processing tape T is attached (refer to Figure 3B ). In the back grinding step, as Figure 3C and Figure 3D shown, the semiconductor wafer is ground to reduce its thickness. Specifically, a back grinding tape G is attached to the surface on which the grooves are formed, and on the other hand, the initially attached wafer processing tape T is peeled off (refer to Figure 3C ). Grinding is performed in the state where the back grinding tape G is attached until the semiconductor wafer W reaches a specified thickness (refer to Figure 3D ).

[0176] In the mounting step, as Figures 4A to 4B shown, after the dicing ring R is mounted on the adhesive layer 2 of the dicing tape 10, the semi-diced semiconductor wafer W is attached to the exposed surface of the chip bonding layer 3 (refer to Figure 4A ). Thereafter, the back grinding tape G is peeled off from the semiconductor wafer W (refer to Figure 4B ).

[0177] In the expanding step, asFigures 5A to 5C As shown, the dicing ring R is fixed to the holder H of the expansion device. The dicing die bonding film 20 is lifted from the lower side using the lifting member U provided in the expansion device, thereby stretching the dicing die bonding film 20 and expanding it in the surface direction (see Figure 5B ). Thus, the semiconductor wafer W that has been half-cut is cut under a specific temperature condition. The temperature condition is, for example, -20 to 5°C, preferably -15 to 0°C, and more preferably -10 to -5°C. The extended state is released by lowering the lifting member U (see Figure 5C ).

[0178] Furthermore, in the expansion process, Figures 6A to 6B As shown, the dicing tape 10 is stretched under a higher temperature condition (eg, room temperature (23° C.)) to expand the area. Thus, the cut adjacent semiconductor chips W are separated in the plane direction of the film surface, and the interval is further increased.

[0179] Here, the dicing die-bonding film 20 of the present embodiment can further improve the cutting property from a semiconductor wafer to a plurality of semiconductor chips by expansion under low temperature conditions because the tensile storage modulus of the die-bonding tape 10 at -5°C is 100 MPa or more.

[0180] In the incision maintenance process, Figure 7 As shown, hot air (eg, 100 to 130° C.) is directed toward the dicing tape 10 to heat shrink the dicing tape 10, and then the dicing tape 10 is cooled and solidified, thereby maintaining the distance (kerf) between the cut adjacent semiconductor chips W.

[0181] In the picking process, Figure 8 As shown, the semiconductor chip W with the die bonding layer 3 attached thereto is peeled off from the adhesive layer 2 of the dicing tape 10. Specifically, the pin member P is raised to lift up the semiconductor chip W to be picked up through the dicing tape 10. The lifted semiconductor chip is held by the suction jig J.

[0182] In the die bonding step, the semiconductor chip W with the die bonding layer 3 attached thereto is bonded to an adherend.

[0183] In the above-mentioned manufacturing of the semiconductor integrated circuit, an example in which the dicing die-bonding film 20 is used as an auxiliary tool is described. However, when the dicing tape 10 is used as an auxiliary tool, the semiconductor integrated circuit can be manufactured in the same manner as described above.

[0184] Matters disclosed by this specification include the following matters. (1)

[0186] A dicing tape comprising an adhesive layer laminated on a base material layer,

[0187] The tensile storage modulus of the cutting tape at -5°C is 100 MPa or more.

[0188] According to the above constitution, the tensile storage modulus of the above cutting tape at -5°C is 100 MPa or more, so the above cutting tape can have a relatively large hardness.

[0189] Therefore, when the cutting tape is attached to a semiconductor wafer and expanded at a low temperature (for example, -15°C to 5°C) to cut the semiconductor wafer into a plurality of semiconductor chips, at the start of expansion, a tensile force can be sufficiently applied to the entire cutting tape.

[0190] Thus, it is easy to cut the semiconductor wafer into a plurality of semiconductor chips, and it is easy to obtain semiconductor chips that are cut more evenly.

[0191] That is, the cuttability of the semiconductor wafer can be further improved. (2)

[0193] For the cutting tape described in the above (1), the tensile storage modulus at -5°C is 400 MPa or less.

[0194] According to the above constitution, a sufficient tensile force is applied to the entire cutting tape, and the cutting tape is relatively easy to elongate. Therefore, it is possible to further suppress the rupture of the cutting tape caused by the tensile force when cutting the semiconductor wafer attached to the cutting tape into a plurality of semiconductor chips, and improve the cuttability from the semiconductor wafer to the plurality of semiconductor chips.

[0195] In addition, by making the 30% tensile stress at -5°C 30 N / 10 mm or less, in particular, the cuttability from the semiconductor wafer to a plurality of small semiconductor chips can be further improved. (3)

[0197] For the cutting tape described in the above (1) or (2), the 30% tensile stress at -5°C is 5.5 N / 10 mm or more.

[0198] According to the above constitution, the 30% tensile stress at -5°C is 5.5 N / 10 mm or more. Therefore, when the cutting tape is attached to a semiconductor wafer and expanded at a low temperature to cut the semiconductor wafer into a plurality of semiconductor chips, the cutting tape can also have a relatively large hardness during expansion.

[0199] Therefore, it becomes easier to cut the semiconductor wafer into a plurality of semiconductor chips, and it is easier to obtain semiconductor chips that are cut more evenly.

[0200] That is, the cuttability of the semiconductor wafer can be further improved. (4)

[0202] The dicing tape according to any one of (1) to (3) above, wherein the 30% tensile stress at -5°C is 30 N / 10 mm or less.

[0203] According to the above configuration, during the expansion of the dicing tape attached to the semiconductor wafer to cut the semiconductor wafer into a plurality of semiconductor chips, since a sufficient tensile force is applied to the entire dicing tape during the expansion and the dicing tape is made to be easily elongated, the breakage of the dicing tape caused by the expansion can be further suppressed, and the cuttability from the semiconductor wafer to the plurality of semiconductor chips can be improved.

[0204] In addition, by making the 30% tensile stress at -5°C 30 N / 10 mm or less, the cuttability from the semiconductor wafer to a plurality of small semiconductor chips can be further improved, in particular. (5)

[0206] The dicing tape according to any one of (1) to (4) above, wherein the 30% tensile stress at room temperature is 3.2 N / 10 mm or more.

[0207] According to the above configuration, since the 30% tensile stress at room temperature is 3.2 N / 10 mm or more, when the dicing tape is attached to the semiconductor wafer and the dicing tape is expanded under low temperature conditions to cut the semiconductor wafer into a plurality of semiconductor chips, the cuttability of the semiconductor wafer can be further improved during the expansion.

[0208] In addition, the transfer of the tensile stress generated in the dicing tape between the cut semiconductor chips to the semiconductor chip side can be suppressed.

[0209] Therefore, the situation where a relatively large force is applied to the outer edge portion of the semiconductor chip to cause the outer edge portion of the semiconductor chip to float from the surface of the dicing tape (chip floating) can be relatively suppressed. (6)

[0211] The dicing tape according to any one of (1) to (5) above, wherein the 30% tensile stress at room temperature is 30 N / 10 mm or less.

[0212] According to the above configuration, during the expansion of the dicing tape attached to the semiconductor wafer to cut the semiconductor wafer into a plurality of semiconductor chips, since a sufficient tensile force is applied to the entire dicing tape during the expansion and the dicing tape is made to be easily elongated, the breakage of the dicing tape caused by the expansion can be further suppressed, and the cuttability from the semiconductor wafer to the plurality of semiconductor chips can be improved.

[0213] In addition, by setting the 30% tensile stress at room temperature to 30 N / 10 mm or less, in particular, the cutability from a semiconductor wafer into a plurality of small semiconductor chips can be further improved. (7)

[0215] The dicing tape according to any one of the above (1) to (6), wherein the ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is 1.7 or more.

[0216] According to the above configuration, since the ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is 1.7 or more, when the dicing tape is attached to a semiconductor wafer and the dicing tape is expanded under low-temperature conditions to cut the semiconductor wafer into a plurality of semiconductor chips, the cutability of the semiconductor wafer can be further improved during the expansion.

[0217] In addition, the chip floating caused by the transfer of the tensile stress generated by the dicing tape to the semiconductor chip side can be relatively suppressed. (8)

[0219] The dicing tape according to any one of the above (1) to (7), wherein the ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is 3.0 or less.

[0220] According to the above configuration, during the expansion of the dicing tape attached to a semiconductor wafer to cut the semiconductor wafer into a plurality of semiconductor chips, a sufficient tensile force is applied to the entire dicing tape during the expansion and the dicing tape is easily elongated, so that the dicing tape can be further broken due to the expansion and the cutability from the semiconductor wafer into a plurality of semiconductor chips can be improved.

[0221] In addition, by making the ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature 3.0 or less, in particular, the cutability from a semiconductor wafer into a plurality of small semiconductor chips can be further improved. (9)

[0223] The dicing tape according to any one of the above (1) to (8), wherein the base material layer is formed into a three-layer structure having an elastomer layer as a center layer and non-elastomer layers on both opposite sides of the center layer.

[0224] According to the above configuration, the elastomer layer can function as a stress relaxation layer for relaxing the tensile stress. That is, the tensile stress generated by the base material layer can be relatively reduced, so that the base material layer can have an appropriate hardness and be easily stretched.

[0225] Thus, the cutability from a semiconductor wafer into a plurality of semiconductor chips can be improved.

[0226] In addition, breakage of the base material layer during expansion in the cutting process can be suppressed, thereby preventing damage. (10)

[0228] A cutting chip bonding film, comprising:

[0229] A cutting tape having an adhesive layer laminated on a base material layer, and

[0230] A chip bonding layer laminated on the adhesive layer of the cutting tape,

[0231] The tensile storage modulus of the cutting chip bonding film at -5°C is 100 MPa or more.

[0232] According to the above configuration, when the cutting tape is attached to a semiconductor wafer and the cutting tape is expanded under low-temperature conditions (e.g., -15°C to 5°C) to cut the semiconductor wafer into a plurality of semiconductor chips, a tensile force can be sufficiently applied to the entire cutting tape at the start of expansion.

[0233] Thus, the cutability of the semiconductor wafer can be further improved, and the cutability of the chip bonding layer can also be improved.

[0234] It should be noted that the cutting tape and the cutting chip bonding film of the present invention are not limited by the above-described embodiments. In addition, the cutting tape and the cutting chip bonding film of the present invention are not limited by the above-described effects. The cutting tape and the cutting chip bonding film of the present invention can be variously modified without departing from the gist of the present invention.

[0235] Examples

[0236] After that, examples are given to further specifically illustrate the present invention. The following examples are examples for further detailed illustration of the present invention and do not limit the scope of the present invention.

[0237] [Example 1]

[0238] <Molding of the base material layer>

[0239] A substrate layer having a three-layer structure of layer A / layer B / layer C (a three-layer structure with layer B as the central layer and layer A and layer C as outer layers laminated on both sides of layer B) is formed using two three-layer extrusion T-die molding machines. As the resins for layer A and layer C, metallocene PP (trade name: WINTEC WXK1233, manufactured by Japan Polypropylene Corporation) is used, and as the resin for layer B, EVA (trade name: Evaflex EV250, manufactured by Mitsui DuPont Polychemical Co., Ltd.) is used.

[0240] The above extrusion molding is carried out at a die head temperature of 190 °C. That is, layer A, layer B, and layer C are extrusion molded at 190 °C. The thickness of the substrate layer obtained by extrusion molding is 100 μm. It should be noted that the thickness ratio (layer thickness ratio) of layer A: layer B: layer C is layer A: layer B: layer C = 1:10:1.

[0241] After the formed substrate layer is sufficiently cured, the cured substrate layer is wound into a roll shape to form a rolled body.

[0242] <Production of cutting tape>

[0243] An adhesive composition is coated on one surface of the rolled substrate layer from the rolled substrate layer using an applicator to a thickness of 10 μm. The substrate layer coated with the adhesive composition is heated and dried at 110 °C for 3 minutes to form an adhesive layer, thereby obtaining a cutting tape.

[0244] The above adhesive composition is prepared as described below.

[0245] First, 173 parts by mass of INA (isononyl acrylate), 54.5 parts by mass of HEA (2-hydroxyethyl acrylate), 0.46 parts by mass of AIBN (2,2'-azobisisobutyronitrile), and 372 parts by mass of ethyl acetate are mixed to obtain a first resin composition.

[0246] After that, the above first resin composition is added into the above round-bottom detachable flask of the polymerization experimental device equipped with a round-bottom detachable flask (capacity 1 L), a thermometer, a nitrogen inlet tube, and stirring blades. While stirring the first resin composition, the liquid temperature of the first resin composition is brought to room temperature (23 °C), and the inside of the round-bottom detachable flask is purged with nitrogen for 6 hours.

[0247] Next, while nitrogen is flowing into the above round-bottom detachable flask, while stirring the first resin composition, the liquid temperature of the first resin composition is maintained at 62 °C for 3 hours, and then further maintained at 75 °C for 2 hours to polymerize the above INA, the above HEA, and the above AIBN to obtain a second resin composition. After that, the inflow of nitrogen into the above round-bottom detachable flask is stopped.

[0248] The above-described second resin composition was cooled until the liquid temperature reached room temperature, and then 52.5 parts by mass of 2-isocyanatoethyl methacrylate (manufactured by Showa Denko K.K., trade name “Karenz MOI (registered trademark)”), which is a compound having a polymerizable carbon-carbon double bond, and 0.26 parts by mass of dibutyltin dilaurate IV (manufactured by Wako Pure Chemical Industries, Ltd.) were added to the above-described second resin composition to obtain a third resin composition. The obtained third resin composition was stirred at a liquid temperature of 50° C. in an air atmosphere for 24 hours.

[0249] Thereafter, 0.75 parts by mass of CORONATE L (isocyanate compound) and 2 parts by mass of Omnirad 127 (photoinitiator) were added to the above-described third resin composition per 100 parts by mass of the polymer solid content, and then the above-described third resin composition was diluted with ethyl acetate until the solid content concentration reached 20 mass %, thereby preparing an adhesive composition.

[0250] <Fabrication of a diced chip bonding film>

[0251] 100 parts by mass of an acrylic resin (manufactured by Nagase ChemteX Corporation, trade name “SG-P3”, glass transition temperature 12° C.), 46 parts by mass of an epoxy resin (manufactured by Mitsubishi Chemical Corporation, trade name “JER1001”), 51 parts by mass of a phenolic resin (manufactured by Meiwafosis Co., Ltd., trade name “MEH-7851ss”), 191 parts by mass of spherical silica (manufactured by Admatechs Co., Ltd., trade name “SO-25R”), and 0.6 parts by mass of a curing catalyst (manufactured by Shikoku Kasei Kogyo Co., Ltd., trade name “CUREZOL PHZ”) were added to methyl ethyl ketone and mixed to obtain a chip bonding composition having a solid content concentration of 20 mass %.

[0252] Thereafter, the above-described chip bonding composition was applied onto the silicone-treated surface of a PET-based separator (thickness 50 μm) serving as a release liner to a thickness of 10 μm using a coater, and dried at 130° C. for 2 minutes to remove the solvent from the above-described chip bonding composition, thereby obtaining a chip bonding sheet having a chip bonding layer laminated on the above-described release liner.

[0253] Thereafter, one side of the above-described chip bonding sheet on which the above-described release sheet was not laminated was bonded to the above-described adhesive layer of the above-described dicing tape, and then the above-described release liner was peeled off from the above-described chip bonding layer to obtain a diced chip bonding film having a chip bonding layer.

[0254] For the cut tape obtained as described above, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured as described below. In addition, the floating of the chip from the cut chip bonding film during expansion (hereinafter referred to as chip floating) and the cutability of the chip and the chip bonding layer (hereinafter referred to as cutability) were evaluated.

[0255] (Tensile storage modulus at -5°C)

[0256] A test piece with a length of 40 mm (measurement length) × width of 10 mm was cut from the cut tape of Example 1. Using a solid viscoelasticity measuring device (Model RSAIII, manufactured by Rheometric Scientific Co., Ltd.), the tensile storage modulus of the above test piece was measured in the temperature range of -50 to 100°C under the conditions of a frequency of 1 Hz, a deformation amount of 0.1%, a heating rate of 10°C / minute, and a distance between clamps of 22.5 mm. At this time, the tensile storage modulus at -5°C was obtained by reading the value of the tensile elastic modulus at -5°C.

[0257] (30% Tensile stress at -5°C and room temperature)

[0258] A test piece with a length of 100 mm × width of 10 mm was cut from the cut tape of Example 1. Using a tensile testing machine (Tensilon universal testing machine, manufactured by Shimadzu Corporation), the above test piece was stretched at the measurement temperatures (-5°C and room temperature) under the conditions of a distance between clamps of 50 mm and a stretching speed of 100 mm / minute, and the stress at the time when the elongation rate reached 30% (distance between clamps of 65 mm) was measured.

[0259] (Evaluation of chip floating)

[0260] A bare wafer (diameter 300 mm) and a cutting ring were attached to the cut chip bonding film of Example 1. Then, a semiconductor wafer and the chip bonding layer were cut using a chip separation device DDS230 (manufactured by DISCO Corporation), and the chip floating after cutting was evaluated. The bare wafer was cut into bare chips with a size of length 12 mm × width 4 mm × thickness 0.055 mm.

[0261] It should be noted that a warped wafer was used as the bare wafer.

[0262] The warped wafer was produced as described below.

[0263] First, the following (a) to (f) were dissolved in methyl ethyl ketone to obtain a warpage adjustment composition with a solid component concentration of 20% by mass.

[0264] (a) Acrylic resin (manufactured by Nagase ChemteX Corporation, trade name "SG-70L"): 5 parts by mass

[0265] (b) Epoxy resin (manufactured by Mitsubishi Chemical Corporation, trade name "JER828"): 5 parts by mass

[0266] (c) Phenolic resin (manufactured by Meiwafosis Co., Ltd., trade name "LDR8210"): 14 parts by mass

[0267] (d) Epoxy resin (manufactured by Mitsubishi Chemical Corporation, trade name "MEH-8005"): 2 parts by mass

[0268] (e) Spherical silica (manufactured by Admatechs Co., Ltd., trade name "SO-25R"): 53 parts by mass

[0269] (f) Phosphorus-based catalyst (TPP-K): 1 part by mass

[0270] After that, using an applicator, the above-mentioned warpage adjustment composition was coated onto the silicone-treated surface of a PET-based separator (thickness 50 μm) as a release liner with a thickness of 25 μm, and dried at 130 °C for 2 minutes to remove the solvent from the above-mentioned warpage adjustment composition, thereby obtaining a warpage adjustment sheet having a warpage adjustment layer laminated on the above-mentioned release liner.

[0271] After that, using a laminator (manufactured by MCK Corporation, model MRK-600), a bare wafer was attached to the side of the above-mentioned warpage adjustment sheet where the above-mentioned release liner was not laminated under the conditions of 60 °C, 0.1 MPa, and 10 mm / s, placed in an oven, and heated at 175 °C for 1 hour to thermally cure the resin of the above-mentioned warpage adjustment layer. As a result, the above-mentioned warpage adjustment layer shrank, and a warped bare wafer was obtained.

[0272] After the above-mentioned warpage adjustment layer shrank, a wafer processing tape (manufactured by Nitto Denko Corporation, trade name "V-12SR2") was attached to the side of the warped bare wafer where the above-mentioned warpage adjustment layer was not laminated. Then, a dicing ring was fixed to the warped bare wafer by means of the above-mentioned wafer processing tape. After that, the above-mentioned warpage adjustment layer was removed from the warped bare wafer.

[0273] Using a dicing device (manufactured by DISCO Corporation, model 6361), grooves with a depth of 100 μm starting from the entire surface (hereinafter referred to as one surface) of the warped bare wafer from which the above-mentioned warpage adjustment layer was removed were formed in a grid pattern (width 20 μm).

[0274] After that, a back grinding tape was attached to one surface of the warped bare wafer, and the above-mentioned wafer processing tape was removed from the other surface (the surface opposite to the above-mentioned one surface) of the warped bare wafer.

[0275] Thereafter, the warped bare wafer was ground from the other side using a back grinder (manufactured by DISCO Corporation, model DGP8760) until the thickness of the warped bare wafer reached 55 μm (0.055 mm), and the obtained wafer was used as the warped wafer.

[0276] Specifically, chip floating was evaluated as follows.

[0277] First, the bare wafer and the chip bonding layer were cut using a cold expansion unit under the conditions of an expansion temperature of -5°C, an expansion speed of 100 mm / second, and an expansion amount of 12 mm to obtain a semiconductor chip with a chip bonding layer.

[0278] Thereafter, expansion was performed at room temperature, an expansion speed of 1 mm / second, and an expansion amount of 5 mm. Then, while maintaining the expanded state, the cut chip bonding film at the boundary portion with the outer edge of the bare wafer was thermally shrunk under the conditions of a heating temperature of 200°C, a heating distance of 18 mm, and a rotation speed of 5° / second.

[0279] Thereafter, for the surface of the substrate layer of the cut chip bonding film, the floating state of the semiconductor chip with the chip bonding layer was photographed by microscopic observation and binarized, and thus the floating area was calculated. Thereafter, a case where the floating area was less than 4% was evaluated as ○, and a case where it was 4% or more was evaluated as ×.

[0280] (Evaluation of cuttability)

[0281] A bare wafer (diameter 300 mm) and a cutting ring were attached to the cut chip bonding film of Example 1. Thereafter, the bare wafer and the chip bonding layer were cut using a chip separation device DDS230 (manufactured by DISCO Corporation).

[0282] The bare wafer was cut into bare chips having a size of length 3.2 mm × width 1.4 mm × thickness 0.025 mm.

[0283] Specifically, cuttability was evaluated as follows.

[0284] First, the bare wafer and the chip bonding layer were cut using a cold expansion unit under the conditions of an expansion temperature of -5°C, an expansion speed of 100 mm / second, and an expansion amount of 14 mm to obtain a semiconductor chip with a chip bonding layer.

[0285] Thereafter, expansion was performed at room temperature, an expansion speed of 1 mm / second, and an expansion amount of 10 mm. Then, while maintaining the expanded state, the cut chip bonding film at the boundary portion with the outer edge of the bare wafer was thermally shrunk under the conditions of a heating temperature of 200°C, a heating distance of 18 mm, and a rotation speed of 5° / second.

[0286] After that, the cut portion of the semiconductor chip with the chip bonding layer was observed through a microscope, and the cutting rate was calculated. After that, a case where the cutting rate was 90% or more was evaluated as ○, and a case where the cutting rate was less than 90% was evaluated as ×.

[0287] [Example 2]

[0288] The substrate layer was set to 80 μm, and the rest was carried out in the same manner as in Example 1 to obtain the cutting tape and the cutting chip bonding film of Example 2.

[0289] In addition, for the cutting tape of Example 2, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1.

[0290] Furthermore, the chip floating and cuttability of the cutting chip bonding film of Example 2 were evaluated.

[0291] [Example 3]

[0292] The EVA of the B layer (center layer) constituting the substrate layer was set to Evaflex EV550 (manufactured by Mitsui DuPont Polychemical Co., Ltd.), and the substrate layer was set to 80 μm. The rest was carried out in the same manner as in Example 1 to obtain the cutting tape and the cutting chip bonding film of Example 3.

[0293] In addition, for the cutting tape of Example 3, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1.

[0294] Furthermore, the chip floating and cuttability of the cutting chip bonding film of Example 3 were evaluated.

[0295] [Example 4]

[0296] The resin of the B layer was set to an acrylic elastomer (trade name: Vistamaxx 3980, manufactured by ExxonMobil Chemical company), and the rest was carried out in the same manner as in Example 1 to obtain the cutting tape and the cutting chip bonding film of Example 4.

[0297] In addition, for the cutting tape of Example 4, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1.

[0298] Furthermore, the chip floating and cuttability of the cutting chip bonding film of Example 4 were evaluated.

[0299] [Example 5]

[0300] The thickness of the base material layer was set to 80 μm, and the layer thickness ratio of the base material layer was set to A layer:B layer:C layer = 1:4:1. Otherwise, the same procedure as in Example 1 was carried out to obtain the dicing tape and the diced chip bonding film of Example 5.

[0301] In addition, for the dicing tape of Example 5, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1.

[0302] Furthermore, the diced chip bonding film of Example 5 was evaluated for chip floating and cuttability.

[0303] [Example 6]

[0304] The metallocene PP of the A layer and the C layer (outer layer) constituting the base material layer was set to WINTEC WMX03 (manufactured by Japan Polypropylene Corporation). Otherwise, the same procedure as in Example 1 was carried out to obtain the dicing tape and the diced chip bonding film of Example 6.

[0305] In addition, for the dicing tape of Example 6, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1.

[0306] Furthermore, the diced chip bonding film of Example 6 was evaluated for chip floating and cuttability.

[0307] [Example 7]

[0308] The EVA resin of the B layer constituting the base material layer was set to Ultrathene651 (manufactured by Tosoh Corporation). Otherwise, the same procedure as in Example 1 was carried out to obtain the dicing tape and the diced chip bonding film of Example 7.

[0309] In addition, for the dicing tape of Example 7, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1.

[0310] Furthermore, the diced chip bonding film of Example 7 was evaluated for chip floating and cuttability.

[0311] [Example 8]

[0312] The base material layer was set to a single-layer structure, and the thickness of the base material layer was set to 125 μm. Otherwise, the same procedure as in Example 1 was carried out to obtain the dicing tape and the diced chip bonding film of Example 8.

[0313] A single-layer extrusion T-die molding machine was used to mold the base material layer. As the resin of the base material layer, a propylene-based elastomer (trade name: Vistamaxx3980, manufactured by ExxonMobil Chemical company) was used.

[0314] In addition, for the cutting tape of Example 8, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1.

[0315] Furthermore, the chip floating and cuttability of the cut chip bonding film of Example 8 were evaluated.

[0316] [Example 9]

[0317] The thickness of the base material layer was set to 100 μm, and the rest was carried out in the same manner as in Example 8 to obtain the cutting tape and the cut chip bonding film of Example 9.

[0318] In addition, for the cutting tape of Example 9, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1.

[0319] Furthermore, the chip floating and cuttability of the cut chip bonding film of Example 9 were evaluated.

[0320] [Comparative Example 1]

[0321] The resin of the base material layer was set to Evaflex EV250 (manufactured by Mitsui DuPont Polychemical Co., Ltd.), and the rest was carried out in the same manner as in Example 8 to obtain the cutting tape and the cut chip bonding film of Comparative Example 1.

[0322] In addition, for the cutting tape of Comparative Example 1, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1.

[0323] Furthermore, the chip floating and cuttability of the cut chip bonding film of Comparative Example 1 were evaluated.

[0324] [Comparative Example 2]

[0325] The thickness of the base material layer was set to 100 μm, and the rest was carried out in the same manner as in Comparative Example 1 to obtain the cutting tape and the cut chip bonding film of Comparative Example 2.

[0326] In addition, for the cutting tape of Comparative Example 2, the tensile storage modulus at -5°C and the 30% tensile stress at -5°C and 23°C were measured in the same manner as in Example 1.

[0327] Furthermore, the chip floating and cuttability of the cut chip bonding film of Comparative Example 2 were evaluated.

[0328] The measurement results of the tensile storage modulus at -5°C, the tensile stress at -5°C and 23°C of the cutting tape for each example, and the evaluation results of the chip floating and cuttability of the cutting chip bonding film for each example are shown in Table 1 below.

[0329]

Table 1

[0330]

[0331] As can be seen from Table 1, the values of the tensile storage modulus at -5°C of the cutting tapes of Examples 1 to 9 are all shown to be 100 MPa or more, and the cuttability of the cutting chip bonding films of Examples 1 to 9 is excellent.

[0332] In addition, as can be seen from Table 1, the cutting chip bonding films of Examples 1 to 7 having the cutting tapes of Examples 1 to 7, that is, the cutting tapes with a three-layer structure of the base material layer, can all suppress chip floating.

[0333] In contrast, it can be seen that the values of the tensile storage modulus at -5°C of the cutting tapes of Comparative Examples 1 and 2 are both lower than 100 MPa, the cuttability of the cutting chip bonding films of Comparative Examples 1 and 2 is poor, and chip floating cannot be suppressed.

[0334] It should be noted that although the results revealed in Table 1 are regarding the cutting chip bonding film, it can be predicted that the cutting tape contained in the cutting chip bonding film will also obtain the same results as those shown in Table 1.

Claims

1. A cutting tape having an adhesive layer laminated on a substrate layer, The tensile storage modulus of the cutting tape at -5°C is 100 MPa or more.

2. The cutting tape according to claim 1, wherein, The 30% tensile stress at -5°C is 5.5 N / 10 mm or more.

3. The cutting tape according to claim 1 or 2, wherein, The 30% tensile stress at room temperature is 3.2 N / 10 mm or more.

4. The cutting tape according to claim 1, wherein, The ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is 1.7 or more.

5. The cutting belt according to claim 2, wherein, The ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is 1.7 or more.

6. The cutting tape according to claim 3, wherein, The ratio of the 30% tensile stress at -5°C to the 30% tensile stress at room temperature is 1.7 or more.

7. A cutting chip bonding film, comprising: A cutting tape having an adhesive layer laminated on a substrate layer, and A chip bonding layer laminated on the adhesive layer of the cutting tape, The tensile storage modulus of the cutting chip bonding film at -5°C is 100 MPa or more.

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