Integrated circuit wafer PN well morphology characterization method based on silicon carbide
By using high-concentration dyeing solution with HNO3, HF and C6H8O7 configurations for chemical corrosion and combining ion grinding to prepare samples, the problem of morphological characterization of PN well of silicon carbide integrated circuit wafers was solved, and clear morphological characteristics were realized and efficient dyeing effect was achieved.
Patent Information
- Application Number
- CN202311818168.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-26
- Publication Date
- 2025-06-27
AI Technical Summary
Silicon carbide integrated circuit wafers lack effective PN well morphological characterization methods. Traditional methods cannot effectively corrode SiC materials, resulting in the inability to show the morphological characteristics of PN well.
Chemical corrosion was performed using high concentrations of the dyeing solution of HNO3, HF and C6H8O7 configuration, and samples were prepared by ionic grinding to reveal the morphological characteristics of the PN well.
It has achieved effective characterization of the PN well morphology of silicon carbide integrated circuit wafer, with good dyeing effect, clear boundaries of the PN well source region and obvious morphological characteristics, which is suitable for the evaluation and failure analysis of SiC integrated circuit devices.
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Figure CN120213995A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of destructive analysis of integrated circuit devices, and particularly to a method for characterizing the PN well morphology of an integrated circuit wafer based on silicon carbide. Background Art
[0002] In the field of integrated circuit devices, a PN well refers to a P-type or N-type semiconductor structure formed by doping different impurities into semiconductor materials such as silicon or germanium. The well depth and morphology of an integrated circuit device are important parameters for characterizing the device process node. Currently, many studies have been conducted on the PN well characterization methods for traditional silicon-based integrated circuit devices. SiC (silicon carbide), as a new type of gradually mature composite material, has begun to be widely used in power integrated circuit devices for automotive electronics due to its higher thermal conductivity, better electrical insulation, and thermal stability than ordinary silicon.
[0003] For traditional silicon-based integrated circuit devices, methods such as chemical solution staining and ion mass spectrometer analysis are used for PN well morphology characterization. The chemical solution staining method has been popular in the industry because of its low cost and simple process. It generally uses a mixture of solutions such as HNO3 (nitric acid), CH3COOH (acetic acid), and HF (hydrofluoric acid), or a BOE (NH4F, HF, HNO3, CH3COOH) solution. However, CH3COOH has a strong smell and is likely to affect the laboratory test environment. In terms of sample preparation, the commonly used mechanical grinding method is likely to cause delamination between the metal layer and the substrate of the wafer, and the metal layer is prone to extension during the grinding process, making it difficult to meet the requirements for the fineness of the prepared sample cross-section. In the prior art, FIB (Focus Ion Beam) is also used for ion cutting, and samples are prepared by digging holes or grooves. However, this method is inefficient and costly. Only the sample cross-section is made through holes or grooves, and the stained area is small, which does not meet the staining requirements for the entire cross-section of the wafer.
[0004] Such as Figure 1The figure shows a schematic diagram of a PN well in a SiC structure. The SiC integrated circuit wafer has a lattice structure similar to the layered structure of graphite, while the lattice structure of a pure silicon-based integrated circuit wafer is a diamond crystal structure. The layered structure of graphite is relatively more compact than the diamond crystal structure, with higher hardness, better thermal conductivity, and corrosion resistance. The staining solution used for ordinary silicon-based integrated circuit wafers cannot corrode the cross-section of the silicon carbide integrated circuit wafer, thus failing to play a staining role and unable to reveal the morphological characteristics of the PN well. Due to its hardness and excellent thermal stability, the thickness and size of general chip products of silicon carbide integrated circuit wafers are smaller than those of silicon-based chips, and the wafer structure is also more delicate. Traditional mechanical grinding methods are prone to causing chip fragmentation or excessive grinding. The differences in physical structures such as the lattice structure and hardness between SiC and traditional silicon-based materials result in differences in the PN well staining method for SiC integrated circuit wafers in aspects such as staining solution preparation and sample preparation compared to traditional silicon-based integrated circuit wafers. Currently, there is still a lack of a mature solution for PN well staining, sample preparation, and further morphological characterization of PN wells in SiC integrated circuit wafers. Summary of the Invention
[0005] The technical problem to be solved by the present invention is: the lack of a morphological characterization solution for silicon carbide integrated circuit wafers.
[0006] To achieve the above object, the present invention provides a method for morphological characterization of a PN well in a silicon carbide-based integrated circuit wafer, the method comprising the following steps:
[0007] Step S1, preparing a silicon carbide integrated circuit wafer sample by means of ion milling;
[0008] Step S2, selecting HNO3 with a concentration of 98%, HF with a concentration of 40%, and C6H8O7 with a concentration of 30% to prepare a staining solution;
[0009] Step S3, immersing the cross-section of the prepared silicon carbide integrated circuit wafer sample into the prepared staining solution for staining, then taking out the sample, rinsing it with deionized water, and drying it;
[0010] Step S4, observing and measuring the morphology of the cross-section of the dried silicon carbide integrated circuit wafer sample after staining through SEM.
[0011] Preferably, in step S2, the volume ratio of HNO3, HF, and C6H8O7 is HNO3:HF:C6H8O7 = 50:1:5 - 10.
[0012] Preferably, after preparing the staining solution according to the volume ratio in step S2, the staining solution is fully mixed evenly, and the shelf life of the staining solution is 2 hours.
[0013] Preferably, in the step S1, the specific method for preparing the silicon carbide integrated circuit wafer sample that needs to be characterized by the PN well morphology by ion milling is as follows: Physically bombard the sample with an argon ion beam to grind the silicon carbide integrated circuit wafer to be tested to the position of the cross-section to be dyed.
[0014] Preferably, in the step S3, when the cross-section of the prepared silicon carbide integrated circuit wafer sample is immersed in the prepared staining solution for staining, the specific staining time is related to the cross-sectional size of the prepared silicon carbide integrated circuit wafer sample. The larger the cross-section, the longer the required staining time. The preferred staining time is 15 seconds to 30 seconds.
[0015] Preferably, in the step S3, rinse with deionized water for at least 30 seconds.
[0016] Due to the corrosion resistance of the SiC material, the staining solution prepared with medium-concentration HNO3 for pure silicon-based integrated circuit wafers cannot chemically corrode the SiC material, so it cannot stain the PN well and cannot reveal the morphological characteristics of the PN well. The technical solution of the present invention uses high-concentration HNO3 to prepare the staining solution. High-concentration HNO3 is combined with HF to achieve the purpose of chemical corrosion of the cross-section of the silicon carbide integrated circuit wafer and achieve the staining effect. At the same time, CH3COOH in the traditional staining solution is replaced with C6H8O7, which has stronger acidity and no pungent smell. In addition, in view of the differences in the lattice structure, size, hardness, etc. between the SiC integrated circuit wafer and the pure silicon-based integrated circuit wafer, the ion milling method is used to prepare the sample to avoid problems such as scratches, dirt, and metal extension caused by stress in mechanical milling. The prepared sample is put into the staining solution for staining, then rinsed with deionized water and dried, and the stained cross-section can be observed and measured by SEM. By adopting the technical solution of the present invention, a staining solution prepared with high-concentration HNO3, HF, and C6H8O7 is used to chemically corrode the cross-section of the silicon carbide integrated circuit wafer, revealing the morphological characteristics of the PN well at the cross-section, and at the same time avoiding the pungent smell of the traditional PN well staining solution; the ion milling method is used to prepare the sample, improving the problems of wafer delamination and breakage during the sample preparation process, and realizing the morphological characterization of the PN well of the integrated circuit wafer based on the new material SiC. This method is simple, economical, efficient, has a good staining effect, the source region boundary of the PN well is clear, and the morphological characteristics are obvious, which can help the subsequent evaluation and failure analysis of SiC integrated circuit devices. Description of the Drawings
[0017] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:
[0018] Figure 1 It is a schematic diagram of a PN well in a SiC structure.
[0019] Figure 2 It is a schematic diagram of the steps of a method for characterizing the PN well morphology of an integrated circuit wafer based on silicon carbide provided by an embodiment of the present invention.
[0020] Figure 3 It is an effect diagram of cross-section sample preparation in an embodiment of the present invention.
[0021] Figure 4 It is an effect diagram of cross-section staining observed by SEM in an embodiment of the present invention. Detailed implementation manners
[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts shall fall within the protection scope of the present invention.
[0023] The general idea of the present invention is as follows: In view of the corrosion resistance of SiC materials, a high-concentration HNO3 is used to prepare the staining solution. At the same time, CH3COOH in the staining solution in the traditional solution is replaced with C6H8O7 (citric acid) which has stronger acidity and no pungent smell. In addition, the ion milling method is used to prepare the sample to avoid problems such as scratches, dirt, and metal extension caused by stress in mechanical milling.
[0024] The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings of the specification. It should be understood that the embodiments described herein are only used to illustrate and explain the present invention and are not used to limit the present invention.
[0025] The present invention is applicable to the characterization of the PN well morphology of an integrated circuit wafer based on silicon carbide. The integrated circuit wafer based on silicon carbide refers to an integrated circuit device made of SiC semiconductor materials, in contrast to traditional silicon-based integrated circuit devices.
[0026] Figure 2 It is a schematic diagram of the steps of a method for characterizing the PN well morphology of an integrated circuit wafer based on silicon carbide provided by an embodiment of the present invention. As Figure 2 shown, an embodiment of the present invention provides a method for characterizing the PN well morphology of an integrated circuit wafer based on silicon carbide, and the method includes the following steps:
[0027] Step S1, preparing a silicon carbide integrated circuit wafer sample by using the ion milling method;
[0028] The specific method for preparing a silicon carbide integrated circuit wafer sample that requires PN well morphology characterization by ion milling is as follows: Physically bombard the sample with an argon ion beam to grind the silicon carbide integrated circuit wafer to be tested to the position of the cross-section to be stained.
[0029] In the embodiment of the present invention, in step S2, the sample preparation uses the method of ion milling. Ion milling is a high-precision surface processing technology that uses a high-energy ion beam to damage and remove material on the surface, thereby achieving fine processing of the surface. Ion milling is carried out in a vacuum environment. After the low-pressure inert gas in the ion gun is ionized, it is accelerated by an electric field and bombards the sample surface. Thus, a smooth sample surface in the millimeter range is prepared. Ar (argon) belongs to inert gas and basically does not chemically react with the sample. Therefore, Ar is commonly used as the ion source for ion milling. During the ion milling process, there is almost no stress, and there is no residue such as grinding debris in the vacuum environment, and problems such as sample deformation and oxidation will not occur. In the embodiment of the present invention, physical bombardment with an argon ion beam is used to cut and surface polish the silicon carbide integrated circuit wafer, ensuring the flatness and clarity between the wafer metal and the substrate material at the cross-section, and avoiding problems such as scratches, dirt, and metal extension caused by stress in mechanical grinding, thereby achieving the purpose of cross-section cutting and grinding for sample preparation.
[0030] For silicon carbide integrated circuit wafers, due to their hardness and excellent thermal stability, the thickness and size of their general chip products are smaller than those of silicon-based chips, and the wafer structure is also more delicate. Traditional mechanical grinding methods are likely to cause chip breakage or excessive grinding. The argon ion milling and polishing cross-section polishing instrument can be used to prepare materials with different hardnesses, while mechanical grinding and polishing can only be used to prepare samples with uniform hardness. Therefore, ion milling is a more suitable sample preparation method for SiC.
[0031] In the embodiment of the present invention, a PECSII MODEL685 ion cutting-polishing instrument is used. The ion gun angle is set to 0°, and the ion gun beam energy is set to the maximum energy value of 8 kev, that is, cutting is carried out using the Ar ion beam with the maximum energy on the front of the ion gun. The grinding time is 1-2 hours, which is more efficient than using FIB for ion cutting. As Figure 3 shown is the cross-section sample preparation effect diagram of the embodiment of the present invention.
[0032] Step S2: Select HNO3 with a concentration of 98%, HF with a concentration of 40%, and C6H8O7 with a concentration of 30% to prepare the staining solution;
[0033] The volume ratio of HNO3, HF, and C6H8O7 is HNO3:HF:C6H8O7 = 50:1:5-10. After preparing the staining solution according to the volume ratio, mix the staining solution thoroughly. The shelf life of the staining solution is 2 hours.
[0034] In the embodiments of the present invention, the volume ratio of HNO3, HF, and C6H8O7 is HNO3:HF:C6H8O7 = 50:1:5. After pouring HNO3, HF, and C6H8O7 into a container according to the volume ratio, stir the solution to make the components in the solution mix evenly. To avoid the volatilization of concentrated nitric acid over time, which may affect the staining effect, it is recommended to use up the prepared staining solution within 2 hours.
[0035] To ensure the uniform distribution of the staining agent on the surface of the sample and avoid the occurrence of color spots or uneven colors, it is necessary to mix the components in the staining solution evenly by means of stirring or the like.
[0036] For the traditional PN well staining of silicon-based materials, nitric acid with a relatively low concentration is generally used for preparation. In the embodiments of the present invention, considering the corrosion resistance characteristics of SiC materials, the staining solution prepared with nitric acid at a relatively low concentration cannot corrode SiC materials, so it cannot play a staining role and cannot reveal the morphological characteristics of the PN well. Therefore, in the embodiments of the present invention, a concentrated nitric acid is used to prepare the staining solution. The strong oxidizing property of the concentrated nitric acid oxidizes SiC at the cross-section to generate SiO2, and the corresponding chemical reaction formula is: SiC + 8HNO3 (concentrated) → CO2 + SiO2 + 8NO2 + 4H2O. HF has good complexing properties and can react with SiO2 at a relatively low temperature. The corresponding chemical reaction formula is: SiO2 + 4HF → SiF4 + 2H2O. The mixed solution of concentrated nitric acid and hydrofluoric acid can achieve the chemical etching effect on the cross-section of the silicon carbide integrated circuit wafer. The SiC substrate is doped to present P and N well regions. Different doping concentrations result in different potential differences at the PN well, making the corrosion rates of the mixed solution of concentrated nitric acid and hydrofluoric acid inconsistent, so that the morphology of the PN well at the cross-section can be revealed. In the silicon-based staining method, acetic acid is used to slow down the reaction rate to facilitate the control of the staining time. In the embodiments of the present invention, traditional acetic acid is replaced with citric acid. As shown in the reaction formula C6H8O7 → C6H5O7 + H+, the hydrogen ions generated after the ionization of citric acid can reduce the ionization degree of concentrated nitric acid in the mixed solution, thereby weakening the strong oxidizing property of concentrated nitric acid and slowing down the reaction rate. As a weak acid, citric acid is stronger in acidity than acetic acid and has no pungent odor, which can better meet the staining requirements of SiC.
[0037] Citric acid is used to adjust the reaction rate, and its proportion can be appropriately adjusted. If there is too much citric acid, too many hydrogen ions ionized from citric acid will seriously affect the strong oxidizing property of concentrated nitric acid, thereby affecting the staining effect. The recommended volume ratio of HNO3, HF, and C6H8O7 is HNO3:HF:C6H8O7 = 50:1:5 - 10.
[0038] Step S3: Immerse the cross-section of the prepared silicon carbide integrated circuit wafer sample in the prepared staining solution for staining, then take out the sample, rinse it with deionized water, and dry it.
[0039] After dyeing the cross-section of the prepared silicon carbide integrated circuit wafer, the PN well profile can be obtained for observing the PN well size and diffusion condition of the wafer.
[0040] The specific dyeing time is related to the cross-section size of the prepared silicon carbide integrated circuit wafer sample. The larger the cross-section, the longer the required dyeing time. The preferred dyeing time is 15 seconds to 30 seconds.
[0041] It is rinsed with deionized water, and the rinsing time is not less than 30 seconds.
[0042] In the embodiment of the present invention, the immersion time of the sample prepared in step S3 in the configured dyeing solution is 20 seconds. During the immersion process, it should be ensured that the cross-section to be dyed is completely immersed in the dyeing solution. For safety, the upper part of the sample to be dyed can be clamped with tweezers and then immersed in the dyeing solution. The PN well size is usually at the micron level, and the single dyeing time is similar. The larger the cross-section, the more the number of PN wells. In practical applications, the dyeing time is appropriately adjusted according to the size of the sample cross-section. 15 seconds to 30 seconds is the preferred dyeing time. If the dyeing time is insufficient, the dyeing interface is likely to be unclear. If the dyeing time is too long, over-dyeing is likely to occur, and the entire cross-section is completely dyed. During the actual operation process, it is necessary to repeatedly test according to the cross-section size and dyeing effect to select the most suitable dyeing time.
[0043] After dyeing is completed, it is immediately rinsed with deionized water. It is recommended to rinse for at least 30 seconds. Rinsing can remove the acid and dirt remaining on the cross-section, avoid further corrosion by the remaining acid, and is beneficial to subsequent cross-section observation.
[0044] Step S4, the cross-section of the dried silicon carbide integrated circuit wafer sample after dyeing is observed and measured by SEM (Scanning Electron Microscope). At this time, the cross-section morphology and depth of the PN well of the silicon carbide integrated circuit wafer can be inspected and measured. As Figure 4 shown is the cross-section dyeing effect diagram observed by SEM in the embodiment of the present invention.
[0045] Using SEM, a high-resolution image at the nanometer level of the cross-section of the silicon carbide integrated circuit wafer can be obtained. From the image, the morphological features of the PN well, such as the boundary, shape, size, steepness of the well edge, surface roughness, etc., can be clearly observed or measured.
[0046] Due to the corrosion resistance of SiC materials, the staining solution prepared with medium-concentration HNO3 for pure silicon-based integrated circuit wafers cannot chemically corrode SiC materials, so it cannot stain the PN well and cannot reveal the morphological characteristics of the PN well. The technical solution of the present invention uses high-concentration HNO3 to prepare the staining solution. The high-concentration HNO3 is combined with HF to achieve the purpose of chemical etching of the cross-section of the silicon carbide integrated circuit wafer, achieving a staining effect. At the same time, CH3COOH in the traditional staining solution is replaced with C6H8O7, which has stronger acidity and no pungent smell. In addition, in view of the differences in the lattice structure, size, hardness, etc. between SiC integrated circuit wafers and pure silicon-based integrated circuit wafers, the ion milling method is used to prepare samples to avoid problems such as scratches, dirt, and metal elongation caused by stress in mechanical milling. The prepared samples are placed in the staining solution for staining, then rinsed with deionized water and dried, and the stained cross-section can be observed and measured by SEM. Using the technical solution of the present invention, the staining solution prepared with high-concentration HNO3, HF, and C6H8O7 chemically etches the cross-section of the silicon carbide integrated circuit wafer, revealing the morphological characteristics of the PN well at the cross-section, and at the same time avoiding the pungent smell of the traditional PN well staining solution; using the ion milling method to prepare samples improves the problems of wafer delamination and breakage during the sample preparation process, and realizes the morphological characterization of the PN well of the integrated circuit wafer based on the new material SiC. This method is simple, economical, efficient, has a good staining effect, the source region boundary of the PN well is clear, and the morphological characteristics are obvious, which can help the subsequent evaluation and failure analysis of SiC integrated circuit devices.
[0047] The above are only specific embodiments of the present invention and cannot be used to limit the scope of the present invention. Equivalent changes made by those of ordinary skill in the art according to this creation, as well as changes well-known to those skilled in the art, should still fall within the scope covered by the present invention.
Claims
1. A method for characterizing the PN well morphology of a silicon carbide-based integrated circuit wafer, the method comprising the following steps: Step S1, preparing a silicon carbide integrated circuit wafer sample by ion milling; Step S2, preparing a staining solution by using HNO3 with a concentration of 98%, HF with a concentration of 40%, and C6H8O7 with a concentration of 30%; Step S3, immersing the cross-section of the prepared silicon carbide integrated circuit wafer sample into the prepared staining solution for staining, then taking out the sample, rinsing it with deionized water and drying it; Step S4, observing and measuring the morphology of the cross-section of the dried silicon carbide integrated circuit wafer sample after staining by SEM.
2. The method for characterizing the PN well topography of a silicon carbide-based integrated circuit wafer according to claim 1, wherein In step S2, the volume ratio of HNO3, HF, and C6H8O7 is HNO3:HF:C6H8O7 = 50:1:5 - 10.
3. The method for characterizing the PN well topography of a silicon carbide-based integrated circuit wafer according to claim 2, wherein In step S2, after preparing the staining solution according to the volume ratio, mix the staining solution thoroughly. The shelf life of the staining solution is 2 hours.
4. The method for characterizing the PN well topography of a silicon carbide-based integrated circuit wafer according to claim 1, wherein In step S1, the specific method for preparing the silicon carbide integrated circuit wafer sample to be characterized for the PN well morphology by ion milling is: physically bombarding the sample with an argon ion beam and grinding the silicon carbide integrated circuit wafer to be tested to the position of the cross-section to be stained.
5. The method for characterizing the PN well topography of a silicon carbide-based integrated circuit wafer according to claim 1, characterized in that, In step S3, when immersing the cross-section of the prepared silicon carbide integrated circuit wafer sample into the prepared staining solution for staining, the specific staining time is related to the size of the cross-section of the prepared silicon carbide integrated circuit wafer sample. The larger the cross-section, the longer the required staining time. The preferred staining time is 15 seconds - 30 seconds.
6. The method for characterizing the PN well topography of a silicon carbide-based integrated circuit wafer according to claim 1, wherein, In step S3, when rinsing with deionized water, the rinsing time is not less than 30 seconds.