Continuous high-precision pulse width measurement method and system based on high-speed serdes

Abstract

The invention discloses a continuous high-precision pulse width measurement method and system based on a high-speed serdes, and relates to the technical field of electronic measurement, and the method comprises the steps: S1, transmitting a matching calibration signal; s2, a calibration signal is selected and copied; s3, setting an initial delay value; s4, receiving the data and performing template comparison to complete initial calibration; s5, setting phase offsets of a plurality of links; s6, carrying out delay adjustment on the link; s7, carrying out precise delay calibration on link data; s8, analyzing the measurement precision; s9, selecting and copying a tested signal; s10, carrying out parallel interleaving sampling to output sampling data; s11, calculating a pulse width value; s12, calculating a compensated pulse width value according to the compensation coefficient; through the method, the time resolution is less than or equal to 10ps, and the maximum throughput rate is greater than 300M event / s; channel expansion is supported, and the interleaving sampling rate is improved; and a time delay chip with higher resolution can be used as a time delay adjusting module, so that the performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic measurement technologies, and particularly to a continuous high-precision pulse width measurement method and system based on high-speed SerDes. Background Art

[0002] In many application scenarios, such as laser ranging, particle physics experiments, communication signal processing, etc., high requirements are imposed on the accuracy and continuity of time measurement. Traditional time measurement methods mainly rely on time-to-digital converters (TDCs) or high-speed analog-to-digital converters (ADCs) for sampling, and have the following limitations:

[0003] 1. Commercial TDC chips have a limited number of channels, making it difficult to achieve multi-channel parallel measurement;

[0004] 2. The sampling rate of ADCs is limited by device technology, and the sampling rate is usually less than 10 GSps, resulting in insufficient time resolution;

[0005] 3. Existing interleaved sampling schemes require complex clock tree designs, resulting in poor system stability;

[0006] 4. There is a dead time during continuous measurement, making it impossible to capture high-frequency events and continuously acquire multiple pulse signals;

[0007] 5. Some implementation methods using carry chains in field-programmable gate arrays (FPGAs) to implement delay taps have low accuracy and are difficult to calibrate due to differences in layout and wiring during programmable device implementation, making it difficult to apply in practical scenarios. Summary of the Invention

[0008] The object of the present invention is to design a continuous high-precision pulse width measurement method and system based on high-speed SerDes to solve the above problems.

[0009] The present invention achieves the above object through the following technical solutions:

[0010] A continuous high-precision pulse width measurement method based on high-speed SerDes, comprising:

[0011] S1. The serializer / deserializer (SerDes) transmitter at the sending end circularly sends a characteristic template pattern;

[0012] S2. The selection module selects a calibration signal as the input signal, and the fan-out driver module copies the input signal to obtain signals on multiple links;

[0013] S3. The multi-channel interleaved calibration module adjusts and sets the initial delay value of each link , the initial delay value of each link is the same value, and the delay adjustment module adjusts the signals of multiple links according to the initial delay value of each link;

[0014] S4. The serial deserializer SerDes receiver receives data, and the received data is the signals after delay adjustment of each link. The multi-channel interleaving calibration module analyzes the received data and compares it with the feature template pattern to obtain the initial delay setting at which the receiver of the delay adjustment module of each link can stably receive data , , , … , and complete the initial calibration;

[0015] S5. Set the phase offset of multiple links. The phase offset is the sampling period Tclk / N, where N is the total number of links;

[0016] S6. Adjust the delay of each link through the delay adjustment module so that the sampling points of each link are evenly distributed, obtain the unit interval UI, and determine the arrangement order of the signals of each link;

[0017] S7. Using the phase adjustment algorithm, the delay adjustment module performs precise delay calibration on the data of each link according to the phase offset;

[0018] S8. Using the frequency offset adjustment algorithm, analyze the measurement accuracy of the sampling data sampled by the serial deserializer SerDes receiver;

[0019] S9. The selection module selects the signal under test as the input signal, and the fan-out drive module copies the input signal to obtain the signals of multiple links;

[0020] S10. Multiple serial deserializer SerDes receivers perform parallel interleaved sampling on the signals of multiple links and output the sampling data. The temperature collector collects the working temperature of the system;

[0021] S11. The multi-parallel pulse width time measurement module extracts the pulse signal of the sampling data through the edge processing circuit and calculates the pulse width value through the parallel summation circuit;

[0022] S12. Determine the compensation coefficient at the working temperature and calculate the compensated pulse width value according to the compensation coefficient.

[0023] A continuous high-precision pulse width measurement system based on high-speed serdes, comprising:

[0024] At least two input modules; the input module is used for inputting calibration signals or signals under test;

[0025] Selection module: The selection module is used to select a signal input by an input module;

[0026] The fan-out driving module is used to copy the input signal into signals of multiple links, and the signal output end of the selection module is connected to the signal input end of the fan-out driving module;

[0027] Multiple delay adjustment modules; one delay adjustment module is used for delay adjustment of a link signal.

[0028] The signal output terminals of the fan-out driving module are respectively connected to the signal input terminals of the multi-channel delay adjustment modules;

[0029] Temperature measurement module: The temperature measurement module is used to detect the temperature of the working environment of the measurement system;

[0030] FPGA chip; the signal output ends of the multiple delay adjustment modules and the signal output ends of the temperature measurement module are connected to the signal input end of the FPGA chip, the FPGA chip is provided with a serial deserializer SerDes, and the serial deserializer SerDes sending end is used to send a calibration signal to the input module;

[0031] Storage module; the storage module stores temperature compensation data;

[0032] FPGA chips include:

[0033] Multiple serial deserializers SerDes; the multi-channel parallel signals after delay conditioning are respectively connected to the receiving ends of the multiple parallel serial deserializers SerDes to sample and obtain sampled data;

[0034] A first-in-first-out data buffer FIFO; the data buffer FIFO is used to perform synchronous clock processing on the sampled data;

[0035] Multi-channel interleaving calibration module: The multi-channel interleaving calibration module determines the sampling phase of each sampling data after synchronization according to the multi-channel interleaving algorithm, and evenly distributes the sampling clock phases of multiple serial deserializer SerDes receiving ends within a sampling period through the phase adjustment function of the serial deserializer SerDes receiving end and the delay setting of each link. After the calibration is completed, the multi-parallel quantized data stream of interleaved sampling is output;

[0036] Multi-parallel pulse width time measurement module; The multi-parallel pulse width time measurement module performs high-precision pulse width time calculation on multi-parallel quantized data streams through a pulse width retrieval circuit.

[0037] The beneficial effects of the present invention are as follows: By means of this method, a time resolution of ≤10 ps and a maximum throughput rate of >300 M event / s can be achieved; support for channel expansion to improve the interleaved sampling rate: the performance can be linearly improved by using a delay chip with higher resolution as the delay adjustment module and increasing the number of parallel Serdes; seamless acquisition of zero dead zone continuous measurement is realized by utilizing the inherent serial-to-parallel conversion structure of the serializer / deserializer (Serdes); it has a system self-calibration function and can achieve self-calibration of system accuracy; multi-channel parallelism can be carried out: the selected devices and peripheral circuits are simple, the volume is small, and high-precision multi-channel parallel acquisition can be carried out. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is the architecture block diagram of a continuous high-precision pulse width measurement system based on high-speed serdes;

[0039] Figure 2 is the hardware circuit block diagram;

[0040] Figure 3 is the calibration algorithm flow chart;

[0041] Figure 4 is the multi-channel interleaved sampling relationship diagram;

[0042] Figure 5 is the phase adjustment diagram of multi-channel interleaved sampling;

[0043] Figure 6 is the temperature calibration compensation diagram;

[0044] Figure 7 is the propagation delay schematic diagram;

[0045] Figure 8 is the sampling schematic diagram of the interleaved sampling channel;

[0046] Figure 9 is the schematic diagram of data segmentation;

[0047] Figure 10 is the schematic diagram of measurement accuracy analysis; DETAILED DESCRIPTION OF THE EMBODIMENTS

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and illustrated in the drawings here can be arranged and designed in various different configurations.

[0049] Accordingly, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0050] It should be noted that like reference numerals and letters denote like items in the following figures, and thus, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0051] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "inner", "outer", "left", "right", etc. is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the inventive product is customarily placed during use, or the orientation or positional relationship commonly understood by those skilled in the art. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0052] In the description of the present invention, it should also be noted that unless otherwise clearly defined and limited, terms such as "set" and "connect" should be understood in a broad sense. For example, "connect" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0053] The following will describe in detail the specific embodiments of the present invention with reference to the accompanying drawings.

[0054] A continuous high-precision pulse width measurement method based on high-speed SerDes includes:

[0055] S1. The serial deserializer SerDes transmitter cyclically transmits a matching calibration signal as a feature template pattern; the pulse start feature of the feature template pattern satisfies a time relationship, and the time relationship is expressed as: , where is the period of the feature template pattern, is the propagation delay of the signal, including the data reception inside the FPGA chip from the input of the calibration signal; after the input feature template pattern is synchronously sent to the receiving end of the multi-channel serial deserializer SerDes in the FPGA chip, the receiving ends of each link can sample and align the same pulse edge to prevent the received data from deviating from the period during alignment due to the too small signal period. By controlling the pulse width of the calibration signal, it can be verified whether the pulse widths of the receiving ends of each link are correct.

[0056] At the sending end of the serial deserializer SerDes, data is sent according to a certain feature encoding, and the feature encoding needs to have a pulse start feature and meet the duration requirements of the above sampling delay. In the design, a total of 128-bit hexadecimal data: FF55AA00_00000000_00000000_00000000 is used as the matching encoding pattern, and the sending end circularly sends this feature encoding as the feature template pattern.

[0057] S2. The selection module selects the calibration signal as the input signal, controls the sending end of the serial deserializer SerDes in the FPGA chip, and sends out a pulse signal with a known period and pulse width. The fan-out driving module copies the input signal to obtain signals for multiple links.

[0058] S3. The multi-channel interleaved calibration module adjusts and sets the initial delay value of each link , the initial delay value of each link is the same value, and the delay adjustment module adjusts the signals of multiple links according to the initial delay value of each link; when returning from S404 to S3, the multi-channel interleaved calibration module adjusts the initial delay value of each link according to the minimum adjustment step value of the delay adjustment module , and the adjustment range is 0 to the sampling period. For example, if the sampling rate of each link is 25 Gsps, the adjustment range is from the initial value to the initial value + 40 ps.

[0059] S4. The receiving end of the serial deserializer SerDes receives data, and the received data is the signals of each link after delay adjustment. The multi-channel interleaved calibration module analyzes the received data and compares it with the feature template pattern to obtain the initial delay setting at which the receiving end of the delay adjustment module of each link can stably receive data 、 、 、… , and the initial calibration is completed; specifically including:

[0060] S401. The receiving end of the serial deserializer SerDes receives data;

[0061] S402. The multi-channel interleaved calibration module shifts the data under the main clock of the serial deserializer SerDes;

[0062] S403. Compare the acquired data under each data master clock. If a data rising edge appears, determine whether the 128-bit received data starting from the current beat is consistent with the feature template pattern. If it is consistent, the matching is successful, output the matching success status of each link, and enter S405; otherwise, set m = m + 1 and enter S404, where m is a positive integer.

[0063] S404. Determine whether m is greater than the preset number of loop times. If it is, return to S3; otherwise, perform bitslip on the data and return to S401. The preset number of loop times is 128 times.

[0064] S405. Record the link delay settings at which each link can stably receive the feature template pattern during the adjustment process, and take the intermediate delay value that each link can stably match as the initial delay setting for each link. 、 、 、… to complete the initial calibration. It can be considered that the different propagation delays of all links have been aligned through the adjustment of the initial delay settings, as Figure 7 shown.

[0065] S5. Set the phase offset of N links. The phase offset is the sampling period Tclk / N, where N is the total number of links. The sampling rate of each link is 25 Gsps. When N is 4, the corresponding offset is 10 ps.

[0066] S6. The delay adjustment module performs delay adjustment on each link through the digital control and voltage control of the delay line, so that the sampling points of each link are evenly distributed to obtain a unit interval UI of 10 ps, as Figure 8 shown. The parallel output of the multi-channel serial deserializer SerDes receiver is an interleaved sampled data frame, and the arrangement order of the multi-channel data is determined according to the delay setting relationship of each link.

[0067] S7. Using the phase adjustment algorithm, the delay adjustment module performs precise delay calibration on the data of each link according to the phase offset. Specifically, it includes:

[0068] S701. Adjust the transmission clock phase of the serial deserializer SerDes transmitter according to the phase offset to obtain a calibration signal with a fixed frequency and continuously changing phase delay. Specifically: The TXPIPPM controller for serial deserializer SerDes phase adjustment can be used to manually adjust the transmit phase interpolation PI controller of the serial deserializer SerDes transmitter, and can establish a controllable phase relationship between the reference clock and the output of the transmitter of the GTH transceiver. Determine whether the transmit end TX phase is advanced or retracted by setting the register port TXPIPPMSTEPSIZE, and then adjust TXPIPPMSTEPSIZE [3:0] according to the formula to obtain an appropriate step size. , which is expressed as: ; In this mode, TXPIPPMEN should generate pulses for two TXUSRCLK cycles, so that the phase interpolation controller steps one level; TXPIPPMSTEPSIZE [3:0] is a settable phase stepping control value set to 8, and TXOUT_DIV is the clock division coefficient. TXOUT_DIV can be set to 1, 2, 4, 8, 16. Here it is 16, and the obtained STEP_SIZE (UI) is 2.8125°. After 32 steps, a 90° delay is generated for data transmission.

[0069] S702. The receiver of the serial deserializer SerDes performs parallel interleaved sampling and outputs sampled data.

[0070] S703. Among the parallel interleaved sampled data obtained by the receiver of the serial deserializer SerDes, the rising edge is expected to shift from the first sampling point in the parallel link to the second sampling point. Determine whether the sampled data is correct. If not, adjust it through the analog delay fine-tuning terminal of the delay adjustment module to ensure that the delay phase is within the range of 90° ± 45°, and realize the calibration parameters of the delay of each link.

[0071] S8. Use the frequency offset adjustment algorithm to analyze the measurement accuracy of the sampled data sampled by the receiver of the serial deserializer SerDes. Specifically, it includes:

[0072] S801. The transmitter of the serial deserializer SerDes changes the frequency offset of the transmission clock through frequency offset adjustment to obtain a standard signal with periodic changes. Specifically: Control the output of the transmitter TX of the serial deserializer SerDes to operate at a frequency with a fixed parts per million ppm offset from the reference clock, and use the continuous PI code update mode to change the output clock period. As Figure 10 shown in the application scenario of frequency adjustment: Data may be received at a certain frequency and then retransmitted at a different frequency without the need for an additional external clock source;

[0073] The frequency offset can be generated by the following operations: Set TXPIPPMSTEPSIZE[4] = 1 to adjust in the increasing mode, set TXPIPPMSTEPSIZE[4] = 0 to decrement the counter, and set TXPIPPMSTEPSIZE[3:0] according to the formula to determine the required offset. , which is expressed as: ; where TXOUT_DIV can be set to 1, 2, 4, 8, 16, TXPI_SYNFREQ_PPM can be set from 1 to 7, and TXPIPPMSTEPSIZE can be set from 0 to 15;

[0074] By changing the transmission clock frequency offset of the transmitter of the serial deserializer SerDes, a calibration signal with periodic variation is obtained;

[0075] S802. At a certain frequency, the pulse widths of multiple interleaved samplings are statistically analyzed to obtain an analysis curve; the specific analysis of the measurement results is as follows: Find the maximum and minimum values, calculate the maximum deviation; calculate the root mean square value and find the difference from the TX signal at the transmitter. Use the linearly increasing TX input pulse width at the transmitter as the horizontal axis and record the corresponding measurement results as the vertical axis to obtain the corresponding measurement result analysis curve.

[0076] The temperature error compensation is specifically as follows:

[0077] After completing the above measurement accuracy calculation, change the ambient temperature of the system operation, obtain the corresponding system operating temperature through a temperature measuring device, and draw an error-temperature curve with temperature as the horizontal axis and measurement deviation as the vertical axis, as Figure 6 shown. Obtain the measurement error compensation values at different temperatures through the measurement deviations at different temperatures and store them in the system. When the system is operating, obtain the operating temperature in real time, query the corresponding compensation coefficient, and perform temperature compensation.

[0078] The system operating temperature range is 0 to 40 °C, and temperature calibration is performed per degree Celsius. Place the system in a constant temperature test chamber, set the corresponding operating temperature Temp, after completing warm-up and temperature equilibrium, control the system to enter the calibration mode, output a calibration signal with a known pulse width Tcal, obtain the system measurement result Tmea, after 1000 measurements, take the root mean square value of the results to get Tmea_rms, then the error compensation value under this condition Temp is Temp_com = Tcal - Tmea_rms;

[0079] Perform piecewise linear fitting on the compensation values at the corresponding temperatures. When measuring the pulse width, add the corresponding error compensation value to the original measurement value to obtain the corrected measurement result.

[0080] S9. The selection module selects the signal under test as the input signal, and the fan-out driving module copies the input signal to obtain signals for multiple links;

[0081] S10. Multiple serial deserializer (SerDes) receivers perform parallel interleaved sampling on the signals of multiple links, output the sampled data, and determine the arrangement order of the multiplexed sampled data according to the delay setting relationship of each link. The temperature collector collects the operating temperature of the system;

[0082] S11. The multi-parallel pulse width time measurement module extracts the pulse signal of the sampled data through the edge processing circuit. After data segmentation of the interleaved sampled signals, as Figure 9 shown, and calculates the pulse width value through the parallel summation circuit; specifically including:

[0083] S1101. Extract the pulse signal of the interleaved sampled signal through the edge processing circuit;

[0084] S1102. Divide the pulse signal into multiple groups of data, and retain the last 1 bit of data of the previous group in each group of data; Data segmentation is to reduce the difficulty of data processing, reduce the number of logic processing levels, and reduce the timing implementation risk brought by the multi-carry chain. The parallel large-bitwidth sampled data is divided into multiple groups of data with each bitwidth not exceeding 16 bits. At the same time, in order to process the decision of the first pulse of each group, it is necessary to retain the last 1 bit of data of the previous group in each data group to determine the accurate position of the pulse start.

[0085] S1103. Distinguish whether each group of data is in the rising edge state or the falling edge state; specifically: Judge the adjacent two values in each group of data. If the sampling values are in the order of 0-1, it is considered a rising edge; if the sampling values are in the order of 1-0, it is considered a falling edge. Set each bit according to the judgment position to obtain the rising edge state and the falling edge state of each group of 16 bits.

[0086] S1104. Perform bitwise summation on the rising edge states of the preset number of groups to obtain the total number Rise_sum of clock rising edges; perform bitwise summation on the falling edge states of the preset number of groups to obtain the total number Fall_sum of clock falling edges; The preset number of groups is 20 groups; The statistical results are shown in Table 1;

[0087] S1105. Analyze the pulse width according to the total number of clock rising edges and the total number of clock falling edges; specifically:

[0088] As shown in Table 1, set the positive pulse width counter pos_pulse_cnt and the negative pulse width counter neg_pulse_cnt;

[0089] Serial number 1: When the total number of clock rising edges Rise_sum and the total number of clock falling edges Fall_sum are both 0, when the signal is all 1, increment the positive pulse width counter pos_pulse_cnt by 1, and when the signal is all 0, increment the negative pulse width counter neg_pulse_cnt by 1;

[0090] Serial number 2: When the total number of clock rising edges Rise_sum is 0 and the total number of clock falling edges Fall_sum is 1, map the corresponding positive and negative pulse width values according to the determined falling edge one-hot code, sum them with the corresponding positive and negative pulse width counters to obtain the corresponding pulse width;

[0091] Serial number 3: When the total number of clock rising edges Rise_sum is 1 and the total number of clock falling edges Fall_sum is 0, map the corresponding positive and negative pulse width values according to the determined rising edge one-hot code, sum them with the corresponding positive and negative pulse width counters to obtain the corresponding pulse width;

[0092] Serial number 4: When the total number of clock rising edges Rise_sum and the total number of clock falling edges Fall_sum are both 1, make a judgment according to the sequence of the rising edge and the falling edge. If the rising edge is in front, it is the positive pulse width, and use the falling edge position minus the rising edge position to obtain the corresponding positive pulse width output; if the falling edge is in front, it is the negative pulse width, and use the rising edge position minus the falling edge position to obtain the corresponding negative pulse width output;

[0093] Serial number 5: When the total number of clock rising edges Rise_sum is 2 and the total number of clock falling edges Fall_sum is 1, store the corresponding acquisition code value and the corresponding sampling moment in the data buffer FIFO, and at the same time record the position of the second rising edge, and cooperate with the subsequent positive pulse width counter pos_pulse_cnt to calculate the positive pulse width length;

[0094] Serial number 6: When the total number of clock rising edges Rise_sum is 1 and the total number of clock falling edges Fall_sum is 2, store the corresponding acquisition code value and the corresponding sampling moment in the data buffer FIFO, and at the same time record the position of the second falling edge, and cooperate with the subsequent negative pulse width counter neg_pulse_cnt to calculate the negative pulse width length;

[0095] Serial number 7: When the total number of clock rising edges Rise_sum and the total number of clock falling edges Fall_sum are both greater than or equal to 2, store the corresponding acquisition code value and the corresponding sampling moment in the data buffer FIFO;

[0096] By adding an offset to each set of parallel data, the specific positions of the corresponding rising and falling edges in the parallel data are obtained; when there is only one pulse within each FPGA main clock cycle, or when the pulse period is greater than the FPGA main clock cycle, the corresponding pulse width measurement results can be obtained at each clock; if there are multiple pulse periods within each FPGA main clock cycle, the data buffer FIFO can be read channel by channel for analysis to obtain the width and corresponding occurrence time of each pulse. The analysis method is to read out the parallel data cached in the data buffer FIFO and perform serial conversion into 1-channel data, then judge the rising and falling edges of the data in the 1-channel data. By calculating the bit difference between the rising edge and the falling edge, the corresponding pulse width information can be obtained. When the FPGA main clock is 312.5 MHz, at least 1 pulse width measurement result can be obtained at each main clock, and the maximum throughput > 300M event / s.

[0097] S12. Determine the compensation coefficient at the working temperature and calculate the compensated pulse width value according to the compensation coefficient.

[0098] Table 1

[0099] Serial number Rise_sum value Fall_sum value Description 1 0 0 Data all 0 or all 1 2 0 1 Data falling edge 3 1 0 Data rising edge 4 1 1 According to the sequence judgment, positive pulse or negative pulse 5 2 1 Short positive pulse and long positive pulse 6 1 2 Short negative pulse and long negative pulse 7 ≥2 ≥2 Multiple positive / negative pulses

[0100] A continuous high-precision pulse width measurement system based on high-speed serdes, as Figure 1 、 Figure 2 shown, includes:

[0101] At least two input modules; the input modules are used for inputting calibration signals or signals to be measured;

[0102] A selection module; the selection module is used for selecting the signal input by one input module;

[0103] A fan-out driving module; the fan-out driving module is used for copying the input signal into signals of multiple links, and the signal output end of the selection module is connected to the signal input end of the fan-out driving module;

[0104] Multiple delay adjustment modules; one delay adjustment module is used for delay adjustment of the signal of one link,

[0105] The signal output ends of the fan-out driving module are respectively connected to the signal input ends of the multiple delay adjustment modules;

[0106] A temperature measurement module; the temperature measurement module is used for detecting the temperature of the working environment of the measurement system;

[0107] FPGA chip; the signal output ends of multiple delay adjustment modules and the signal output end of the temperature measurement module are all connected to the signal input end of the FPGA chip. The FPGA chip is provided with a serial deserializer SerDes, and the transmitter of the serial deserializer SerDes is used to send a calibration signal to the input module;

[0108] Storage module; temperature compensation data is stored in the storage module;

[0109] The FPGA chip includes:

[0110] Multiple serial deserializer SerDes; the multiplexed parallel signals after delay conditioning are respectively connected to the receivers of the multiplexed parallel serial deserializer SerDes for sampling to obtain sampling data;

[0111] Data buffer FIFO; the data buffer FIFO is used to perform synchronous clock processing on the sampling data;

[0112] Multiplexed interleaving calibration module; the multiplexed interleaving calibration module judges the sampling phases of the sampled data of each path after synchronization according to the multiplexed interleaving algorithm, and through the phase adjustment function of the transmitter of the serial deserializer SerDes and the adjustment of the time delay settings of each link, evenly distributes the sampling clock phases of the receivers of multiple serial deserializer SerDes within a sampling period. After calibration, an interleaved sampled multi-parallel quantization data stream is output;

[0113] Multi-parallel pulse width time measurement module; the multi-parallel pulse width time measurement module performs high-precision pulse width time calculation on the multi-parallel quantization data stream through a pulse width retrieval circuit.

[0114] The measurement system further includes an input buffer driver module. The input buffer driver module converts the single-ended input measured signal into a differential form through an ultra-wideband fixed-gain fully differential amplifier and adjusts the common-mode level of the output differential signal. The measured input signal can accept single-ended or differential forms. Passing the input signal through the ultra-wideband fixed-gain fully differential amplifier can convert the single-ended input signal into a differential form and adjust the common-mode level of the output differential signal. Utilizing the excellent bandwidth performance and low distortion characteristics of the device, the impedance of signal transmission is carried out, and the driving ability of the signal to the subsequent circuit is improved.

[0115] The calibration signal is generated using the transmitter Tx port of the high-speed serial deserializer SerDes built in the FPGA chip. The highest speed signal differential signal that can be generated is 32.75 Gbps, and DC coupling is supported. High and low pulse signals with different pulse widths can be generated through configuration, and the phase of the output signal can be finely adjusted through the clock phase adjustment function. And during the calibration process, output signals with different rates can be generated by adjusting the clock offset to generate a calibration signal to test the phase calibration of the multiplexed parallel.

[0116] The selection module uses a high-speed analog multiplexer to select the signal under test. During the calibration phase, the Tx signal of the serial deserializer SerDes is selected for the calibration of the multi-channel parallel system; during the measurement phase, the signal under test is selected for input calibration.

[0117] The fan-out driving module uses a multi-channel signal fan-out circuit and an ultra-low additional jitter differential clock buffer to perform multi-channel fan-out of signals, drive the subsequent stage of each channel delay adjustment circuit, and has an output level adjustment function, which can flexibly adapt to a variety of electrical standards. Its ultra-low jitter is at the fs level, which can avoid introducing large jitter errors to the entire measurement system and affecting the measurement accuracy of the system.

[0118] The delay adjustment module is a parallel multi-channel delay adjustment circuit, which uses a high-precision adjustable delay chip to accurately adjust the delay of each channel signal. This device has programmable step delay adjustment and continuous delay adjustment controlled by an analog voltage. Through step coarse adjustment and continuous fine adjustment, the delay of each line can be accurately controlled. Among them, the programming fine adjustment is realized by controlling the FPGA chip, and the analog voltage adjustment is realized by using a high-precision DAC with multi-channel output. The parallel multi-channel delay adjustment circuit is configured with a multi-channel interleaved calibration algorithm to achieve high-precision sampling phase adjustment, achieving the effect of uniform interleaving of the sampling moments of multi-channel signals. Accurately controlling the phase delay of multi-channel parallel signals is the key point to realize multi-channel interleaving to improve the system sampling rate and time resolution accuracy.

[0119] The FPGA chip completes the high-speed acquisition of each channel signal, the output of the calibration signal, the implementation of the multi-channel interleaved calibration algorithm, the sampling quantization of the signal under test, the pulse width calculation of high-resolution data, the error correction of the calculation result, control and communication. It is implemented by using an FPGA chip with a high-performance serial deserializer SerDes.

[0120] In the entire hardware design, power noise suppression, transmission line signal integrity control, and clock system accuracy are processed to reduce the jitter of the signal under test and improve the stability and accuracy of the system.

[0121] Strictly in accordance with the voltage range requirements in the device manual, the power supplies MGTAVCC, MGTAVTT, and MGTVCCAUX of the high-speed interface are powered by separate linear voltage regulators, controlling the power supply ripple to be less than 10mVpp, and using a capacitor combination of 4.7uF and 0.1uF for power supply decoupling and voltage stabilization.

[0122] The reference clock is transmitted using an AC coupling method. A 0.1uF capacitor is used for AC coupling to reduce the possibility of low-frequency noise coupling. The unused reference clock input terminals are connected to GND to reduce the impact of spatial electromagnetic interference on the clock quality. During PCB design, differential traces between each link ensure a spacing of more than three times, and vias are evenly and alternately distributed along the signal trace path to avoid the impact of adjacent line crosstalk on the signal edge.

[0123] A filter circuit is used at the output of the crystal oscillator to reduce the electromagnetic radiation of the crystal oscillator to the outside. A metal shielding cover is used to isolate the crystal oscillator circuit. A separate linear voltage regulator power supply is used for the power supply of the crystal oscillator to avoid noise interference coupling to other lines. A high-precision temperature-compensated crystal oscillator is used as the clock reference to ensure the clock accuracy of the system.

[0124] The number of peripheral circuits of the entire system is small. The core components include a driver, an analog multiplexer, a signal fan-out, a delay adjustment chip, and a core FPGA. The circuit design is simple and easy to use.

[0125] The process flow of the multi-channel interleaved sampling calibration algorithm:

[0126] In the design, the initial clock phase calibration of the sampling clock is carried out through the Figure 3 process shown:

[0127] Set the transmitter TX of the serializer / deserializer SerDes to send a matching calibration signal: Use the transmitter TX interface to output a signal with the encoded value of the feature template pattern. The period of the feature template pattern signal is the data clock period after serial-to-parallel conversion of the data at the receiver RX interface of the serializer / deserializer SerDes. For example, if the receiver RX interface of the serializer / deserializer SerDes serial-to-parallel converts the received 25Gbps data into a format of 80-bit data at 312.5MHz, then the period of the signal sent by the transmitter TX is 80 bits. And the minimum repetition period of the digital signal sent by the transmitter TX of the serializer / deserializer SerDes is 80 bits, that is, it shows a repetitive pattern every 80 bits.

[0128] The input selection is the calibration signal input of the transmitter TX: Select the calibration signal input for the subsequent calibration process.

[0129] Set the delay of each link to the same initial value: Set the delay values of each delay link to the same initial value. The setting of this delay value needs to be within a reasonable range so that the delay of each line can be adjusted within the range from the initial value to 5 sampling clock periods. For example, when the sampling rate of each link is 25Gbps, each link can be adjusted within 40ps×5, that is, within 200ps.

[0130] The receiving end RX receives data for feature template pattern matching: The receiving end RX of the serializer / deserializer SerDes is used to sample the data, and the sampled data is compared with the feature template pattern of the transmitted data. If the received data is different from the transmitted data, first adjust it by adjusting the data cyclic shift bitslip of the receiving end, and then compare it again after adjustment. If after a certain number of parallel path bitslips (such as 80 times), the feature template pattern comparison still fails, then adjust the delay of this line through step delay control. After adjusting the delay, repeat the comparison process. Since the transmitting end TX sends data at the same sampling rate under the same reference clock, under the condition that the hardware circuit works normally, after the receiving end RX adjusts the signal delay, it can correctly receive the corresponding feature template pattern. After completing the reception of the feature template pattern, it is necessary to continuously monitor a certain number of cycles to ensure the stable operation of the transmitting and receiving ends under a large amount of data. After completion, record the initial delay value of each line respectively.

[0131] Precise positioning of the multi-channel sampling phase: For each link, after stable sampling, the precise relationship between its sampling clock phase and the calibration signal cannot be confirmed. By increasing the delay of each link, the acquired sampling data can be shifted backward. Gradually increase the delay of each link. When the overall acquired sampling result is shifted backward by 1 bit, record the delay value dly_1bit at this time; continue to increase the delay. When the overall acquired sampling structure is shifted backward by 2 bits, record the delay value dly_2bit at this time; calculate the average value of dly_1bit and dly_2bit to obtain the starting delay value dly_start of the sampling, as Figure 4 shown.

[0132] Phase adjustment of multi-channel interleaved sampling: Calculate the corresponding sampling period Tsample according to the sampling rate Sample_lane of each link. According to the principle of multi-channel interleaved parallel sampling, calculate the phase adjustment delay value dly_phase_add that needs to be increased for each link. Add the phase adjustment delay value dly_phase_add to the sampling starting delay value dly_start of each link to obtain the delay value setting of this link. Update the corresponding delay value to each link, as Figure 5 shown.

[0133] Interleaved Sampling Result Verification: After setting the delay of interleaved sampling, it is also necessary to test and verify the interleaved sampling results. By adjusting the transmission clock frequency of the transmitter TX, corresponding frequency deviation settings are made to adjust the transmission data rate. The transmitter TX sends a signal with a fixed code. When the data rate changes, the corresponding high and low pulse times will change accordingly. When the transmission frequency decreases, the signal period becomes longer; when the transmission frequency increases, the signal period becomes shorter.

[0134] The relationship between the transmission frequency, signal period, and pulse width can be obtained through calculation.

[0135] By calculating the high and low pulse widths of the high-speed data stream obtained through interleaved sampling, the correctness of interleaved sampling can be verified.

[0136] Temperature Compensation Algorithm for Interleaved Sampling: When the operating temperature of the system changes, due to the temperature drift of the crystal oscillator frequency, the measurement of the system may drift accordingly. A temperature sensor is reserved in the design to obtain the operating temperature of the system in real time. By inputting a standard pulse width signal through an external constant-temperature high-stability crystal oscillator, the measurement results at different temperatures are fitted by the least squares method to obtain the corresponding temperature compensation coefficients, which are stored in a non-volatile storage device. When the system is operating, by reading the operating temperature in real time, the corresponding compensation coefficient is found, and the original result obtained by the FPGA chip is operated with the compensation coefficient to obtain the accurate compensated result.

[0137] The technical solution of the present invention is not limited to the limitations of the above specific embodiments. Any technical deformation made according to the technical solution of the present invention falls within the protection scope of the present invention.

Claims

1. A continuous high-precision pulse width measurement method based on high-speed SerDes, characterized in that, Including: S1. The serial deserializer SerDes transmitter cyclically transmits a matching calibration signal as a feature template pattern. S2. The selection module selects the calibration signal as the input signal, and the fan-out driver module copies the input signal to obtain signals for multiple links. S3. The multi-channel interleaved calibration module adjusts and sets the initial delay value of each link , and the initial delay value of each link is the same value. The delay adjustment module adjusts the signals of multiple links according to the initial delay value of each link; S4. The serial deserializer SerDes receiver receives data, where the received data is the signal after delay adjustment for each link. The multi-channel interleaving calibration module analyzes the received data and performs template comparison with the feature template pattern to obtain the initial delay setting at which the receiver of the delay adjustment module for each link can stably receive data. , , ,... , and the initial calibration is completed. S5. Set the phase offsets of multiple links, where the phase offset is the sampling period Tclk / N, and N is the total number of links. S6. Through the delay adjustment module, perform delay adjustment on each link so that the sampling points of each link are evenly distributed, obtain the unit interval UI, and determine the arrangement order of the signals of each link. S7. Using the phase adjustment algorithm, the delay adjustment module performs precise delay calibration on the data of each link according to the phase offset. S8. Using the frequency offset adjustment algorithm, perform measurement accuracy analysis on the sampled data sampled by the serial deserializer SerDes receiver. S9. The selection module selects the signal under test as the input signal, and the fan-out driver module copies the input signal to obtain signals for multiple links. S10. Multiple serial deserializer SerDes receivers perform parallel interleaved sampling on the signals of multiple links, output the sampled data, and the temperature collector collects the operating temperature of the system. S11. The multi-parallel pulse width time measurement module extracts the pulse signal of the sampled data through the edge processing circuit and calculates the pulse width value through the parallel summation circuit. S12. Determine the compensation coefficient at the operating temperature and calculate the compensated pulse width value according to the compensation coefficient.

2. The continuous high-precision pulse width measurement method based on high-speed serdes according to claim 1, characterized in that, In S1, the pulse start feature of the feature template pattern satisfies a time relationship, which is expressed as: , where is the period of the feature template pattern, is the propagation delay of the signal.

3. The continuous high-precision pulse width measurement method based on high-speed SerDes according to claim 1, characterized in that In S4, it includes: S401. The serial deserializer SerDes receiver receives data. S402. The multi-channel interleaved calibration module shifts the data under the main clock of the serial deserializer SerDes receiver. S403. Compare the acquired data under the main clock of each data. If a data rising edge appears, determine whether the received data starting from the current beat is consistent with the feature template pattern. If it is consistent, the matching is successful, output the matching success status of each link, and enter S405; otherwise, let m = m + 1 and enter S404; where m is a positive integer. S404. Determine whether m is greater than the preset number of cycles. If so, return to S3; otherwise, perform bitslip on the data and return to S401. S405. During the recording of the adjustment process, set the link delay at which each link can stably receive the feature template pattern, and take the intermediate delay value that can be stably matched by each link as the initial delay setting for each link. , , ,... , and complete the initial calibration.

4. The continuous high-precision pulse width measurement method based on high-speed SerDes according to claim 3, wherein When returning from S404 to S3, the multiplexed interleaving calibration module adjusts the initial delay value of each link according to the minimum adjustment step value .

5. The continuous high-precision pulse width measurement method based on high-speed serdes according to claim 1, wherein In S7, it specifically includes: S701. Adjust the transmission clock phase of the serial deserializer SerDes transmitter according to the phase offset to obtain a calibration signal with a fixed frequency and continuously changing phase delay. S702. The serial deserializer SerDes receiver performs parallel interleaved sampling and outputs the sampled data. S703. Determine whether the sampled data is correct. If it is not correct, adjust it through the analog delay fine-tuning terminal of the delay adjustment module to implement the calibration parameters of the delay of each link.

6. The method for continuously and highly precisely measuring pulse width based on high-speed SerDes according to claim 1, wherein In S8, it includes: S801. The serial deserializer SerDes transmitter changes the frequency offset of the transmission clock through frequency offset adjustment to obtain a standard signal with a periodic change. S802. Statistically analyze the pulse widths of multiple interleaved samplings and analyze the measurement results to obtain an analysis curve.

7. The method for continuously and highly precisely measuring pulse width based on high-speed SerDes according to claim 1, wherein In S11, after data segmentation of the interleaved sampling signal, the pulse width value is analyzed by a parallel summation circuit; specifically: S1101. Extract the pulse signal of the interleaved sampling signal through an edge processing circuit; S1102. Divide the pulse signal into multiple groups of data, and retain the last 1 bit of data in the previous group in each group of data; S1103. Determine whether each group of data is in the rising edge state or the falling edge state; S1104. Perform bitwise summation on the rising edge states of a preset number of groups to obtain the total number Rise_sum of clock rising edges; perform bitwise summation on the falling edge states of a preset number of groups to obtain the total number Fall_sum of clock falling edges; S1105. Analyze the pulse width based on the total number of clock rising edges and the total number of clock falling edges.

8. The method for continuously and highly precisely measuring pulse width based on high-speed SerDes according to claim 7, wherein Specifically in S1105: Set a positive pulse width counter pos_pulse_cnt and a negative pulse width counter neg_pulse_cnt; When both the total number Rise_sum of clock rising edges and the total number Fall_sum of clock falling edges are 0, increment the positive pulse width counter pos_pulse_cnt by 1 when the signal is all 1, and increment the negative pulse width counter neg_pulse_cnt by 1 when the signal is all 0; When the total number Rise_sum of clock rising edges is 0 and the total number Fall_sum of clock falling edges is 1, map the corresponding positive and negative pulse width values according to the determined falling edge one-hot code, sum them with the corresponding positive and negative pulse width counters to obtain the corresponding pulse width; When the total number Rise_sum of clock rising edges is 1 and the total number Fall_sum of clock falling edges is 0, map the corresponding positive and negative pulse width values according to the determined rising edge one-hot code, sum them with the corresponding positive and negative pulse width counters to obtain the corresponding pulse width; When both the total number Rise_sum of clock rising edges and the total number Fall_sum of clock falling edges are 1, make a judgment based on the order of the rising edge and the falling edge. If the rising edge is before, it is a positive pulse width, and use the falling edge position minus the rising edge position to obtain the corresponding positive pulse width output; if the falling edge is before, it is a negative pulse width, and use the rising edge position minus the falling edge position to obtain the corresponding negative pulse width output; When the total number Rise_sum of clock rising edges is 2 and the total number Fall_sum of clock falling edges is 1, store the corresponding acquisition coding value and the corresponding sampling moment in the data buffer FIFO, and record the second rising edge position at the same time, and cooperate with the subsequent positive pulse width counter pos_pulse_cnt to calculate the positive pulse width length; When the total number Rise_sum of clock rising edges is 1 and the total number Fall_sum of clock falling edges is 2, store the corresponding acquisition coding value and the corresponding sampling moment in the data buffer FIFO, and record the second falling edge position at the same time, and cooperate with the subsequent negative pulse width counter neg_pulse_cnt to calculate the negative pulse width length; When the total number of rising edges of a clock, Rise_sum, and the total number of falling edges of a clock, Fall_sum, are both greater than or equal to 2, the corresponding acquisition coding value and the corresponding sampling moment are stored in the data buffer FIFO. By adding an offset to each set of parallel data, the specific positions of the corresponding rising and falling edges in the parallel data are obtained; when there is only one pulse or the pulse period is greater than the FPGA main clock period within each FPGA main clock cycle, the corresponding pulse width measurement results can be obtained at each clock. If there are multiple pulse periods within each FPGA main clock cycle, the data buffer FIFO can be read through channels for analysis to obtain the width of each pulse and the corresponding occurrence moment.

9. A continuous high-precision pulse width measurement system based on high-speed SerDes, characterized in that, It includes: At least two input modules; The input module is used for inputting calibration signals or signals to be measured. A selection module; The selection module is used to select the signal input by one input module. A fan-out driver module; the fan-out driver module is used to copy the input signal into signals of multiple links, and the signal output end of the selection module is connected to the signal input end of the fan-out driver module. Multiple delay adjustment modules; One delay adjustment module is used for delay adjustment of the signal of one link. The signal output ends of the fan-out driver module are respectively connected to the signal input ends of the multiple delay adjustment modules. A temperature measurement module; the temperature measurement module is used to detect the temperature of the working environment of the measurement system. An FPGA chip; The signal output ends of the multiple delay adjustment modules and the signal output end of the temperature measurement module are both connected to the signal input end of the FPGA chip. The FPGA chip is provided with a serial deserializer SerDes, and the transmitting end of the serial deserializer SerDes is used to send calibration signals to the input module. A storage module; The storage module stores temperature compensation data. The FPGA chip includes: Multiple serial deserializer SerDes; the multiplexed parallel signals after delay conditioning are respectively connected to the receiving ends of the multiplexed parallel serial deserializer SerDes for sampling to obtain sampling data. A data buffer FIFO; the data buffer FIFO is used for synchronous clock processing of the sampling data. A multiplexed interleaved calibration module; the multiplexed interleaved calibration module judges the sampling phases of the sampled data of each path after synchronization according to the multiplexed interleaved algorithm, and through the phase adjustment function of the receiving end of the serial deserializer SerDes and the adjustment of the time delays of each link, evenly distributes the sampling clock phases of the receiving ends of the multiple serial deserializer SerDes within a sampling period. After calibration, an interleaved sampled multi-parallel quantization data stream is output. A multi-parallel pulse width time measurement module; the multi-parallel pulse width time measurement module performs high-precision pulse width time calculation on the multi-parallel quantization data stream through a pulse width retrieval circuit.

10. The continuous high-precision pulse width measurement system based on high-speed SerDes according to claim 9, characterized in that, The measurement system further includes an input buffer driver module, which converts the single-ended input signal to be measured into a differential form through an ultra-wideband fixed-gain fully differential amplifier and adjusts the common-mode level of the output differential signal.

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