Onboard automatic triggering method and device for dynamic acquisition of inverter status

Abstract

An onboard automatic triggering method and device for dynamic acquisition of inverter status belongs to the field of inverter technology. The onboard automatic triggering includes configurable triggering and configurable acquisition. The configurable triggering captures dynamic signals from the inverter's switching transistors. The capture conditions for dynamic parameters include transition triggering and stable triggering. Transition triggering includes linked transition triggering and independent transition triggering, while stable triggering includes high-level triggering and low-level triggering. After configurable triggering, configurable data acquisition is performed. The configurable acquisition allows for parameterized configuration of channel selection, acquisition length, and acquisition accuracy, ultimately achieving real-time synchronous acquisition and storage of data from a specific number of channels. Through parameterized configuration, it can adapt to any triggering and acquisition requirements, realizing the capture, triggering, accurate data acquisition, and storage of specified events under complex inverter control timing, providing an accurate data foundation and reference for inverter fault diagnosis and health assessment.

Description

Technical Field

[0001] This invention relates to the field of inverter technology, and in particular to an onboard automatic triggering method and device for dynamic acquisition of inverter status. Background Technology

[0002] Inverters, as a crucial component of electric drive systems, perform energy conversion and output functions, transforming direct current (DC) into alternating current (AC) of fixed frequency and voltage, or frequency and voltage regulation, to drive motors for motion control or energy conversion. Under the influence of multi-physical field stresses on the working cross-section, aging of the internal components of the inverter chip, its packaging bonding, and pins can lead to a series of failures. Inverter failures can range from minor issues like equipment downtime or loss of functionality, affecting production and equipment operations, resulting in decreased efficiency and increased costs, to severe consequences such as equipment or equipment malfunction, fire, and burnout.

[0003] Switching transistors are core components and weak points in inverters. Accurate acquisition of switching transistor status data is the technical prerequisite and foundation for implementing online real-time monitoring and diagnosis of inverters. Due to the limited size of onboard storage resources, the acquisition of transient data of switching transistors in inverters needs to accurately capture the effective timing window. Due to the diverse triggering conditions and the large number of switching transistors in inverters, the onboard circuit area is difficult to meet the monitoring needs of all transistors. Therefore, how to flexibly solve the dynamic triggering and acquisition of inverter monitoring plays a key role. This will provide strong support for accurately predicting the performance of all switching transistors in the inverter and evaluating the overall performance of the entire inverter.

[0004] There are many types of inverters. This invention can be applied to a three-phase full-bridge inverter in a servo drive system. It consists of three half-bridges composed of six IGBT (Insulated Gate Bipolar Transistor) switching devices, such as... Figure 1 As shown, these are VT1-VT6, where VT1 and VT4 are defined as phase a, VT3 and VT6 as phase b, and VT5 and VT2 as phase c. The output terminals of a, b, and c are connected to the three-phase windings of the motor (equivalent to coils). The six IGBTs combined (with opposite signals in the upper and lower halves of the same bridge arm) provide eight safe switching states, as shown... Figure 2 As shown, 000 and 111 represent the switching states of the three upper bridge arms. When the state of one of the IGBTs in the three-phase full-bridge inverter circuit changes, the switching on and off causes changes in the Vce and Ic currents. When the switching pulse jumps from a high level to a low level, it means that the IGBT is off, and its Vce voltage drop recovers from the saturation voltage drop to the value of the bus voltage minus the saturation voltage drop. Conversely, when the IGBT is turned on, its Vce voltage drop decreases from the bus voltage to the saturation voltage drop.

[0005] The inverter operates by precisely controlling internal switching devices to convert DC into a specific AC voltage for external output. This process relies on the state combination and switching of internal three-phase diodes. Since it uses a multi-diode combination mode, to capture and acquire the dynamic waveform of a single diode switching moment, the instant of state transition must be accurately captured.

[0006] Currently, the detection of inverter faults in electric drive systems typically involves testing the U / V / W three-phase signals at the output of the inverter bridge. If any switch in any phase fails, the effective value of its phase voltage will show a significant drop. The missing phase waveform is used to determine if a fault is caused by an open circuit in one or more switches. This is a fault detection and location technique after an electric drive failure has occurred, referencing the system-level signals of the electric drive inverter. It cannot track the failure evolution process of internal switches or detect problems in advance. While specialized instruments such as oscilloscopes can be used to test and analyze inverter switches, this requires in-depth disassembly and the installation of test points, making the operation complex. In practical engineering applications, it is often not feasible to remove switches from the circuit board for testing and then solder them back for continued use, which would also introduce other reliability issues. Currently, there is no universally applicable onboard solution that enables flexible triggering and automatic acquisition and transmission of data. Summary of the Invention

[0007] To address the aforementioned technical problems, this invention proposes an onboard automatic triggering method and device for dynamic acquisition of inverter status, belonging to the field of inverter technology. The onboard automatic triggering includes configurable triggering and configurable acquisition. The configurable triggering captures dynamic signals from the inverter's switching transistors, with capture conditions including jump triggering and stable triggering. Jump triggering includes linked jump triggering and independent jump triggering; stable triggering includes high-level triggering and low-level triggering. After configurable triggering, configurable data acquisition is performed. Configurable acquisition allows for parameterized configuration of channel selection, acquisition length, and acquisition accuracy, ultimately achieving real-time synchronous acquisition and storage of data from a specific number of channels. Through parameterized configuration, it can adapt to any triggering and acquisition requirements, realizing the capture, triggering, accurate data acquisition, and storage of specified events under complex inverter control timing, providing an accurate data foundation and reference for inverter fault diagnosis and health assessment.

[0008] An onboard automatic triggering method for dynamically acquiring inverter status includes the following steps:

[0009] Step 1, obtain the differential control signals of the inverter switching transistors: The differential control signals of the IGBT (Insulated Gate Bipolar Transistor) switching transistors are the gate G and the collector E;

[0010] Step 2: Input the differential control signal to the isolation conversion circuit for amplitude conditioning and opto-isolation conversion to obtain a single-ended pulse signal; the amplitude conditioning includes scaling and biasing.

[0011] Step 3: Input the single-ended pulse signal into the threshold transformation circuit for specific threshold feature recognition and filtering anti-interference to obtain the dual threshold comparison trigger pulse;

[0012] Step 4: The dual threshold comparison trigger pulse is transmitted to the event capture unit as the basic event. The event capture unit performs timing identification on the switching transistor to obtain the trigger signal.

[0013] Step 5: Input the trigger signal to the controller (ARM). The controller starts the acquisition after being triggered by an external interrupt.

[0014] Furthermore, in step 2, the number of isolation conversion circuits is the same as the number of switching transistors; the isolation conversion circuits sequentially include four parts: a differential amplifier module, a voltage bias module, a linear opto-isolation module, and a voltage amplification follower module;

[0015] The differential amplifier module includes an operational amplifier U89, a proportional setting resistor, a capacitor C219, and ports. The port voltages are Vin+ and Vin-, respectively. The operational amplifier U89 includes U89A and U89B. The proportional setting resistor includes resistors R323, R324, R333, R334, R343, and R349, satisfying R323 + R324 = R333 + R334, and R343 = R349. The port voltage Vin+ is connected in series with R323 and R324. 324, after being superimposed with the bias voltage Vbias, is connected to the positive input terminal of U89A. The positive input terminal of the power supply of U89A is simultaneously connected to ground via a series capacitor C219. The port voltage Vin- is connected in series with R333 and R334, and after passing through resistor R334, it is split into two paths. One path is connected to the negative input terminal of operational amplifier U89A, and the negative terminal of operational amplifier U89A is grounded. The other path is connected to the output terminal of operational amplifier U89A via a series resistor R349, forming a negative feedback loop.

[0016] The voltage bias module includes resistors R341 and R347; one end of resistor R341 is connected to one end of resistor R347, the other end of resistor R341 is connected to +5V, and the other end of resistor R347 is grounded. After voltage division, the voltage is connected to the positive input terminal of operational amplifier U89B; the output terminal and negative input terminal of U89B are interconnected to form a voltage follower. Operational amplifiers U89B and U89A share the positive and negative input terminals of the power supply.

[0017] The linear opto-isolation module includes an isolator U85, resistors R327 and R339, and capacitors C223 and C227. The isolator U85 has pins including a positive input terminal IN+, a negative input terminal IN-, a positive output terminal OUT+, a negative output terminal OUT-, a voltage matching region VDD1, a voltage matching region VDD2, a ground isolation region GNG1, and a ground isolation region GND2. One end of resistor R327 is connected in series with one end of resistor R339. The other end of resistor R327 is connected to the output of operational amplifier U89A, and the other end of resistor R339 is connected to digital ground. After a second voltage division, the voltage is grounded after being connected in parallel with capacitor C223 and simultaneously connected to the positive input terminal IN+ of isolator U85. The negative input terminal IN- of isolator U85, the other end of capacitor C223, and ground isolation region GNG1 are all connected to digital ground. Voltage matching region VDD1 is connected to one end of capacitor C227, and the other end of capacitor C227 is connected to digital ground.

[0018] The voltage amplification and follower module includes an operational amplifier U90A, configuration resistors, capacitors C228 and C233, and a low-pass filter circuit. The configuration resistors include R329, R337, R344, and R351, satisfying R329 = R337 and R344 = R351. The low-pass filter circuit includes capacitor C225 and resistor R331. One end of resistor R329 is connected to the positive output terminal OUT+ of the isolation device U85, and the other end of resistor R329 is connected to the positive input terminal of the operational amplifier U90A. The other end of resistor R329 is connected in series with R344 and then grounded, equivalent to the bias voltage. When set to 0, the positive input terminal of the operational amplifier U90A is connected to ground via a series capacitor C233; one end of resistor R337 is connected to the negative output terminal OUT- of the isolation device U85, and the other end of resistor R337 is connected to the negative input terminal of the operational amplifier U90A, and connected to the output terminal of the operational amplifier U90A via a series resistor R351, forming a feedback path. The negative input terminal of the operational amplifier U90A is also grounded. One end of R331 is connected to the output terminal of the operational amplifier U90A, and the other end of R331 is connected to ground via a series capacitor C225, and the output voltage Vout is generated.

[0019] The isolation converter circuit processes the differential control signal in the following steps:

[0020] Step 2.1: The port receives the differential control signal from the switching transistor and converts the differential control signal into a single-ended signal. The operational amplifier U89A reduces the voltage of the single-ended signal by a ratio β1. The voltage range after reduction is -1.2 to 2V. The reduction ratio β1 = R349 / (R323+R324).

[0021] Step 2.2: The voltage bias function is achieved by setting resistors R341 and R347. The biased voltage range is 0.05V to 3.25V. The bias voltage Vbias = 5*(R341 / (R341+R347)).

[0022] Step 2.3: By setting resistors R327 and R339, the biased single-ended signal is first reduced by a ratio β2 while ensuring driving capability. The reduced voltage range is 0.025V to 1.625V. Then, it is input to the isolation device U85 for linear opto-isolation. The input range of the isolation device U85 is 0V-2V. The reduction ratio β2 = R327 / (R327+R339).

[0023] Step 2.4: The single-ended signal after linear opto-isolation is amplified and recovered by operational amplifier U90A according to ratio β3. The amplified voltage range is 0.05V to 3.25V; the amplification ratio β3 = R351 / R329. The voltage amplification and following module cancels the reduction ratio before entering the linear opto-isolation module and enhances the current driving capability to the threshold conversion circuit, ensuring that the current consumption of multiple threshold conversion branches will not cause waveform distortion.

[0024] Step 2.5, the output voltage of the isolation change circuit is Vout = (Vbias + ((Vin+) - (Vin-)) * β1) * β2 * β3, and the range of Vout is from 0.05V to 3.25V.

[0025] Furthermore, in step 3, the threshold transformation circuit uses a configurable comparison voltage to achieve signal threshold feature recognition and obtain a dual threshold comparison trigger pulse;

[0026] The number of threshold conversion circuits is the same as the number of inverter switching transistors; the threshold conversion circuits sequentially include a multi-channel DAC (digital-to-analog converter), a buffer, a high-speed comparator, and a high-speed optocoupler; there are two high-speed optocouplers, and the two high-speed optocouplers are identical; the high-speed comparator includes high-speed comparator A and high-speed comparator B, high-speed comparator A is used to implement comparison triggering on the rising edge, and high-speed comparator B is used to implement comparison triggering on the falling edge;

[0027] The controller controls the output voltage of the multi-channel DAC via the integrated circuit bus IIC, making the output voltage range 0V-3V; the output voltage of the multi-channel DAC is buffered to become a reference voltage, which is used to compare with the single-ended signal.

[0028] The single-ended signals at the output of the isolation conversion circuit are connected in parallel and input to the negative terminal of high-speed comparator A and the positive terminal of high-speed comparator B, respectively; the reference voltage is input to the positive terminal of high-speed comparator A and the negative terminal of high-speed comparator B, respectively; when the positive terminal voltages of high-speed comparator A and high-speed comparator B are both greater than the negative terminal voltages, the threshold conversion circuit outputs a high level; otherwise, it outputs a low level.

[0029] The output signal of high-speed comparator A is input to one of the high-speed optocouplers, and the output signal of high-speed comparator B is input to the other high-speed optocoupler. After the signal is filtered and anti-interference by the high-speed optocouplers, a dual threshold comparison trigger pulse is obtained. The function of the high-speed optocouplers is to isolate and protect the event capture unit, so as to avoid timing misjudgment caused by signal crosstalk in the event capture unit in a harsh electromagnetic environment.

[0030] Furthermore, in step 4, the event capture unit is based on a programmable logic device (FPGA) to implement event capture;

[0031] The event capture unit includes an SPI communication interface module (SPI slave), a read / write control timing module, a configuration register module, a status register module, and a logic recognition module;

[0032] The SPI communication interface module is interconnected with the controller via a synchronous clock Clk, a data line MISO, and a data line MOSI. As a slave device of the SPI, the SPI communication interface module provides a data read / write interface to the controller. Under the tick of the controller's synchronous clock Clk, it serially receives read / write commands, which include read / write identifiers, operation addresses, and operation data information. While responding to the controller's SPI serial communication protocol, the SPI communication interface module controls the read / write control timing module to address and read / write the configuration register module and the status register module. The read / write control timing module is interconnected with the configuration register module and the status register module in an asynchronous read / write mode, which includes an asynchronous clock, a 32-bit data bus, and an 8-bit address bus. The configuration register module and the status register module are implemented using dual-port running memory (RAM). Both modules simultaneously provide read / write interface data to the read / write control timing module and the logic identification module, respectively. The logic identification module writes running status flags and data into the status register module, which the read / write control timing module then reads and sends to the controller via the SPI communication interface, forming a bidirectional data interaction.

[0033] The SPI communication interface module interacts with the controller's SPI Master interface, and the information exchanged includes reading and writing the contents of the configuration register and the status register.

[0034] The configuration register module is used to store the controller's configuration parameters for the event capture logic. The configuration parameters include trigger enable, mode selection, and event customization.

[0035] The status register module stores the recognition status and count of various events from the latching logic recognition module. The status register provides an interface for simultaneous reading and writing by both the logic recognition module and the read / write control timing module. Each module occupies one read / write bus in the dual-port RAM of the status register. The logic recognition module writes event flags triggered in real-time by the differential control signal of the switching transistor. The read / write control timing module writes the controller's clear and manual trigger flags. The controller's clear flag is used to remove the existing trigger status, waiting for and maintaining the new trigger status. The manual trigger flag is only used in debug mode; forced triggering is achieved by actively writing status flags through the controller, used for data acquisition and testing. The priority of manual triggering is higher than that of the logic recognition module. The switching of manual triggering mode is determined by the manual mode control bit in the configuration register. When the manual triggering mode is enabled, the triggering result of the logic recognition module is masked, and no write operation to the status register module occurs.

[0036] The logic recognition module performs timing recognition based on the dual threshold trigger pulses of the switching transistor to capture various events of the switching transistor, and the captured event results are latched into the status register module. The combined output logic of the logic recognition module outputs a trigger interrupt signal to the controller based on the event flag in the current status register module and the trigger enable, mode and event customization source configuration in the configuration register module.

[0037] Furthermore, the timing identification includes single-tube timing identification and multi-tube combined timing identification;

[0038] The single-transistor timing identification first generates a basic event waveform based on the dual-threshold trigger pulse of a single switching transistor, and then realizes the event identification of single-transistor transition triggering and stable triggering based on the rising and falling edges of the basic event waveform of the single-ended signal; the multi-transistor combined timing identification is based on the timing identification of multiple single transistors, and uses a state machine to perform strict timing discrimination based on the transition triggering and stable triggering events of the basic event waveform of multiple transistors, so as to realize the triggering of complex events that meet the timing conditions of multiple transistors.

[0039] Step 4.1, the single-transistor timing identification process is as follows:

[0040] First, basic event waveform generation:

[0041] The dual threshold comparison trigger pulse of a single transistor is input to the logic recognition module. The dual threshold comparison trigger pulse includes a first trigger pulse VH and a second trigger pulse VL. Basic event waveforms are generated through a finite element state machine.

[0042] The finite element state machine adopts asynchronous reset and is set to an idle state.

[0043] When the finite element state machine is idle, the basic event waveform is low level; when a transition from low to high level VH occurs, the finite element state machine changes to state 1, otherwise it remains unchanged;

[0044] When the finite element state machine is in state 1, the basic event waveform is high level. When a transition from low to high level occurs in VL, the finite element state machine changes to state 0; otherwise, it remains unchanged.

[0045] When the finite element state machine is in state 0, the basic event waveform is low level. When a transition from low to high level occurs, the finite element state machine changes to state 1; otherwise, it remains unchanged.

[0046] Secondly, single switch event identification:

[0047] A high-speed clock is used to distinguish the basic event waveform. In each cycle of the high-speed clock, the current state now_state is temporarily stored in the previous state pre_state, and the current basic event waveform level is read out and assigned to pre_state to identify the rising edge transition, falling edge transition and stable high and low level states of the basic event waveform.

[0048] The rising edge transition triggers:

[0049] If pre_state is low and now_state is high, the rising edge transition flag of the single transistor in the status register module is set to 1 and remains so until the controller performs a clear operation via SPI.

[0050] The falling edge transition triggers:

[0051] If pre_state is high and now_state is low, the falling edge transition flag of the single transistor in the status register module is set to 1 and remains so until the controller performs a clear operation via SPI.

[0052] The high / low level trigger:

[0053] If now_state is high, the single-transistor level flag in the status register module is set to 1;

[0054] If now_state is low, the single-transistor level flag in the status register module is set to 0;

[0055] Step 4.2, the multi-tube combination timing identification process is as follows:

[0056] First, a general temporal recognition framework is established, which includes the following general variables:

[0057] The maximum multi-transistor timing state length max_state_len is a constant; the effective multi-transistor timing state length use_state_len is defined in the configuration register module; max_state_len signal variables signal[max_state_len] are defined in the configuration register; signal[0] to signal[use_state_len-1] represent a multi-transistor event, which occurs in the order of signal[0] to signal[use_state_len-1]. The coordinate index of the single-transistor event is stored in signal[0] to signal[use_state_len-1]. Status_register is a single switch status register in the status register module.

[0058] Then, the valid multi-transistor timing state length is written to the use_state_len in the configuration register through the controller's SPI communication bus, and the single-transistor event index is written to signal[0] to signal[use_state_len-1] in sequence to complete the definition of multi-transistor events;

[0059] Finally, a finite element state machine was adopted as the state machine for multi-channel event recognition, and the multi-channel event recognition state machine adopted asynchronous reset. The multi-channel event recognition state machine was set to an idle state, and the event traversal count variable len_temp was defined to count the number of state transitions and was initialized to 0.

[0060] In the idle state: if len_temp is greater than use_state_len, the trigger condition is met and the trigger signal is output; if the Status_register[signal[0]] corresponding to signal[0] is equal to 1, the state machine for recognizing the state multi-transistor event is set to state 1, and len_temp = len_temp + 1; otherwise, it remains unchanged;

[0061] In state 1: if len_temp is greater than use_state_len, the trigger condition is met and the trigger signal is output; if the Status_register[signal[1]] corresponding to signal[1] is equal to 1, the state machine for recognizing state multi-transistor events is set to state 2, len_temp = len_temp + 1; otherwise, it remains unchanged;

[0062] This process continues until len_temp is greater than use_state_len, ultimately achieving multi-tube event triggering by combining the timing sequences of use_state_len single-tube events.

[0063] Step 4.3: Synchronize the single-transistor event and multi-transistor event flags to the status register. The output combination logic in the logic identification module selects the event mode according to the configuration register, reads the flag bit in the status register, and generates an interrupt signal. The interrupt signal triggers the controller to start data acquisition.

[0064] An onboard automatic triggering device for dynamically acquiring inverter status is disclosed. The device includes an isolation conversion circuit, a threshold conversion circuit, an event capture logic unit, a controller, a memory, an analog switching module, an analog-to-digital converter (ADC), and a communication module. The isolation conversion circuit, threshold conversion circuit, and inverter switching transistors are of the same number (six in total). The differential control signal of each switching transistor is converted to a single-ended signal by the isolation conversion circuit, and then passed through the threshold conversion circuit to obtain a dual-threshold comparison trigger pulse. This dual-threshold comparison trigger pulse is transmitted as a basic event to the event capture unit for timing identification to obtain the trigger signal. The system is as follows: a trigger signal is input to the controller, which initiates data acquisition upon triggering an external interrupt; the memory is an on-chip storage unit mounted on the controller bus and interconnected with the controller; the controller is interconnected with the analog-to-digital converter (ADC), which performs signal sampling, holding, quantization, and encoding output; the controller configures and reads data from the ADC and temporarily stores the converted data in the memory's buffer; the output signal of the analog switch module is connected to the input of the ADC, and the analog switch module switches different channels for signal acquisition based on different trigger events; the controller communicates with external devices via the communication module.

[0065] Furthermore, the analog switch module includes seven analog switching devices, each with an eight-channel selector function. The analog input signals of the analog switching devices include 29 signals from the six switching transistors in the inverter. These 29 signals include six signals for the gate-emitter voltage Vge, six signals for the collector-emitter voltage Vc, six signals for the collector current Ice, six signals for the saturation voltage drop Vce_sat, one signal for the bus voltage, one signal for the bus current, one signal for the U-phase current Iu, one signal for the V-phase current Iv, and one signal for the W-phase current Iw. The signals to be acquired are connected to the analog switch module to achieve data synchronization for multi-channel acquisition.

[0066] Furthermore, in step 5, before receiving the interrupt trigger input from the logic recognition module, the controller needs to complete the following process:

[0067] Step 5.1: The controller initializes itself and enters the Ethernet communication listening state after initialization. The initialization includes configuring the working modes of the main frequency, GPIO, interrupt, ADC, SPI, IIC, extended memory bus and Ethernet interface.

[0068] Step 5.2: If the acquisition command and parameters are received from the host computer via Ethernet, first write the asynchronous reset flag in the configuration register of the event capture device corresponding to all switching transistors through the SPI bus, stop all current event capture processes and put them in the initial state;

[0069] Step 5.3: Based on the acquisition parameters from the host computer, select the corresponding switch transistor in the threshold conversion module of the host computer via IIC. Switch transistors not mentioned in the acquisition command do not need to be configured and can be ignored.

[0070] Step 5.4: Based on the acquisition parameters from the host computer, select the event capture unit of the corresponding switch transistor on the host computer via the SPI bus, set the configuration register in the event capture unit, set the event capture unit to the disabled state, further set the trigger mode, and trigger the event definition; the switch transistors not involved in the acquisition command do not need to be configured and are ignored directly.

[0071] Step 5.5: Clear the existing external interrupt flags of the controller and reset the external trigger operating mode of the controller;

[0072] Step 5.6: Based on the acquisition parameters from the host computer, configure the startup mode of the analog-to-digital conversion module to external trigger, calculate the sampling rate, conversion accuracy, and sampling channel parameters, and write the values ​​to the registers.

[0073] Step 5.7: Based on the parameters acquired by the host computer, configure the channel selection of the 7 analog switching devices in the analog switching module by controlling the GPIO pin level of the controller;

[0074] Step 5.8: Reset the read / write pointers of the data storage ring buffer and configure the controller's DMA (Direct Memory Access) source and destination addresses;

[0075] Step 5.9: Configure the enable flag bit of the configuration register of the event capture unit corresponding to the switch transistor via the SPI bus. Event capture will then be ready, waiting for the event to be triggered.

[0076] Step 5.10: After the event is triggered, the data collection and storage will be completed automatically. Once completed, the callback parameters will be entered, and the execution result status code will be returned.

[0077] Step 5.11: The controller begins to analyze and process the data, and after obtaining the fault diagnosis conclusion, it sends the result data and the collected raw waveform data to the host computer via Ethernet.

[0078] The controller enables Ethernet receive and transmit interrupts, maps callback functions, and uses callback functions triggered by Ethernet data receive interrupts to receive and parse acquisition commands and parameters from the host computer. The controller configures the registers in the event capture unit via SPI, configures the DAC parameters in the threshold conversion module via IIC, and configures the channel selection of the analog switching device via GPIO; it also accepts commands from the host computer.

[0079] The beneficial effects of this invention are as follows:

[0080] This invention addresses the need for online acquisition of dynamic signals from multiple switching transistors in an inverter. It provides a technical solution for automatically triggering the online acquisition of each switching transistor under operating conditions. This solution can solve the industry problem of difficulty in capturing dynamic signals for online fault diagnosis of inverters and provide technical support for improving the reliability of new energy products that use inverters.

[0081] This invention saves costs by using a small number of paths and circuits to cover the triggering and acquisition of all switching transistors in the inverter, and time-division multiplexing, which greatly saves costs and reduces size. The triggering conditions are programmable and configurable, making it highly applicable and flexible in use. To some extent, it can improve the cost-effectiveness and feasibility of online testing and evaluation schemes for electric drive systems, and bring better market competitiveness.

[0082] This invention selects the turn-on signal of the three-phase two-electric switch of the inverter as a reference, realizing multi-functional dynamic acquisition with configurable trigger conditions and selectable trigger sources for the inverter; it can flexibly capture various transient data of the inverter for fault diagnosis and tracking and analysis of degradation degree, ensuring the operational safety and predictive maintenance guarantee of the electric drive system, and is small in size, adaptable to various trigger conditions, and has engineering transformation value. Attached Figure Description

[0083] Figure 1 Schematic diagram of an inverter for servo drive;

[0084] Figure 2 This refers to the switching status of the inverter used for servo drives.

[0085] Figure 3 Diagram of an online precision triggering and acquisition device for monitoring and evaluating the degradation of inverter switching transistors;

[0086] Figure 4 This is a functional diagram of the isolation circuit conversion module;

[0087] Figure 5 This is a functional diagram of the threshold change circuit module;

[0088] Figure 6 This is a functional diagram of the event capture unit;

[0089] Figure 7 Generate a logic state machine diagram for the basic event waveforms;

[0090] Figure 8 A schematic diagram illustrating the dynamic assignment of monitoring signals;

[0091] Figure 9 Flowchart for dynamically assigning values ​​to monitoring signals;

[0092] Figure 10 A flowchart for event recognition in a multi-channel system;

[0093] Figure 11 The flowchart shows the automatic data acquisition process triggered by the main controller. Detailed Implementation

[0094] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0095] like Figure 3 As shown:

[0096] An onboard automatic triggering method for dynamically acquiring inverter status includes the following steps:

[0097] Step 1, obtain the differential control signals of the inverter switching transistors: The differential control signals of the IGBT (Insulated Gate Bipolar Transistor) switching transistors are the gate G and the collector E;

[0098] Step 2: Input the differential control signal to the isolation conversion circuit for amplitude conditioning and opto-isolation conversion to obtain a single-ended pulse signal; the amplitude conditioning includes scaling and biasing.

[0099] Step 3: Input the single-ended pulse signal into the threshold transformation circuit for specific threshold feature recognition and filtering anti-interference to obtain the dual threshold comparison trigger pulse;

[0100] Step 4: The dual threshold comparison trigger pulse is transmitted to the event capture unit as the basic event. The event capture unit performs timing identification on the switching transistor to obtain the trigger signal.

[0101] Step 5: Input the trigger signal to the controller (ARM). The controller starts the acquisition after being triggered by an external interrupt.

[0102] like Figure 4 As shown:

[0103] Furthermore, in step 2, the number of isolation conversion circuits is the same as the number of switching transistors; the isolation conversion circuits sequentially include four parts: a differential amplifier module, a voltage bias module, a linear opto-isolation module, and a voltage amplification follower module;

[0104] The differential amplifier module includes an operational amplifier U89, a proportional setting resistor, a capacitor C219, and ports. The port voltages are Vin+ and Vin-, respectively. The operational amplifier U89 includes U89A and U89B. The proportional setting resistor includes resistors R323, R324, R333, R334, R343, and R349, satisfying R323 + R324 = R333 + R334, and R343 = R349. The port voltage Vin+ is connected in series with R323 and R324. 324, after being superimposed with the bias voltage Vbias, is connected to the positive input terminal of U89A. The positive input terminal of the power supply of U89A is simultaneously connected to ground via a series capacitor C219. The port voltage Vin- is connected in series with R333 and R334, and after passing through resistor R334, it is split into two paths. One path is connected to the negative input terminal of operational amplifier U89A, and the negative terminal of operational amplifier U89A is grounded. The other path is connected to the output terminal of operational amplifier U89A via a series resistor R349, forming a negative feedback loop.

[0105] The voltage bias module includes resistors R341 and R347; one end of resistor R341 is connected to one end of resistor R347, the other end of resistor R341 is connected to +5V, and the other end of resistor R347 is grounded. After voltage division, the voltage is connected to the positive input terminal of operational amplifier U89B; the output terminal and negative input terminal of U89B are interconnected to form a voltage follower, and operational amplifiers U89B and U89 share the positive and negative input terminals of the power supply.

[0106] The linear opto-isolation module includes an isolator U85, resistors R327 and R339, and capacitors C223 and C227. The isolator U85 has pins including a positive input terminal IN+, a negative input terminal IN-, a positive output terminal OUT+, a negative output terminal OUT-, a voltage matching region VDD1, a voltage matching region VDD2, a ground isolation region GNG1, and a ground isolation region GND2. One end of resistor R327 is connected in series with one end of resistor R339. The other end of resistor R327 is connected to the output of operational amplifier U89A, and the other end of resistor R339 is connected to digital ground. After a second voltage division, capacitor C223 is connected in parallel to ground and also to the positive input terminal IN+ of isolator U85. The negative input terminal IN- of isolator U85, the other end of capacitor C223, and ground isolation region GNG1 are all connected to digital ground. Voltage matching region VDD1 is connected to one end of capacitor C227, and the other end of capacitor C227 is connected to digital ground.

[0107] The voltage amplification and follower module includes an operational amplifier U90A, configuration resistors, capacitors C228 and C233, and a low-pass filter circuit. The configuration resistors include R329, R337, R344, and R351, satisfying R329 = R337 and R344 = R351. The low-pass filter circuit includes capacitor C225 and resistor R331. One end of resistor R329 is connected to the positive output terminal OUT+ of the isolation device U85, and the other end of resistor R329 is connected to the positive input terminal of the operational amplifier U90A. The other end of resistor R329 is connected in series with R344 and then grounded, equivalent to the bias voltage. When set to 0, the positive input terminal of the operational amplifier U90A is connected to ground via a series capacitor C233; one end of resistor R337 is connected to the negative output terminal OUT- of the isolation device U85, and the other end of resistor R337 is connected to the negative input terminal of the operational amplifier U90A, and connected to the output terminal of the operational amplifier U90A via a series resistor R351, forming a feedback path. The negative input terminal of the operational amplifier U90A is also grounded. One end of R331 is connected to the output terminal of the operational amplifier U90A, and the other end of R331 is connected to ground via a series capacitor C225, and the output voltage Vout is generated.

[0108] The isolation converter circuit processes the differential control signal in the following steps:

[0109] Step 2.1: The port receives the differential control signal from the switching transistor and converts the differential control signal into a single-ended signal. The operational amplifier U89A reduces the voltage of the single-ended signal by a ratio β1. The voltage range after reduction is -1.2 to 2V. The reduction ratio β1 = R349 / (R323+R324).

[0110] Step 2.2: The voltage bias function is achieved by setting resistors R341 and R347. The biased voltage range is 0.05V to 3.25V. The bias voltage Vbias = 5*(R341 / (R341+R347)).

[0111] Step 2.3: By setting resistors R327 and R339, the biased single-ended signal is first reduced by a ratio β2 while ensuring driving capability. The reduced voltage range is 0.025V to 1.625V. Then, it is input to the isolation device U85 for linear opto-isolation. The input range of the isolation device U85 is 0V-2V. The reduction ratio β2 = R327 / (R327+R339).

[0112] Step 2.4: The single-ended signal after linear opto-isolation is amplified and recovered by operational amplifier U90A according to ratio β3. The amplified voltage range is 0.05V to 3.25V; the amplification ratio β3 = R351 / R329. The voltage amplification and following module cancels the reduction ratio before entering the linear opto-isolation module and enhances the current driving capability to the threshold conversion circuit, ensuring that the current consumption of multiple threshold conversion branches will not cause waveform distortion.

[0113] Step 2.5, the output voltage of the isolation change circuit is Vout = (Vbias + ((Vin+) - (Vin-)) * β1) * β2 * β3, and the range of Vout is from 0.05V to 3.25V.

[0114] like Figure 5 As shown:

[0115] Furthermore, in step 3, the threshold transformation circuit uses a configurable comparison voltage to achieve signal threshold feature recognition and obtain a dual threshold comparison trigger pulse;

[0116] The number of threshold conversion circuits is the same as the number of inverter switching transistors; the threshold conversion circuits sequentially include a multi-channel DAC (digital-to-analog converter), a buffer, a high-speed comparator, and a high-speed optocoupler; there are two high-speed optocouplers, and the two high-speed optocouplers are identical; the high-speed comparator includes high-speed comparator A and high-speed comparator B, high-speed comparator A is used to implement comparison triggering on the rising edge, and high-speed comparator B is used to implement comparison triggering on the falling edge;

[0117] The controller controls the output voltage of the multi-channel DAC via the integrated circuit bus IIC, making the output voltage range 0V-3V; the output voltage of the multi-channel DAC is buffered to become a reference voltage, which is used to compare with the single-ended signal.

[0118] The single-ended signals at the output of the isolation conversion circuit are connected in parallel and input to the negative terminal of high-speed comparator A and the positive terminal of high-speed comparator B, respectively; the reference voltage is input to the positive terminal of high-speed comparator A and the negative terminal of high-speed comparator B, respectively; when the positive terminal voltages of high-speed comparator A and high-speed comparator B are both greater than the negative terminal voltages, the threshold conversion circuit outputs a high level; otherwise, it outputs a low level.

[0119] The output signal of high-speed comparator A is input to one of the high-speed optocouplers, and the output signal of high-speed comparator B is input to the other high-speed optocoupler. After the signal is filtered and anti-interference by the high-speed optocouplers, a dual threshold comparison trigger pulse is obtained. The function of the high-speed optocouplers is to isolate and protect the event capture unit, so as to avoid timing misjudgment caused by signal crosstalk in the event capture unit in a harsh electromagnetic environment.

[0120] like Figure 6 As shown:

[0121] Furthermore, in step 4, the event capture unit is based on a programmable logic device (FPGA) to implement event capture;

[0122] The event capture unit includes an SPI communication interface module (SPI slave), a read / write control timing module, a configuration register module, a status register module, and a logic recognition module;

[0123] The SPI communication interface module is interconnected with the controller via a synchronous clock Clk, a data line MISO, and a data line MOSI. As a slave device of the SPI, the SPI communication interface module provides a data read / write interface to the controller. Under the tick of the controller's synchronous clock Clk, it serially receives read / write commands, which include read / write identifiers, operation addresses, and operation data information. While responding to the controller's SPI serial communication protocol, the SPI communication interface module controls the read / write control timing module to address and read / write the configuration register module and the status register module. The read / write control timing module is interconnected with the configuration register module and the status register module in an asynchronous read / write mode, which includes an asynchronous clock, a 32-bit data bus, and an 8-bit address bus. The configuration register module and the status register module are implemented using dual-port running memory (RAM). Both modules simultaneously provide read / write interface data to the read / write control timing module and the logic identification module, respectively. The logic identification module writes running status flags and data into the status register module, which the read / write control timing module then reads and sends to the controller via the SPI communication interface, forming a bidirectional data interaction.

[0124] The SPI communication interface module interacts with the controller's SPI Master interface, and the information exchanged includes reading and writing the contents of the configuration register and the status register.

[0125] The configuration register module is used to store the controller's configuration parameters for the event capture logic. The configuration parameters include trigger enable, mode selection, and event customization.

[0126] The status register module stores the recognition status and count of various events from the latching logic recognition module. The status register provides an interface for simultaneous reading and writing by both the logic recognition module and the read / write control timing module. Each module occupies one read / write bus in the dual-port RAM of the status register. The logic recognition module writes event flags triggered in real-time by the differential control signal of the switching transistor. The read / write control timing module writes the controller's clear and manual trigger flags. The controller's clear flag is used to remove the existing trigger status, waiting for and maintaining the new trigger status. The manual trigger flag is only used in debug mode; forced triggering is achieved by actively writing status flags through the controller, used for data acquisition and testing. The priority of manual triggering is higher than that of the logic recognition module. The switching of manual triggering mode is determined by the manual mode control bit in the configuration register. When the manual triggering mode is enabled, the triggering result of the logic recognition module is masked, and no write operation to the status register module occurs.

[0127] The logic recognition module performs timing recognition based on the dual threshold trigger pulses of the switching transistor to capture various events of the switching transistor, and the captured event results are latched into the status register module. The combined output logic of the logic recognition module outputs a trigger interrupt signal to the controller based on the event flag in the current status register module and the trigger enable, mode and event customization source configuration in the configuration register module.

[0128] like Figure 7 As shown:

[0129] Furthermore, the timing identification includes single-tube timing identification and multi-tube combined timing identification;

[0130] The single-transistor timing identification first generates a basic event waveform based on the dual-threshold trigger pulse of a single switching transistor, and then realizes the event identification of single-transistor transition triggering and stable triggering based on the rising and falling edges of the basic event waveform of the single-ended signal; the multi-transistor combined timing identification is based on the timing identification of multiple single transistors, and uses a state machine to perform strict timing discrimination based on the transition triggering and stable triggering events of the basic event waveform of multiple transistors, so as to realize the triggering of complex events that meet the timing conditions of multiple transistors.

[0131] Step 4.1, the single-transistor timing identification process is as follows:

[0132] First, basic event waveform generation:

[0133] The dual threshold comparison trigger pulse of a single transistor is input to the logic recognition module. The dual threshold comparison trigger pulse includes a first trigger pulse VH and a second trigger pulse VL. Basic event waveforms are generated through a finite element state machine.

[0134] The finite element state machine adopts asynchronous reset and is set to an idle state.

[0135] When the finite element state machine is idle, the basic event waveform is low level; when a transition from low to high level VH occurs, the finite element state machine changes to state 1, otherwise it remains unchanged;

[0136] When the finite element state machine is in state 1, the basic event waveform is high level. When a transition from low to high level occurs in VL, the finite element state machine changes to state 0; otherwise, it remains unchanged.

[0137] When the finite element state machine is in state 0, the basic event waveform is low level. When a transition from low to high level occurs, the finite element state machine changes to state 1; otherwise, it remains unchanged.

[0138] Secondly, single switch event identification:

[0139] A high-speed clock is used to distinguish the basic event waveform. In each cycle of the high-speed clock, the current state now_state is temporarily stored in the previous state pre_state, and the current basic event waveform level is read out and assigned to pre_state to identify the rising edge transition, falling edge transition and stable high and low level states of the basic event waveform.

[0140] The rising edge transition triggers:

[0141] If pre_state is low and now_state is high, the rising edge transition flag of the single transistor in the status register module is set to 1 and remains so until the controller performs a clear operation via SPI.

[0142] The falling edge transition triggers:

[0143] If pre_state is high and now_state is low, the falling edge transition flag of the single transistor in the status register module is set to 1 and remains so until the controller performs a clear operation via SPI.

[0144] The high / low level trigger:

[0145] If now_state is high, the single-transistor level flag in the status register module is set to 1;

[0146] If now_state is low, the single-transistor level flag in the status register module is set to 0;

[0147] Step 4.2, the multi-tube combination timing identification process is as follows:

[0148] First, a general temporal recognition framework is established, which includes the following general variables:

[0149] The maximum multi-transistor timing state length `max_state_len` is a constant; the effective multi-transistor timing state length `use_state_len` is defined in the configuration register module; `max_state_len` signal variables `signal[max_state_len]` are defined in the configuration register; `signal[0]` to `signal[use_state_len-1]` represent a multi-transistor event, occurring sequentially from `signal[0]` to `signal[use_state_len-1]`, and `signal[0]` to `signal[use_state_len-1]` store the coordinates `index` of the single-transistor events; `Status_register` is the status register of a single switch in the status register module; each single switch event is defined according to the coordinate values ​​in Table 1; for example, V T1 The index = 0 for a single-transistor event triggered by the rising edge indicates that Status_register[0] corresponds to V. T1 Rising edge triggered events, and so on for others;

[0150] Table 1. Coordinate Definitions for Single-Pipe Events

[0151] Then, the valid multi-transistor timing state length is written to the configuration register `use_state_len` via the controller's SPI communication bus, and the single-transistor event index is written sequentially to `signal[0]` to `signal[use_state_len-1]`, thus completing the definition of the multi-transistor event, such as... Figure 8 As shown;

[0152] Finally, a finite element state machine was adopted as the state machine for multi-channel event recognition, and the multi-channel event recognition state machine adopted asynchronous reset. The multi-channel event recognition state machine was set to an idle state, and the event traversal count variable len_temp was defined to count the number of state transitions and was initialized to 0.

[0153] In the idle state: if len_temp is greater than use_state_len, the trigger condition is met and the trigger signal is output; if the Status_register[signal[0]] corresponding to signal[0] is equal to 1, the state machine for recognizing the state multi-transistor event is set to state 1, and len_temp = len_temp + 1; otherwise, it remains unchanged;

[0154] In state 1: if len_temp is greater than use_state_len, the trigger condition is met and the trigger signal is output; if the Status_register[signal[1]] corresponding to signal[1] is equal to 1, the state machine for recognizing state multi-transistor events is set to state 2, len_temp = len_temp + 1; otherwise, it remains unchanged;

[0155] This process continues until len_temp is greater than use_state_len, ultimately achieving multi-tube event triggering by combining the timing sequences of use_state_len single-tube events.

[0156] Step 4.3: Synchronize the single-transistor event and multi-transistor event flags to the status register. The output combination logic in the logic identification module selects the event mode according to the configuration register, reads the flag bit in the status register, and generates an interrupt signal. The interrupt signal triggers the controller to start data acquisition.

[0157] An onboard automatic triggering device for dynamically acquiring inverter status is disclosed. The device includes an isolation conversion circuit, a threshold conversion circuit, an event capture logic unit, a controller, a memory, an analog switching module, an analog-to-digital converter (ADC), and a communication module. The isolation conversion circuit, threshold conversion circuit, and inverter switching transistors are of the same number (six in total). The differential control signal of each switching transistor is converted to a single-ended signal by the isolation conversion circuit, and then passed through the threshold conversion circuit to obtain a dual-threshold comparison trigger pulse. This dual-threshold comparison trigger pulse is transmitted as a basic event to the event capture unit for timing identification to obtain the trigger signal. The system is as follows: a trigger signal is input to the controller, which initiates data acquisition upon triggering an external interrupt; the memory is an on-chip storage unit mounted on the controller bus and interconnected with the controller; the controller is interconnected with the analog-to-digital converter (ADC), which performs signal sampling, holding, quantization, and encoding output; the controller configures and reads data from the ADC and temporarily stores the converted data in the memory's buffer; the output signal of the analog switch module is connected to the input of the ADC, and the analog switch module switches different channels for signal acquisition based on different trigger events; the controller communicates with external devices via the communication module.

[0158] Furthermore, the analog switch module includes seven analog switching devices, each with an 8-channel selector function. The input analog quantities of the analog switching devices include 29 signals from the six switching transistors in the inverter. These 29 signals include six signals for the gate-emitter voltage Vge, six signals for the collector-emitter voltage Vc, six signals for the collector current Ice, six signals for the saturation voltage drop Vce_sat, one signal for the bus voltage, one signal for the bus current, one signal for the U-phase current Iu, one signal for the V-phase current Iv, and one signal for the W-phase current Iw. The signals to be acquired are connected to the analog switch module to achieve data synchronization for multi-channel acquisition. The mapping relationship between analog quantities and analog switching devices is shown in Table 2 below.

[0159] Table 2 Mapping Relationship between Analog Quantities and Analog Switching Devices

[0160]

[0161] like Figure 11 As shown:

[0162] Furthermore, in step 5, before receiving the interrupt trigger input from the logic recognition module, the controller needs to complete the following process:

[0163] Step 5.1: The controller initializes itself and enters the Ethernet communication listening state after initialization. The initialization includes configuring the working modes of the main frequency, GPIO, interrupt, ADC, SPI, IIC, extended memory bus and Ethernet interface.

[0164] Step 5.2: If the acquisition command and parameters are received from the host computer via Ethernet, first write the asynchronous reset flag in the configuration register of the event capture device corresponding to all switching transistors through the SPI bus, stop all current event capture processes and put them in the initial state;

[0165] Step 5.3: Based on the acquisition parameters from the host computer, select the corresponding switch transistor in the threshold conversion module of the host computer via IIC. Switch transistors not mentioned in the acquisition command do not need to be configured and can be ignored.

[0166] Step 5.4: Based on the acquisition parameters from the host computer, select the event capture unit of the corresponding switch transistor on the host computer via the SPI bus, set the configuration register in the event capture unit, set the event capture unit to the disabled state, further set the trigger mode, and trigger the event definition; the switch transistors not involved in the acquisition command do not need to be configured and are ignored directly.

[0167] Step 5.5: Clear the existing external interrupt flags of the controller and reset the external trigger operating mode of the controller;

[0168] Step 5.6: Based on the acquisition parameters from the host computer, configure the startup mode of the analog-to-digital conversion module to external trigger, calculate the sampling rate, conversion accuracy, and sampling channel parameters, and write the values ​​to the registers.

[0169] Step 5.7: Based on the parameters acquired by the host computer, configure the channel selection of the 7 analog switching devices in the analog switching module by controlling the GPIO pin level of the controller;

[0170] Step 5.8: Reset the read / write pointers of the data storage ring buffer and configure the controller's DMA (Direct Memory Access) source and destination addresses;

[0171] Step 5.9: Configure the enable flag bit of the configuration register of the event capture unit corresponding to the switch transistor via the SPI bus. Event capture will then be ready, waiting for the event to be triggered.

[0172] Step 5.10: After the event is triggered, the data collection and storage will be completed automatically. Once completed, the callback parameters will be entered, and the execution result status code will be returned.

[0173] Step 5.11: The controller begins to analyze and process the data, and after obtaining the fault diagnosis conclusion, it sends the result data and the collected raw waveform data to the host computer via Ethernet.

[0174] The controller enables Ethernet receive and transmit interrupts, maps callback functions, and uses callback functions triggered by Ethernet data receive interrupts to receive and parse acquisition commands and parameters from the host computer. The controller configures the registers in the event capture unit via SPI, configures the DAC parameters in the threshold conversion module via IIC, and configures the channel selection of the analog switching device via GPIO; it also accepts commands from the host computer.

Claims

1. An onboard automatic triggering method for dynamically acquiring inverter status, characterized in that, The onboard automatic triggering method includes the following steps: Step 1, obtain the differential control signals of the inverter switching transistors: the differential control signals of the IGBT switching transistors are the gate G and the collector E; Step 2: Input the differential control signal to the isolation conversion circuit for amplitude conditioning and opto-isolation conversion to obtain a single-ended pulse signal; the amplitude conditioning includes scaling and biasing. Step 3: Input the single-ended pulse signal into the threshold transformation circuit for specific threshold feature recognition and filtering anti-interference to obtain the dual threshold comparison trigger pulse; The threshold transformation circuit uses a configurable comparison voltage to identify signal threshold features and obtain a dual threshold comparison trigger pulse. The number of threshold conversion circuits is the same as the number of inverter switching transistors; the threshold conversion circuits sequentially include a multi-channel DAC, a buffer, a high-speed comparator, and a high-speed optocoupler; there are two high-speed optocouplers, and the two high-speed optocouplers are identical; the high-speed comparator includes high-speed comparator A and high-speed comparator B, high-speed comparator A is used to implement comparison triggering on the rising edge, and high-speed comparator B is used to implement comparison triggering on the falling edge. The controller controls the output voltage of the multi-channel DAC via the integrated circuit bus IIC, making the output voltage range 0V-3V; the output voltage of the multi-channel DAC is buffered to become a reference voltage, which is used to compare with the single-ended signal. The single-ended signals at the output of the isolation conversion circuit are connected in parallel and input to the negative terminal of high-speed comparator A and the positive terminal of high-speed comparator B, respectively; the reference voltage is input to the positive terminal of high-speed comparator A and the negative terminal of high-speed comparator B, respectively; when the positive terminal voltages of high-speed comparator A and high-speed comparator B are both greater than the negative terminal voltages, the threshold conversion circuit outputs a high level; otherwise, it outputs a low level. The output signal of high-speed comparator A is input to one of the high-speed optocouplers, and the output signal of high-speed comparator B is input to the other high-speed optocoupler. After the signal is filtered and anti-interference by the high-speed optocouplers, a dual threshold comparison trigger pulse is obtained. The function of the high-speed optocouplers is to isolate and protect the event capture unit, so as to avoid timing misjudgment caused by signal crosstalk in the event capture unit in a harsh electromagnetic environment. Step 4: The dual threshold comparison trigger pulse is transmitted to the event capture unit as the basic event. The event capture unit performs timing identification on the switching transistor to obtain the trigger signal. Step 5: Input the trigger signal to the controller. The controller will start the acquisition after being triggered by an external interrupt.

2. The onboard automatic triggering method according to claim 1, characterized in that, In step 2, the number of isolation conversion circuits is the same as the number of switching transistors; the isolation conversion circuits sequentially include four parts: a differential amplifier module, a voltage bias module, a linear opto-isolation module, and a voltage amplification follower module; The differential amplifier module includes an operational amplifier U89, a proportional setting resistor, a capacitor C219, and ports. The port voltages are Vin+ and Vin-, respectively. The operational amplifier U89 includes U89A and U89B. The proportional setting resistor includes resistors R323, R324, R333, R334, R343, and R349, satisfying R323 + R324 = R333 + R334, and R343 = R349. The port voltage Vin+ is connected in series with R323 and R324. 324, after being superimposed with the bias voltage Vbias, is connected to the positive input terminal of U89A. The positive input terminal of the power supply of U89A is simultaneously connected to ground via a series capacitor C219. The port voltage Vin- is connected in series with R333 and R334, and after passing through resistor R334, it is split into two paths. One path is connected to the negative input terminal of operational amplifier U89A, and the negative terminal of operational amplifier U89A is grounded. The other path is connected to the output terminal of operational amplifier U89A via a series resistor R349, forming a negative feedback loop. The voltage bias module includes resistors R341 and R347; one end of resistor R341 is connected to one end of resistor R347, the other end of resistor R341 is connected to +5V, and the other end of resistor R347 is grounded. After voltage division, the voltage is connected to the positive input terminal of operational amplifier U89B; the output terminal and negative input terminal of U89B are interconnected to form a voltage follower. Operational amplifiers U89B and U89A share the positive and negative input terminals of the power supply. The linear opto-isolation module includes an isolator U85, resistors R327 and R339, and capacitors C223 and C227. The isolator U85 has pins including a positive input terminal IN+, a negative input terminal IN-, a positive output terminal OUT+, a negative output terminal OUT-, a voltage matching region VDD1, a voltage matching region VDD2, a ground isolation region GNG1, and a ground isolation region GND2. One end of resistor R327 is connected in series with one end of resistor R339. The other end of resistor R327 is connected to the output of operational amplifier U89A, and the other end of resistor R339 is connected to digital ground. After a second voltage division, the voltage is grounded after being connected in parallel with capacitor C223 and simultaneously connected to the positive input terminal IN+ of isolator U85. The negative input terminal IN- of isolator U85, the other end of capacitor C223, and ground isolation region GNG1 are all connected to digital ground. Voltage matching region VDD1 is connected to one end of capacitor C227, and the other end of capacitor C227 is connected to digital ground. The voltage amplification and follower module includes an operational amplifier U90A, configuration resistors, capacitors C228 and C233, and a low-pass filter circuit. The configuration resistors include R329, R337, R344, and R351, satisfying R329 = R337 and R344 = R351. The low-pass filter circuit includes capacitor C225 and resistor R331. One end of resistor R329 is connected to the positive output terminal OUT+ of the isolation device U85, and the other end of resistor R329 is connected to the positive input terminal of the operational amplifier U90A. The other end of resistor R329 is connected in series with R344 and then grounded, equivalent to the bias voltage. When set to 0, the positive input terminal of the operational amplifier U90A is connected to ground via a series capacitor C233; one end of resistor R337 is connected to the negative output terminal OUT- of the isolation device U85, and the other end of resistor R337 is connected to the negative input terminal of the operational amplifier U90A, and connected to the output terminal of the operational amplifier U90A via a series resistor R351, forming a feedback path. The negative input terminal of the operational amplifier U90A is also grounded. One end of R331 is connected to the output terminal of the operational amplifier U90A, and the other end of R331 is connected to ground via a series capacitor C225, and the output voltage Vout is generated. The isolation converter circuit processes the differential control signal in the following steps: Step 2.1: The port receives the differential control signal from the switching transistor and converts the differential control signal into a single-ended signal. The operational amplifier U89A reduces the voltage of the single-ended signal by a ratio β1. The voltage range after reduction is -1.2 to 2V. The reduction ratio β1 = R349 / (R323+R324). Step 2.2: The voltage bias function is achieved by setting resistors R341 and R347. The biased voltage range is 0.05V to 3.25V. The bias voltage Vbias = 5*(R341 / (R341+R347)). Step 2.3: By setting resistors R327 and R339, the biased single-ended signal is first reduced by a ratio β2 while ensuring driving capability. The reduced voltage range is 0.025V to 1.625V. Then, it is input to the isolation device U85 for linear opto-isolation. The input range of the isolation device U85 is 0V-2V. The reduction ratio β2 = R327 / (R327+R339). Step 2.4: The single-ended signal after linear opto-isolation is amplified and recovered by operational amplifier U90A according to ratio β3. The amplified voltage range is 0.05V to 3.25V; the amplification ratio β3 = R351 / R329. The voltage amplification and following module cancels the reduction ratio before entering the linear opto-isolation module and enhances the current driving capability to the threshold conversion circuit, ensuring that the current consumption of multiple threshold conversion branches will not cause waveform distortion. Step 2.5, the output voltage of the isolation change circuit is Vout = (Vbias + ((Vin+) - (Vin-)) * β1) * β2 * β3, and the range of Vout is from 0.05V to 3.25V.

3. The onboard automatic triggering method according to claim 1, characterized in that, In step 4, the event capture unit implements event capture based on a programmable logic device; The event capture unit includes an SPI communication interface module, a read / write control timing module, a configuration register module, a status register module, and a logic recognition module. The SPI communication interface module is interconnected with the controller via a synchronous clock Clk, a data line MISO, and a data line MOSI. As a slave device of the SPI, the SPI communication interface module provides a data read / write interface to the controller. Under the tick of the controller's synchronous clock Clk, it serially receives read / write commands, which include read / write identifiers, operation addresses, and operation data information. While responding to the controller's SPI serial communication protocol, the SPI communication interface module controls the read / write control timing module to address and read / write the configuration register module and the status register module. The read / write control timing module is interconnected with the configuration register module and the status register module in an asynchronous read / write mode, which includes an asynchronous clock, a 32-bit data bus, and an 8-bit address bus. The configuration register module and the status register module are implemented using a dual-port RAM approach. Both modules simultaneously provide read / write interface data to the read / write control timing module and the logic identification module, respectively. The logic identification module writes running status flags and data into the status register module, which the read / write control timing module then reads and sends to the controller via the SPI communication interface, forming a bidirectional data interaction. The SPI communication interface module interacts with the SPI Master interface of the controller, and the information exchanged includes reading and writing the contents of the configuration register and the status register. The configuration register module is used to store the controller's configuration parameters for the event capture logic. The configuration parameters include trigger enable, mode selection, and event customization. The status register module stores the recognition status and count of various events from the latching logic recognition module. The status register provides an interface for simultaneous reading and writing by both the logic recognition module and the read / write control timing module. Each module occupies one read / write bus in the dual-port RAM of the status register. The logic recognition module writes event flags triggered in real-time by the differential control signal of the switching transistor. The read / write control timing module writes the controller's clear and manual trigger flags. The controller's clear flag is used to remove the existing trigger status, waiting for and maintaining the new trigger status. The manual trigger flag is only used in debug mode; forced triggering is achieved by actively writing status flags through the controller, used for data acquisition and testing. The priority of manual triggering is higher than that of the logic recognition module. The switching of manual triggering mode is determined by the manual mode control bit in the configuration register. When the manual triggering mode is enabled, the triggering result of the logic recognition module is masked, and no write operation to the status register module occurs. The logic recognition module performs timing recognition based on the dual threshold trigger pulses of the switching transistor, thereby capturing various events of the switching transistor and latching the captured event results into the status register module. The combined output logic of the logic recognition module outputs a trigger interrupt signal to the controller based on the event flag in the current status register module and the trigger enable, mode, and event customization source configuration in the configuration register module.

4. The onboard automatic triggering method according to claim 3, characterized in that, The timing identification includes single-tube timing identification and multi-tube combined timing identification; The single-transistor timing identification first generates a basic event waveform based on the dual-threshold trigger pulse of a single switching transistor, and then realizes the event identification of single-transistor transition triggering and stable triggering based on the rising and falling edges of the basic event waveform of the single-ended signal; the multi-transistor combined timing identification is based on the timing identification of multiple single transistors, and uses a state machine to perform strict timing discrimination based on the transition triggering and stable triggering events of the basic event waveform of multiple transistors, so as to realize the triggering of complex events that meet the timing conditions of multiple transistors. Step 4.1, the single-transistor timing identification process is as follows: First, basic event waveform generation: A single-transistor dual-threshold comparison trigger pulse is input to the logic recognition module. The dual-threshold comparison trigger pulse includes VH and VL. Basic event waveforms are generated through a finite element state machine. The finite element state machine adopts asynchronous reset and is set to an idle state. When the finite element state machine is idle, the basic event waveform is low level; when a transition from low to high level VH occurs, the finite element state machine changes to state 1, otherwise it remains unchanged; When the finite element state machine is in state 1, the basic event waveform is high level. When a transition from low to high level occurs in VL, the finite element state machine changes to state 0; otherwise, it remains unchanged. When the finite element state machine is in state 0, the basic event waveform is low level. When a transition from low to high level occurs, the finite element state machine changes to state 1; otherwise, it remains unchanged. Secondly, single switch event identification: A high-speed clock is used to distinguish the basic event waveform. In each cycle of the high-speed clock, now_state is temporarily stored in pre_state, and the current basic event waveform level is read out and assigned to pre_state to identify the rising edge transition, falling edge transition and stable state of high and low level of the basic event waveform. The rising edge transition triggers: If pre_state is low and now_state is high, the rising edge transition flag of the single transistor in the status register module is set to 1 and remains so until the controller performs a clear operation via SPI. The falling edge transition triggers: If pre_state is high and now_state is low, the falling edge transition flag of the single transistor in the status register module is set to 1 and remains so until the controller performs a clear operation via SPI. The high / low level trigger: If now_state is high, the single-transistor level flag in the status register module is set to 1; If now_state is low, the single-transistor level flag in the status register module is set to 0; Step 4.2, the multi-tube combination timing identification process is as follows: First, a general temporal recognition framework is established, which includes the following general variables: The maximum multi-transistor timing state length max_state_len is a constant; the effective multi-transistor timing state length use_state_len is defined in the configuration register module; max_state_len signal variables signal[max_state_len] are defined in the configuration register; signal[0] to signal[use_state_len-1] represent a multi-transistor event, which occurs in the order of signal[0] to signal[use_state_len-1]. The coordinate index of the single-transistor event is stored in signal[0] to signal[use_state_len-1]. Status_register is a single switch status register in the status register module. Then, the valid multi-transistor timing state length is written to the use_state_len in the configuration register through the controller's SPI communication bus, and the single-transistor event index is written to signal[0] to signal[use_state_len-1] in sequence to complete the definition of multi-transistor events; Ultimately, a finite element state machine was adopted as the state machine for multi-transistor event recognition, and the multi-transistor event recognition state machine adopted asynchronous reset. Set the multi-channel event recognition state machine to the idle state, define the event traversal count variable len_temp to count the number of state transitions, and assign an initial value of 0; In the idle state: if len_temp is greater than use_state_len, the trigger condition is met, and a trigger signal is output; If the Status_register[signal[0]] corresponding to signal[0] is equal to 1, the recognition state machine of the state multi-transistor event is set to state 1, and len_temp = len_temp + 1; otherwise, it remains unchanged. In state 1: if len_temp is greater than use_state_len, the trigger condition is met, and the trigger signal is output; If the Status_register[signal[1]] corresponding to signal[1] is equal to 1, the state machine for recognizing the state multi-transistor event is set to state 2, and len_temp = len_temp + 1; otherwise, it remains unchanged. This process continues until len_temp is greater than use_state_len, ultimately achieving multi-tube event triggering by combining the timing sequences of use_state_len single-tube events. Step 4.3: Synchronize the single-transistor event and multi-transistor event flags to the status register. The output combination logic in the logic identification module selects the event mode according to the configuration register, reads the flag bit in the status register, and generates an interrupt signal. The interrupt signal triggers the controller to start data acquisition.

5. The onboard automatic triggering method according to claim 1, characterized in that, In step 5, before receiving the interrupt trigger from the logic recognition module, the controller needs to complete the following process: Step 5.1: The controller initializes itself and enters the Ethernet communication listening state after initialization. The initialization includes configuring the working modes of the main frequency, GPIO, interrupt, ADC, SPI, IIC, extended memory bus and Ethernet interface. Step 5.2: If the acquisition command and parameters are received from the host computer via Ethernet, first write the asynchronous reset flag in the configuration register of the event capture device corresponding to all switching transistors through the SPI bus, stop all current event capture processes and put them in the initial state; Step 5.3: Based on the acquisition parameters from the host computer, select the corresponding switch transistor in the threshold conversion module of the host computer via IIC. Switch transistors not mentioned in the acquisition command do not need to be configured and can be ignored. Step 5.4: Based on the acquisition parameters from the host computer, select the event capture unit of the corresponding switch transistor on the host computer via the SPI bus, set the configuration register in the event capture unit, set the event capture unit to the disabled state, further set the trigger mode, and trigger the event definition; the switch transistors not involved in the acquisition command do not need to be configured and are ignored directly. Step 5.5: Clear the existing external interrupt flags of the controller and reset the external trigger operating mode of the controller; Step 5.6: Based on the acquisition parameters from the host computer, configure the startup mode of the analog-to-digital conversion module to external trigger, calculate the sampling rate, conversion accuracy, and sampling channel parameters, and write the values ​​to the registers. Step 5.7: Based on the parameters acquired by the host computer, configure the channel selection of the 7 analog switching devices in the analog switching module by controlling the GPIO pin level of the controller; Step 5.8: Reset the read / write pointers of the data storage ring buffer and configure the controller's DMA (Direct Memory Access) source and destination addresses; Step 5.9: Configure the enable flag bit of the configuration register of the event capture unit corresponding to the switch transistor via the SPI bus. Event capture will then be ready, waiting for the event to be triggered. Step 5.10: After the event is triggered, the data collection and storage will be completed automatically. Once completed, the callback parameters will be entered, and the execution result status code will be returned. Step 5.11: The controller begins to analyze and process the data, and after obtaining the fault diagnosis conclusion, it sends the result data and the collected raw waveform data to the host computer via Ethernet. The controller enables Ethernet receive and transmit interrupts, maps callback functions, and uses callback functions triggered by Ethernet data receive interrupts to receive and parse acquisition commands and parameters from the host computer. The controller configures the registers in the event capture unit via SPI, configures the DAC parameters in the threshold conversion module via IIC, and configures the channel selection of the analog switching device via GPIO; it also accepts commands from the host computer.

6. An onboard automatic triggering device for performing the method according to any one of claims 1 to 5, characterized in that, The onboard automatic triggering device includes an isolation conversion circuit, a threshold conversion circuit, an event capture logic unit, a controller, a memory, an analog switch module, an analog-to-digital conversion module, and a communication module. The isolation conversion circuit, the threshold conversion circuit, and the number of inverter switching transistors are the same, with six inverter switching transistors. The differential control signal of each switching transistor is converted into a single-ended signal by the isolation conversion circuit, and then passed through the threshold conversion circuit to obtain a double threshold comparison trigger pulse. The double threshold comparison trigger pulse is transmitted as a basic event to the event capture unit for timing identification to obtain a trigger signal. The trigger signal is input to the controller, and the controller starts acquisition after being triggered by an external interrupt. The memory is an on-chip storage unit mounted on the controller bus, and it is interconnected with the controller. The controller is interconnected with the analog-to-digital converter (ADC), which performs signal sampling, holding, quantization, and encoding output. The controller configures the ADC and reads data from it, and temporarily stores the converted data in the memory's buffer. The output signal of the analog switch module is connected to the input terminal of the ADC, and the analog switch module switches different channels for signal acquisition based on different trigger events. The controller communicates with external devices through the communication module.

7. The onboard automatic triggering device according to claim 6, characterized in that, The analog switch module includes 7 analog switch devices, each with an 8-channel selector function; the input analog quantities of the analog switch devices include 29 signals from the 6 switching transistors in the inverter; The 29 signals include 6 signals of gate-emitter voltage Vge, 6 signals of collector-emitter voltage Vc, 6 signals of collector current Ice, 6 signals of saturation voltage drop Vce_sat, 1 signal of bus voltage, 1 signal of bus current, 1 signal of U-phase current Iu, 1 signal of V-phase current Iv and 1 signal of W-phase current Iw; The signal to be acquired is connected to the analog switch module to achieve data synchronization of multi-channel acquisition.

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