Chip test data management system and method based on big data analysis

Abstract

The invention relates to the field of chip testing, in particular to a chip testing data management system and method based on big data analysis, and the system comprises a testing circuit module, a time sequence analysis module, a scanning chain module, a signal generation module and a fault positioning module, the testing circuit module is used for generating a scanning function and recording an output signal; the time sequence analysis module is used for carrying out time sequence analysis on an input and output function, the scan chain module is used for connecting a test chain in series and generating a scan thread, the signal generation module is used for calculating dynamic power consumption, and the fault positioning module is used for testing a chip and finding a fault core. The performance indexes of the chip are accurately evaluated, testability and stability of the chip are ensured, unnecessary repeated tests are reduced, the test coverage rate is improved, time and resource cost required by the tests are reduced, meanwhile, the test precision and accuracy are improved, and the quality and reliability of chip products are ensured.

Description

Technical Field

[0001] The present invention relates to the field of chip testing, and specifically to a chip test data management system and method based on big data analysis. Background Technique

[0002] Various defects may occur during the chip production process, such as parasitic transistor effects, oxide layer penetration, surface defects, and electromigration. Therefore, it is necessary to test and verify the functions, performance, stability, etc. of integrated circuit chips to ensure the quality and reliability of the chips.

[0003] Most of the currently produced chips are system-on-chips (SOCs) with multiple register cores, and the scan chain design is often adopted to connect the cores in series for the test process to obtain a higher fault coverage rate. However, verifying the scan chain requires a large amount of test data support. When there are more chip cores, the test delay and complexity of the traditional scan chain increase significantly, and as the signal jumps between high and low levels, the circuit power consumption changes dynamically. The scan chain design is prone to cause capacitor depletion, affecting the test efficiency.

[0004] In addition, the physical qualities of each chip are different when leaving the factory. Some chips lack test value, while some other chips have different processing speeds and response times. If the chips are tested according to the same standard, it may cause the scan rate to be higher than the response rate, resulting in signal crosstalk, interfering with the test data, and reducing the accuracy of chip testing. Summary of the Invention

[0005] The purpose of the present invention is to provide a chip test data management system and method based on big data analysis to solve the problems raised in the above background technique.

[0006] To solve the above technical problems, the present invention provides the following technical solution: A chip test data management system based on big data analysis, including: a test circuit module, a timing analysis module, a scan chain module, a signal generation module, and a fault location module;

[0007] The test circuit module is used to randomly generate a scan function with a fixed value range at the input port of the chip, adjust the voltage of the input high-level signal according to the scan function, input the voltage-adjusted signal into the chip to be tested, set signal reading devices at the pins of each output port of the chip, record the output signals of each output port, and obtain the port output function;

[0008] The timing analysis module is used to compare the port output function and the standard output function, and to inspect the constant voltage ports and unstable ports among them. When the number of constant voltage ports or unstable ports exceeds the preset value and reaches a fixed ratio, the chip is regarded as a defective product, and the remaining detection processes are skipped. Then, timing analysis is performed on the scan function and the output function, and the correlation function is obtained from the analysis results. The time shift when the correlation function takes the minimum value is recorded as the port response delay, and the integral of the correlation function within the domain is used as the scan error of the chip.

[0009] The scan chain module is used to connect the core registers of the chip under test in series to form a test chain. The number of cores included in each test chain decreases in a preset multiple. Each test chain constructs an independent scan interval, randomly samples the scan function, generates a set of test vectors for each test chain. For each set of test vectors, the vector with the smallest number of identical code elements between adjacent vectors is taken as the first vector, and all test vectors in the group are arranged according to the similarity to the first vector to obtain the scan thread.

[0010] The signal generation module is used to, in one scan thread, determine the ports where the irrelevant bits of the input test vector and the previous test vector are located, freeze the ports of the irrelevant bits, calculate the dynamic power consumption during the test process of each scan thread, select the scan thread with the minimum power consumption to input the test chain. During the input process of the scan thread, ensure that the input interval of each test vector is greater than the maximum port response delay.

[0011] The fault location module is used to compare the output result of the chip with the expected input result, calculate the bit error rate of each test chain. When the total bit error rate of the test chain is less than the preset value, it is judged that all cores in the test chain are qualified. When the bit error rate is higher than the preset value, the test chain is unchained to take out the cores, and a sub-test chain is constructed to perform the test again until the faulty core is found.

[0012] Further, the test circuit module includes: a circuit voltage regulation unit and a signal reading unit;

[0013] The circuit voltage regulation unit is used to adjust the voltage connected to the chip input port according to the value of the scan function until the clock of the scan function generator reaches zero.

[0014] The signal reading unit is used to detect the voltage at the chip output port and record the voltage change function.

[0015] Further, the timing analysis module includes: an output comparison unit and a correlation fitting unit;

[0016] The output comparison unit is used to inspect the constant voltage ports and unstable ports when the high level is input, compare with the designed ports of the chip, and identify defective chips.

[0017] The associated fitting unit is used for the timing analysis of the scanning function and the output function, and outputs the response delay of the output port and the scanning error.

[0018] Further, the scan chain module includes: a core series unit, a test vector unit, and a scan circuit unit;

[0019] The core series unit is used to take out or isolate the chip core, and make the chip cores be connected in series as a test chain according to the multiple rule;

[0020] The test vector unit is used to generate test vectors, perform similarity analysis on the test vectors, arrange all the test vectors according to the similarity, and obtain the scan thread;

[0021] The scan circuit unit is used to build a hardware platform for the scan thread to the test chain port, and predict the output result of the scan thread.

[0022] Further, the signal generation module includes: an interface latch unit, a dynamic power consumption unit, and a delay scan unit;

[0023] The interface latch unit is used to calculate the irrelevant bits between the test vectors, and perform input latching on the adjacent irrelevant bits input to the same port;

[0024] The dynamic power consumption unit is used to calculate the dynamic power consumption during the test according to the ratio of high and low levels and the switching frequency in the test vectors;

[0025] The delay scan unit is used to adjust the time interval between adjacent test signals input to the chip port, so that adjacent test signals do not cause crosstalk.

[0026] Further, the fault location module includes: a symbol comparison unit and a loop test unit;

[0027] The symbol comparison unit is used to compare the actual output result and the expected output result of the chip, and judge the bit error rate of the test chain;

[0028] The loop test unit is used to, when the bit error rate of the test chain is unqualified, unchain the unqualified test chain and test again until the faulty core in the chip is found.

[0029] A chip test data management method based on big data analysis includes the following steps:

[0030] Step S1. Build a chip test platform, randomly generate a scan function with a fixed value range, regulate the voltage of the high-level signal according to the scan function, connect the regulated voltage signal to the input port of the chip, until the clock of the scan signal generator returns to zero, record the output voltage of each port at the chip output port, and obtain the port output function;

[0031] Step S2. Inspect the constant voltage ports and unstable ports when a high-level input is applied, compare them with the designed ports of the chip. Chips that do not meet the design requirements are skipped from the remaining detection process. For chips that meet the requirements, perform a timing analysis on the output function of each port and the scanning function to obtain a correlation function, and obtain the port response delay based on the timing offset when the correlation function reaches the minimum value.

[0032] Step S3. Take out the cores of the chips to be tested and connect them in series as a test chain. The number of cores included in each test chain decreases according to a preset series connection multiple. Generate a set of test vectors randomly for each test chain. For each set of test vectors, use the vector with the fewest adjacent irrelevant bits as the first vector, and arrange the vectors within the group in descending order of similarity to the first vector to obtain a scanning thread.

[0033] Step S4. Calculate the dynamic power consumption during the test process, select the scanning thread with the minimum power consumption for chip testing, record the irrelevant bits of adjacent vectors in a single scanning thread, and latch the irrelevant bits input to the same port.

[0034] Step S5. Compare the actual output sequence and the standard output sequence of the test chain, calculate the bit error rate of each test chain. When the bit error rate is unqualified, unchain the test chain, construct a sub-test chain and test again until the faulty core is located.

[0035] Further, Step S1 includes:

[0036] Step S11. Construct a chip test platform. The test platform includes: a signal generator, a signal collector, an ATE tester, a load board, an adjustable power supply, and a chip fixture. Generate a scanning function F(t) with a domain of [0, t0] and a range of [0, Q0] in the signal generator, where t0 represents the clock length of the signal generator, Q0 represents the maximum voltage of the high-level signal, and t represents time.

[0037] Step S12. Adjust the voltage of the high-level signal according to the scanning function to make the input voltage value equal to the scanning function until the clock of the scanning signal generator reaches zero. Collect the output signals from each output port of the chip until the signal at the output port no longer changes or the output times out, to obtain the output function of each port.

[0038] Further, Step S2 includes:

[0039] Step S21. Inspect the ports whose output signal voltages are constantly at a specified value as constant voltage ports, and the ports with unstable signal changes as unstable ports. Record the positions and quantities of the constant voltage ports and unstable ports, and compare them with the designed ports of the chip. When the quantity of the constant voltage ports or unstable ports exceeds the design capacity and the excess capacity reaches a fixed proportion of the design capacity, the chip is regarded as a non-conforming product and skipped from the remaining detection process.

[0040] Step S22. For the chips that meet the requirements, perform the timing analysis of the output function and the scan function in the following manner to obtain the correlation function:

[0041]

[0042] Among them, W(t) represents the correlation function, G(t) represents the output function of the port when the input is F(t), Tr is the clock length of the signal generator, and e is the base of the natural logarithm;

[0043] Step S23. Calculate the minimum value of the correlation function W(t), record the time difference between the value of the independent variable t when the minimum value is taken and the starting moment as the port response delay, record the integral of the correlation function within the domain as the scan error of the chip, and store the tested data in the database.

[0044] Further, Step S3 includes:

[0045] Step S31. Adopt the method of taking out or isolating to serially connect the core registers in the chip. Preset the serial connection multiple k, take out n / k cores for one serial connection, where n is the total number of cores in the chip, round up n / k, and form a test chain. Take out n / k cores again from the remaining chip cores for one serial connection, and repeat the serial connection operation until all cores are included in the test chain;

[0046] Step S32. For each test chain, randomly generate a one-dimensional test vector with m columns, where m is the number of input interfaces in the test chain, and group every x test vectors into a group, where x is the preset test length;

[0047] Step S33. For each group of test vectors, calculate the number of same-position code elements between each vector and the adjacent vectors in the group as the number of irrelevant bits of the vector, select the vector with the smallest number of irrelevant bits as the first vector, and arrange all the test vectors in the group in descending order of similarity to the first vector. After the arrangement, the scan thread is obtained.

[0048] Further, Step S4 includes:

[0049] Step S41. Calculate the dynamic power consumption according to the level switching state of each port in the scan thread:

[0050]

[0051] Among them, P is the tested dynamic power consumption, Vd is the voltage of the standard high-level signal, f is the input frequency of the test vector, a i is the number of times the signal of the i-th input interface flips, and C i is the node capacitance of the i-th input interface;

[0052] Step S42. Select the scan thread with the minimum dynamic power consumption, and input each test vector in the scan thread into the test chain one by one, with the input interval being higher than the port response delay. During the input process, when the levels of adjacent test vectors input to the same port are the same, freeze the port until the level of the input port changes.

[0053] Further, step S5 includes:

[0054] Step S51. Obtain the actual output sequence of signals for each test chain, obtain the standard output sequence based on the test results of the reference chip, calculate the bit error rate between the actual output sequence and the standard output sequence. When the bit error rate is lower than the preset value, it means that the test of the test chain passes. After all the test chains in the chip pass, restore the serial connection state of the core and enter the chip packaging process;

[0055] Step S52. When the bit error rate is higher than the preset value, unchain the test chain, construct a sub-test chain, take out the core according to the method of step S32, and then test each sub-test chain again until all the chip cores with a bit error rate higher than the preset value are found and marked as faulty cores.

[0056] Compared with the prior art, the beneficial effects achieved by the present invention are:

[0057] 1. The present invention performs circuit voltage regulation through a randomly generated scan function, conducts timing analysis on the scan function and the output function to obtain a correlation function, thereby obtaining the test delay and scan error of the chip, avoiding timing chaos during the test process, being able to evaluate the performance indicators of the chip, removing chips that do not meet the requirements in advance, and ensuring the testability and stability of the chip.

[0058] 2. The present invention can connect the core registers of the chip to be tested in series to form a test chain, with the number of serial connections decreasing in multiples, randomly select test vectors, compress the test vectors through a similarity algorithm, and intelligently select the order of test vectors to improve the test efficiency, which can reduce unnecessary repeated tests and increase the test coverage rate, and reduce the time and resource costs required for the test.

[0059] 3. The present invention can freeze the irrelevant bits when adjacent test vectors are input, calculate the dynamic power consumption during the test process according to the distribution of the unfrozen code elements of the test vectors, select the test vector with the minimum power consumption for scanning, unchain the test chain with a high scan bit error rate and test it again until the faulty core is found, which can improve the test accuracy and ensure a comprehensive detection of the chip performance and functions, avoid the influence of insufficient power consumption on the test process, and ensure the quality and reliability of the chip product. Description of the Drawings

[0060] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the present invention and do not constitute a limitation to the present invention. In the drawings:

[0061] Figure 1 is a schematic structural diagram of a chip test data management system based on big data analysis according to the present invention;

[0062] Figure 2 is a schematic diagram of the steps of a chip test data management method based on big data analysis according to the present invention. Detailed Embodiments

[0063] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0064] Please refer to Figure 1 , the present invention provides a technical solution: a chip test data management system based on big data analysis, including: a test circuit module, a timing analysis module, a scan chain module, a signal generation module, and a fault location module;

[0065] The test circuit module is used to randomly generate a scan function with a fixed value range at the input port of the chip, adjust the voltage of the input high-level signal according to the scan function, input the voltage-adjusted signal into the chip to be tested, set signal reading devices at the pins of each output port of the chip, record the output signals of each output port, and obtain a port output function;

[0066] The timing analysis module is used to compare the port output function and the standard output function, check the constant voltage ports and unstable ports among them. When the number of constant voltage ports or unstable ports exceeds a preset value and reaches a fixed ratio, the chip is regarded as a non-conforming product, skipping the remaining detection process, performing timing analysis on the scan function and the output function, obtaining an association function from the analysis results, recording the time shift when the association function takes the minimum value as the port response time delay, and taking the integral of the association function within the domain as the scan error of the chip;

[0067] The scan chain module is used to connect the core registers of the chip to be tested in series as a test chain. The number of cores included in each test chain decreases in a preset multiple. Each test chain constructs an independent scan interval, randomly samples the scan function, generates a set of test vectors for each test chain, for each set of test vectors, takes the vector with the smallest number of identical code elements between adjacent vectors as the first vector, and arranges all the test vectors in the group according to the similarity to the first vector to obtain a scan thread;

[0068] The signal generation module is used to, in one scan thread, determine the ports where the irrelevant bits of the input test vector and the previous test vector are located, freeze the ports of the irrelevant bits, calculate the dynamic power consumption during the test process of each scan thread, select the scan thread with the minimum power consumption to input the test chain, and ensure that the input interval of each test vector is greater than the maximum port response delay during the input process of the scan thread;

[0069] The fault location module is used to compare the output result of the chip with the expected input result, calculate the bit error rate of each test chain, determine that all cores in the test chain are qualified when the total bit error rate of the test chain is less than the preset value, and when the bit error rate is higher than the preset value, unchain the test chain to take out the cores, construct a sub-test chain to conduct tests again until the faulty core is found.

[0070] Further, the test circuit module includes: a circuit voltage regulation unit and a signal reading unit;

[0071] The circuit voltage regulation unit is used to adjust the voltage connected to the chip input port according to the value of the scan function until the clock of the scan function generator returns to zero;

[0072] The signal reading unit is used to detect the voltage at the chip output port and record the voltage change function.

[0073] Further, the timing analysis module includes: an output comparison unit and a correlation fitting unit;

[0074] The output comparison unit is used to check the constant voltage ports and unstable ports when the high level is input, compare them with the design ports of the chip, and identify unqualified chips;

[0075] The correlation fitting unit is used for the timing analysis of the scan function and the output function, and outputs the port response delay and scan error.

[0076] Further, the scan chain module includes: a core series connection unit, a test vector unit, and a scan circuit unit;

[0077] The core series connection unit is used to take out or isolate the chip cores, and connect the chip cores in series as a test chain according to the multiple rule;

[0078] The test vector unit is used to generate test vectors, conduct similarity analysis on the test vectors, arrange all the test vectors according to the similarity, and obtain scan threads;

[0079] The scan circuit unit is used to build a hardware platform for the scan thread to the test chain ports and predict the output result of the scan thread.

[0080] Further, the signal generation module includes: an interface latching unit, a dynamic power consumption unit, and a delay scan unit;

[0081] The interface latching unit is used to calculate the don't-care bits between test vectors and latch the input of adjacent don't-care bits input to the same port.

[0082] The dynamic power consumption unit is used to calculate the dynamic power consumption during the test according to the ratio of high and low levels and the switching frequency in the test vector.

[0083] The delay scan unit is used to adjust the time interval between adjacent test signals input to the chip port so that adjacent test signals do not cause crosstalk.

[0084] Furthermore, the fault location module includes: a symbol comparison unit and a loop test unit;

[0085] The symbol comparison unit is used to compare the actual output result and the expected output result of the chip to judge the bit error rate of the test chain.

[0086] The loop test unit is used to unchain the unqualified test chain and retest it when the bit error rate of the test chain is unqualified until the fault core in the chip is found.

[0087] As Figure 2 shown, the chip test data management method based on big data analysis includes the following steps:

[0088] Step S1. Build a chip test platform, randomly generate a scan function with a fixed value range, adjust the voltage of the high-level signal according to the scan function, connect the regulated signal to the input port of the chip, until the clock of the scan signal generator returns to zero, and record the output voltage of each port at the chip output port to obtain the port output function.

[0089] Step S2. Check the constant voltage ports and unstable ports when inputting high levels, compare them with the designed ports of the chip, skip the remaining detection processes for the chips that do not meet the design requirements, and for the chips that meet the requirements, perform timing analysis on the output function of each port and the scan function to obtain the correlation function, and obtain the port response delay based on the timing offset when the correlation function takes the minimum value.

[0090] Step S3. Take out the cores of the chips to be tested and connect them in series to form a test chain. The number of cores included in each test chain decreases according to a preset series connection multiple. Randomly generate a set of test vectors for each test chain. For each set of test vectors, take the vector with the fewest adjacent don't-care bits as the first vector, and arrange the vectors in the group in descending order of similarity to the first vector to obtain the scan thread.

[0091] Step S4. Calculate the dynamic power consumption during the test, select the scan thread with the minimum power consumption for chip testing, record the don't-care bits between adjacent vectors in a single scan thread, and latch the don't-care bits input to the same port.

[0092] Step S5. Compare the actual output sequence and the standard output sequence of the test chain, calculate the bit error rate of each test chain. When the bit error rate is unqualified, unchain the test chain, construct a sub-test chain and test again until the core of the fault is located.

[0093] Further, step S1 includes:

[0094] Step S11. Construct a chip test platform, which includes: a signal generator, a signal collector, an ATE tester, a load board, an adjustable power supply, and a chip fixture. Generate a scanning function F(t) with a domain of [0, t0] and a range of [0, Q0] in the signal generator, where t0 represents the clock length of the signal generator, Q0 represents the maximum voltage of the high-level signal, and t represents time;

[0095] Step S12. Adjust the voltage of the high-level signal according to the scanning function to make the input voltage value equal to the scanning function until the clock of the scanning signal generator returns to zero. Collect the output signals from each output port of the chip until the signal at the output port no longer changes or the output times out, and obtain the output function of each port.

[0096] Further, step S2 includes:

[0097] Step S21. Inspect the ports where the voltage of all output signals is constantly a fixed value as constant voltage ports, and the ports with unstable signal changes as non-stable ports. Record the positions and quantities of the constant voltage ports and non-stable ports, and compare them with the designed ports of the chip. When the quantity of the constant voltage ports or non-stable ports exceeds the designed capacity and the excess capacity reaches a fixed proportion of the designed capacity, regard the chip as a non-conforming product and skip the remaining detection processes;

[0098] Step S22. For the chips that meet the requirements, perform the timing analysis of the output function and the scanning function in the following way to obtain the correlation function:

[0099]

[0100] Among them, W(t) represents the correlation function, G(t) represents the output function of the port when the input is F(t), Tr is the clock length of the signal generator, and e is the base of the natural logarithm;

[0101] Step S23. Calculate the minimum value of the correlation function W(t), record the time difference between the value of the independent variable t when the minimum value is taken and the starting moment as the port response delay, record the integral of the correlation function within the domain as the scanning error of the chip, and store the tested data in the database.

[0102] Further, step S3 includes:

[0103] Step S31. Adopt the method of taking out or isolating to connect the core registers in the chip in series. Preset the serial connection multiple k, take out n / k cores for one-time serial connection, where n is the number of all cores in the chip, and round up n / k to form a test chain. Take out n / k cores from the remaining chip cores for one-time serial connection again, and repeat the serial connection operation until all cores are incorporated into the test chain;

[0104] Step S32. For each test chain, randomly generate a one-dimensional test vector of m columns, where m is the number of input interfaces in the test chain. Every x test vectors are grouped into one group, and x is the preset test length;

[0105] Step S33. For each group of test vectors, calculate the number of same-position code elements between each vector and the adjacent vectors in the group as the number of irrelevant bits of the vector. Select the vector with the smallest number of irrelevant bits as the first vector, and arrange all the test vectors in the group in descending order according to the similarity with the first vector. After the arrangement, the scan thread is obtained.

[0106] Further, step S4 includes:

[0107] Step S41. Calculate the dynamic power consumption according to the level switching state of each port in the scan thread:

[0108]

[0109] Among them, P is the dynamic power consumption of the test, Vd is the voltage of the standard high-level signal, f is the input frequency of the test vector, a i is the number of times the signal of the i-th input interface flips, and C i is the node capacitance of the i-th input interface;

[0110] Step S42. Select the scan thread with the minimum dynamic power consumption, and input each test vector in the scan thread into the test chain one by one. The input interval is higher than the port response delay. During the input process, when the levels of adjacent test vectors input to the same port are the same, freeze the port until the level of the input port changes.

[0111] Further, step S5 includes:

[0112] Step S51. Obtain the actual output sequence of signals of each test chain, get the standard output sequence according to the test results of the reference chip, and calculate the bit error rate of the actual output sequence and the standard output sequence. When the bit error rate is lower than the preset value, it means that the test of the test chain passes. After all the test chains in the chip pass, restore the serial connection state of the cores and enter the chip packaging process;

[0113] Step S52. When the bit error rate is higher than the preset value, unchain the test chain, construct a sub-test chain, after taking out the core according to the method of step S32, test each sub-test chain again until all the chip cores with a bit error rate higher than the preset value are found and marked as faulty cores.

[0114] Embodiment: The chip to be tested has 8 cores, and the preset multiple is 2, so 4 test chains are constructed, with the number of cores being 4, 2, 1, and 1 respectively. Among them, the 4-core test chain has 7 input ports, and the 3 test vectors generated by the scan thread with the minimum dynamic power consumption are [1011010], [0101001], and [1001101] respectively, and the dynamic power consumption is 0.5W. Input the test vectors into the ports one by one, the level state of port 4 is continuously latched, the output signal sequence is obtained, and after comparing with the standard signal sequence, the bit error rate is 0, indicating that the test chain passes the test.

[0115] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device.

[0116] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A chip test data management method based on big data analysis, characterized in that: The method comprises the following steps: Step S1. Build a chip test platform, randomly generate a scanning function with a fixed value range, adjust the voltage of the high-level signal according to the scanning function, connect the voltage-adjusted signal to the input port of the chip until the clock of the scanning signal generator returns to zero, record the output voltage of each port at the chip output port, and obtain the port output function; Step S2. Check the constant voltage port and the unstable port when the high level input is applied, and compare them with the designed port of the chip. The chip that does not meet the design requirements will skip the remaining detection process. For the chip that meets the requirements, the output function of each port and the scanning function are analyzed in timing to obtain the correlation function, and the port response delay is obtained by the timing offset when the correlation function takes the minimum value; Step S3. Take out the cores of the chip to be tested and connect them in series as a test chain. The number of cores contained in each test chain decreases according to the preset series multiple. A group of test vectors is randomly generated for each test chain. For each group of test vectors, the vector with the least adjacent irrelevant bits is used as the first vector. The vectors in the group are arranged in descending order according to the similarity with the first vector to obtain a scanning thread. Step S4. Calculate the dynamic power consumption during the test, select the scan thread with the lowest power consumption to perform chip testing, record the irrelevant bits of adjacent vectors in a single scan thread, and latch the irrelevant bits input to the same port; Step S5. Compare the actual output sequence of the test chain with the standard output sequence, calculate the bit error rate of each test chain, and if the bit error rate is unqualified, unlink the test chain, build a sub-test chain, and test again until the faulty core is located.

2. The chip test data management method based on big data analysis according to claim 1, characterized in that: Step S1 includes: Step S11. Construct a chip test platform, which includes: a signal generator, a signal collector, an ATE test machine, a load board, an adjustable power supply and a chip fixture, and generate a scanning function F(t) with a domain of [0, t0] and a range of [0, Q0] in the signal generator, where t0 represents the clock length of the signal generator, Q0 represents the maximum voltage of the high-level signal, and t represents time; Step S12. Adjust the voltage of the high-level signal according to the scanning function so that the input voltage value is equal to the scanning function until the clock of the scanning signal generator returns to zero, collect output signals from each output port of the chip until the signal of the output port no longer changes or the output times out, and obtain the output function of each port.

3. The chip test data management method based on big data analysis according to claim 2, characterized in that: Step S2 includes: Step S21. Check that the voltage of all output signals is constant. The customized ports are regarded as constant voltage ports, and the ports with unstable signal changes are regarded as unstable ports. The positions and numbers of the constant voltage ports and unstable ports are recorded and compared with the designed ports of the chip. When the number of constant voltage ports or unstable ports exceeds the designed capacity, and the excess capacity reaches a fixed proportion of the designed capacity, the chip is regarded as a failed product and the remaining inspection process is skipped. Step S22. For chips that meet the requirements, perform timing analysis of the output function and the scanning function in the following manner to obtain a correlation function: Where W(t) represents the correlation function, G(t) represents the output function of the port when the input is F(t), Tr is the clock length of the signal generator, and e is the base of the natural logarithm; Step S23. Calculate the minimum value of the correlation function W(t), record the time difference between the value of the independent variable t and the starting time when the minimum value is taken as the port response delay, and record the integral of the correlation function within the definition domain as the scanning error of the chip, and store the tested data in the database.

4. The chip test data management method based on big data analysis according to claim 3 is characterized in that: Step S3 includes: Step S31. The core registers in the chip are serially connected by taking out or isolating them, and a serial connection multiple k is preset. n / k cores are taken out for serial connection, where n is the number of all cores in the chip, and n / k is rounded up to form a test chain. n / k cores are taken out again from the remaining chip cores for serial connection, and the serial connection operation is repeated until all cores are included in the test chain. Step S32. For each test chain, randomly generate m columns of one-dimensional test vectors, where m is the number of input interfaces in the test chain, and every x test vectors are grouped into a group, where x is the preset test length; Step S33. For each group of test vectors, calculate the number of code elements in the same position between each vector and the adjacent vectors in the group as the number of irrelevant bits of the vector, select the vector with the smallest number of irrelevant bits as the first vector, and arrange all test vectors in the group in descending order of similarity with the first vector. After the arrangement is completed, obtain the scanning thread.

5. The chip test data management method based on big data analysis according to claim 4 is characterized in that: Step S4 includes: Step S41. Calculate the dynamic power consumption according to the level switching state of each port in the scanning thread: Where P is the dynamic power consumption of the test, Vd is the voltage of the standard high-level signal, f is the input frequency of the test vector, and a i is the number of times the i-th input interface signal flips, C i is the node capacitance of the i-th input interface; Step S42. Select the scan thread with the smallest dynamic power consumption, input each test vector in the scan thread into the test chain one by one, and the input interval is higher than the port response delay. During the input process, when the levels of adjacent test vectors input to the same port are the same, freeze the port until the level of the input port changes; Step S5 includes: Step S51. Obtain the actual output sequence of the signal of each test chain, obtain the standard output sequence according to the test result of the reference chip, calculate the bit error rate of the actual output sequence and the standard output sequence, and when the bit error rate is lower than the preset value, it means that the test chain has passed the test. After all the test chains in the chip have passed, the core serial connection state is restored and the chip packaging process is entered; Step S52. When the bit error rate is higher than the preset value, the test chain is unlinked and a sub-test chain is constructed. After the core is taken out according to the method of step S32, each sub-test chain is tested again until all chip cores with bit error rates higher than the preset value are found and marked as faulty cores.

6. A chip test data management system based on big data analysis, characterized in that: The system includes the following modules: a test circuit module, a timing analysis module, a scan chain module, a signal generation module and a fault location module; The test circuit module is used to randomly generate a scanning function with a fixed value range at the input port of the chip, adjust the voltage of the input high-level signal according to the scanning function, input the voltage-adjusted signal to the chip to be tested, set a signal reading device at the pin of each output port of the chip, record the output signal of each output port, and obtain the port output function; The timing analysis module is used to compare the port output function with the standard output function, check the constant voltage port and the unstable port therein, and when the number of the constant voltage port or the unstable port exceeds the preset value to reach a fixed ratio, the chip is regarded as a substandard product, the remaining detection process is skipped, and the scanning function and the output function are subjected to timing analysis, and the correlation function is obtained from the analysis result, and the time shift when the correlation function takes the minimum value is recorded as the port response delay, and the integral of the correlation function within the definition domain is taken as the scanning error of the chip; The scan chain module is used to connect the core registers of the chip to be tested into a test chain in series. The number of cores contained in each test chain decreases according to a preset multiple. Each test chain constructs an independent scan interval, randomly samples the scan function, and generates a group of test vectors for each test chain. For each group of test vectors, the vector with the smallest number of identical code elements with adjacent vectors is taken as the first vector, and all test vectors are arranged in the group according to the similarity with the first vector to obtain a scan thread; The signal generation module is used to determine the ports where the irrelevant bits of the input test vector and the previous test vector are located in a scan thread, freeze the irrelevant bit ports, calculate the dynamic power consumption during the test process of each scan thread, select the scan thread with the minimum power consumption to input the test chain, and ensure that the input interval of each test vector is greater than the maximum port response delay during the scan thread input process; The fault location module is used to compare the output results of the chip with the expected input results, calculate the bit error rate of each test chain, and judge that all cores in the test chain are qualified when the total bit error rate of the test chain is less than the preset value. When the bit error rate is higher than the preset value, the test chain is unlinked to remove the core, and a sub-test chain is constructed to test again until the faulty core is found.

7. The chip test data management system based on big data analysis according to claim 6, characterized in that: The test circuit module includes: a circuit voltage regulating unit and a signal reading unit; The circuit voltage regulating unit is used to adjust the voltage of the input port of the chip according to the value of the scanning function until the clock of the scanning function generator returns to zero; The signal reading unit is used to detect the voltage at the chip output port and record the voltage change function; The time series analysis module includes: an output comparison unit and an association fitting unit; The output comparison unit is used to check the constant voltage port and unstable port when high level input is applied, and compare with the designed port of the chip to identify unqualified chips; The correlation fitting unit is used for timing analysis of scanning function and output function, output port response delay and scanning error.

8. The chip test data management system based on big data analysis according to claim 7, characterized in that: The scan chain module includes: a core series unit, a test vector unit and a scan circuit unit; The core series connection unit is used to take out or isolate the chip core, so that the chip cores are connected in series to form a test chain according to the multiple rule; The test vector unit is used to generate test vectors, perform similarity analysis on the test vectors, arrange all test vectors according to similarity, and obtain a scanning thread; The scanning circuit unit is used to construct a hardware platform for scanning threads to test chain ports and predict output results of the scanning threads.

9. The chip test data management system based on big data analysis according to claim 8, characterized in that: The signal generation module includes: an interface latch unit, a dynamic power consumption unit and a delay scanning unit; The interface latch unit is used to calculate the don't care bits between test vectors and input latches the adjacent don't care bits input to the same port; The dynamic power consumption unit is used to calculate the dynamic power consumption during the test process according to the ratio of high and low levels and the switching frequency in the test vector; The delay scanning unit is used to adjust the time interval of adjacent test signals inputting into the chip port so that adjacent test signals do not cause crosstalk.

10. The chip test data management system based on big data analysis according to claim 9, characterized in that: The fault location module includes: a code element comparison unit and a loop test unit; The code element comparison unit is used to compare the actual output result of the chip with the expected output result to determine the bit error rate of the test chain; The cyclic testing unit is used to unlink the unqualified test chain and test it again when the bit error rate of the test chain fails to meet the requirements, until the faulty core in the chip is found.

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