Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel. The array substrate is provided with a display area and a frame area. The array substrate comprises a virtual structure and a lead. The virtual structure is located in the frame area. The lead is located in the frame area and electrically connected with the virtual structure, and at least one closed loop is formed. In the heating stage, the lead receives a heating signal, and the closed loop serves as a heating loop. The lead is connected with the virtual structure of the frame area to form the closed loop, so that the closed loop can be used as a heating loop in the heating stage, and the display panel can be heated in a low-temperature environment to improve the display reaction speed of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to an array substrate and a display panel. Background Art

[0002] Most liquid crystal displays (LCDs) are backlight liquid crystal displays, which include a housing, a liquid crystal display panel disposed in the housing, and a backlight module in the housing. The liquid crystal display needs to emit light normally by the light source provided by the backlight module.

[0003] Generally, the liquid crystal display panel is formed by laminating two glass substrates (Array Glass and Color Filter Glass), and liquid crystal is filled between the two glass substrates. Pixel electrodes and common electrodes are respectively disposed on the opposite inner sides of the two glass substrates, and the rotation direction of the liquid crystal molecules is controlled by the voltage field strength to refract the light of the backlight module to generate an image.

[0004] Due to the characteristics of the material of the liquid crystal molecules themselves, LCDs have a large adhesion force, resulting in poor response speed. Especially at low temperatures, the smearing is more obvious, seriously affecting the display quality. Summary of the Invention

[0005] The main technical problem to be solved by the present application is to provide an array substrate and a display panel to solve the problem of poor response speed of liquid crystal molecules in the prior art.

[0006] To solve the above technical problem, the first technical solution provided by the present application is: providing an array substrate having a display area and a border area; wherein, it includes:

[0007] A virtual structure located in the border area;

[0008] Leads located in the border area, electrically connected to the virtual structure, and forming at least one closed loop;

[0009] In the heating stage, the leads receive a heating signal, and the closed loop serves as a heating loop.

[0010] Wherein, the virtual structure includes a virtual gate line, a virtual data line, and a virtual pixel electrode; the virtual pixel electrode surrounds the display area and is located on the side of the virtual gate line close to the display area and on the side of the virtual data line close to the display area;

[0011] The virtual gate line includes a first virtual gate line and a second virtual gate line extending along a first direction, and the first virtual gate line and the second virtual gate line are located on opposite sides of the display area along a second direction;

[0012] The virtual data lines include a first virtual data line and a second virtual data line that extend along a second direction, and the first virtual data line and the second virtual data line are located on opposite sides of the display area along a first direction;

[0013] The first direction intersects with the second direction; the lead is located on one side of the display area.

[0014] Wherein, the number of leads is twice the number of closed loops; each closed loop corresponds to two leads.

[0015] Wherein, the array substrate includes a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked; the virtual gate line is formed on the first conductive layer, the virtual data line is formed on the second conductive layer, and the virtual pixel electrode is formed on the third conductive layer.

[0016] Wherein, the lead includes a first lead and a second lead; the first lead, the first virtual gate line, the virtual pixel electrode, the first virtual data line, the second virtual gate line, the second virtual data line, and the second lead are sequentially connected to form a closed loop;

[0017] In the heating stage, the first lead and the second lead respectively receive heating signals so that the closed loop serves as a heating loop.

[0018] Wherein, the virtual pixel electrode includes a first virtual pixel electrode and a second virtual pixel electrode that are insulated; the first virtual pixel electrode extends along the first direction and is located on the side of the first virtual gate line close to the display area; the second virtual pixel electrode semi - surrounds the display area and is located on the side of the virtual data line close to the display area, and on the side of the first virtual gate line close to the display area.

[0019] Wherein, the lead includes a first lead, a second lead, a third lead, a fourth lead, a fifth lead, and a sixth lead;

[0020] The first lead, the first virtual gate line, the first virtual pixel electrode, and the second lead form a first closed loop;

[0021] The third lead, the second virtual pixel electrode, and the fourth lead form a second closed loop;

[0022] The fifth lead, the first virtual data line, the second virtual gate line, the second virtual data line, and

[0023] The sixth lead form a third closed loop;

[0024] In the heating stage, at least one of the first closed loop, the second closed loop, and the third closed loop serves as a heating loop.

[0025] Among them, the array substrate further includes at least one temperature sensing element; the temperature sensing element has a source electrode, a drain electrode and a gate electrode, and the source electrode, the drain electrode and the gate electrode are respectively electrically connected to different closed loops;

[0026] In the temperature sensing stage, at least one lead in each closed loop receives a temperature sensing signal to control the temperature sensing element to sense the temperature;

[0027] The temperature sensing stage and the heating stage are carried out at different times.

[0028] Among them, the temperature sensing element and the lead are located on the same side of the display area, and the temperature sensing element is located at the corner of the display area.

[0029] To solve the above technical problems, the second technical solution provided by this application is: to provide a display panel, which includes:

[0030] An array substrate, which is the above-mentioned array substrate;

[0031] A control circuit, which is electrically connected to the array substrate and transmits a heating signal to the array substrate.

[0032] The beneficial effects of this application: Different from the prior art, this application provides an array substrate and a display panel. The array substrate has a display area and a border area. The array substrate includes a virtual structure and leads. The virtual structure is located in the border area. The leads are located in the border area, are electrically connected to the virtual structure, and form at least one closed loop. In the heating stage, the leads receive the heating signal, and the closed loop serves as a heating loop. By connecting the leads to the virtual structure in the border area to form a closed loop, the closed loop can serve as a heating loop in the heating stage, so that the display panel can be heated in a low-temperature environment to improve the display response speed of the display panel. Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of this application. For those of ordinary skill in the art, without any creative work, other drawings can also be obtained according to these drawings.

[0034] Figure 1 is the liquid crystal response time table at different temperatures provided by this application;

[0035] Figure 2 is a schematic diagram of the virtual pixel electrode around the display area provided by this application;

[0036] Figure 3 is a schematic structural diagram of an embodiment of the array substrate provided by this application;

[0037] Figure 4 It is a schematic structural diagram of an embodiment of a pixel unit provided by the present application.

[0038] Figure 5 It is a schematic structural diagram of another embodiment of the array substrate provided by the present application;

[0039] Figure 6 It is a schematic plan view of an embodiment of the display panel provided by the present application;

[0040] Figure 7 It is a schematic longitudinal view of an embodiment of the display panel provided by the present application.

[0041] Explanation of the reference numerals in the drawings:

[0042] 100. Array substrate; 110. Display area; 120. Border area; 1201. Diagonal area; 1202. Wiring area; 1203. Corner; 10. Virtual structure; 11. Virtual gate line; 111. First virtual gate line; 112. Second virtual gate line; 12. Virtual data line; 121. First virtual data line; 122. Second virtual data line; 13. Virtual pixel electrode; 131. First virtual pixel electrode; 132. Second virtual pixel electrode; 20. Lead; 21. First lead; 22. Second lead; 23. Third lead; 24. Fourth lead; 25. Fifth lead; 26. Sixth lead; 30. Temperature sensing element; 31. Source; 32. Drain; 33. Gate; 40. Via; 200. Control circuit; 300. Opposing substrate; 400. Liquid crystal layer; 500. Filter layer; 510. Color filter film; 520. Light-shielding structure; 600. Display panel. Detailed implementation manners

[0043] The following will describe the solutions of the embodiments of the present application in detail with reference to the drawings in the specification.

[0044] In the following description, specific details such as specific system structures, interfaces, and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the present application.

[0045] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0046] The terms "first", "second", and "third" in this application are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", and "third" may explicitly or implicitly include at least one of such features. In the description of this application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined. All directional indications (such as up, down, left, right, front, back...) in the embodiments of this application are only used to explain the relative positional relationship, movement conditions, etc. between components in a specific posture (as shown in the drawings). If the specific posture changes, then the directional indications will change accordingly. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0047] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of this application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0048] Please refer to Figure 1 and Figure 2 , Figure 1 is the liquid crystal response time schedule at different temperatures provided by this application, Figure 2 is a schematic diagram of the virtual pixel electrodes around the display area provided by this application.

[0049] The ambient temperature will affect the response speed of liquid crystal molecules in the display panel. As Figure 1 shown, the higher the temperature, the faster the response speed of the liquid crystal molecules.

[0050] In the related art, virtual pixel electrodes are provided around the display area of the display panel to improve the process uniformity of the display area. Virtual gate lines ( Figure 2 not shown) are provided on the upper and lower sides of the display area, and virtual data lines ( Figure 2 not shown) are provided on the left and right sides of the display area.

[0051] Please refer to Figures 1 to 3 , Figure 3 is a schematic structural diagram of an embodiment of the array substrate provided by this application.

[0052] On this basis, the present application provides an array substrate 100. The array substrate 100 has a display area 110 and a border area 120. The array substrate 100 includes a dummy structure 10 and a lead 20. The dummy structure 10 is located in the border area 120. The lead 20 is located in the border area 120, electrically connected to the dummy structure 10, and forms at least one closed loop. During the heating stage, the lead 20 receives a heating signal, and the closed loop serves as a heating loop.

[0053] By connecting the lead 20 to the dummy structure 10 in the border area 120 to form a closed loop, the closed loop can serve as a heating loop during the heating stage, so that the display panel 600 (see Figure 5 ) can be heated in a low-temperature environment to improve the display response speed of the display panel 600.

[0054] The border area 120 is designed to surround the four sides of the display area 110. The display area 110 can be a polygon such as a rectangle, trapezoid, parallelogram, or an arc-shaped polygon.

[0055] Exemplarily, the display area 110 is a rectangle.

[0056] The dummy structure 10, namely Dummy Structures. The design of the dummy structure 10 does not directly participate in image display. The dummy structure 10 is used to reduce edge effects, assist in testing and debugging, and improve the uniformity of the manufacturing process.

[0057] The lead 20 is used to receive corresponding signals according to the working stage of the array substrate 100. For example, it receives a heating signal during the heating stage.

[0058] The heating stage and the display stage are carried out separately to avoid the dummy structure 10 interfering with the normal display of the display area 110.

[0059] In some embodiments, the dummy structure 10 includes a dummy gate line 11, a dummy data line 12, and a dummy pixel electrode 13. The dummy pixel electrode 13 is disposed around the display area 110, and is located on the side of the dummy gate line 11 close to the display area 110 and on the side of the dummy data line 12 close to the display area 110.

[0060] The dummy gate line 11 includes a first dummy gate line 111 and a second dummy gate line 112 extending along a first direction, and the first dummy gate line 111 and the second dummy gate line 112 are located on opposite sides of the display area 110 along a second direction.

[0061] The dummy data line 12 includes a first dummy data line 121 and a second dummy data line 122 extending along a second direction, and the first dummy data line 121 and the second dummy data line 122 are located on opposite sides of the display area 110 along a first direction.

[0062] The first direction intersects with the second direction. The lead 20 is located on one side of the display area 110.

[0063] The virtual gate line 11 is a non-functional gate line in the array substrate 100. For example, during the photolithography and etching processes, if the actual gate line distribution is uneven, it may lead to differences in etching rates and cause line width deviations. The virtual gate line 11 fills the low-density areas to ensure etching uniformity. Another example is that during the circuit testing phase, the virtual gate line 11 may serve as a probe contact point to avoid damaging the functional lines.

[0064] The virtual data line 12 is a non-functional data signal line and is a redundant design of the data signal lines. For example, during the deposition and etching of the metal layer, it balances the pattern density in the data signal line area to prevent the line width from being too thin or the line from breaking. Another example is that during high-speed signal transmission, the virtual data line 12 can reduce the edge effect and lower the electromagnetic interference (EMI) between adjacent functional lines.

[0065] The virtual pixel electrode 13 is a pixel electrode without actual display function. For example, during the coating of the liquid crystal alignment layer on the array substrate 100, the virtual pixel electrode 13 can balance the electric field distribution and avoid abnormal arrangement of liquid crystal molecules in the edge area.

[0066] The first virtual gate line 111 and the second virtual gate line 112 are arranged at intervals and are both strip-shaped structures.

[0067] The first virtual data line 121 and the second virtual data line 122 are arranged at intervals and are both strip-shaped structures.

[0068] The first virtual gate line 111, the first virtual data line 121, the second virtual gate line 112, and the second virtual data line 122 jointly enclose the display area 110.

[0069] Exemplarily, the first direction is perpendicular to the second direction.

[0070] In other embodiments, the first direction and the second direction may be non-perpendicular and are selected according to actual requirements.

[0071] In some embodiments, the number of leads 20 is twice the number of closed loops. Each closed loop corresponds to two leads 20.

[0072] The virtual structure 10 receives signals through the lead 20 and is used as a heating trace during the heating stage. It can heat the display panel 600 in a low-temperature environment and also reduce the setting of heating traces in the border area 120, which is beneficial to the narrow border design.

[0073] In some embodiments, the array substrate 100 includes a first conductive layer (not shown in the figure), a second conductive layer (not shown in the figure), and a third conductive layer (not shown in the figure) that are sequentially stacked. The virtual gate line 11 is formed on the first conductive layer, the virtual data line 12 is formed on the second conductive layer, and the virtual pixel electrode 13 is formed on the third conductive layer.

[0074] The first conductive layer and the second conductive layer are metal layers. The third conductive layer is a transparent conductive layer.

[0075] Please refer to Figures 1 to 4 , Figure 4 which is a schematic structural diagram of an embodiment of a pixel unit provided in this application.

[0076] The first conductive layer is further used to form the gate line in the display area 110. The second conductive layer is further used to form the data line in the display area 110. The third conductive layer is further used to form the pixel electrode in the display area 110.

[0077] The gate line, the data line, and the pixel electrode are key structures for realizing image display.

[0078] Specifically, the gate line is used to provide a control signal to the transistor in each pixel unit. By applying a voltage to the gate line, the corresponding transistor can be turned on or off. The data line is responsible for transmitting video signals or data signals to each pixel unit. These signals determine the brightness or color of each pixel. The pixel electrode receives the signal from the data line and adjusts the state of the pixel according to the signal. When the transistor is turned on, the signal on the data line is transmitted to the pixel electrode through the transistor, causing the pixel electrode to be charged to the required voltage level to display the correct brightness or color.

[0079] In some embodiments, the lead 20 includes a first lead 21 and a second lead 22. The first lead 21, the first virtual gate line 111, the virtual pixel electrode 13, the first virtual data line 121, the second virtual gate line 112, the second virtual data line 122, and the second lead 22 are sequentially connected to form a closed loop. During the heating stage, the first lead 21 and the second lead 22 respectively receive heating signals so that the closed loop serves as a heating loop.

[0080] Exemplarily, the virtual pixel electrode 13 is a ring-shaped opening structure. The virtual pixel electrode 13 surrounds the periphery of the display area 110.

[0081] The ends of the virtual pixel electrode 13 are all located at the same corner 1203 of the display area 110 to reduce the connection traces between the first virtual gate line 111 and the virtual pixel electrode 13, and to reduce the connection traces between the virtual pixel electrode 13 and the first virtual data line 121, which is beneficial to the narrow border design.

[0082] The first end of the first lead 21 receives a first signal, and the second end is electrically connected to the end of the first virtual gate line 111 close to the second virtual data line 122.

[0083] The end of the first virtual gate line 111 close to the first virtual data line 121 is electrically connected to the end of the first virtual data line 121.

[0084] The end of the first virtual data line 121 close to the second virtual gate 33 is electrically connected to the end of the second virtual gate line 112.

[0085] The end of the second virtual gate line 112 close to the second virtual data line 122 is electrically connected to the second virtual data line 122.

[0086] The end of the second virtual data line 122 close to the first virtual gate line 111 is electrically connected to the second end of the second lead 22, and the first end of the second lead 22 receives a second signal.

[0087] In the heating stage, both the first signal and the second signal are heating signals, and there is a voltage difference between the first signal and the second signal so that the closed loop can be used as a heating loop. The heating effect can be adjusted according to the voltage difference between the first signal and the second signal. The specific value of the voltage difference is not limited here and is selected according to actual needs.

[0088] Please refer to Figures 1 to 5 , Figure 5 which is a schematic structural diagram of another embodiment of the array substrate provided by the present application.

[0089] In some embodiments, the virtual pixel electrode 13 includes a first virtual pixel electrode 131 and a second virtual pixel electrode 132 that are insulated from each other. The first virtual pixel electrode 131 extends along the first direction and is located on the side of the first virtual gate line 111 close to the display area 110. The second virtual pixel electrode 132 semi-surrounds the display area 110 and is located on the side of the virtual data line 12 close to the display area 110 and on the side of the first virtual gate line 111 close to the display area 110.

[0090] Exemplarily, the second virtual pixel electrode 132 has a U-shaped structure. The ends of the second virtual pixel electrode 132 are all close to the first pixel virtual pixel electrode 13 so that the second virtual pixel electrode 132 and the first virtual pixel electrode 131 jointly enclose the display area 110.

[0091] In some embodiments, the lead 20 includes a first lead 21, a second lead 22, a third lead 23, a fourth lead 24, a fifth lead 25, and a sixth lead 26.

[0092] The first lead 21, the first virtual gate line 111, the first virtual pixel electrode 131, and the second lead 22 form a first closed loop.

[0093] The third lead 23, the second virtual pixel electrode 132, and the fourth lead 24 form a second closed loop.

[0094] The fifth lead 25, the first virtual data line 121, the second virtual gate line 112, the second virtual data line 122, and the sixth lead 26 form a third closed loop.

[0095] During the heating stage, at least one of the first closed loop, the second closed loop, and the third closed loop serves as a heating loop.

[0096] The first closed loop is located on the same side of the display area 110 and can heat one side of the display area 110.

[0097] Specifically, the first end of the first lead 21 receives a first signal, and the second end of the first lead 21 is electrically connected to the end of the first virtual gate line 111 close to the second virtual data line 122. The end of the first virtual gate line 111 close to the first virtual data line 121 is electrically connected to the end of the first virtual pixel electrode 131 close to the first virtual data line 121. The end of the first virtual pixel electrode 131 close to the second virtual data line 122 is electrically connected to the second end of the second lead 22. The first end of the second lead 22 receives a second signal.

[0098] During the heating stage, both the first signal and the second signal are heating signals, and there is a voltage difference between the first signal and the second signal, so that the first closed loop can serve as a heating loop.

[0099] In the second closed loop, the second virtual pixel electrode 132 is arranged to semi-surround the display area 110 and can heat three sides of the display area 110.

[0100] Specifically, the first end of the third lead 23 receives a third signal, the second end of the third lead 23 is electrically connected to the first end of the second virtual pixel electrode 132, and the second end of the second virtual pixel electrode 132 is electrically connected to the second end of the fourth lead 24. The first end of the fourth lead 24 receives a fourth signal. The two ends of the second virtual pixel electrode 132 are respectively located at different corners 1203 of the display area 110 to reduce the connection traces with the lead 20, which can simplify the manufacturing process and facilitate the narrow border design.

[0101] During the heating stage, both the third signal and the fourth signal are heating signals, and there is a voltage difference between the third signal and the fourth signal, so that the second closed loop can serve as a heating loop.

[0102] In the third closed loop, the first virtual data line 121, the second virtual gate line 112, and the second virtual data line 122 are arranged to semi-surround the display area 110, and can selectively heat three sides of the display area 110.

[0103] Specifically, the first end of the fifth lead 25 receives a fifth signal, and the second end of the fifth lead 25 is electrically connected to the end of the first virtual data line 121 close to the first virtual gate line 111. The end of the first virtual data line 121 close to the second virtual gate line 112 is electrically connected to the second virtual gate line 112. The end of the second virtual gate line 112 close to the second virtual data line 122 is electrically connected to the second virtual data line 122. The end of the second virtual data line 122 close to the first virtual gate line 111 is electrically connected to the second end of the sixth lead 26. The first end of the sixth lead 26 receives a sixth signal.

[0104] In the heating stage, both the fifth signal and the sixth signal are heating signals, and there is a voltage difference between the fifth signal and the sixth signal, so that the third closed loop can be used as a heating loop.

[0105] The virtual structure 10 and the leads 20 form three closed loops, and the display panel 600 can be selectively heated according to the heating requirements.

[0106] In the embodiments of the present application, vias 40 and other methods can be used for electrical connection between different conductive layers, which are not limited here and are selected according to actual requirements. For example, a metal wire-changing hole is used for electrical connection between the first virtual gate line 111 and the first virtual pixel electrode 131.

[0107] In some embodiments, the array substrate 100 further includes at least one temperature sensing element 30. The temperature sensing element 30 has a source electrode 31, a drain electrode 32, and a gate electrode 33, and the source electrode 31, the drain electrode 32, and the gate electrode 33 are respectively electrically connected to different closed loops.

[0108] In the temperature sensing stage, at least one lead 20 in each closed loop receives a temperature sensing signal to control the temperature sensing element 30 to sense the temperature.

[0109] The temperature sensing stage and the heating stage are carried out at different times.

[0110] The temperature sensing element 30 is used to sense the ambient temperature. Whether to heat the display panel 600 and adjust the heating amount of the closed loop in the heating stage can be determined according to the sensed ambient temperature. For example, in response to the sensed ambient temperature being within the threshold range, there is no need to heat the display panel 600. In response to the sensed ambient temperature being lower than the threshold range, the display panel 600 is heated. The threshold range is not limited here and is selected according to actual requirements.

[0111] Specifically, the temperature sensing element 30 is a Thermal Sensor TFT (Thin Film Transistor). The Thermal Sensor TFT has a channel layer (not shown in the figure), and the channel layer is made of a semiconductor material sensitive to temperature, and its electrical properties (such as carrier concentration or mobility) change with the change of temperature.

[0112] When the ambient temperature changes, the carrier concentration or mobility in the channel layer material changes, resulting in a corresponding change in the channel resistance. Due to the change of the channel resistance, the current between the source 31 and the drain 32 also changes accordingly. When the temperature rises, if the carrier concentration of the material increases, the current increases; vice versa.

[0113] Connecting the temperature sensing element 30 to a closed loop, and performing the temperature sensing stage and the heating stage separately in time, can reduce the number of signal interfaces.

[0114] Exemplarily, it is described by taking the source 31 of the temperature sensing element 30 being electrically connected to the first closed loop, the drain 32 of the temperature sensing element 30 being electrically connected to the second closed loop, and the gate 33 of the temperature sensing element 30 being electrically connected to the third closed loop as an example.

[0115] Exemplarily, in the temperature sensing stage, two leads 20 in each closed loop receive temperature sensing signals.

[0116] Specifically, the first signal and the second signal are the same temperature sensing signal. The third signal and the fourth signal are both the same temperature sensing signal. The fifth signal and the sixth signal are both the same temperature sensing signal. The first signal and the third signal are different signals. The first signal is used as a reference signal, and the temperature change is detected by monitoring the current change of the third lead 23 and / or the fourth lead 24.

[0117] Exemplarily, in the temperature sensing stage, one lead 20 in each closed loop receives a temperature sensing signal.

[0118] Specifically, one of the first lead 21 and the second lead 22 receives a temperature sensing signal. One of the third lead 23 and the fourth lead 24 receives a temperature sensing signal. One of the fifth lead 25 and the sixth lead 26 receives a temperature sensing signal. Exemplarily, taking the first lead 21 receiving the temperature sensing signal and the third lead 23 receiving the temperature sensing signal as an example, the first signal is used as a reference signal, and the temperature change is detected by monitoring the current change of the third lead 23.

[0119] Integrating the temperature sensing element 30 on the array substrate 100 can sense the ambient temperature without using an external temperature sensing component.

[0120] In some embodiments, the temperature sensing element 30 and the lead 20 are located on the same side of the display area 110, and the temperature sensing element 30 is located at the corner 1203 of the display area 110.

[0121] Multiple leads 20 are located on the same side of the display area 110. Specifically, the lead 20 is located on the first side of the display area 110, and at least a part of the lead 20 is inclined with respect to the side of the first side of the display area 110. The area where the lead 20 is located is defined as the diagonal area 1201.

[0122] Define the side adjacent to the first side of the display area 110 as the adjacent side, and the corresponding border area 120 of the adjacent side of the display area 110 is the routing area 1202. The signal lines in the routing area 1202 are externally connected to signals through the diagonal area 1201. The routing space is different from the diagonal area 1201 to the routing area 1202, the routing width changes, the impedance mutates, and the current density changes. The signal lines are prone to heat generation at the intersection of the routing area 1202 and the diagonal area 1201, resulting in overheating of the surrounding area and liquid crystal polarization. The temperature sensing element 30 is disposed at the corner 1203 (i.e., the intersection of the routing area 1202 and the diagonal area 1201) to monitor the temperature at the intersection of the routing area 1202 and the diagonal area 1201, regulate the driving signal of the signal line, and improve liquid crystal polarization.

[0123] Exemplarily, a GDL (Gate Driver on Array) is provided in the routing area 1202. The GDL signal routing connects the lines of the GDL integrated circuit and various parts of the display panel 600, and is responsible for transmitting the gate driving signal to control the switching state of each row of pixels. The GDL signal routing is externally connected to the driving signal through the diagonal area 1201. The temperature sensing element 30 monitors the temperature at the intersection of the routing area 1202 and the diagonal area 1201, and improves liquid crystal polarization by regulating the driving signal of the GDL.

[0124] In other embodiments, other circuits may be provided in the routing area 1202, which is not limited here too much and is selected according to actual needs.

[0125] Exemplarily, there are two temperature sensing elements 30, which are respectively located at different corners 1203 of the display area 110.

[0126] By monitoring the temperature at multiple corners 1203 in real time, it can help to timely detect and handle potential overheating points, prevent damage to the display panel 600 caused by local overheating, and extend the service life of the device.

[0127] Please refer to Figures 1 to 7 , Figure 6 which is a schematic plan view of an embodiment of the display panel provided by this application, Figure 7It is a longitudinal schematic diagram of an embodiment of the display panel provided by the present application.

[0128] The present application provides a display panel 600. The display panel 600 includes the above-mentioned array substrate 100 and control circuit 200. The control circuit 200 is electrically connected to the array substrate 100 and transmits a heating signal to the array substrate 100.

[0129] Specifically, the control circuit 200 is electrically connected to the lead 20 and is used to transmit a heating signal to the lead 20 during the heating stage.

[0130] In some embodiments, the control circuit 200 is further used to transmit a temperature sensing signal to the lead 20 during the temperature sensing stage.

[0131] The display panel 600 further includes a counter substrate 300 and a liquid crystal layer 400. The counter substrate 300 is disposed opposite to the array substrate 100. The liquid crystal layer 400 is disposed between the counter substrate 300 and the array substrate 100.

[0132] The display panel 600 further includes a filter layer 500. The filter layer 500 includes a color filter film 510 and a light shielding structure 520. The color filter film 510 includes filter films of multiple colors and is used to selectively transmit or block light of specific wavelengths, thereby realizing color display. For example, the color filter film 510 includes filter films of three colors: red (R), green (G), and blue (B). The light shielding structure 520 is located between the filter films and is used to block the light between adjacent pixel units, prevent light leakage and color mixing, and improve the contrast and color purity of the image. For example, the light shielding structure 520 can be a black matrix (BM).

[0133] Exemplarily, the filter layer 500 is disposed in the counter substrate 300. That is, the counter substrate 300 is a color film substrate. The color film substrate mainly provides a color display function for the display panel 600. By filtering and modulating light, the finally displayed image has rich colors.

[0134] In other embodiments, the filter layer 500 can be disposed in the array substrate 100, which is not limited here too much and is selected according to actual needs.

[0135] The common electrode layer (not shown in the figure) of the counter substrate 300 and the pixel electrode layer of the array substrate 100 control the orientation and movement of the liquid crystal molecules in the liquid crystal layer 400 by generating an electric field. The liquid crystal layer 400 then modulates light according to the action of the electric field, thereby realizing the image display function of the display panel 600. The three work together in coordination and are indispensable.

[0136] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For the parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0137] The above are only the implementation manners of the present application, and do not limit the patent protection scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. An array substrate having a display area and a frame area; characterized in that: include: A virtual structure located in the border area; A lead wire is located in the frame area and is electrically connected to the dummy structure to form at least one closed loop; During the heating phase, the lead receives a heating signal and the closed loop serves as a heating loop.

2. The array substrate according to claim 1, characterized in that: The virtual structure includes a virtual gate line, a virtual data line and a virtual pixel electrode; the virtual pixel electrode is arranged around the display area and is located on a side of the virtual gate line close to the display area and on a side of the virtual data line close to the display area; The virtual gate line includes a first virtual gate line and a second virtual gate line extending along a first direction, and the first virtual gate line and the second virtual gate line are located at two opposite sides of the display area along a second direction; The virtual data lines include a first virtual data line and a second virtual data line extending along the second direction, and the first virtual data line and the second virtual data line are located at two opposite sides of the display area along the first direction; The first direction intersects with the second direction; the lead is located at one side of the display area.

3. The array substrate according to claim 2, characterized in that: The number of the lead wires is twice the number of the closed loops; each closed loop corresponds to two lead wires.

4. The array substrate according to claim 2, characterized in that: The array substrate includes a first conductive layer, a second conductive layer and a third conductive layer stacked in sequence; the virtual gate line is formed in the first conductive layer, the virtual data line is formed in the second conductive layer, and the virtual pixel electrode is formed in the third conductive layer.

5. The array substrate according to claim 3, characterized in that: The lead wire comprises a first lead wire and a second lead wire; the first lead wire, the first virtual gate line, the virtual pixel electrode, the first virtual data line, the second virtual gate line, the second virtual data line and the second lead wire are connected in sequence to form a closed loop; During the heating phase, the first lead and the second lead respectively receive heating signals to make the closed loop serve as a heating loop.

6. The array substrate according to claim 3, characterized in that: The virtual pixel electrode includes a first virtual pixel electrode and a second virtual pixel electrode which are insulated; the first virtual pixel electrode is extended along the first direction and is located on a side of the first virtual gate line close to the display area; the second virtual pixel electrode semi-surrounds the display area and is located on a side of the virtual data line close to the display area, and is located on a side of the first virtual gate line close to the display area.

7. The array substrate according to claim 6, characterized in that: The leads include a first lead, a second lead, a third lead, a fourth lead, a fifth lead and a sixth lead; The first lead line, the first virtual gate line, the first virtual pixel electrode and the second lead line form a first closed loop; The third lead, the second virtual pixel electrode and the fourth lead form a second closed loop; The fifth lead line, the first virtual data line, the second virtual gate line, the second virtual data line and the sixth lead line form a third closed loop; In the heating stage, at least one of the first closed loop, the second closed loop and the third closed loop serves as a heating loop.

8. The array substrate according to claim 7, characterized in that: The array substrate further comprises at least one temperature sensing element; the temperature sensing element comprises a source electrode, a drain electrode and a gate electrode, and the source electrode, the drain electrode and the gate electrode are electrically connected to different closed loops respectively; In the temperature sensing stage, at least one lead in each of the closed loops receives a temperature sensing signal to control the temperature sensing element to sense temperature; The temperature sensing stage and the heating stage are performed in different time periods.

9. The array substrate according to claim 8, characterized in that: The temperature sensing element and the lead are located on the same side of the display area, and the temperature sensing element is located at a corner of the display area.

10. A display panel, characterized in that: include: An array substrate, which is the array substrate according to any one of claims 1 to 9; The control circuit is electrically connected to the array substrate and transmits a heating signal to the array substrate.

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