Reset operation method and system, analysis module, thread module and routing board card

Abstract

The embodiment of the invention provides a reset operation method and system, an analysis module, a thread module and a routing board card. According to the scheme, an upper computer sends a reset instruction packet to a first analysis module; the first analysis module sends a first reset signal to the thread module based on the received reset instruction packet, and sends a reset data packet to the routing board card; the thread module performs reset operation according to the received first reset signal; and the routing board card performs reset operation according to the received reset data packet. Through the technical scheme provided by the embodiment of the invention, the reset operation of the quantum computing measurement and control system is realized, and a guarantee is provided for normal execution of a quantum computing task.

Description

Technical Field

[0001] The present application relates to the field of quantum computing technology, and in particular, to a reset operation method, system, parsing module, thread module, and routing board. Background Art

[0002] Quantum computing is a computing mode that uses the basic characteristics of quantum mechanics to solve problems. By constructing a quantum physical hardware system that can be precisely operated and running quantum computing software to implement quantum algorithms, computational problems are solved to realize the application of quantum computing in specific problems or fields.

[0003] During the execution of quantum computing tasks, the quantum computing measurement and control system may be affected by factors such as the network environment and the thread running state, which may cause the quantum computing tasks to not be executed normally. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a reset operation method, system, parsing module, thread module, and routing board to implement the reset operation of the quantum computing measurement and control system and provide guarantee for the normal execution of quantum computing tasks. The specific technical solutions are as follows:

[0005] The embodiments of the present application provide a reset operation method applied to a quantum computing measurement and control system. The quantum computing measurement and control system includes a host computer, a central control board, and a routing board. The central control board includes a first parsing module and a thread module. The thread module is used to trigger the routing board to start the parallel execution of multiple quantum computing tasks. The method includes:

[0006] The host computer sends a reset instruction packet to the first parsing module;

[0007] Based on the received reset instruction packet, the first parsing module sends a first reset signal to the thread module and sends a reset data packet to the routing board;

[0008] The thread module performs a reset operation according to the received first reset signal;

[0009] The routing board performs a reset operation according to the received reset data packet.

[0010] The embodiments of the present application also provide a reset operation method applied to the first parsing module in the central control board. The central control board, the host computer, and the routing board constitute a quantum computing measurement and control system. The central control board further includes a thread module for triggering the routing board to start the parallel execution of multiple quantum computing tasks. The method includes:

[0011] Receiving the reset instruction packet sent by the host computer;

[0012] Based on the reset instruction packet, send a first reset signal to the thread module so that the thread module performs a reset operation according to the first reset signal;

[0013] Based on the reset instruction packet, send a reset data packet to the routing board so that the routing board performs a reset operation according to the reset data packet.

[0014] An embodiment of the present application further provides a reset operation method, which is applied to a thread module in a central control board. The central control board, the host computer, and the routing board constitute a quantum computing measurement and control system. The thread module is used to trigger the routing board to start parallel execution of multiple quantum computing tasks. The central control board further includes a first parsing module. The method includes:

[0015] Receive the first reset signal sent by the first parsing module based on the reset instruction packet. The reset instruction packet is sent by the host computer to the first parsing module;

[0016] Perform a reset operation according to the first reset signal.

[0017] An embodiment of the present application further provides a reset operation method, which is applied to a routing board in a quantum computing measurement and control system. The routing board is used to start parallel execution of multiple quantum computing tasks. The quantum computing measurement and control system further includes a host computer and a central control board. The central control board includes a first parsing module. The method includes:

[0018] Receive the reset data packet sent by the first parsing module based on the reset instruction packet. The reset instruction packet is sent by the host computer to the first parsing module;

[0019] Perform a reset operation according to the reset data packet.

[0020] An embodiment of the present application further provides a quantum computing measurement and control system. The quantum computing measurement and control system includes a host computer, a central control board, and a routing board. The central control board includes a first parsing module and a thread module. The thread module is used to trigger the routing board to start parallel execution of multiple quantum computing tasks;

[0021] The host computer is used to send a reset instruction packet to the first parsing module;

[0022] The first parsing module is used to send a first reset signal to the thread module and send a reset data packet to the routing board based on the received reset instruction packet;

[0023] The thread module is used to perform a reset operation according to the received first reset signal;

[0024] The routing board is used to perform a reset operation according to the received reset data packet.

[0025] The embodiment of the present application further provides a first parsing module, which is deployed in the central control board. The central control board, the host computer and the routing board constitute a quantum computing measurement and control system. The central control board further includes a thread module for triggering the routing board to start multiple quantum computing tasks to be executed in parallel.

[0026] The first parsing module includes:

[0027] A first receiving unit, configured to receive a reset instruction packet sent by the host computer;

[0028] A first sending unit, configured to send a first reset signal to the thread module based on the reset instruction packet, so that the thread module performs a reset operation according to the first reset signal;

[0029] A second sending unit, configured to send a reset data packet to the routing board based on the reset instruction packet, so that the routing board performs a reset operation according to the reset data packet.

[0030] The embodiment of the present application further provides a thread module, which is deployed in the central control board. The central control board, the host computer and the routing board constitute a quantum computing measurement and control system. The thread module is used to trigger the routing board to start the parallel execution of multiple quantum computing tasks. The central control board further includes a first parsing module;

[0031] The thread module includes:

[0032] A second receiving unit, configured to receive the first reset signal sent by the first parsing module based on the reset instruction packet, and the reset instruction packet is sent by the host computer to the first parsing module;

[0033] A first reset unit, configured to perform a reset operation according to the first reset signal.

[0034] The embodiment of the present application further provides a routing board, which is used to start the parallel execution of multiple quantum computing tasks. The routing board, the host computer and the central control board constitute a quantum computing measurement and control system. The central control board includes a first parsing module;

[0035] The routing board includes:

[0036] A third receiving unit, configured to receive the reset data packet sent by the first parsing module based on the reset instruction packet, and the reset instruction packet is sent by the host computer to the first parsing module;

[0037] A second reset unit, configured to perform a reset operation according to the reset data packet.

[0038] The embodiment of the present application further provides a central control board card, which includes a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete mutual communication through the communication bus;

[0039] The memory is used to store a computer program;

[0040] The processor is used to implement the steps of the reset operation method described in any one of the above when executing the program stored on the memory.

[0041] The embodiment of the present application further provides a routing board card, which includes a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete mutual communication through the communication bus;

[0042] The memory is used to store a computer program;

[0043] The processor is used to implement the steps of the reset operation method described in any one of the above when executing the program stored on the memory.

[0044] The embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps of the reset operation method described in any one of the above are implemented.

[0045] The embodiment of the present application further provides a computer program product containing instructions, which when running on a computer, causes the computer to execute the reset operation method described in any one of the above.

[0046] Advantages of the embodiment of the present application:

[0047] In the technical solution provided by the embodiment of the present application, after the host computer sends a reset instruction packet to the central control board card, the first parsing module in the central control board card sends a first reset signal to the thread module in the central control board card and sends a reset data packet to the routing board card communicatively connected to the central control board card through parsing the received reset instruction packet. The thread module can perform a reset operation according to the received first reset signal, and the routing board card can also perform a reset operation according to the received reset data packet, realizing the reset of the thread module and the routing board card. This realizes the reset operation of the quantum computing measurement and control system and provides guarantee for the normal execution of quantum computing tasks.

[0048] Of course, it is not necessary for any product or method implementing the present application to achieve all the above advantages at the same time. Description of the Drawings

[0049] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0050] Figure 1 The first signaling diagram of the reset operation method provided by the embodiment of the present application;

[0051] Figure 2 The first structural schematic diagram of the quantum computing measurement and control system provided by the embodiment of the present application;

[0052] Figure 3 The second signaling diagram of the reset operation method provided by the embodiment of the present application;

[0053] Figure 4 The third signaling diagram of the reset operation method provided by the embodiment of the present application;

[0054] Figure 5 The fourth signaling diagram of the reset operation method provided by the embodiment of the present application;

[0055] Figure 6 The fifth signaling diagram of the reset operation method provided by the embodiment of the present application;

[0056] Figure 7 The first flow schematic diagram of the reset operation method provided by the embodiment of the present application;

[0057] Figure 8 The second flow schematic diagram of the reset operation method provided by the embodiment of the present application;

[0058] Figure 9 The third flow schematic diagram of the reset operation method provided by the embodiment of the present application;

[0059] Figure 10 The fourth flow schematic diagram of the reset operation method provided by the embodiment of the present application;

[0060] Figure 11 The second structural schematic diagram of the quantum computing measurement and control system provided by the embodiment of the present application;

[0061] Figure 12 A structural schematic diagram of the first parsing module provided by the embodiment of the present application;

[0062] Figure 13 A structural schematic diagram of the thread module provided by the embodiment of the present application;

[0063] Figure 14The first structural schematic diagram of the routing board card provided by the embodiment of the present application;

[0064] Figure 15 A structural schematic diagram of the central control board card provided by the embodiment of the present application;

[0065] Figure 16 The second structural schematic diagram of the routing board card provided by the embodiment of the present application. Detailed implementation manners

[0066] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0067] To solve the problems in the related art, the embodiment of the present application provides a reset operation method. As Figure 1 shown, Figure 1 The first signaling diagram of the reset operation method provided by the embodiment of the present application. This method can be applied to a quantum computing measurement and control system, which can include a host computer, a central control board card, and a routing board card. The central control board card includes a first parsing module and a thread module, and the thread module is used to trigger the routing board card to start parallel execution of multiple quantum computing tasks. In Figure 1 the method shown includes the following steps.

[0068] Step S101, the host computer sends a reset instruction packet to the first parsing module.

[0069] Step S102, based on the received reset instruction packet, the first parsing module sends a first reset signal to the thread module and sends a reset data packet to the routing board card.

[0070] Step S103, the thread module performs a reset operation according to the received first reset signal.

[0071] Step S104, the routing board card performs a reset operation according to the received reset data packet.

[0072] For ease of understanding, in combination with Figure 2 the above quantum computing measurement and control system is described. Figure 2 The first structural schematic diagram of the quantum computing measurement and control system provided by the embodiment of the present application. In Figure 2 the quantum computing measurement and control system shown may include: a host computer, a central control board card, and a routing board card.

[0073] In Figure 2The central control board card shown may include: a 100M Ethernet driver, a first transmission module, a first parsing module, a thread module, a second parsing module, and a second transmission module. Among them, the thread module may include multiple first thread sub-modules. For example, in a quantum computing measurement and control system corresponding to a 72-bit quantum chip, the thread module may include 5 first thread sub-modules.

[0074] The above quantum computing measurement and control system may include multiple routing board cards, such as Figure 2 the 3 routing board cards shown, and in Figure 2 the three routing board cards are integrated on the same hardware device. In actual design, Figure 2 the three routing board cards shown may be respectively deployed on different hardware devices. In Figure 2 each routing board card shown may include: multiple second thread sub-modules ( Figure 2 not shown in the figure). For example, in a quantum computing measurement and control system corresponding to a 72-bit quantum chip, each routing board card may include 5 second thread sub-modules. That is, the number of second thread sub-modules in each routing board card matches the number of first thread sub-modules in the thread module.

[0075] In Figure 2 the quantum computing measurement and control system shown, the host computer is communicatively connected to the central control board card, that is, the host computer and the central control board card are communicatively connected through the Figure 2 100M Ethernet driver in the central control board card shown. The central control board card is respectively communicatively connected to each routing board card, that is, the central control board card is communicatively connected to each routing board card through the Figure 2 second transmission module shown. In addition, Figure 2 the thread module shown can be directly communicatively connected to each routing board card. For example, the thread module can directly transmit a trigger signal to the routing board card. Each routing board card can be communicatively connected to a lower-layer board card ( Figure 2 not shown in the figure). The host computer can also be directly communicatively connected to the routing board card. For example, receiving the execution result of the quantum computing task returned by the routing board card or the second return command packet in the following text.

[0076] In Figure 2In the quantum computing measurement and control system shown, when each component module in the central control board and the routing board is normal, after the lower-layer board card communicatively connected to the routing board is ready, it sends a ready signal to the routing board. After the routing module is ready, it sends a ready packet to the central control board. When the thread module in the central control board receives the ready packet sent by the routing board, it can generate a trigger signal and send the trigger signal to the routing board. The routing board can, according to the received trigger signal, start the corresponding second thread sub-module, that is, the corresponding second thread sub-module generates a trigger signal according to the trigger data stored therein (i.e., the second trigger data in the following text), thereby triggering the lower-layer board card communicatively connected to execute multiple quantum computing tasks in parallel. During this process, the thread module in the central control board enables the routing board to start the parallel execution of multiple quantum computing tasks through the trigger signal it generates, that is, it prompts the routing board to generate a trigger signal for triggering the parallel execution of multiple quantum computing tasks. The routing module is used to start / trigger the parallel execution of multiple quantum computing tasks in the lower-layer board. Here, the parallel execution process of the quantum computing tasks by the above-mentioned quantum computing measurement and control system will not be specifically described.

[0077] In an embodiment of the present application, for each routing board, the second thread sub-modules included in the routing board correspond one-to-one to the first thread sub-modules in the above-mentioned thread module. That is, in each routing board, there is a second thread sub-module whose identification information is the same as the identification information of any one of the first thread sub-modules.

[0078] In the above Figure 2 In the quantum computing measurement and control system shown, when the quantum computing measurement and control system is running normally, the above-mentioned thread module can store first synchronization data, and each first thread sub-module can store its corresponding first trigger data. The above-mentioned routing board can store second synchronization data, and each second thread sub-module can store second trigger data.

[0079] The above-mentioned first synchronization data can be used to generate a synchronization cycle pulse corresponding to the thread module, and the synchronization cycle pulse is used to ensure signal synchronization among the first thread sub-modules in the thread module. The above-mentioned first trigger data can include the stored data and status data corresponding to each first thread sub-module. The stored data and status data (i.e., trigger information) are used to generate a trigger signal for triggering the routing board to start the parallel execution of multiple quantum computing tasks.

[0080] The above second synchronization data is generated by the routing board according to the above first synchronization data, and the second synchronization data is used to generate a synchronization period pulse corresponding to the routing board. While ensuring signal synchronization between the second thread sub-modules in each routing board, the synchronization period pulse can also ensure signal synchronization between the routing board and the central control board. The above second trigger data may include the number of triggers and the trigger interval corresponding to the trigger signal generated by the routing board.

[0081] In the embodiments of the present application, no specific limitations are imposed on the above first synchronization data, second synchronization data, first trigger data, and second trigger data.

[0082] In the above quantum computing measurement and control system, by deploying multiple thread sub-modules in the thread module of the central control board and each routing board, the central control module and the routing board can simultaneously trigger the parallel execution of multiple quantum computing tasks, realizing multi-threaded quantum computing and improving the efficiency of quantum computing.

[0083] Through the above Figure 1 As shown in the method, after the host computer sends a reset instruction packet to the central control board, the first parsing module in the central control board sends a first reset signal to the thread module in the central control board and a reset data packet to the routing board communicatively connected to the central control board through parsing the received reset instruction packet. The thread module can perform a reset operation according to the received first reset signal, and the routing board can also perform a reset operation according to the received reset data packet, realizing the reset of the thread module and the routing board. This realizes the reset operation of the quantum computing measurement and control system and provides guarantee for the normal execution of quantum computing tasks.

[0084] The embodiments of the present application will be described below through specific examples.

[0085] Regarding the above step S101, that is, the host computer sends a reset instruction packet to the first parsing module.

[0086] In this step, for the central control board and the routing board in the above quantum computing measurement and control system, the host computer can trigger the reset operations of the central control board and the routing board according to user operations or abnormal detection results, etc. At this time, the host computer can generate a reset instruction packet for indicating the reset operation. The host computer can send the reset instruction packet to the central control board, and the first parsing module in the central control board receives the reset instruction packet.

[0087] For example, as shown above Figure 2 After the host computer sends the above reset instruction packet to the central control board, the reset instruction packet will be transmitted to the first transmission module through the 100M network driver in the central control board, and then forwarded by the first transmission module to the first parsing module. Among them, the first transmission module can be a network data transmission module for forwarding instruction packets.

[0088] In the embodiments of the present application, according to different triggering manners of the reset operation, the reset instruction packets generated by the above host computer will also be different. For example, the above reset instruction packets may be a first instruction packet, a second instruction packet, or a third instruction packet. Among them, the first instruction packet is used to indicate a global reset operation, the second instruction packet is used to indicate an abnormal reset operation, and the third instruction packet is used to perform a thread reset operation. The generation manners of the above different reset instruction packets can be seen in the following description and will not be elaborated here.

[0089] Regarding the above step S102, that is, the first parsing module sends a first reset signal to the thread module and sends a reset data packet to the routing board card based on the received reset instruction packet.

[0090] In this step, after the host computer sends the reset instruction packet to the central control board card, the first parsing module in the central control board card will receive the reset instruction packet and perform parsing processing on the received reset instruction packet. By parsing the reset instruction packet, the first parsing module can determine that the thread module and the routing board card in the central control board card need to be reset according to the instruction type of the reset instruction packet. At this time, based on the reset instruction packet, the first parsing module can send a first reset signal to the thread module and send a reset data packet to the routing board card.

[0091] Regarding the above first instruction packet, second instruction packet, and third instruction packet, the instruction types corresponding to these three reset instruction packets are different. Therefore, the above first parsing module can determine the instruction type corresponding to the reset instruction packet by parsing the reset instruction packet. According to this instruction type, the first parsing module will trigger different types of reset operations on the thread module and the routing board card. The specific details can be seen in the following description and will not be elaborated here.

[0092] In the embodiments of the present application, since the above first parsing module and the thread module are both on the above central control board card, the first parsing module can directly send the above first reset signal to the thread module. However, since the central control board card and the routing board card are independent of each other, combining the above Figure 2 The process of the first parsing module sending the reset data packet to the routing board card can be specifically expressed as: the first parsing module sends the reset signal (for easy distinction, denoted as the third reset signal) to the second transmission module, and the second transmission module encapsulates the received third reset signal according to the preset transmission protocol to obtain a reset data packet and transmits the reset data packet to the routing board card.

[0093] In an alternative embodiment, the second transmission module may be an RS422 transmission module, and the preset transmission protocol may be an RS422 transmission protocol. RS422 is a series of data transmission protocols that specify four-wire, full-duplex, differential transmission, and multi-point communication.

[0094] Regarding step S103 above, that is, the thread module performs a reset operation according to the received first reset signal.

[0095] In this step, after the first parsing module sends the first reset signal to the thread module, the thread module can receive the first reset signal. According to the first reset signal, the thread module can trigger its own reset operation and the reset operation of each first thread sub-module included therein.

[0096] Regarding step S104 above, that is, the routing board performs a reset operation according to the received reset data packet.

[0097] In this step, after the first parsing module sends the reset data packet to the routing board, the routing board will receive the reset data packet. According to the reset data packet, the routing board can trigger its own reset operation and the reset operation of the second thread sub-module included therein.

[0098] For the specific manner of the corresponding reset operations of the above thread module and routing board, reference can be made to the following description and will not be elaborated here.

[0099] In the embodiment of the present application, step S103 may be executed before or after step S104, or may be executed simultaneously with step S104. Here, the execution order of step S103 and step S104 is not specifically limited.

[0100] In an alternative embodiment, according to the above Figure 1 shown method, the embodiment of the present application further provides a reset operation method. As Figure 3 shown, Figure 3 This is the second signaling diagram of the reset operation method provided by the embodiment of the present application. The method may include the following steps.

[0101] Step S301, when the host computer receives a start instruction for the quantum computing measurement and control system, generate a first instruction packet, where the first instruction packet is used to indicate a global reset operation.

[0102] In this step, when the user triggers the start operation of the above quantum computing measurement and control system, the host computer in the quantum computing measurement and control system will receive the start instruction for the quantum computing measurement and control system. At this time, in order to ensure the normal operation of the quantum computing measurement and control system, the host computer can generate a reset instruction packet for indicating a global reset operation, that is, the above first instruction packet.

[0103] Step S302: The host computer sends a first instruction packet to the first parsing module.

[0104] The above step S302 is a refinement of the above step S101.

[0105] Through the above steps S301 - S302, when the host computer receives a startup instruction for the quantum computing measurement and control system, it can generate a first instruction packet, thereby triggering a global reset operation for the thread module and the routing board. This enables a global reset operation to be performed every time the quantum computing measurement and control system is started, effectively ensuring that there is no residual data associated with the previous startup process in the quantum computing measurement and control system after each startup. This avoids the impact of the residual data stored in the quantum computing measurement and control system on the execution of the quantum computing task after the current startup. While ensuring the normal progress of the global reset operation of the quantum computing measurement and control system, it effectively improves the accuracy of the execution of the quantum computing task, thereby enhancing the accuracy and effectiveness of quantum computing.

[0106] Step S303: Based on the received reset instruction packet, the first parsing module sends a first reset signal to the thread module and a reset data packet to the routing board.

[0107] In an optional embodiment, when the above reset instruction packet is the above first instruction packet, the above step S303 can be specifically expressed as:

[0108] Based on the received first instruction packet, the first parsing module sends a global reset signal to the thread module and a global reset data packet to the routing board.

[0109] In this step, after receiving the above first instruction packet, the first parsing module can determine that a global reset operation needs to be performed by parsing the first instruction packet. At this time, the first reset signal sent by the first parsing module to the thread module is a global reset signal, and the reset data packet sent by the first parsing module to the routing board is a global reset data packet.

[0110] By sending the above global reset signal and global reset data packet, the thread module and the routing board can perform global reset operations respectively, effectively ensuring the normal execution of the subsequent quantum computing task while achieving the global reset operation of the quantum computing measurement and control system.

[0111] Step S304: The thread module performs a reset operation according to the received first reset signal.

[0112] In an optional embodiment, when the above reset instruction packet is the above first instruction packet, for the above first synchronization data and first trigger data, the global reset operation of the thread module can be specifically expressed as:

[0113] The thread module deletes the first synchronization data and the first trigger data according to the received global reset signal.

[0114] In this step, after receiving the above global reset signal, the thread module will trigger the global reset operations of itself and each first thread sub-module. At this time, the thread module and the first thread sub-module clear all the data stored in them respectively, realizing the global reset of the thread module. That is, the thread module can delete the first synchronization data stored in itself, and each first thread sub-module can delete the first trigger data stored in itself.

[0115] In the embodiment of the present application, by deleting the above first synchronization data and first trigger data, the data stored in the thread module and each first thread sub-module can be effectively cleared, realizing the global reset operations of the thread module and each first thread sub-module, avoiding the influence of the residual data in the thread module and the first thread sub-module on the trigger signal generated by the thread module, and further affecting the parallel execution of multiple quantum computing tasks by the routing board, which provides an important guarantee for the normal execution of quantum computing tasks.

[0116] Step S305, the routing board performs a reset operation according to the received reset data packet.

[0117] In an optional embodiment, when the above reset instruction packet is the above first instruction packet, for the above second synchronization data and second trigger data, the global reset operation of the routing board can be specifically expressed as:

[0118] The routing board deletes the second synchronization data and the second trigger data according to the received global reset data packet.

[0119] In this step, after receiving the above global reset data packet, the routing board will trigger the global reset operations of itself and each second thread sub-module. At this time, the routing board and the second thread sub-module clear all the data stored in them respectively, realizing the global reset of the routing board. That is, the routing board can delete the second synchronization data stored in itself, and each second thread sub-module can delete the second trigger data stored in itself.

[0120] The above step S304 can be executed before or after the above step S305, or can be executed simultaneously with the above step S305. Here, the execution time of the above step S304 and step S305 is not specifically limited.

[0121] In the embodiments of the present application, by deleting the above-mentioned second synchronization data and second trigger data, the data stored in the routing board and each second thread sub-module can be effectively cleared, realizing the global reset operation of the routing board and the second thread sub-module, avoiding the influence of the residual data in the routing board and the second thread sub-module on the parallel execution process of the quantum computing task, and effectively ensuring the normal execution of the quantum computing task.

[0122] In an alternative embodiment, according to the above Figure 1 method shown, the embodiments of the present application also provide a reset operation method. As Figure 4 shown, Figure 4 FIG. is the third signaling diagram of the reset operation method provided by the embodiments of the present application. The method includes the following steps.

[0123] Step S401, the host computer sends a reset instruction packet to the first parsing module.

[0124] The above step S401 is the same as the above step S101.

[0125] Step S402, the first parsing module returns a first response packet to the host computer for the reset instruction packet.

[0126] In this step, when the first parsing module receives the reset instruction packet sent by the host computer, the first parsing module can generate a response packet for the reset instruction packet (denoted as the first response packet), and send the first response packet to the host computer.

[0127] The above first response packet can be the response data packet corresponding to the reset instruction packet. The first response packet can be used to indicate that the central control has received the reset instruction packet and starts the reset operation based on the reset instruction packet. The sending process of the first response packet can be the reverse operation of the above reset data packet sending process, which will not be specifically described here.

[0128] Step S403, the host computer receives the first response packet.

[0129] In this step, after the first parsing module sends the first response packet, the host computer will receive the first response packet. At this time, the host computer can determine that the central control board has received the reset instruction packet sent by it according to the received first response packet, and starts the reset operation according to the reset instruction packet.

[0130] In the embodiments of the present application, through the sending and receiving of the above first response packet, the host computer can timely and accurately determine whether the central control board has received the reset instruction packet and whether it starts the reset operation, ensuring the effective control of the host computer over the reset process, and also facilitating the user to timely understand the reset process through the host computer.

[0131] Step S404: If the host computer does not receive the first response packet within the first preset time period, the host computer generates a second instruction packet and uses the second instruction packet as a reset instruction packet, and returns to execute the step of sending the reset instruction packet to the first parsing module. The second instruction packet is used to indicate an abnormal reset operation.

[0132] In the embodiment of the present application, after the host computer sends the above-mentioned reset instruction packet to the central control board, affected by factors such as the network or system, it may cause the host computer to be unable to receive the first response packet, or the received first response packet times out. For example, affected by factors such as the network or system, the host computer fails to successfully transmit the above-mentioned reset instruction packet to the central control board or the first parsing module. For another example, the first parsing module successfully receives the above-mentioned reset instruction packet, but affected by factors such as the network or system, the first parsing module fails to successfully transmit the above-mentioned first response packet to the host computer.

[0133] After the host computer sends the above-mentioned reset instruction packet to the central control board, it can detect in real time whether it receives the first response packet returned by the first parsing module.

[0134] If the host computer does not receive the first response packet within the first preset time period, the host computer can determine that there is an abnormality in the quantum computing measurement and control system. At this time, the host computer can generate a reset instruction packet for indicating an abnormal reset operation, that is, the above-mentioned second instruction packet. The host computer can re-send the reset instruction packet to the first parsing module based on the second instruction packet, that is, use the second instruction packet as the above-mentioned reset instruction packet, and return to execute the above-mentioned step S401, that is, return to execute the step of sending the reset instruction packet to the first parsing module, which can be specifically expressed as: sending the second instruction packet to the first parsing module.

[0135] In the embodiment of the present application, the reset data packet sent by the host computer before the first time of sending the above-mentioned second instruction packet can be the above-mentioned first instruction packet or the third instruction packet, and no specific limitation is made here.

[0136] The above-mentioned first preset time period can be set according to the data transmission rate between the host computer and the first parsing module, user experience, etc. Here, no specific limitation is made on the above-mentioned first preset time period.

[0137] In the embodiment of the present application, the above-mentioned step S404 can be executed after the above-mentioned step S401, or can be executed after the above-mentioned step S402. Here, no specific limitation is made on the execution time of the above-mentioned step S404.

[0138] In addition, in the case where the first parsing module sends the first response packet to the host computer, the host computer may execute the above-mentioned step S403 or may execute the above-mentioned step S404. Here, no specific limitation is made on the execution of the above-mentioned step S403 and step S404.

[0139] Through the above step S404, in the case that the host computer does not receive the first response packet within the first preset duration, by sending the above second instruction packet, the host computer can trigger the thread module and the routing board in the central control board to perform an abnormal reset operation, thereby effectively coping with the impact caused by the abnormal phenomenon reset operation, ensuring the normal progress of the reset operation of the quantum computing measurement and control system, and improving the fault tolerance rate of the quantum computing measurement and control system and the accuracy of the subsequent quantum computing task execution process.

[0140] Step S405: Based on the received reset instruction packet, the first parsing module sends a first reset signal to the thread module and sends a reset data packet to the routing board.

[0141] In an optional embodiment, when the above reset instruction packet is the above second instruction packet, step S405 can be specifically expressed as:

[0142] Based on the received second instruction packet, the first parsing module sends an abnormal reset signal to the thread module and sends an abnormal reset data packet to the routing board.

[0143] In this step, after receiving the above second instruction packet, the first parsing module can determine that an abnormal reset operation needs to be performed by parsing the second instruction packet. At this time, the first reset signal sent by the first parsing module to the thread module is an abnormal reset signal, and the reset data packet sent by the first parsing module to the routing board is an abnormal reset data packet.

[0144] When an abnormal phenomenon occurs, by sending the above abnormal reset signal and abnormal reset data packet, the thread module and the routing board can respectively perform an abnormal reset operation. While realizing the reset operation of the quantum computing measurement and control system, it effectively avoids the impact of the abnormal phenomenon on the reset operation of the quantum computing measurement and control system, improves the accuracy of the reset operation of the quantum computing measurement and control system, thereby improving the accuracy of the subsequent quantum computing task execution and the accuracy of quantum computing.

[0145] Step S406: The thread module performs a reset operation according to the received first reset signal.

[0146] In an optional embodiment, when the above reset instruction packet is the above second instruction packet, for the above first synchronization data and first trigger data, the abnormal reset operation of the thread module can be specifically expressed as:

[0147] The thread module deletes the first trigger data according to the received abnormal reset signal.

[0148] In this step, after receiving the above abnormal reset signal, the thread module will trigger each first thread sub-module included therein to perform an abnormal reset operation. At this time, each first thread sub-module can clear all the data stored therein, realizing the abnormal reset of the thread module. That is, only the first trigger data is deleted during the abnormal reset operation of the thread module, and the first synchronization data stored in the thread module is retained.

[0149] In the embodiment of the present application, since the first trigger data in each of the above first thread sub-modules is stored according to the information in the respective received ready packets, the accuracy of the first trigger data is affected by factors such as the transmission network or system. Once an abnormal phenomenon occurs, the accuracy and validity of the first trigger data stored in each first thread sub-module cannot be guaranteed. Therefore, during the abnormal reset operation of the above thread module, by deleting the first trigger data in each first thread sub-module, the possibility of the first trigger data stored in each first thread sub-module being abnormal can be effectively reduced, ensuring the accuracy of the trigger signal generated based on the first trigger data later, and thus avoiding the influence of the trigger signal generated based on the abnormal first trigger data on the execution of the later quantum computing task.

[0150] In addition, since the first synchronization data in the above thread module is a control variable related to the quantum computing task execution environment, during the abnormal reset operation of the quantum computing measurement and control system, by retaining the first synchronization data, the consistency between the later quantum computing task corresponding execution environment and the execution environment before the abnormal reset operation can be effectively guaranteed, providing a guarantee for the continuous execution of the quantum computing task.

[0151] Step S407, the routing board performs a reset operation according to the received reset data packet.

[0152] In an optional embodiment, when the above reset instruction packet is the above second instruction packet, for the above second synchronization data and second trigger data, the abnormal reset operation of the routing board can be specifically expressed as:

[0153] The routing board deletes the second trigger data according to the received abnormal reset data packet.

[0154] In this step, after receiving the above abnormal reset data packet, the routing board will trigger each second line sub-module included therein to perform an abnormal reset operation. At this time, each second thread sub-module can clear all the data stored therein, realizing the abnormal reset of the routing board. That is, only the above second trigger data is deleted during the abnormal reset operation of the routing board, and the second synchronization data in the routing board is retained.

[0155] The above step S406 may be executed before or after the above step S407, or may be executed simultaneously with the above step S407. Here, the execution time of the above step S406 and step S407 is not specifically limited.

[0156] In the embodiments of the present application, the second trigger data in each of the above second thread sub-modules may be sent by the above host computer and stored in the routing board. During this process, affected by factors such as the transmission network or system, once an abnormal phenomenon occurs, the accuracy of the second trigger data stored in the second thread sub-module will be affected. Therefore, during the abnormal reset operation of the above routing board, by deleting the second trigger data in each second thread sub-module, the possibility of the second trigger data stored in the second thread sub-module being abnormal can be effectively reduced, thereby avoiding the influence of abnormal second trigger data on the execution process of the later quantum computing task, ensuring the accuracy of the second trigger data stored in the second thread sub-module, and the accuracy of the execution of the later quantum computing task.

[0157] In addition, since the second synchronization data in the above routing board is also a control variable related to the quantum computing task execution environment, during the abnormal reset operation of the quantum computing measurement and control system, by retaining the second synchronization data, the consistency of the execution environment corresponding to the later quantum computing task and the execution environment before the abnormal reset operation can be effectively ensured, providing a guarantee for the continuous execution of the quantum computing task.

[0158] In the above Figure 4 In the illustrated embodiment, only the issuance of a second instruction packet is taken as an example for illustration. In addition, after the host computer sends a second instruction packet to the first parsing module, if a return packet for the second instruction packet is not received within the first preset time period, the host computer will re-send the second instruction packet to the first parsing module, and so on. When the abnormal phenomenon persists, the host computer will send a second instruction packet once every first preset time period.

[0159] In an alternative embodiment, to avoid waste of network resources, the host computer may count the number of consecutive second instruction packets sent. When the number is equal to the preset number, the host computer may generate a prompt message, which can be used to prompt the user that there is an abnormal phenomenon, so that the user can learn of the existence of the abnormal phenomenon and eliminate the abnormal phenomenon in a timely manner, ensuring the normal operation of the quantum computing measurement and control system.

[0160] In the embodiments of the present application, the above central control board may further include the above second parsing module, which is used to assist the thread module. For example, the above second parsing module may be a ready packet parsing module, and the above ready packet is sent to the central control board in the form of a serial data packet. At this time, Figure 2When the second transmission module shown forwards the received serial data packet to the second parsing module, the second parsing module can perform serial-to-parallel conversion on the serial data packet to facilitate the thread module to process it one by one.

[0161] In an optional embodiment, according to the above Figure 1 , Figure 3 and Figure 4 shown method, when the above reset instruction packet is the above first instruction packet or the second instruction packet, the embodiment of the present application also provides a reset operation method. As Figure 5 shown, Figure 5 is the fourth signaling diagram of the reset operation method provided by the embodiment of the present application. This method adds the following steps, that is, step S105-step S106.

[0162] Step S105, based on the received reset instruction packet, the first parsing module sends a second reset signal to the second parsing module.

[0163] In an optional embodiment, if the reset instruction packet is the first instruction packet, the first parsing module sends a global reset signal to the second parsing module based on the received first instruction packet.

[0164] In another optional embodiment, if the reset instruction packet is the second instruction packet, the first parsing module sends an abnormal reset signal to the second parsing module based on the received second instruction packet.

[0165] The manner in which the above first parsing module sends a global reset signal or an abnormal reset signal to the second parsing module may refer to the manner in which the first parsing module sends a global reset signal or an abnormal reset signal to the thread module, and will not be specifically described here.

[0166] In the embodiment of the present application, when the above reset instruction packet is the first instruction packet or the second instruction packet, the first parsing module can perform a global reset operation or an abnormal reset operation on the first parsing module and the parsing module by sending a global reset signal or an abnormal reset signal to the above second parsing module, thereby realizing a global reset operation or an abnormal reset operation on the quantum computing measurement and control system, and ensuring the normal execution of the quantum computing task.

[0167] The above step S105 can be executed simultaneously with the above step S102.

[0168] Step S106, the second parsing module performs a reset operation according to the received second reset signal.

[0169] In the embodiment of the present application, the above second parsing module includes a shift register and an acquisition counter. Among them, the shift register is used to parse each ready packet in the above serial data packet, and the acquisition counter is used to determine the transmission rate of each parsed ready packet.

[0170] In an alternative embodiment, when the first parsing module sends a global reset signal to the second parsing module, the second parsing module can reset the shift register and the acquisition counter according to the received global reset signal.

[0171] In another alternative embodiment, when the first parsing module sends an abnormal reset signal to the second parsing module, the second parsing module can reset the shift register and the acquisition counter according to the received abnormal reset signal.

[0172] The reset of the shift register and the acquisition counter can be specifically represented as: deleting the data stored in the shift register and clearing the count of the acquisition counter.

[0173] In the embodiment of the present application, by resetting the shift register and the acquisition counter in the second parsing module, a global reset operation or an abnormal reset operation of the second parsing module can be realized.

[0174] Through the above steps S105 - S106, when the reset instruction packet is the first instruction packet or the second instruction packet, the reset operation of the central control board card includes not only the reset operation of the above thread module, but also the reset operation of the second parsing module in the central control board card, effectively ensuring the comprehensiveness of the reset operation of the central control board card, thereby improving the integrity and accuracy of the reset operation of the quantum computing measurement and control system, and providing guarantee for the normal execution of quantum computing tasks.

[0175] In an alternative embodiment, according to the above Figure 1 shown method, the embodiment of the present application also provides a reset operation method. As Figure 6 shown, Figure 6 is the fifth signaling diagram of the reset operation method provided by the embodiment of the present application. The method includes the following steps.

[0176] Step S601, the host computer receives a second response packet, which is sent by the routing board card when the target quantum computing task is completed.

[0177] In this step, for each quantum computing task, when the quantum computing task is completed, the lower - layer board card will notify the routing board card. At this time, the routing board card can send a second response packet to the host computer for the completed quantum computing task (denoted as the target quantum computing task). The host computer will also receive this second response packet.

[0178] The above - mentioned second response packet is used to indicate the completion of the execution of the corresponding target quantum computing task.

[0179] Through the sending and receiving of the above-mentioned second response packet, the host computer can determine the completion of the execution of the target quantum computing task based on the received second response packet, that is, determine that the computing resources corresponding to the corresponding second thread sub-module in the routing board are released and can be used for the execution of other quantum computing tasks, so as to facilitate the user to timely know the execution situation of the quantum computing task, and then reasonably arrange the execution of each quantum computing task.

[0180] Step S602: If the host computer does not receive the second response packet within the second preset time period, the host computer sends a third instruction packet carrying identification information to the first parsing module. The third instruction packet instructs to perform a thread reset operation, and the identification information matches the second thread sub-module that triggers the execution of the target quantum computing task.

[0181] In this step, for each second thread sub-module in the routing board, after the second thread sub-module triggers the execution of the above-mentioned target quantum computing task, if the host computer does not receive the above-mentioned second response packet within the second preset time period, the host computer can send a third instruction packet for instructing to perform a thread reset operation to the first parsing module. The third instruction packet may include the identification information of the second thread sub-module corresponding to the target quantum computing task.

[0182] In the embodiment of the present application, the number of the identification information carried in the above-mentioned third instruction packet may be one or more. Here, the number of the identification information included in the above-mentioned third instruction packet is not specifically limited. For the convenience of understanding, only one identification information is taken as an example for illustration below, which does not play any limiting role.

[0183] The above-mentioned second preset time period can be set according to the data transmission rate between the host computer and the routing board and user experience, etc. Here, the above-mentioned second preset time period is not specifically limited.

[0184] The above-mentioned step S602 is a refinement of the above-mentioned step S101.

[0185] In the embodiment of the present application, the above-mentioned step S601 and step S602 are respectively the steps executed when the host computer receives the second response packet and when the host computer does not receive the second response packet. Here, the execution of the above-mentioned step S601 and step S602 is not specifically limited.

[0186] Through the above-mentioned step S602, for the situation where the host computer does not receive the second response packet within the second preset time period, by issuing the above-mentioned third instruction packet, the host computer triggers the reset operation of the second thread sub-module corresponding to the target quantum computing task and also triggers the reset operation of the first thread sub-module corresponding to the second thread sub-module, thereby effectively coping with the influence caused by the abnormality of a small number of thread sub-modules, ensuring that the normal operation of other thread sub-modules is not affected, and improving the execution efficiency of the quantum computing task.

[0187] Step S603: Based on the received reset instruction packet, the first parsing module sends a first reset signal to the thread module and sends a reset data packet to the routing board.

[0188] In an optional embodiment, when the above-mentioned reset instruction packet is the above-mentioned third instruction packet, the above-mentioned step S603 can be specifically expressed as:

[0189] Based on the received third instruction packet, the first parsing module sends a thread reset signal including identification information to the thread module and sends a thread reset data packet including identification information to the routing board.

[0190] In this step, after receiving the above-mentioned third instruction packet, the first parsing module can determine, by parsing the third instruction packet, that a reset operation needs to be performed on the thread sub-module matching the identification information. At this time, the first reset signal sent by the first parsing module to the thread module is a thread reset signal carrying the identification information, and the reset data packet sent by the first parsing module to the routing board is a thread reset data packet carrying the identification information.

[0191] By sending the above-mentioned thread reset signal and thread reset data packet, the thread module and the routing board can perform a reset operation on the first thread sub-module and the second thread sub-module matching the identification information, avoiding the influence of the abnormal second thread sub-module on the execution process of the quantum computing task, realizing the reset operation on the abnormal second thread sub-module, and ensuring the normal execution of the subsequent quantum computing task.

[0192] Step S604: The thread module performs a reset operation according to the received first reset signal.

[0193] In an optional embodiment, when the above-mentioned reset instruction packet is the above-mentioned third instruction packet, for the above-mentioned first synchronization data and first trigger data, the thread reset operation of the thread module can be specifically expressed as:

[0194] The thread module deletes the first trigger data in the first thread sub-module matching the identification information according to the received thread reset signal.

[0195] In this step, after receiving the above-mentioned thread reset signal, the thread module can determine, according to the identification information in the thread reset signal, the first thread sub-module that needs to perform a reset operation, that is, the first thread sub-module matching the identification information, thereby triggering the reset operation on the first thread sub-module. That is, deleting the first trigger data stored in the first thread sub-module.

[0196] In an embodiment of the present application, when an exception occurs in the second thread sub-module, the first thread sub-module in the thread module that is associated with the exception second thread sub-module is: the first thread sub-module with matching identification information. Therefore, the thread reset operation in the thread module is only performed on the first thread sub-module that matches the identification information in the thread reset signal. This reset operation is only for the first thread sub-module associated with the exception second thread sub-module, effectively avoiding the impact of this reset operation on other first thread sub-modules in the thread module, ensuring the normal operation of other first thread sub-modules, and thus ensuring the normal operation of the second thread sub-modules associated with other first thread sub-modules. This effectively improves the pertinence and accuracy of the thread reset operation in the thread module. While implementing the reset operation for one or more first thread sub-modules, it does not affect the normal operation of other first thread sub-modules, improving the accuracy and effectiveness of the thread module operation.

[0197] In addition, during the thread reset operation of the above thread module, the first synchronization data in the thread module is not processed. This allows other first thread sub-modules in the thread module, except for the first thread sub-module performing the reset operation, to synchronize the trigger signal based on the synchronization cycle pulse corresponding to the first synchronization data, ensuring the normal operation of other first thread sub-modules in the thread module.

[0198] Step S605: The routing board performs a reset operation according to the received reset data packet.

[0199] In an optional embodiment, when the above reset instruction packet is the above third instruction packet, for the above second synchronization data and second trigger data, the thread reset operation of the routing board can be specifically expressed as:

[0200] The routing board deletes the second trigger data in the second thread sub-module that matches the identification information according to the received thread reset data packet.

[0201] In this step, after receiving the above thread reset data packet, the routing board can determine the second thread sub-module that needs to perform the reset operation according to the identification information in the thread reset data packet, that is, the second thread sub-module that matches the identification information, thereby triggering the reset operation on this second thread sub-module. That is, deleting the second trigger data stored in this second thread sub-module.

[0202] The above step S605 can be executed before or after the above step S604, or can be executed simultaneously with the above step S604. Here, the execution time of the above step S604 and step S605 is not specifically limited.

[0203] In the embodiment of the present application, when an exception occurs in the second thread sub-module that triggers the execution of the target quantum computing task, the thread reset operation in the routing board is performed on this second thread sub-module, which enables other second thread sub-modules in the routing board to operate normally, improving the pertinence and accuracy of the thread reset operation in the routing board. While implementing the reset operation for one or more second thread sub-modules, it does not affect the normal operation of other second thread sub-modules, improving the accuracy and effectiveness of the routing board operation.

[0204] In addition, during the thread reset operation of the above routing board, the second synchronization data in the routing board is not processed, which enables other second thread sub-modules in the routing board to perform synchronization processing of the quantum computing task based on the synchronization period pulse signal corresponding to the second synchronization data, ensuring the normal operation of other second thread sub-modules in the routing board.

[0205] Based on the same inventive concept, according to the reset operation method provided in the embodiment of the present application, the embodiment of the present application also provides a reset operation method. As Figure 7 shown, Figure 7 FIG. 10 is a first flow chart of the reset operation method provided by the embodiment of the present application. This method can be applied to the first parsing module in the above central control board. The central control board, the host computer, and the routing board constitute a quantum computing measurement and control system. The central control board further includes a thread module for triggering the routing board to start multiple quantum computing tasks to execute in parallel. In Figure 7 the method shown includes the following steps.

[0206] Step S701, receive a reset instruction packet sent by the host computer.

[0207] In this step, the host computer can send a reset instruction packet to the central control board. Through other modules in the central control board, such as the 100M network driver and the first transmission module shown above, this reset instruction packet will be transmitted to the first parsing module in the central control board. At this time, the first parsing module will receive this reset instruction packet. Figure 2 In an optional embodiment, the above reset instruction packet can be a first instruction packet, a second instruction packet, or a third instruction packet. Among them, the first instruction packet is used to indicate a global reset operation, the second instruction packet is used to indicate an abnormal reset operation, and the third instruction packet is used to indicate a thread reset operation.

[0208] Step S702, based on the reset instruction packet, send a first reset signal to the thread module, so that the thread module performs a reset operation according to the first reset signal.

[0209]

[0210] ​In this step, after receiving the above reset instruction packet, the first parsing module can parse and process the reset instruction packet to determine that a reset operation is required. At this time, the first parsing module can send a first reset signal to the thread module in the central control board. After receiving the first reset signal, the thread module can perform a reset operation.

[0211] In the embodiment of the present application, multiple first thread sub-modules may be included in the above thread module. Among them, first synchronization data may be stored in the thread module, and first trigger data may be stored in each first thread sub-module.

[0212] In an optional embodiment, if the reset instruction packet is a first instruction packet, based on the first instruction packet, the first parsing module can send a global reset signal to the thread module, so that the thread module deletes the first synchronization data and the first trigger data according to the global reset signal.

[0213] In another optional embodiment, if the reset instruction packet is a second instruction packet, based on the second instruction packet, the first parsing module can send an abnormal reset signal to the thread module, so that the thread module deletes the first trigger data according to the abnormal reset signal.

[0214] In yet another optional embodiment, if the reset instruction packet is a third instruction packet carrying identification information, based on the third instruction packet, the first parsing module can send a thread reset signal including the identification information to the thread module, so that the thread module deletes the first trigger data in the first thread sub-module matching the identification information based on the thread reset signal.

[0215] In the embodiment of the present application, according to the instruction type corresponding to the above reset instruction packet and the different information carried by the reset instruction packet, the first parsing module can send different reset signals to the thread module, so that the thread module and the first thread sub-modules in the thread module adopt different reset methods to implement the reset operation of the thread module, ensuring the validity and accuracy of the data stored in the thread module and the first thread sub-modules, and providing guarantee for the generation of trigger signals in the later stage.

[0216] Step S703, based on the reset instruction packet, send a reset data packet to the routing board, so that the routing board performs a reset operation according to the reset data packet.

[0217] In this step, when the first parsing module parses the reset instruction packet and determines that a reset operation is required, it can send a reset data packet to the above routing board. After receiving the reset data packet, the routing board can perform a reset operation.

[0218] In the embodiments of the present application, the above routing board card may include multiple second thread sub-modules. Among them, second synchronization data may be stored in the routing board card, and second trigger data corresponding to the quantum computing task may be stored in each second thread sub-module.

[0219] In an optional embodiment, if the reset instruction packet is the first instruction packet, based on the first instruction packet, the first parsing module may send a global reset data packet to the routing board card, so that the routing board card deletes the second synchronization data and the second trigger data according to the global reset data packet.

[0220] In another optional embodiment, if the reset instruction packet is the second instruction packet, based on the second instruction packet, the first parsing module may send an abnormal reset data packet to the routing board card, so that the routing board card deletes the second trigger data according to the abnormal reset data packet.

[0221] In yet another optional embodiment, if the reset instruction packet is the third instruction packet, based on the third instruction packet, the first parsing module may send a thread reset data packet including identification information to the routing board card, so that the routing board card deletes the second trigger data in the second thread sub-module that matches the identification information according to the thread reset data packet.

[0222] In the embodiments of the present application, according to the instruction type corresponding to the above reset instruction packet and the difference in the information carried by the reset instruction packet, the first parsing module may send different reset data packets to the routing board card, so that the routing board card and the second thread sub-module in the routing board card adopt different reset methods, realizing the reset operation of the routing board card, ensuring the validity and accuracy of the data stored in the routing board card and the second thread sub-module, and providing guarantee for the execution of the subsequent quantum computing task.

[0223] By Figure 7 the method shown, after the host computer sends a reset instruction packet to the central control board card, the first parsing module in the central control board card sends a first reset signal to the thread module in the central control board card and sends a reset data packet to the routing board card communicatively connected to the central control board card through the parsing of the received reset instruction packet. The thread module may perform a reset operation according to the received first reset signal, and the routing board card may also perform a reset operation according to the received reset data packet, realizing the reset of the thread module and the routing board card. This realizes the reset operation of the quantum computing measurement and control system and provides guarantee for the normal execution of the quantum computing task.

[0224] In an optional embodiment, after receiving the above reset instruction packet, the above first parsing module may send a first response packet for the reset instruction packet to the host computer.

[0225] In an optional embodiment, according to the above Figure 7For the method shown above, when the above reset instruction packet is the above first instruction packet or the second instruction packet, the embodiments of the present application also provide a reset operation method. As Figure 8 shown, Figure 8 This is the second flow diagram of the reset operation method provided by the embodiments of the present application. In Figure 8 the method shown above, the following step is added, that is, step S704.

[0226] Step S704: Based on the first instruction packet / second instruction packet, send a second reset signal to the second parsing module, so that the second parsing module performs a reset operation according to the second reset signal.

[0227] In this step, when the reset instruction packet received by the first parsing module is the above first instruction packet or the second instruction packet, the first parsing module can send a second reset signal to the second parsing module. The second reset signal can be a global reset signal or an exception reset signal. That is, when the above reset instruction packet is the first instruction packet, the second reset signal is a global reset signal; when the above reset instruction packet is the second instruction packet, the second reset signal is an exception reset signal. After receiving the second reset signal, the second parsing module can perform a reset operation.

[0228] In the embodiments of the present application, the above second parsing module is used to assist the above thread module. The second parsing module may include a shift register and an acquisition counter.

[0229] In an optional embodiment, when the above reset instruction packet is the first instruction packet, the first parsing module can send a global reset signal to the second parsing module based on the first instruction packet, so that the second parsing module resets the shift register and the acquisition counter according to the global reset signal.

[0230] In another optional embodiment, when the above reset instruction packet is the second instruction packet, the first parsing module can send an exception reset signal to the second parsing module based on the second instruction packet, so that the second parsing module resets the shift register and the acquisition counter according to the exception reset signal.

[0231] Through the above step S704, when the above reset instruction packet is the above first instruction packet or the second instruction packet, the first parsing module makes the second parsing module perform a reset operation according to the received reset signal by sending a reset signal to the second parsing module. While realizing the reset of the second parsing module, it ensures the comprehensiveness of the control board card reset during the global reset process and the exception reset process, thereby ensuring the comprehensiveness of the reset provided for quantum computing measurement and control.

[0232] In addition, in the embodiments of the present application, when the above reset instruction packet is the above third instruction packet, the first parsing module does not perform a reset operation on the second parsing module, which ensures the normal operation of other first thread sub-modules in the thread module that have not been reset and other second thread sub-modules in the routing board that have not been reset.

[0233] Based on the same inventive concept, according to the reset operation method provided in the above embodiments of the present application, the embodiments of the present application also provide a reset operation method. As Figure 9 shown, Figure 9 FIG. 9 is a third flowchart of the reset operation method provided in the embodiments of the present application. This method is applied to the thread module in the above central control board. The central control board, the host computer, and the routing board constitute a quantum computing measurement and control system. The thread module is used to trigger the routing board to start the parallel execution of multiple quantum computing tasks. The central control board may further include a first parsing module. In Figure 9 the method shown includes the following steps.

[0234] Step S901: Receive a first reset signal sent by the first parsing module based on a reset instruction packet. The reset instruction packet is sent by the host computer to the first parsing module.

[0235] In this step, the host computer in the quantum computing measurement and control system may send a reset instruction packet to the central control board. The reset instruction packet is transmitted to the first parsing module in the central control board and is parsed and processed by the first parsing module to determine that a reset operation needs to be performed. At this time, the first parsing module may send a first reset signal to the thread module.

[0236] In the embodiments of the present application, according to the different instruction types corresponding to the reset instruction packet, the above first reset signal will also be different. For example, when the above reset instruction packet is the first instruction packet for indicating a global reset, the above first reset signal may be a global reset signal; when the above reset instruction packet is the second instruction packet for indicating an abnormal reset, the above first reset signal may be an abnormal reset signal; when the above reset instruction packet is the third instruction packet for indicating a thread reset, the above first reset signal may be a thread reset signal. Here, the above reset instruction packet and the above first reset signal are not specifically limited.

[0237] Step S902: Perform a reset operation according to the first reset signal.

[0238] In the embodiments of the present application, the thread module may include multiple first thread sub-modules. Among them, the first synchronization data may be stored in the thread module, and the first trigger data may be stored in each first thread sub-module.

[0239] In an alternative embodiment, if the first reset signal is a global reset signal, the thread module may delete the first synchronization data and the first trigger data according to the global reset signal.

[0240] In another alternative embodiment, if the first reset signal is an exception reset signal, the thread module may delete the first trigger data according to the exception reset signal.

[0241] In yet another alternative embodiment, if the first reset signal is a thread reset signal carrying identification information, the thread module may delete the first trigger data in the first thread sub-module that matches the identification information according to the thread reset signal.

[0242] In the embodiments of the present application, according to the different reset signals received by the above thread module, the thread module will perform reset operations using different reset methods to achieve the reset of the thread module, avoiding the influence of abnormal phenomena on the thread module.

[0243] By Figure 9 the method shown, after the host computer sends a reset instruction packet to the central control board card, the first parsing module in the central control board card sends a first reset signal to the thread module in the central control board card and a reset data packet to the routing board card communicatively connected to the central control board card by parsing the received reset instruction packet. The thread module may perform a reset operation according to the received first reset signal, and the routing board card may also perform a reset operation according to the received reset data packet, realizing the reset of the thread module and the routing board card. This realizes the reset operation of the quantum computing measurement and control system and provides guarantee for the normal execution of quantum computing tasks.

[0244] Based on the same inventive concept, according to the reset operation method provided by the embodiments of the present application above, the embodiments of the present application also provide a reset operation method. As Figure 10 shown, Figure 10 is the fourth process schematic diagram of the reset operation method provided by the embodiments of the present application. This method is applied to the routing board card in the above quantum computing measurement and control system. The routing board card is used to start the parallel execution of multiple quantum computing tasks. The quantum computing measurement and control system may further include a host computer and a central control board card, and the central control board card may include a first parsing module. In Figure 10 the method shown includes the following steps.

[0245] Step S1001: Receive the reset data packet sent by the first parsing module based on the reset instruction packet, and the reset instruction packet is sent by the host computer to the first parsing module.

[0246] In this step, the host computer in the quantum computing measurement and control system can send a reset instruction packet to the central control board. The reset instruction packet is transmitted to the first parsing module in the central control board and is parsed and processed by the first parsing module to determine that a reset operation is required. At this time, the first parsing module can send a reset data packet to the routing board.

[0247] In the embodiments of the present application, according to the different instruction types corresponding to the reset instruction packet, the above-mentioned reset data packet will also be different. For example, when the above-mentioned reset instruction packet is the first instruction packet for indicating a global reset, the above-mentioned reset data packet can be a global reset data packet; when the above-mentioned reset instruction packet is the second instruction packet for indicating an abnormal reset, the above-mentioned reset data packet can be an abnormal reset data packet; when the above-mentioned reset instruction packet is the third instruction packet for indicating a thread reset, the above-mentioned reset data packet can be a thread reset data packet. Here, no specific limitations are imposed on the above-mentioned reset instruction packet and the above-mentioned reset data packet.

[0248] Step S1002, perform a reset operation according to the reset data packet.

[0249] In the embodiments of the present application, the above-mentioned routing board may include a plurality of second thread sub-modules. Among them, the routing board may store second synchronization data, and each second thread sub-module may store second trigger data corresponding to the quantum computing task.

[0250] In an optional embodiment, if the reset data packet is a global reset data packet, the routing board may delete the second synchronization data and the second trigger data according to the global reset data packet.

[0251] In another optional embodiment, if the reset data packet is an abnormal reset data packet, the routing board may delete the second trigger data according to the abnormal reset data packet.

[0252] In yet another optional embodiment, if the reset data packet is a thread reset data carrying identification information, the routing board may delete the second trigger data in the second thread sub-module that matches the identification information according to the thread reset data packet.

[0253] In the embodiments of the present application, according to the different reset data packets received by the above-mentioned routing board, the routing board will perform a reset operation using different reset methods, achieving the reset of the routing board and avoiding the influence of abnormal phenomena on the routing board.

[0254] By Figure 10In the method shown, after the host computer sends a reset instruction packet to the central control board card, the first parsing module in the central control board card sends a first reset signal to the thread module in the central control board card and sends a reset data packet to the routing board card communicatively connected to the central control board card by parsing the received reset instruction packet. The thread module can perform a reset operation according to the received first reset signal, and the routing board card can also perform a reset operation according to the received reset data packet, realizing the reset of the thread module and the routing board card. This realizes the reset operation of the quantum computing measurement and control system and provides guarantee for the normal execution of quantum computing tasks.

[0255] In an optional embodiment, for each second thread sub-module in the above-mentioned routing board card, when the second thread sub-module determines that the quantum computing task is completed, it can send the above-mentioned second response packet to the host computer.

[0256] Based on the same inventive concept, according to the operation method provided in the embodiment of the present application above, the embodiment of the present application also provides a quantum computing measurement and control system. As Figure 11 shown, Figure 11 is the second structural schematic diagram of the quantum computing measurement and control system provided by the embodiment of the present application. The quantum computing measurement and control system includes a host computer 1101, a central control board card 1102, and a routing board card 1103. The central control board card 1102 includes a first parsing module 1104 and a thread module 1105. The thread module 1105 is used to trigger the routing board card 1103 to start the parallel execution of multiple quantum computing tasks;

[0257] The above-mentioned host computer 1101 is used to send a reset instruction packet to the first parsing module 1104;

[0258] The above-mentioned first parsing module 1104 is used to send a first reset signal to the thread module 1105 and send a reset data packet to the routing board card 1103 based on the received reset instruction packet;

[0259] The above-mentioned thread module 1105 is used to perform a reset operation according to the received first reset signal;

[0260] The above-mentioned routing board card 1103 is used to perform a reset operation according to the received reset data packet.

[0261] Optionally, the above-mentioned host computer 1101 can also be used to generate a first instruction packet for instructing a global reset operation if a start instruction for the quantum computing measurement and control system is received before the host computer 1101 sends a reset instruction packet to the first parsing module 1104;

[0262] The above-mentioned host computer 1101 is specifically used to send the first instruction packet to the first parsing module 1104.

[0263] Optionally, the above-mentioned thread module 1105 may include multiple first thread sub-modules, the above-mentioned routing board 1103 may include multiple second thread sub-modules, the thread module 1105 stores first synchronization data, each first thread sub-module stores first trigger data, the routing board 1103 stores second synchronization data, and each second thread sub-module stores second trigger data corresponding to the quantum computing task;

[0264] The above-mentioned first parsing module 1104 may specifically be configured to send a global reset signal to the thread module 1105 and send a global reset data packet to the routing board 1103 based on the received first instruction packet;

[0265] The above-mentioned thread module 1105 may specifically be configured to delete the first synchronization data and the first trigger data according to the received global reset signal;

[0266] The above-mentioned routing board 1103 may specifically be configured to delete the second synchronization data and the second trigger data according to the received global reset data packet.

[0267] Optionally, the above-mentioned first parsing module 1104 may further be configured to return a first response packet for the reset instruction packet to the host computer 1101 after the first parsing module 1104 receives the reset instruction packet;

[0268] The above-mentioned host computer 1101 may further be configured to receive the first response packet;

[0269] The above-mentioned host computer 1101 may further be configured to, if the host computer 1101 does not receive the first response packet within the first preset time period, generate a second instruction packet, use the second instruction packet as a reset instruction packet, and return to execute the step of sending the reset instruction packet to the first parsing module 1104, where the second instruction packet is used to indicate an abnormal reset operation.

[0270] Optionally, the above-mentioned thread module 1105 may include multiple first thread sub-modules, the above-mentioned routing board 1103 may include multiple second thread sub-modules, the thread module 1105 stores first synchronization data, each first thread sub-module stores first trigger data, the routing board 1103 stores second synchronization data, and each second thread sub-module stores second trigger data corresponding to the quantum computing task;

[0271] The above-mentioned first parsing module 1104 may specifically be configured to send an abnormal reset signal to the thread module 1105 and send an abnormal reset data packet to the routing board 1103 based on the received second instruction packet;

[0272] The above-mentioned thread module 1105 may specifically be configured to delete the first trigger data according to the received abnormal reset signal;

[0273] The above-mentioned routing board 1103 can specifically be used to delete the second trigger data according to the received abnormal reset data packet.

[0274] Optionally, the above-mentioned central control board 1102 may further include a second parsing module, and the second parsing module can be used to assist the thread module 1105;

[0275] The above-mentioned first parsing module 1104 can also be used to send a second reset signal to the second parsing module based on the received reset instruction packet;

[0276] The above-mentioned second parsing module can also be used to perform a reset operation according to the received second reset signal.

[0277] Optionally, the above-mentioned second parsing module may include a shift register and an acquisition counter;

[0278] The above-mentioned first parsing module 1104 can specifically be used to, if the reset instruction packet is a first instruction packet, send a global reset signal to the second parsing module based on the received first instruction packet; if the reset instruction packet is a second instruction packet, send an abnormal reset signal to the second parsing module based on the received second instruction packet;

[0279] The above-mentioned second parsing module can specifically be used to reset the shift register and the acquisition counter according to the received global reset signal / abnormal reset signal.

[0280] Optionally, the above-mentioned routing board 1103 may include multiple second thread sub-modules;

[0281] The above-mentioned host computer 1101 can also be used to receive a second response packet before the host computer 1101 sends a reset instruction packet to the first parsing module 1104, and the second response packet is sent by the routing board 1103 when the target quantum computing task is completed;

[0282] The above-mentioned host computer 1101 can specifically be used to, if the second response packet is not received within a second preset time period, send a third instruction packet carrying identification information to the first parsing module 1104, and the third instruction packet instructs to perform a thread reset operation, and the identification information matches the second thread sub-module that triggers the execution of the target quantum computing task.

[0283] Optionally, the above-mentioned thread module 1105 may include multiple first thread sub-modules, the above-mentioned thread module 1105 may store first synchronization data, each first thread sub-module stores first trigger data, the routing board 1103 stores second synchronization data, and each second thread sub-module stores second trigger data corresponding to the quantum computing task;

[0284] The above-mentioned first parsing module 1104 can be specifically configured to send a thread reset signal including identification information to the thread module 1105 and send a thread reset data packet including identification information to the routing board 1103 based on the received third instruction packet;

[0285] The above-mentioned thread module 1105 can be specifically configured to delete the first trigger data in the first thread sub-module that matches the identification information according to the received thread reset signal;

[0286] The above-mentioned routing board 1103 can be specifically configured to delete the second trigger data in the second thread sub-module that matches the identification information according to the received thread reset data packet.

[0287] Through Figure 11 the system shown, after the host computer sends a reset instruction packet to the central control board, the first parsing module in the central control board parses the received reset instruction packet, sends a first reset signal to the thread module in the central control board, and sends a reset data packet to the routing board communicatively connected to the central control board. The thread module can perform a reset operation according to the received first reset signal, and the routing board can also perform a reset operation according to the received reset data packet, realizing the reset of the thread module and the routing board. This realizes the reset operation of the quantum computing measurement and control system and provides guarantee for the normal execution of quantum computing tasks.

[0288] Based on the same inventive concept, according to the reset operation method provided in the embodiment of the present application above, the embodiment of the present application also provides a first parsing module. As Figure 12 shown, Figure 12 is a schematic structural diagram of the first parsing module provided in the embodiment of the present application. This first parsing module is deployed in the above-mentioned central control board. The central control board, the host computer, and the routing board constitute a quantum computing measurement and control system. The central control board further includes a thread module for triggering the routing board to start multiple quantum computing tasks to execute in parallel. Figure 12 The first parsing module shown includes:

[0289] A first receiving unit 1201, configured to receive a reset instruction packet sent by the host computer;

[0290] A first sending unit 1202, configured to send a first reset signal to the thread module based on the reset instruction packet, so that the thread module performs a reset operation according to the first reset signal;

[0291] A second sending unit 1203, configured to send a reset data packet to the routing board based on the reset instruction packet, so that the routing board performs a reset operation according to the reset data packet.

[0292] Optionally, the above thread module may include multiple first thread sub-modules, the above routing board may include multiple second thread sub-modules, the thread module stores first synchronization data, each first thread sub-module stores first trigger data, the routing board stores second synchronization data, and each second thread sub-module stores second trigger data corresponding to a quantum computing task;

[0293] The above first sending unit 1202 may specifically be configured to, if the reset instruction packet is a first instruction packet, based on the first instruction packet, send a global reset signal to the thread module, so that the thread module deletes the first synchronization data and the first trigger data according to the global reset signal;

[0294] If the reset instruction packet is a second instruction packet, based on the second instruction packet, send an abnormal reset signal to the thread module, so that the thread module deletes the first trigger data according to the abnormal reset signal;

[0295] If the reset instruction packet is a third instruction packet carrying identification information, based on the third instruction packet, send a thread reset signal including the identification information to the thread module, so that the thread module deletes the first trigger data in the first thread sub-module matching the identification information based on the thread reset signal;

[0296] The above second sending unit may specifically be configured to, if the reset instruction packet is a first instruction packet, based on the first instruction packet, send a global reset data packet to the routing board, so that the routing board deletes the second synchronization data and the second trigger data according to the global reset data packet;

[0297] If the reset instruction packet is a second instruction packet, based on the second instruction packet, send an abnormal reset data packet to the routing board, so that the routing board deletes the second trigger data according to the abnormal reset data packet;

[0298] If the reset instruction packet is a third instruction packet, based on the third instruction packet, send a thread reset data packet including the identification information to the routing board, so that the routing board deletes the second trigger data in the second thread sub-module matching the identification information according to the thread reset data packet;

[0299] Wherein, the first instruction packet is used to indicate a global reset operation, the second instruction packet is used to indicate an abnormal reset operation, and the third instruction packet is used to indicate a thread reset operation.

[0300] Optionally, the above central control board may further include a second parsing module for assisting the thread module;

[0301] If the reset data packet is a first instruction packet / second instruction packet, the above first parsing module may further include:

[0302] A third sending unit, configured to send a second reset signal to a second parsing module based on the first instruction packet / the second instruction packet, so that the second parsing module performs a reset operation according to the second reset signal.

[0303] Optionally, the second parsing module may include a shift register and an acquisition counter;

[0304] The third sending unit may specifically be configured to send a global reset signal / an exception reset signal to the second parsing module based on the first instruction packet / the second instruction packet, so that the second parsing module resets the shift register and the acquisition counter according to the global reset signal / the exception reset signal.

[0305] Based on the same inventive concept, according to the reset operation method provided in the embodiment of the present application, the embodiment of the present application further provides a thread module. As Figure 13 shown, Figure 13 is a schematic structural diagram of a thread module provided in an embodiment of the present application. The thread module is deployed in a central control board. The central control board, a host computer, and a routing board form a quantum computing measurement and control system. The thread module is used to trigger the routing board to start parallel execution of multiple quantum computing tasks. The central control board further includes a first parsing module. In Figure 13 the thread module shown includes:

[0306] A second receiving unit 1301, configured to receive a first reset signal sent by the first parsing module based on a reset instruction packet, and the reset instruction packet is sent by the host computer to the first parsing module;

[0307] A first reset unit 1302, configured to perform a reset operation according to the first reset signal.

[0308] Optionally, the thread module may include multiple first thread sub-modules. First synchronization data is stored in the thread module, and first trigger data is stored in each first thread sub-module;

[0309] The first reset unit 1302 may specifically be configured to, if the first reset signal is a global reset signal, delete the first synchronization data and the first trigger data according to the global reset signal;

[0310] if the first reset signal is an exception reset signal, delete the first trigger data according to the exception reset signal;

[0311] if the first reset signal is a thread reset signal carrying identification information, delete the first trigger data in the first thread sub-module matching the identification information according to the thread reset signal.

[0312] Based on the same inventive concept, according to the reset operation method provided in the embodiment of the present application, the embodiment of the present application further provides a routing board. As Figure 14As shown Figure 14 This is the first structural schematic diagram of the routing board provided by the embodiment of the present application. This routing board can be used to start the parallel execution of multiple quantum computing tasks. The routing board, the host computer, and the central control board form a quantum computing measurement and control system, and the central control board includes a first parsing module. Figure 14 The routing board shown in the figure includes:

[0313] A third receiving unit 1401, configured to receive a reset data packet sent by the first parsing module based on a reset instruction packet, and the reset instruction packet is sent by the host computer to the first parsing module;

[0314] A second reset unit 1402, configured to perform a reset operation according to the reset data packet.

[0315] Optionally, the above routing board may include multiple second thread sub-modules. Second synchronization data is stored in the routing board, and second trigger data corresponding to the quantum computing task is stored in each second thread sub-module;

[0316] The above third reset unit is specifically configured to, if the reset data packet is a global reset data packet, delete the second synchronization data and the second trigger data according to the global reset data packet;

[0317] If the reset data packet is an abnormal reset data packet, delete the second trigger data according to the abnormal reset data packet;

[0318] If the reset data packet is a thread reset data carrying identification information, delete the second trigger data in the second thread sub-module matching the identification information according to the thread reset data packet.

[0319] By Figures 12 - 14 The first parsing module, the thread module, and the routing board shown in the figure, after the host computer sends a reset instruction packet to the central control board, the first parsing module in the central control board sends a first reset signal to the thread module in the central control board and sends a reset data packet to the routing board communicatively connected to the central control board by parsing the received reset instruction packet. The thread module can perform a reset operation according to the received first reset signal, and the routing board can also perform a reset operation according to the received reset data packet, realizing the reset of the thread module and the routing board. This realizes the reset operation of the quantum computing measurement and control system and provides guarantee for the normal execution of the quantum computing task.

[0320] Based on the same inventive concept, according to the operation method provided by the embodiment of the present application, the embodiment of the present application also provides a central control board, as Figure 15As shown in the figure, it includes a processor 1501, a communication interface 1502, a memory 1503, and a communication bus 1504. Among them, the processor 1501, the communication interface 1502, and the memory 1503 complete their mutual communication through the communication bus 1504.

[0321] The memory 1503 is used to store computer programs.

[0322] When the processor 1501 is used to execute the program stored in the memory 1503, it implements the method steps of any of the above reset operations.

[0323] Based on the same inventive concept, according to the operation method provided in the embodiments of the present application, the embodiments of the present application also provide a routing board card, as Figure 16 shown in the figure, it includes a processor 1601, a communication interface 1602, a memory 1603, and a communication bus 1604. Among them, the processor 1601, the communication interface 1602, and the memory 1603 complete their mutual communication through the communication bus 1604.

[0324] The memory 1603 is used to store computer programs.

[0325] When the processor 1601 is used to execute the program stored in the memory 1603, it implements the method steps of any of the above reset operations.

[0326] The communication bus mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, only a thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0327] The communication interface is used for the communication between the above electronic device and other devices.

[0328] The memory can include a Random Access Memory (RAM), and can also include a Non-Volatile Memory (NVM), such as at least one disk memory. Optionally, the memory can also be at least one storage device located far from the aforementioned processor.

[0329] The above-mentioned processor may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0330] Based on the same inventive concept, according to the operation method provided in the above embodiments of the present application, the embodiments of the present application further provide a quantum computer, and the quantum computer includes the above-mentioned quantum computing measurement and control system, and the method steps of any of the above reset operations are implemented when the quantum computer measurement and control system is executed.

[0331] Based on the same inventive concept, according to the operation method provided in the above embodiments of the present application, the embodiments of the present application further provide a computer-readable storage medium, and a computer program is stored in the computer-readable storage medium, and the steps of any of the above reset operation methods are implemented when the computer program is executed by a processor.

[0332] Based on the same inventive concept, according to the operation method provided in the above embodiments of the present application, the embodiments of the present application further provide a computer program product containing instructions, and when it runs on a computer, the computer is caused to execute any of the reset operation methods in the above embodiments.

[0333] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center to another website, computer, server, or data center via wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that includes one or more integrated available media. The available medium may be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)).

[0334] It should be noted that, in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0335] Each embodiment in this specification is described in a related manner. The same or similar parts among the embodiments can be referred to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for embodiments such as quantum computing measurement and control systems, first parsing modules, thread modules, routing boards, central control boards, quantum computers, computer-readable storage media, and computer program products, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0336] The above are only the preferred embodiments of the present application and are not intended to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application are all included in the protection scope of the present application.

Claims

1. A reset operation method, characterized in that, Applied to a quantum computing measurement and control system, the quantum computing measurement and control system includes a host computer, a central control board card, and a routing board card. The central control board card includes a first parsing module and a thread module. The thread module is used to trigger the routing board card to start parallel execution of multiple quantum computing tasks. The method includes: The host computer sends a reset instruction packet to the first parsing module; Based on the received reset instruction packet, the first parsing module sends a first reset signal to the thread module and a reset data packet to the routing board card; The thread module performs a reset operation according to the received first reset signal; The routing board card performs a reset operation according to the received reset data packet.

2. The method according to claim 1, characterized in that, Before the host computer sends a reset instruction packet to the first parsing module, the method further includes: When the host computer receives a start instruction for the quantum computing measurement and control system, it generates a first instruction packet, and the first instruction packet is used to indicate a global reset operation; The step of the host computer sending a reset instruction packet to the first parsing module includes: The host computer sends the first instruction packet to the first parsing module.

3. The method according to claim 2, wherein The thread module includes multiple first thread sub-modules, the routing board card includes multiple second thread sub-modules, the thread module stores first synchronization data, each first thread sub-module stores first trigger data, the routing board card stores second synchronization data, and each second thread sub-module stores second trigger data; The step of the first parsing module sending a first reset signal to the thread module and a reset data packet to the routing board card based on the received reset instruction packet includes: Based on the received first instruction packet, the first parsing module sends a global reset signal to the thread module and a global reset data packet to the routing board card; The step of the thread module performing a reset operation according to the received first reset signal includes: The thread module deletes the first synchronization data and the first trigger data according to the received global reset signal; The step of the routing board card performing a reset operation according to the received reset data packet includes: The routing board card deletes the second synchronization data and the second trigger data according to the received global reset data packet.

4. The method according to claim 1, wherein After the first parsing module receives the reset instruction packet, the method further includes: The first parsing module returns a first response packet for the reset instruction packet to the host computer; The host computer receives the first response packet; The method further includes: If the host computer does not receive the first response packet within a first preset time period, the host computer generates a second instruction packet and uses the second instruction packet as a reset instruction packet, and returns to execute the step of sending the reset instruction packet to the first parsing module. The second instruction packet is used to indicate an abnormal reset operation.

5. The method according to claim 4, wherein The thread module includes a plurality of first thread sub-modules, the routing board card includes a plurality of second thread sub-modules, the thread module stores first synchronization data, each first thread sub-module stores first trigger data, the routing board card stores second synchronization data, and each second thread sub-module stores second trigger data; The step that the first parsing module sends a first reset signal to the thread module and sends a reset data packet to the routing board card based on the received reset instruction packet includes: The first parsing module sends an abnormal reset signal to the thread module and sends an abnormal reset data packet to the routing board card based on the received second instruction packet; The step that the thread module performs a reset operation according to the received first reset signal includes: The thread module deletes the first trigger data according to the received abnormal reset signal; The step that the routing board card performs a reset operation according to the received reset data packet includes: The routing board card deletes the second trigger data according to the received abnormal reset data packet.

6. The method according to claim 2 or 4, characterized in that, The central control board card further includes a second parsing module, and the second parsing module is used to assist the thread module; The method further includes: The first parsing module sends a second reset signal to the second parsing module based on the received reset instruction packet; The second parsing module performs a reset operation according to the received second reset signal.

7. The method according to claim 6, characterized in that The second parsing module includes a shift register and an acquisition counter; The step that the first parsing module sends a second reset signal to the second parsing module based on the received reset instruction packet includes: If the reset instruction packet is a first instruction packet, the first parsing module sends a global reset signal to the second parsing module based on the received first instruction packet; If the reset instruction packet is a second instruction packet, the first parsing module sends an abnormal reset signal to the second parsing module based on the received second instruction packet; The step that the second parsing module performs a reset operation according to the received second reset signal includes: The second parsing module resets the shift register and the acquisition counter according to the received global reset signal / abnormal reset signal.

8. The method according to claim 1, characterized in that, The routing board card includes a plurality of second thread sub-modules; Before the host computer sends a reset instruction packet to the first parsing module, the method further includes: The host computer receives a second return packet, and the second return packet is sent by the routing board card when the target quantum computing task is completed; The step that the host computer sends a reset instruction packet to the first parsing module includes: If the host computer does not receive the second return packet within a second preset time period, the host computer sends a third instruction packet carrying identification information to the first parsing module, the third instruction packet instructs to perform a thread reset operation, and the identification information matches the second thread sub-module that triggers the execution of the target quantum computing task.

9. The method according to claim 8, wherein The thread module includes a plurality of first thread sub-modules. The thread module stores first synchronization data, and each first thread sub-module stores first trigger data. The routing board card stores second synchronization data, and each second thread sub-module stores second trigger data; The step that the first parsing module sends a first reset signal to the thread module and sends a reset data packet to the routing board card based on the received reset instruction packet includes: The first parsing module sends a thread reset signal including the identification information to the thread module and sends a thread reset data packet including the identification information to the routing board card based on the received third instruction packet; The step that the thread module performs a reset operation according to the received first reset signal includes: The thread module deletes the first trigger data in the first thread sub-module that matches the identification information according to the received thread reset signal; The step that the routing board card performs a reset operation according to the received reset data packet includes: The routing board card deletes the second trigger data in the second thread sub-module that matches the identification information according to the received thread reset data packet.

10. A reset operation method, characterized in that, Applied to the first parsing module in the central control board card, the central control board card, the upper computer and the routing board card constitute a quantum computing measurement and control system. The central control board card further includes a thread module for triggering the routing board card to start multiple quantum computing tasks to execute in parallel. The method includes: Receiving a reset instruction packet sent by the upper computer; Based on the reset instruction packet, sending a first reset signal to the thread module so that the thread module performs a reset operation according to the first reset signal; Based on the reset instruction packet, sending a reset data packet to the routing board card so that the routing board card performs a reset operation according to the reset data packet.

11. The method according to claim 10, wherein The thread module includes a plurality of first thread sub-modules. The routing board card includes a plurality of second thread sub-modules. The thread module stores first synchronization data, and each first thread sub-module stores first trigger data. The routing board card stores second synchronization data, and each second thread sub-module stores second trigger data; The step of, based on the reset instruction packet, sending a first reset signal to the thread module so that the thread module performs a reset operation according to the first reset signal includes: If the reset instruction packet is a first instruction packet, then based on the first instruction packet, sending a global reset signal to the thread module so that the thread module deletes the first synchronization data and the first trigger data according to the global reset signal; If the reset instruction packet is a second instruction packet, then based on the second instruction packet, sending an abnormal reset signal to the thread module so that the thread module deletes the first trigger data according to the abnormal reset signal; If the reset instruction packet is a third instruction packet carrying identification information, based on the third instruction packet, send a thread reset signal including the identification information to the thread module, so that the thread module deletes the first trigger data in the first thread sub-module matching the identification information based on the thread reset signal; The step of sending a reset data packet to the routing board card based on the reset instruction packet to enable the routing board card to perform a reset operation according to the reset data packet includes: If the reset instruction packet is the first instruction packet, based on the first instruction packet, send a global reset data packet to the routing board card, so that the routing board card deletes the second synchronization data and the second trigger data according to the global reset data packet; If the reset instruction packet is the second instruction packet, based on the second instruction packet, send an abnormal reset data packet to the routing board card, so that the routing board card deletes the second trigger data according to the abnormal reset data packet; If the reset instruction packet is the third instruction packet, based on the third instruction packet, send a thread reset data packet including the identification information to the routing board card, so that the routing board card deletes the second trigger data in the second thread sub-module matching the identification information according to the thread reset data packet; Wherein, the first instruction packet is used to indicate a global reset operation, the second instruction packet is used to indicate an abnormal reset operation, and the third instruction packet is used to indicate a thread reset operation.

12. The method according to claim 11, wherein The central control board card further includes a second parsing module for assisting the thread module; If the reset data packet is the first instruction packet / the second instruction packet, the method further includes: Based on the first instruction packet / the second instruction packet, send a second reset signal to the second parsing module, so that the second parsing module performs a reset operation according to the second reset signal.

13. The method according to claim 12, wherein The second parsing module includes a shift register and an acquisition counter; The step of sending a second reset signal to the second parsing module based on the first instruction packet / the second instruction packet to enable the second parsing module to perform a reset operation according to the second reset signal includes: Based on the first instruction packet / the second instruction packet, send a global reset signal / an abnormal reset signal to the second parsing module, so that the second parsing module resets the shift register and the acquisition counter according to the global reset signal / the abnormal reset signal.

14. A reset operation method, characterized in that, Applied to the thread module in the central control board card, the central control board card, the upper computer and the routing board card form a quantum computing measurement and control system. The thread module is used to trigger the routing board card to start parallel execution of multiple quantum computing tasks. The central control board card further includes a first parsing module. The method includes: Receive a first reset signal sent by the first parsing module based on a reset instruction packet, where the reset instruction packet is sent by the upper computer to the first parsing module; Perform a reset operation according to the first reset signal.

15. The method according to claim 14, wherein The thread module includes a plurality of first thread sub-modules. The thread module stores first synchronization data, and each first thread sub-module stores first trigger data; The step of performing a reset operation according to the first reset signal includes: If the first reset signal is a global reset signal, delete the first synchronization data and the first trigger data according to the global reset signal; If the first reset signal is an abnormal reset signal, delete the first trigger data according to the abnormal reset signal; If the first reset signal is a thread reset signal carrying identification information, delete the first trigger data in the first thread sub-module that matches the identification information according to the thread reset signal.

16. A reset operation method, characterized in that, Applied to a routing board in a quantum computing measurement and control system, the routing board is used to start the parallel execution of multiple quantum computing tasks. The quantum computing measurement and control system further includes a host computer and a central control board. The central control board includes a first parsing module. The method includes: Receive a reset data packet sent by the first parsing module based on a reset instruction packet, where the reset instruction packet is sent by the host computer to the first parsing module; Perform a reset operation according to the reset data packet.

17. The method according to claim 16, wherein The routing board includes a plurality of second thread sub-modules. The routing board stores second synchronization data, and each second thread sub-module stores second trigger data; The step of performing a reset operation according to the reset data packet includes: If the reset data packet is a global reset data packet, delete the second synchronization data and the second trigger data according to the global reset data packet; If the reset data packet is an abnormal reset data packet, delete the second trigger data according to the abnormal reset data packet; If the reset data packet is a thread reset data carrying identification information, delete the second trigger data in the second thread sub-module that matches the identification information according to the thread reset data packet.

18. A quantum computing measurement and control system, characterized in that, The quantum computing measurement and control system includes a host computer, a central control board, and a routing board. The central control board includes a first parsing module and a thread module. The thread module is used to trigger the routing board to start the parallel execution of multiple quantum computing tasks; The host computer is used to send a reset instruction packet to the first parsing module; The first parsing module is used to send a first reset signal to the thread module and a reset data packet to the routing board based on the received reset instruction packet; The thread module is used to perform a reset operation according to the received first reset signal; The routing board is used to perform a reset operation according to the received reset data packet.

19. A first parsing module, characterized in that, The first parsing module is deployed in the central control board. The central control board, the host computer, and the routing board form a quantum computing measurement and control system. The central control board further includes a thread module for triggering the routing board to start the parallel execution of multiple quantum computing tasks; The first parsing module includes: A first receiving unit for receiving the reset instruction packet sent by the host computer; A first sending unit, configured to send a first reset signal to the thread module based on the reset instruction packet, so that the thread module performs a reset operation according to the first reset signal; A second sending unit, configured to send a reset data packet to the routing board card based on the reset instruction packet, so that the routing board card performs a reset operation according to the reset data packet.

20. A thread module, characterized in that, The thread module is deployed in the central control board card. The central control board card, the upper computer and the routing board card form a quantum computing measurement and control system. The thread module is used to trigger the routing board card to start parallel execution of multiple quantum computing tasks. The central control board card further includes a first parsing module; The thread module includes: A second receiving unit, configured to receive the first reset signal sent by the first parsing module based on the reset instruction packet, and the reset instruction packet is sent by the upper computer to the first parsing module; A first reset unit, configured to perform a reset operation according to the first reset signal.

21. A routing board, characterized in that, The routing board card is used to start parallel execution of multiple quantum computing tasks. The routing board card, the upper computer and the central control board card form a quantum computing measurement and control system. The central control board card includes a first parsing module; The routing board card includes: A third receiving unit, configured to receive the reset data packet sent by the first parsing module based on the reset instruction packet, and the reset instruction packet is sent by the upper computer to the first parsing module; A second reset unit, configured to perform a reset operation according to the reset data packet.

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