Processor, processing method and system for automatically selecting RISC-V or X86 instruction set in initialization phase

Abstract

The invention discloses a processor, a processing method and a system for automatically selecting an RISC-V or X86 instruction set in an initialization phase, the processor comprises an instruction stream detection module and a decoding configuration module, the decoding configuration module comprises a multiplexer, an RISC-V decoding circuit and an X86 decoding circuit, the instruction stream detection module is configured to take out an instruction stream, detect and analyze the instruction stream and then output a corresponding ISA control signal; the multiplexer is configured to receive the ISA control signal and switch on the corresponding decoding circuit according to the ISA control signal; the ISA control signal comprises a first signal and a second signal, and when the instruction stream detection module outputs the first signal, the multiplexer switches on the X86 decoding circuit; and when the instruction stream detection module outputs a second signal, the multiplexer switches on the RISC-V decoding circuit. The processor can automatically detect the characteristics of the instruction stream and configure the corresponding decoding circuit, and the CPU initialization process is simplified.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and particularly to a processor, a processing method, and a system for automatically selecting the RISC-V or X86 instruction set during the initialization phase. Background Art

[0002] The Instruction Set Architecture (ISA) is the core abstract model of a computer architecture and determines how a processor is controlled by software. Common ISAs include X86 (widely used in personal computers and servers) and RISC-V (popular in embedded systems and emerging fields due to its open-source nature and low power consumption characteristics). The ISA allows different implementations of the same architecture to vary in performance, size, and cost while maintaining binary compatibility. However, traditional CPUs are designed to be fixed to a single ISA (such as X86 or RISC-V) and cannot adapt to different software environments during initialization, resulting in wasted hardware resources or the need for multiple dedicated CPUs. The design of a single-ISA CPU limits its application in multi-ISA environments, especially in scenarios that require compatibility with different software ecosystems. In modern computing, the demand for supporting multiple ISAs is increasing. For example, in cloud computing, virtual machines may need to run applications for both X86 and RISC-V; in Internet of Things devices, it may be necessary to switch ISAs according to task requirements to optimize power consumption and performance. Therefore, developing a CPU that can flexibly support multiple ISAs has become an important technical challenge.

[0003] To address the above problems, in the prior art, a common approach is to achieve compatibility by software emulation to simulate the execution environment of another ISA on a CPU of one ISA. For example, QEMU can run RISC-V programs on an X86 processor. Although it can achieve compatibility between different ISAs, there are significant technical deficiencies. Its main problems include high performance overhead, low resource efficiency, and poor real-time performance; the instruction translation or interpretation process leads to low execution efficiency and is difficult to meet the requirements of high-performance computing; at the same time, the emulation environment occupies additional resources and reduces system efficiency; for applications with high real-time requirements, the latency and uncertainty of emulation further limit its applicability. On the other hand, existing processors that support multiple ISAs usually require complex hardware design or software intervention during initialization to determine which ISA to use. This method not only increases the development difficulty but may also introduce additional runtime overhead.

[0004] The disclosure of the above background art content is only for assisting in understanding the inventive concept and technical solution of the present invention. It does not necessarily belong to the prior art of the present application and does not necessarily provide technical teachings. Without clear evidence indicating that the above content was publicly available before the filing date of the present application, the above background art should not be used to evaluate the novelty and inventiveness of the present application. Summary of the Invention

[0005] An object of the present invention is to provide a processor, a processing method, and a system for automatically selecting the RISC-V or X86 instruction set during the initialization phase, which can automatically detect the instruction stream characteristics and configure the corresponding decoding circuit, and can simplify the CPU initialization process.

[0006] To achieve the above object, the technical solution adopted by the present invention is as follows: A processor for automatically selecting the RISC-V or X86 instruction set during the initialization phase includes an instruction stream detection module and a decoding configuration module. The decoding configuration module includes a multiplexer, a RISC-V decoding circuit, and an X86 decoding circuit. The multiplexer is selectively electrically connected to the RISC-V decoding circuit or the X86 decoding circuit. The instruction stream detection module is configured to extract the instruction stream, detect and analyze it, and then output a corresponding ISA control signal. The instruction stream includes a RISC-V instruction sequence and / or an X86 instruction sequence. The multiplexer is configured to receive the ISA control signal output by the instruction stream detection module and select and connect to the corresponding decoding circuit according to the ISA control signal. The ISA control signal includes a first signal and a second signal. When the instruction stream detection module outputs the first signal, the multiplexer selects and connects to the X86 decoding circuit. When the instruction stream detection module outputs the second signal, the multiplexer selects and connects to the RISC-V decoding circuit.

[0007] Through the collaborative work of the instruction stream detection module and the decoding configuration module, the present invention realizes an efficient mechanism for the CPU to automatically select the X86 decoding circuit or the RISC-V decoding circuit according to the instruction stream characteristics during the initialization phase. The decoding configuration module generates an ISA control signal according to the detection result of the instruction stream detection module, and then activates the X86 decoding circuit or the RISC-V decoding circuit inside the CPU. This dynamic configuration method can ensure that instructions are executed in the native manner without translation or emulation, thus significantly improving the initialization efficiency. This design enables a single CPU chip to automatically adapt to the corresponding instruction set according to the real instruction content during initialization, greatly improving the flexibility of the system and reducing the waste of hardware resources. In addition, the decoding configuration module realizes fast switching through a hardware multiplexer, which is beneficial to optimizing the system performance.

[0008] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the instruction stream detection module includes an instruction register and a fetch unit. The instruction register is electrically connected to the fetch unit. The instruction stream is stored in the instruction register, and the fetch unit is configured to fetch the lower 8 bits of the instruction stream.

[0009] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the instruction stream detection module further includes a first comparator and a second comparator. Both the first comparator and the second comparator are connected to the fetch unit.

[0010] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the first comparator is configured to compare the lower 8 bits of the instruction stream fetched by the fetch unit with a preset first fixed-bit pattern and output a comparison result. The second comparator is configured to compare the lower 7 bits of the instruction stream fetched by the fetch unit with a preset second fixed-bit pattern and output a comparison result. In some embodiments of the present invention, the first fixed-bit pattern is the binary number 11101010, and the second fixed-bit pattern is the binary number 1101111.

[0011] When the CPU starts up, the instruction stream detection module reads the initial instruction stream from the reset vector in the memory of the instruction register and quickly analyzes its features using hardware logic (the first comparator and the second comparator). The features include instruction length and opcode pattern. By analyzing these features, the RISC-V instruction set and the X86 instruction set can be efficiently distinguished.

[0012] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the multiplexer includes a control port and an output port. The control port is selectively electrically connected to the first comparator or the second comparator and is configured to receive an ISA control signal. The output port is selectively electrically connected to the RISC-V decoding circuit or the X86 decoding circuit and is configured to connect the corresponding decoding circuit according to the ISA control signal.

[0013] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, when the comparison result of the first comparator is consistent, the first comparator outputs the first signal to the multiplexer. When the comparison result of the first comparator is inconsistent, the second comparator responds to the comparison result and compares the lower 7 bits of the instruction stream fetched by the fetch unit with the preset second fixed-bit pattern.

[0014] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, when the comparison result of the second comparator is consistent, the second comparator outputs the second signal to the multiplexer. Otherwise, the second comparator outputs an abnormal signal.

[0015] Specifically, when the first comparator outputs a first signal after analysis and comparison, the control port of the multiplexer is electrically connected to the first comparator at this time. Meanwhile, the output port of the multiplexer is connected to the X86 decoding circuit, so that the current instruction stream can be accurately sent to the X86 decoding circuit for subsequent processing. When the first comparator outputs a signal indicating inconsistent comparison results after analysis and comparison, the second comparator will further compare the lower 7 bits of the instruction stream. When the second comparator outputs a second signal after analysis and comparison, the control port of the multiplexer is electrically connected to the second comparator at this time. Meanwhile, the output port of the multiplexer is connected to the RISC-V decoding circuit, so that the current instruction stream can be accurately sent to the RISC-V decoding circuit for subsequent processing.

[0016] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, it further includes an exception handling module. The second comparator is also connected to the exception handling module, and the exception handling module is configured to receive the exception signal and perform exception handling on the instruction stream.

[0017] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the first fixed-bit pattern is stored in the first comparator, and the second fixed-bit pattern is stored in the second comparator.

[0018] According to another aspect of the present invention, there is provided a processing method for automatically selecting the RISC-V or X86 instruction set during the initialization phase based on the above processor, including the following steps: During the CPU initialization phase, the instruction stream detection module fetches the instruction stream, detects and analyzes it, and then outputs a corresponding ISA control signal to the multiplexer; After receiving the ISA control signal, the multiplexer selects and connects to the RISC-V decoding circuit or the X86 decoding circuit, so that the instruction stream is sent to the corresponding decoding circuit.

[0019] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the method by which the instruction stream detection module fetches the instruction stream, detects and analyzes it, and then outputs a corresponding ISA control signal to the multiplexer is as follows: The instruction stream detection module first compares the lower 8 bits of the fetched instruction stream with a preset first fixed-bit pattern. If the comparison results are consistent, it outputs a first signal; If the comparison results are inconsistent, it compares the lower 7 bits of the fetched instruction stream with a preset second fixed-bit pattern. If the comparison results are consistent, it outputs a second signal; otherwise, it outputs an exception signal.

[0020] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the method further includes the following steps: When the instruction stream detection module compares the lower 7 bits of the fetched instruction stream with a preset second fixed-bit pattern and the comparison result is inconsistent, the instruction stream detection module transmits the abnormal signal to the exception handling module, so that the instruction stream enters the exception handling process. When the first comparator and the second comparator both fail to meet the feature conditions after comparison, the instruction stream detection module determines that the current instruction stream is abnormal, and then makes it enter the exception handling process.

[0021] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the exception handling process includes the following steps: After the exception handling module discovers an illegal instruction, it enters the exception handling mechanism; Save the register information; Jump to the exception handling program entry and execute the exception handling program; If the exception handling fails or there is no response for a long time, the system restarts for reset.

[0022] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the initialization phase is the phase after the CPU is powered on or reset.

[0023] According to another aspect of the present invention, the present invention provides a computer system, including a processor for automatically selecting the RISC-V or X86 instruction set during the initialization phase as described in any one of the foregoing technical solutions or a combination of multiple technical solutions. The computer system is based on the above processor and executes the above processing method.

[0024] The beneficial effects brought by the technical solutions provided by the present invention are as follows: a. The present invention directly analyzes the instruction stream characteristics and configures the corresponding decoding circuit during the CPU initialization through the instruction stream detection module, avoiding the simulation process, enabling the instructions in the initialization phase to execute instructions in a native manner, which is beneficial to improving the performance of the system and ensuring a fast and efficient initialization process, and is particularly suitable for scenarios such as cloud computing and embedded systems; b. The present invention supports the X86 and RISC-V instruction set architectures with a single CPU, without the need to equip independent hardware for each instruction set architecture, which is beneficial to reducing the power consumption and manufacturing cost of the chip and optimizing the resource utilization rate; c. Through the hardware modular design, the present invention can automatically complete the selection and decoding configuration of the instruction set architecture, simplifies the system architecture, without the need for a complex initialization mechanism or software intervention, which is beneficial to reducing the design complexity, improving the maintainability and scalability of the system, and shortening the development cycle. Description of the Drawings

[0025] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments recorded in the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0026] Figure 1 Schematic diagram of a processor for automatically selecting the RISC-V or X86 instruction set in the initialization stage provided for an exemplary embodiment of the present invention; Figure 2 Flowchart of the operation of a processor for automatically selecting the RISC-V or X86 instruction set in the initialization stage provided for an exemplary embodiment of the present invention. Detailed implementation manners

[0027] In order to enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0028] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above accompanying drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order different from those illustrated or described here. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, device, product or equipment including a series of steps or units does not necessarily have to be limited to those clearly listed steps or units, but may include other steps or units not clearly listed or inherent to these processes, methods, products or equipment.

[0029] See Figure 1, in an embodiment of the present invention, a processor for automatically selecting the RISC-V or X86 instruction set during the initialization phase is provided, including an instruction stream detection module, a decoding configuration module, and an exception handling module. The decoding configuration module and the exception handling module are both connected to the instruction stream detection module, and the instruction stream therein includes RISC-V instruction sequences and / or X86 instruction sequences; the instruction stream detection module is configured to fetch the instruction stream, detect and analyze it, and then output corresponding ISA control signals. The decoding configuration module is configured to receive the ISA control signals and accordingly turn on the corresponding decoding circuit; in addition, the instruction stream detection module is further configured to fetch the instruction stream, detect and analyze it, and then output an exception signal (when the instruction stream does not meet the characteristic conditions of the RISC-V instruction set or the X86 instruction set), and the exception handling module is configured to receive the exception signal and perform exception handling on the instruction stream.

[0030] Among them, the ISA control signals include a first signal and a second signal. When the instruction stream detection module outputs the first signal, it indicates that the characteristics of the fetched instruction stream conform to the characteristics of the X86 instruction set; when the instruction stream detection module outputs the second signal, it indicates that the characteristics of the fetched instruction stream conform to the characteristics of the RISC-V instruction set.

[0031] Further, the instruction stream detection module includes an instruction register, a fetch unit, a first comparator, and a second comparator. The instruction register is electrically connected to the fetch unit, and the instruction stream is stored in the instruction register. The fetch unit is configured to fetch the lower 8 bits of the instruction stream; both the first comparator and the second comparator are connected to the fetch unit. Moreover, a first fixed-bit pattern is preset in the first comparator, and a second fixed-bit pattern is preset in the second comparator. The first fixed-bit pattern in this embodiment is the binary number 11101010, and the second fixed-bit pattern is the binary number 1101111.

[0032] The first comparator is configured to compare the lower 8 bits of the instruction stream fetched by the fetch unit with the preset first fixed-bit pattern 11101010 and output a comparison result. The second comparator is configured to compare the lower 7 bits of the instruction stream fetched by the fetch unit with the preset second fixed-bit pattern 1101111 and output a comparison result. Among them, the characteristics compared by the first comparator and the second comparator include the instruction length and the opcode pattern.

[0033] Further, the decoding configuration module includes a multiplexer, a RISC-V decoding circuit, and an X86 decoding circuit. The multiplexer is selectively electrically connected to the RISC-V decoding circuit or the X86 decoding circuit, and is configured to receive the ISA control signal output by the instruction stream detection module and select and connect to the corresponding decoding circuit according to the ISA control signal. Among them, the multiplexer is used to select one of multiple input signal sources as the output according to the control signal. It includes a control port and an output port. The control port is selectively electrically connected to the first comparator or the second comparator and is configured to receive the ISA control signal; the output port is selectively electrically connected to the RISC-V decoding circuit or the X86 decoding circuit and is configured to connect to the corresponding decoding circuit according to the ISA control signal. The setting of the hardware multiplexer can ensure the rapid switching between the RISC-V decoding circuit and the X86 decoding circuit according to the characteristics of the instruction stream, which is beneficial to optimizing the system performance.

[0034] When the lower 8 bits of the instruction stream compared by the first comparator are consistent with the preset first fixed-bit pattern, the first comparator outputs a first signal. At this time, the control port of the multiplexer is electrically connected to the first comparator. The multiplexer receives the first signal from the first comparator and, in response to the first signal, causes the output port of the multiplexer to select and connect to the X86 decoding circuit, so that the current instruction stream can be accurately sent to the X86 decoding circuit for subsequent processing. When the lower 8 bits of the instruction stream compared by the first comparator are inconsistent with the preset first fixed-bit pattern, the first comparator transmits the signal of this comparison result to the second comparator. The second comparator responds to this comparison result and compares the lower 7 bits of the instruction stream fetched from the value fetching unit with the preset second fixed-bit pattern. When the lower 7 bits of the instruction stream compared by the second comparator are consistent with the preset second fixed-bit pattern, the control port of the multiplexer at this time will switch to be electrically connected to the second comparator. The multiplexer receives the second signal from the second comparator and, in response to the second signal, causes the output port of the multiplexer to select and connect to the RISC-V decoding circuit, so that the current instruction stream can be accurately sent to the RISC-V decoding circuit for subsequent processing. When the lower 7 bits of the instruction stream compared by the second comparator are inconsistent with the preset second fixed-bit pattern, it is determined that the current instruction stream is abnormal, and the second comparator outputs an abnormal signal.

[0035] Further, the second comparator is also connected to an exception handling module. After receiving the abnormal signal output by the second comparator, the exception handling module performs exception handling on the instruction stream, so that the current instruction stream enters the exception handling process.

[0036] As Figure 2 shown, the present invention also provides a processing method based on the above-mentioned processor, including the following steps: During the CPU initialization phase, the instruction stream is stored in the instruction register. The lower 8 bits of the instruction stream stored in the instruction register are extracted by the fetch unit in the instruction stream detection module. Here, the initialization phase is the phase after the CPU is powered on or reset. First, the first comparator compares the lower 8 bits of the instruction stream fetched by the fetch unit with the preset first fixed-bit pattern 11101010. When the comparison result is consistent, the first comparator outputs a first signal and is electrically connected to the control port of the multiplexer. After receiving the first signal, the multiplexer controls its output port to select and connect to the X86 decoding circuit to turn on the X86 decoding circuit, and the instruction stream accurately enters the X86 decoding circuit for subsequent processing.

[0037] Subsequently, if the lower 8 bits of the instruction stream compared by the first comparator are inconsistent with the preset first fixed-bit pattern 11101010, the second comparator will be triggered to compare the lower 7 bits of the fetched instruction stream with the preset second fixed-bit pattern 1101111. When the comparison result is consistent, the second comparator outputs a second signal to the multiplexer. The multiplexer will switch to connect the control port to the second comparator and control the output port to select and connect to the RISC-V decoding circuit to turn on the RISC-V decoding circuit, and the instruction stream accurately enters the RISC-V decoding circuit for subsequent processing.

[0038] If the lower 7 bits of the instruction stream compared by the second comparator are inconsistent with the preset second fixed-bit pattern 1101111, an exception signal is transmitted to the exception handling module. The exception handling module responds to the exception signal to cause the instruction stream to enter the exception handling process. The exception handling process includes: the exception handling module enters the exception handling mechanism after detecting an illegal instruction; saves the PC register information; jumps to the exception handling program entry and executes the exception handling program; if the exception handling fails or there is no response for a long time, the system restarts for reset.

[0039] A computer system including a processor for automatically selecting the RISC-V or X86 instruction set during the initialization phase as described above, based on the above processor and executing the above processing method to automatically identify the instruction stream characteristics and configure the corresponding decoding circuit during the CPU initialization phase, without relying on software emulation or manual intervention, can greatly improve the flexibility of the system, reduce the waste of hardware resources, and simplify the initialization process under multi-architecture support.

[0040] The processor of the present invention works in cooperation with an instruction stream detection module and a decoding configuration module, realizing an efficient mechanism for the CPU to automatically select an X86 decoding circuit or a RISC-V decoding circuit according to the characteristics of the instruction stream during the initialization phase. This dynamic configuration method can ensure that instructions are executed in a native manner without translation or emulation, thus significantly improving the initialization efficiency; enabling a single CPU chip to automatically adapt to the corresponding instruction set according to the real instruction content during initialization, greatly enhancing the flexibility of the system and reducing the waste of hardware resources.

[0041] Due to the advancement of this technical solution, the technology of the present invention is particularly suitable for being applied to general-purpose processors, server chips, edge computing devices, and high-performance embedded systems that support both RISC-V and X86 instruction sets, which can effectively improve the startup efficiency and reduce the complexity of development.

[0042] Generally speaking, compared with the prior art, this technical solution has significant advantages in terms of performance improvement, resource efficiency, cost reduction, and simplifying the design of heterogeneous CPUs.

[0043] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of another identical element in the process, method, article or device including the said element.

[0044] The above are only specific embodiments of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present application.

Claims

1. A processor for automatically selecting the RISC-V or X86 instruction set during the initialization phase, characterized in that, It includes an instruction stream detection module and a decoding configuration module. The decoding configuration module includes a multiplexer, a RISC-V decoding circuit, and an X86 decoding circuit. The multiplexer is selectively electrically connected to the RISC-V decoding circuit or the X86 decoding circuit. The instruction stream detection module is configured to fetch the instruction stream, detect and analyze it, and then output a corresponding ISA control signal. The instruction stream includes a RISC-V instruction sequence and / or an X86 instruction sequence; the multiplexer is configured to receive the ISA control signal output by the instruction stream detection module and select and connect to the corresponding decoding circuit according to the ISA control signal; The ISA control signal includes a first signal and a second signal. When the instruction stream detection module outputs the first signal, the multiplexer selects and connects to the X86 decoding circuit; when the instruction stream detection module outputs the second signal, the multiplexer selects and connects to the RISC-V decoding circuit.

2. The processor according to claim 1, wherein The instruction stream detection module includes an instruction register and a fetching unit. The instruction register is electrically connected to the fetching unit. The instruction stream is stored in the instruction register. The fetching unit is configured to fetch the lower 8 bits of the instruction stream.

3. The processor according to claim 2, wherein, The instruction stream detection module further includes a first comparator and a second comparator. Both the first comparator and the second comparator are connected to the fetching unit.

4. The processor according to claim 3, wherein The first comparator is configured to compare the lower 8 bits of the instruction stream fetched by the fetching unit with a preset first fixed-bit pattern and output a comparison result. The second comparator is configured to compare the lower 7 bits of the instruction stream fetched by the fetching unit with a preset second fixed-bit pattern and output a comparison result.

5. The processor according to claim 4, wherein The multiplexer includes a control port and an output port. The control port is selectively electrically connected to the first comparator or the second comparator. The control port is configured to receive the ISA control signal; the output port is selectively electrically connected to the RISC-V decoding circuit or the X86 decoding circuit. The output port is configured to connect to the corresponding decoding circuit according to the ISA control signal.

6. The processor according to claim 5, characterized in that When the comparison result of the first comparator is consistent, the first comparator outputs the first signal to the multiplexer; when the comparison result of the first comparator is inconsistent, the second comparator responds to this comparison result and compares the lower 7 bits of the instruction stream fetched by the fetching unit with the preset second fixed-bit pattern.

7. The processor according to claim 6, wherein When the comparison result of the second comparator is consistent, the second comparator outputs the second signal to the multiplexer; otherwise, the second comparator outputs an abnormal signal.

8. The processor according to claim 7, wherein It further includes an exception handling module. The second comparator is also connected to the exception handling module. The exception handling module is configured to receive the abnormal signal and perform exception handling on the instruction stream.

9. The processor according to claim 4, wherein The first fixed-bit pattern is stored in the first comparator, and the second fixed-bit pattern is stored in the second comparator.

10. A processing method based on the processor according to any one of claims 1-9, characterized in that, It includes the following steps: In the CPU initialization stage, the instruction stream detection module fetches the instruction stream, detects and analyzes it, and then outputs a corresponding ISA control signal to the multiplexer; After receiving the ISA control signal, the multiplexer selects and connects to the RISC-V decoding circuit or the X86 decoding circuit, so that the instruction stream is sent to the corresponding decoding circuit.

11. The processing method according to claim 10, characterized in that, The method for the instruction stream detection module to extract the instruction stream, detect and analyze it, and then output the corresponding ISA control signal to the multiplexer is as follows: The instruction stream detection module first compares the lower 8 bits of the fetched instruction stream with a preset first fixed-bit pattern. If the comparison result is consistent, it outputs a first signal; If the comparison result is inconsistent, it compares the lower 7 bits of the fetched instruction stream with a preset second fixed-bit pattern. If the comparison result is consistent, it outputs a second signal; Otherwise, it outputs an exception signal.

12. The processing method according to claim 11, wherein It further includes the following steps: When the instruction stream detection module compares the lower 7 bits of the fetched instruction stream with the preset second fixed-bit pattern and the comparison result is inconsistent, the instruction stream detection module transmits the exception signal to the exception handling module, so that the instruction stream enters the exception handling process.

13. The processing method according to claim 12, characterized in that, The exception handling process includes the following steps: After the exception handling module discovers an illegal instruction, it enters the exception handling mechanism; Save the register information; Jump to the exception handling program entry and execute the exception handling program; If the exception handling fails or there is no response for a long time, the system restarts for reset.

14. The processing method according to claim 10, characterized in that, The initialization stage is the stage after the CPU is powered on or reset.

15. A computer system, characterized in that, It includes a processor for automatically selecting the RISC-V or X86 instruction set during the initialization stage as described in any one of claims 1-9.

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