Data processing method of coprocessor, coprocessor, processing system and medium
By dividing the first register stack in the coprocessor and sharing bus resources, the problem of low register utilization in the coprocessor is solved, and more efficient register resource utilization is achieved.
Patent Information
- Application Number
- CN202510292722.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-12
- Publication Date
- 2025-06-27
AI Technical Summary
The utilization rate of registers in the coprocessor is not high, resulting in waste of resources and inefficiency.
By dividing the first register stack in the coprocessor, it is used to store data of source operands and other types, and sharing the register stack through two or more buses, register resources are flexibly allocated.
Improve the register utilization rate in the coprocessor, avoid resource waste, and enhance the efficiency of the processing system.
Smart Images
Figure CN120216038A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of data processing, and particularly to a data processing method for a coprocessor, a coprocessor, a processing system, and a medium. Background Art
[0002] A coprocessor is a processor developed and applied to assist a Central Processing Unit (CPU) in completing processing tasks that it cannot execute or that have low execution efficiency or effectiveness, and is used to relieve the specific processing tasks of the system microprocessor.
[0003] When a coprocessor is connected to multiple buses, registers are usually allocated for each bus, and the bus uses the allocated registers to store data.
[0004] However, this results in low utilization of the registers in the coprocessor. Summary of the Invention
[0005] The present disclosure provides a data processing method for a coprocessor, a coprocessor, a processing system, and a medium, so as to solve the problem of low utilization of the registers in the coprocessor and achieve the effect of improving the utilization of the registers in the coprocessor.
[0006] In a first aspect, the present disclosure provides a data processing method applied to a coprocessor. The coprocessor is connected to a main processor through two or more buses respectively; the coprocessor includes a first register bank for storing data of a first data type, and the first data type includes a source operand type; the first register bank corresponds to a first address range; the method includes:
[0007] Receiving a first write instruction through a first bus, where the first write instruction includes a first address and a first data; the two or more buses include the first bus;
[0008] If the first address belongs to the first address range, allocate a first register from the registers in the idle state in the first register bank; the state of the register includes an idle state, and the register in the idle state refers to a register that does not store data;
[0009] Store the first data in the first register.
[0010] In some embodiments, after allocating the first register from the registers in the idle state in the first register bank, the method further includes:
[0011] If the first write instruction is the first write instruction corresponding to the calculation task, start timing;
[0012] If the timing duration reaches the preset duration and the start calculation instruction corresponding to the first write instruction is not received through the first bus during the timing process, then change the states of all the second registers to the idle state; the second registers are the registers that store the data in the second write instruction, and the second write instruction includes: the first write instruction and the write instructions received after the first write instruction from the first bus.
[0013] In some embodiments, the state of the register further includes: the busy state; after storing the first data into the first register, it further includes:
[0014] If the states of all the registers in the first register bank are the busy state, then output the first handshake signal to all the buses respectively, and the first handshake signal is used to indicate that the current coprocessor cannot write data of the first data type.
[0015] In some embodiments, the outputting the first handshake signal to all the buses respectively includes:
[0016] If there are registers in the idle state in the first register bank, then output the second handshake signal to all the buses respectively, and the second handshake signal is used to indicate that the current coprocessor receives the written data.
[0017] In some embodiments, the method further includes:
[0018] If the start calculation instruction corresponding to the first write instruction is received through the first bus and the timing duration does not reach the preset duration, then perform the calculation task corresponding to the first write instruction based on the data stored in all the second registers to obtain the first calculation result.
[0019] In some embodiments, the first data type further includes the calculation result type; after performing the calculation task corresponding to the first write instruction based on the data stored in all the second registers to obtain the first calculation result, it further includes:
[0020] Allocate a third register for the first calculation result from the idle registers in the first register bank;
[0021] Store the first calculation result into the third register.
[0022] In some embodiments, after storing the first calculation result into the third register, it further includes:
[0023] If the current first bus indicates receiving data, then send the first calculation result through the first bus;
[0024] If the current indication of the first bus is not to receive data, output a first handshake signal to the first bus, where the first handshake signal is used to indicate that the current coprocessor cannot write data of the first data type.
[0025] In some embodiments, the coprocessor further includes a second register bank, where the second register bank is used to store data of a second data type, and the second data type includes a configuration type; the second register bank corresponds to a second address range; the second address range has no intersection with the first address range; the method further includes:
[0026] If the first address belongs to the second address range and there is no other write instruction that needs to write to the first address currently, store the first data in the register corresponding to the first address.
[0027] In some embodiments, the method further includes:
[0028] Receive a third write instruction through a second bus, where the third write instruction includes the first address and second data; the two or more buses include the second bus, and the second bus is different from the first bus;
[0029] If the first address belongs to the second address range and there is the third write instruction that needs to write to the first address currently, store the data included in the write instruction sent by the bus with a higher priority in the register corresponding to the first address, and reduce the priority of the bus with a higher priority, so that the priority of the bus with a higher priority is lower than the priority of the bus with a lower priority; the bus with a higher priority refers to the bus with a higher priority among the first bus and the second bus.
[0030] In some embodiments, the method further includes:
[0031] Receive a first read instruction through the first bus, where the first read instruction includes a second address;
[0032] Obtain third data stored in the register corresponding to the second address;
[0033] Send the third data through the first bus.
[0034] In a second aspect, the present disclosure provides a coprocessor, where the coprocessor is connected to a main processor through a first bus and a second bus respectively; the coprocessor includes:
[0035] A first register bank, which is used to store data of a first data type, and the first data type includes a source operand type; the first register bank corresponds to a first address range;
[0036] A receiving module, configured to receive a first write instruction via a first bus, where the first write instruction includes a first address and a first data;
[0037] A scheduling module, configured to, if the first address belongs to the first address range, allocate a first register from the registers in the first register bank in an idle state; the registers in the idle state refer to the registers that do not store data; store the first data in the first register; and change the state of the first register to a busy state.
[0038] In some embodiments, the scheduling module is further configured to:
[0039] If the first write instruction is the first write instruction of the calculation task corresponding to the first write instruction, start timing;
[0040] If the timing duration reaches a preset duration and the start calculation instruction corresponding to the first write instruction is not received via the first bus during the timing process, change the states of all the second registers to the idle state; the second registers are the registers that store the data in the second write instruction, and the second write instruction includes: the first write instruction and the write instructions received via the first bus after the first write instruction.
[0041] In some embodiments, the state of the register further includes: a busy state; the scheduling module is further configured to:
[0042] If the states of all the registers in the first register bank are in the busy state, output first handshake signals to all the buses respectively, where the first handshake signals are used to indicate that the current coprocessor cannot write data of the first data type.
[0043] In some embodiments, the scheduling module is specifically configured to:
[0044] If there are registers in the first register bank in an idle state, output second handshake signals to all the buses respectively, where the second handshake signals are used to indicate that the current coprocessor receives the written data.
[0045] In some embodiments, the scheduling module is further configured to:
[0046] If the start calculation instruction corresponding to the first write instruction is received via the first bus and the timing duration does not reach the preset duration, execute the calculation task corresponding to the first write instruction based on the data stored in all the second registers to obtain a first calculation result.
[0047] In some embodiments, the first data type further includes a calculation result type; the scheduling module is further configured to:
[0048] Allocate a third register for the first calculation result from the free registers of the first register bank;
[0049] Store the first calculation result in the third register.
[0050] In some embodiments, the scheduling module is further configured to:
[0051] If the first bus currently indicates receiving data, send the first calculation result through the first bus;
[0052] If the first bus currently indicates not receiving data, output a first handshake signal to the first bus, where the first handshake signal is used to indicate that the current coprocessor cannot write data of the first data type.
[0053] In some embodiments, the coprocessor further includes a second register bank, where the second register bank is used to store data of a second data type, and the second data type includes a configuration type; the second register bank corresponds to a second address range; the second address range has no intersection with the first address range;
[0054] The scheduling module is further configured to:
[0055] If the first address belongs to the second address range and there is no other write instruction that needs to write to the first address currently, store the first data in the register corresponding to the first address.
[0056] In some embodiments, the scheduling module is further configured to:
[0057] Receive a third write instruction through the second bus, where the third write instruction includes the first address and the second data; the two or more buses include the second bus, and the second bus is different from the first bus;
[0058] If the first address belongs to the second address range and there is the third write instruction that needs to write to the first address currently, store the data included in the write instruction sent by the bus with a higher priority in the register corresponding to the first address, and reduce the priority of the bus with a higher priority, so that the priority of the bus with a higher priority is lower than the priority of the bus with a lower priority; the bus with a higher priority refers to the bus with a higher priority among the first bus and the second bus.
[0059] In some embodiments, the receiving module is further configured to: receive a first read instruction through the first bus, where the first read instruction includes a second address;
[0060] The scheduling module is further configured to: obtain third data stored in a register corresponding to the second address; and send the third data through the first bus.
[0061] In a third aspect, the present disclosure provides a coprocessor, including a memory and a processor. The memory stores a computer program that can run on the processor, and when the processor executes the program, the steps of the method described in the first aspect above are implemented.
[0062] In a fourth aspect, the present disclosure provides a processing system, including a main processor and a coprocessor; the main processor is respectively connected to the coprocessor through two or more buses; the coprocessor is the coprocessor described in the third aspect above.
[0063] In a fifth aspect, the present disclosure provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method described in the first aspect above are implemented.
[0064] The data processing method, coprocessor, processing system, and medium provided by the embodiments of the present disclosure. When the coprocessor is connected to the main processor through two or more buses, the coprocessor divides a first register bank from its own register file for storing data of types such as source operands. Data of types such as source operands of the two or more buses connected to the coprocessor are all stored in the first register bank. After receiving a first write instruction carrying a first address and first data through any bus, it is determined whether the first address belongs to the first address range corresponding to the first register bank to determine the type of the first data to be stored. When the first address belongs to the first address range corresponding to the first register bank, that is, it is determined that the type of the first data is the first data type, the coprocessor allocates a register in an idle state for this data from the first register bank. By sharing the register bank among two or more buses and writing data of different buses into the shared register bank in a flexible allocation manner, the utilization rate of the registers is improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0065] Figure 1 is a schematic structural diagram of a processing system provided by an embodiment of the present disclosure;
[0066] Figure 2 is a schematic flowchart of a data processing method of a coprocessor provided by an embodiment of the present disclosure;
[0067] Figure 3 is a schematic diagram of register scheduling provided by an embodiment of the present disclosure;
[0068] Figure 4 is a schematic structural diagram of a coprocessor provided by an embodiment of the present disclosure;
[0069] Figure 5 This is a schematic structural diagram of another co - processor provided by an embodiment of the present disclosure. Detailed implementation manners
[0070] Here, exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.
[0071] In the present disclosure, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item)" or its similar expression refers to any combination of these items, including any combination of single item (s) or plural items (s). For example, at least one (item) of a alone, b alone, or c alone can represent: a alone, b alone, c alone, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0072] The orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "upper", "lower", "left", "right", "front", "rear", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present disclosure.
[0073] The terms "connected" and "coupled" should be understood in a broad sense. For example, the "connection" or "coupling" of a circuit structure can refer not only to a physical connection but also to an electrical connection or a signal connection. For example, it can be a direct connection, that is, a physical connection, or it can be indirectly connected through at least one intermediate element, as long as the circuit is connected. It can also be the connection inside two elements; a signal connection can refer not only to a signal connection through a circuit but also to a signal connection through a media medium, such as radio waves. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific situations.
[0074] The data processing method of the coprocessor provided by the present disclosure can be applied in a processing system, and the processing system will be introduced below through specific embodiments.
[0075] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a processing system provided by an embodiment of the present disclosure. The processing system provided in this embodiment may include: a main processor 101 and a coprocessor 102. Among them, the main processor 101 is connected to the coprocessor 102 through one or more buses. It should be noted that Figure 1 exemplarily shows that two buses are respectively connected to the coprocessor 102, and the two buses are bus 1 and bus 2 respectively. Figure 1 The number of buses in
[0076] is only an example and does not limit the present disclosure.
[0077] Step 1: Assume that there is a computing task in bus 1 of the main processor 101 that requires the assistance of the coprocessor 102. The main processor 101 sends one or more write instructions to the coprocessor 102 through bus 1 connected to the coprocessor 102.
[0078] Among them, the write instruction contains the source operands corresponding to the computing task.
[0079] Step 2: The coprocessor 102 stores the source operands contained in the received write instruction in its own register.
[0080] Step 3: After the main processor 101 sends all the source operands of the computing task, it sends a start computing instruction to the coprocessor 102.
[0081] Among them, the start computing instruction is used to instruct the coprocessor 102 to execute the computing task.
[0082] Step 4: The coprocessor 102 executes the computing task based on the source operands of the received computing task through its own computing unit, obtains the computing result of the computing task, and stores the computing result in its own register.
[0083] Furthermore, the computing unit may be an arithmetic and logic unit (ALU for short).
[0084] Step 5: The coprocessor 102 obtains the calculation result from its own register and sends the calculation result to the main processor 101 via the bus 1.
[0085] Through the above steps 1 - step 5, the main processor 101 has completed a calculation task with the assistance of the coprocessor 102.
[0086] If the main processor 101 is connected to the coprocessor 102 through two or more buses respectively, the coprocessor 102 usually allocates register resources for each bus. The bus uses the registers allocated for it to store data, and the registers between different buses cannot share register resources. If some buses are in a scenario where there is no calculation task for a long time, the registers corresponding to those buses will remain idle all the time.
[0087] The present disclosure provides a data processing method for a coprocessor. The coprocessor divides a first register bank from its own register bank to store data of types such as source operands. Data of types such as source operands for two or more buses connected to the coprocessor are all stored in the first register bank. When any bus needs to store data of types such as source operands, the coprocessor allocates an idle register from the first register bank for this data, realizing the sharing of the register bank by two or more buses and improving the utilization rate of register resources in the coprocessor.
[0088] The following uses specific embodiments to elaborate in detail on the technical solutions provided by the present disclosure.
[0089] Please refer to Figure 2 , Figure 2 which is a schematic flowchart of a data processing method for a coprocessor provided by an embodiment of the present disclosure. As Figure 2 shown, the method provided in this embodiment is executed by the coprocessor. The coprocessor is connected to the main processor through two or more buses respectively. The coprocessor includes a first register bank, and the first register bank is used to store data of a first data type, and the first data type includes the source operand type. This coprocessor can be the coprocessor 102 in the processing system shown in the above Figure 1 . This main processor can be the main processor 101 in the processing system shown in the above Figure 1 . The method provided in this embodiment may include the following steps 201 - step 205.
[0090] Step 201: Receive a first write instruction through the first bus.
[0091] Among them, two or more buses include the first bus, that is, the first bus is any bus connected to the coprocessor.
[0092] Among them, the first write instruction includes a first address and a first data. The first write instruction is used to indicate storing the first data into the register corresponding to the first address. In some scenarios, the source operands in a processing task need to be sent to the coprocessor in multiple write instructions, and the first write instruction can be any one of the write instructions corresponding to the processing task.
[0093] Among them, step 201 corresponds to step 1 of the above embodiment.
[0094] When there is a processing task that requires the assistance of the coprocessor on the first bus of the main processor, the main processor sends a first write instruction carrying the first address and the first data to the coprocessor through the first bus connected to the coprocessor.
[0095] Step 202, determine whether the first address belongs to the first address range.
[0096] If so, continue to execute step 203; if not, continue to execute step 205.
[0097] Step 203, allocate a first register from the registers in the free state in the first register bank.
[0098] Among them, the first register bank corresponds to the first address range. Inside the coprocessor, the registers in the first register bank are not corresponding to the addresses within the first address range. After each register is allocated for the first address, the register corresponds to the first address.
[0099] Among them, the state of the register can include but is not limited to the free state and the busy state. A register in the free state refers to a register that does not store data. In some scenarios, after the register stores data, if the data is retrieved, there is no need to continue storing the data, but there may be remnants of the data in the register, that is, there is still data stored in the register, but the state of the register is the free state, that is, a register in the free state refers to a register that does not store valid data. Correspondingly, a register in the busy state refers to a register that stores valid data.
[0100] The coprocessor determines whether the first address belongs to the first address range through the first address carried in the first write instruction. If the first address belongs to the first address range, it indicates that the data type of the first data carried in the first write instruction is the first data type, and then it is necessary to allocate a first register for the first data from the registers in the free state in the first register bank.
[0101] Step 204, store the first data into the first register.
[0102] After storing the first data in the first register, since the first data usually needs to be used further, the state of the first register is changed to the busy state at this time, so that other data cannot be stored in the first register.
[0103] Step 205: Store the first data in the register corresponding to the first address.
[0104] If the first address does not belong to the first address range, then store the first data in the register corresponding to the first address.
[0105] In this embodiment, when the coprocessor is connected to the main processor through two or more buses, the coprocessor divides the first register bank from its own register bank to store data of the first data type such as source operands. Data of the first data type such as source operands of the two or more buses connected to the coprocessor are all stored in the first register bank. After receiving the first write instruction carrying the first address and the first data through any bus, determine the type of the first data to be stored by whether the first address belongs to the first address range corresponding to the first register bank. When the first address belongs to the first address range corresponding to the first register bank, that is, when it is determined that the type of the first data is the first data type, the coprocessor allocates a register in the first register bank with an idle state for this data. By sharing the register bank among two or more buses and writing data from different buses into the shared register bank in a flexible allocation manner, the utilization rate of the registers is improved.
[0106] In some scenarios, for a computing task, the first bus may need to write source operands into the register in multiple times. After writing all the source operands, the start calculation instruction is written. However, during actual operation, the first bus may not write the start calculation instruction after multiple clock cycles after writing some of the source operands, causing the registers storing the above-mentioned source operands that have been written to be occupied for a long time. That is, the source operands of the computing task have been sent through the bus, but the coprocessor may not receive the corresponding start calculation instruction of the computing task for a long time, and the source operands of the computing task that have been stored will always occupy the register resources, resulting in waste of resources. In this embodiment, within a preset time period after receiving the first source operand of the computing task, if the start calculation instruction of this computing task is not received, then change the state of the register occupied by this computing task to the idle state. The following will be described in detail with specific embodiments.
[0107] Further, after step 203, the following steps 206-208 are also included.
[0108] Step 206: Determine whether the first write instruction is the first write instruction of the computing task corresponding to the first write instruction.
[0109] If so, continue to execute step 207; if not, continue to execute step 204.
[0110] Step 207: Start timing.
[0111] It should be noted that steps 207 and 204 have no execution order. Since the coprocessor performs corresponding actions according to the clock cycle, steps 207 and 204 can be executed within the same clock cycle.
[0112] Step 208: If the timing duration reaches the preset duration and the start calculation instruction corresponding to the first write instruction is not received through the first bus during the timing process, change the status of all second registers to the idle state.
[0113] Among them, the timing duration refers to the time length from the start of timing to the current time. The preset duration is the pre-set time length.
[0114] Furthermore, since the coprocessor performs corresponding actions according to the clock cycle, after starting to time, the timing can be performed according to the number of clock cycles passed, that is, during the timing process, the timing duration is the number of clock cycles passed starting from the clock cycle when the timing starts. Correspondingly, the preset duration is the preset number of clock cycles.
[0115] Among them, the second register is a register that stores the data in the second write instruction. The second write instruction includes: the first write instruction and the write instructions after the first write instruction received from the first bus.
[0116] Exemplarily, the start calculation instruction can be writing 1 in the start calculation register to indicate to the coprocessor to start calculating the calculation task.
[0117] It should be noted that after step 207, when each second register is written, it can be judged whether the current timing duration reaches the preset duration. If the timing duration reaches the preset duration, it is judged whether the start calculation instruction corresponding to the first write instruction is received. If the start calculation instruction corresponding to the first write instruction is received, based on the data stored in all second registers, execute the calculation task corresponding to the first write instruction to obtain the first calculation result. If the start calculation instruction corresponding to the first write instruction is not received, execute as in step 208.
[0118] In this embodiment, at the clock cycle when the first write instruction of the calculation task on the bus is written into the register, start timing. If the start calculation instruction is not received within the preset duration, release the second registers in all first register banks for storing the data of this calculation task, that is, change the status of the second calculator to the idle state. This avoids some registers being occupied for a long time and improves the utilization rate of the registers.
[0119] In some scenarios, when all the registers in the first register bank store valid data, that is, there are no registers in the first register bank in an idle state at present, if any bus sends data, it cannot be stored in the first register bank. Therefore, the coprocessor can not receive any data sent by the bus at this time. The following is a detailed description with specific embodiments.
[0120] In some embodiments, the state of the register further includes: busy state. A register in a busy state means that valid data is stored in the register. After step 204, the following step 209 may further be included.
[0121] Step 209: If the states of all the registers in the first register bank are in a busy state, output first handshake signals to all the buses respectively.
[0122] Wherein, the first handshake signal is used to indicate that the current coprocessor cannot write data of the first data type.
[0123] Exemplarily, the first handshake signal can be a high level or a low level, as long as the first handshake signal is a signal known to both the main processor and the coprocessor, and the present disclosure does not make a limitation in this regard.
[0124] In this embodiment, when the states of all the registers in the first register bank are in a busy state, since there are no registers in the first register bank that can store the data sent by the bus, the coprocessor does not receive any data sent by the bus at this time. By means of the first handshake signal, the bus will not send data, thereby improving the working efficiency between the main processor and the coprocessor.
[0125] Further, after step 209, the following step 210 may further be included.
[0126] Step 210: If there are registers in the first register bank in an idle state, output second handshake signals to all the buses respectively.
[0127] Wherein, the second handshake signal is used to indicate that the current coprocessor receives the written data.
[0128] Exemplarily, the second handshake signal can be a high level or a low level, and the second handshake signal is different from the first handshake signal. That is, if the first handshake signal is a high level, the second handshake signal is a low level; if the first handshake signal is a low level, the second handshake signal is a high level.
[0129] In this embodiment, when all the registers in the first register bank are in the busy state, since there are no registers in the first register bank available to store the data sent by the bus, the coprocessor does not receive any data sent by the bus at this time. In the subsequent processing of the coprocessor, after detecting that there are registers in the first register bank in the idle state, the coprocessor can output second handshake signals to all the buses respectively, indicating that the coprocessor can receive the data sent by the bus, thereby improving the working efficiency between the main processor and the coprocessor.
[0130] In some embodiments, after step 207, the following step 211 may further be included.
[0131] Step 211: If a start calculation instruction corresponding to the first write instruction is received through the first bus and the timing duration has not reached the preset duration, then based on the data stored in all the second registers, execute the calculation task corresponding to the first write instruction to obtain a first calculation result.
[0132] Among them, the calculation task corresponding to the first write instruction can be executed by a calculation unit in the coprocessor.
[0133] It should be noted that after step 207, when each second register is written, it can be judged whether the current timing duration has reached the preset duration. If the timing duration has not reached the preset duration, it is judged whether a start calculation instruction corresponding to the first write instruction is received. If a start calculation instruction corresponding to the first write instruction is received, it is executed as in step 211. If a start calculation instruction corresponding to the first write instruction is not received, the write instruction continues to be received.
[0134] Exemplarily, assume that the preset duration is 10 clock cycles and the timing is performed by a counter. In the clock cycle when the data of the first write instruction is written, the timing starts, the counter changes from 0 to 1, and the counter is incremented by 1 at the rising edge of each clock. If the start calculation instruction is written before the counter reaches 10, then in the clock cycle when the start calculation instruction is written, the counter is updated to 0. If the counter reaches 10 and the start calculation instruction has not been written yet, the counter is updated to 0, and starting from the clock cycle when the counter starts counting, the status of the written register is changed to the idle state.
[0135] In this embodiment, in the clock cycle when the first write instruction of the calculation task on the bus is written into the register, the timing starts. If the start calculation instruction is received within the preset duration, then based on the data stored in all the second registers, execute the calculation task corresponding to the first write instruction to obtain a first calculation result. That is, in the process of normal interaction with the main processor, according to the indication of the instruction sent by the bus, the corresponding calculation task is executed, improving the working efficiency between the main processor and the coprocessor.
[0136] Further, after step 211, the following step 212 may also be included.
[0137] Step 212: Allocate a third register from the free registers of the first register bank for the first calculation result.
[0138] Step 213: Store the first calculation result in the third register.
[0139] In this embodiment, after the computing unit completes the computing task corresponding to the first write instruction, the computing result needs to be stored in the first register bank. After the computing unit completes a computing task, a corresponding register needs to be allocated from the first register bank for the computing result, so as to store the computing result in the allocated register. By sharing the register bank with two or more buses and writing the data of different buses into the shared register bank in an allocated manner, the utilization rate of the registers is improved.
[0140] Further, after step 213, the following step 214 may also be included.
[0141] Step 214: Change the status of the third register to the busy state.
[0142] Since the third register has stored the first calculation result, the third register cannot store other data anymore, so the status of the third register needs to be changed to the busy state.
[0143] Further, after step 214, the following step 215 may also be included.
[0144] Step 215: Determine whether the current first bus indicates receiving data.
[0145] If yes, continue to execute step 216; if no, continue to execute step 217.
[0146] Further, it can be determined whether the current first bus indicates receiving data by using the handshake signal output by the first bus to the coprocessor for indicating whether data can be received currently. Among them, the first bus can output a third handshake signal to the coprocessor to indicate that the current first bus can receive data of the first data type. The first bus can output a fourth handshake signal to the coprocessor to indicate that the current first bus does not receive data of the first data type.
[0147] Exemplarily, the third handshake signal can be high level or low level. The third handshake signal only needs to be a signal known to both the main processor and the coprocessor, and the present disclosure does not limit it. Correspondingly, the fourth handshake signal can be high level or low level, and the fourth handshake signal is different from the third handshake signal. That is, if the third handshake signal is high level, the fourth handshake signal is low level; if the third handshake signal is low level, the fourth handshake signal is high level.
[0148] Step 216: Send the calculation result stored in the second register to the bus corresponding to the first calculation result.
[0149] Among them, the bus corresponding to the first calculation result refers to the bus that sends the calculation task corresponding to the first calculation result.
[0150] Step 217: Output the first handshake signal to the first bus.
[0151] Among them, the first handshake signal is used to indicate that the current coprocessor cannot write data of the first data type.
[0152] In this embodiment, after the coprocessor has obtained the calculation result of the calculation task, the calculation result is returned to the main processor through the bus corresponding to the calculation task. If the bus indicates that it cannot receive data at this time, other data sent by the bus will not be received temporarily. Other data sent by the first bus can be received after the first calculation result is successfully sent through the first bus. Thereby, the working efficiency between the main processor and the coprocessor is improved.
[0153] In some scenarios, in addition to requiring the coprocessor to write data of the first data type mentioned above in the register, the main processor also needs the coprocessor to write configuration type data such as configuration information. In this embodiment, for configuration type data, the coprocessor allocates a second register bank from the register file. Each register in the second register bank has a corresponding address, and the bus can directly write data into the corresponding register. The following will be described in detail with specific embodiments.
[0154] Based on the above embodiments, further, the coprocessor provided in this embodiment further includes a second register bank, which is used to store data of a second data type, and the second data type may include, but is not limited to, a configuration type. Exemplarily, the data of the configuration type may be the start calculation instruction mentioned in the above embodiments, or the rounding method (rounding, etc.) information when the calculation result needs to be rounded, or the number of bits to be shifted when the calculation result needs to be shifted, etc., and the present disclosure does not limit this. The second register bank corresponds to a second address range, and each register in the second register bank has a corresponding address. The second address range has no intersection with the first address range. The method provided in this embodiment, step 205 may include the following steps 2051 to 2054.
[0155] Step 2051: If the first address belongs to the second address range, determine whether there is currently another write instruction that needs to write to the first address.
[0156] If not, then continue to execute step 2052; if so, then continue to execute step 2054. Correspondingly, before step 2051, the following step 2053 is further included.
[0157] Step 2052: Store the first data in the register corresponding to the first address.
[0158] In this embodiment, for the register bank of the coprocessor, a second register bank is divided to store data of the configuration type. The second register bank is different from the first register bank, and the second address range corresponding to the second register bank has no intersection with the first address range. Therefore, for the first write instruction sent by the first bus, according to the address range to which the address carried therein belongs, it can be determined the data type of the data carried therein, and correspondingly, it can be determined whether the data carried therein needs to be stored in the first register bank or the second register bank. For the first write instruction whose first address belongs to the second address range, the first data needs to be stored in the second register bank. Since each register in the second register bank has a corresponding address. Therefore, in the case where there is no other write instruction to write to this first address at this time, the first data is stored in the register corresponding to the first address.
[0159] Step 2053: Receive a third write instruction through the second bus, where the third write instruction includes the first address and the second data.
[0160] Among them, two or more buses include the second bus, and the second bus is different from the first bus.
[0161] If the coprocessor receives, while receiving the first write instruction, a third write instruction sent by the second bus for writing to the first address, an address conflict occurs at this time.
[0162] Step 2054: Store the data included in the write instruction sent by the bus with a higher priority into the register corresponding to the first address, and lower the priority of the bus with a higher priority so that the priority of the bus with a higher priority is lower than that of the bus with a lower priority.
[0163] Among them, the bus with a higher priority refers to the bus with a higher priority among the first bus and the second bus. The bus with a lower priority refers to the bus with a lower priority among the first bus and the second bus.
[0164] In this embodiment, the priority can be set for each bus in advance. In the case of an address conflict, the data carried in the write instruction sent by the bus with a higher priority is preferentially stored in the register corresponding to the conflicting first address. Since the bus with a higher priority wins in the case of an address conflict, the priority of the bus with a higher priority is lowered, and the priority of the bus with a lower priority is raised so that the priority relationship between the two buses after adjusting the priority is opposite to that before adjusting the priority. In the next address conflict, the data of the bus that did not win last time is preferentially stored.
[0165] Exemplarily, assume that the priority of the first bus is higher than that of the second bus. This time, store the first data sent by the first bus in the register corresponding to the first address, and then adjust the priority of the first bus so that the priority of the first bus is lower than that of the second bus. In the next case where there is an address conflict between the first bus and the second bus, the data sent by the second bus is preferentially stored.
[0166] In this embodiment, when two or more buses need to write configuration-type data at the same time, the data of the bus with a higher priority is determined by setting the priorities of the two buses. In the next address conflict, the data of the bus with a lower priority last time is stored. Thus, in the case of an address conflict, a polling arbitration method is adopted to ensure the fairness of arbitration as much as possible, allowing the buses to take turns to win, and the bus that wins in the arbitration can write to the register first.
[0167] In some scenarios, when the bus connected to the coprocessor needs to read configuration-type data, it is directly read through the address sent by the bus. The following is a detailed description with specific embodiments.
[0168] Based on any of the above embodiments, further, the method provided in this embodiment may further include the following steps 218-step 220.
[0169] Step 218: Receive a first read instruction through the first bus.
[0170] Among them, the first read instruction includes a second address. The first read instruction is used to request to obtain the third data stored in the register corresponding to the second address.
[0171] Step 219: Obtain the third data stored in the register corresponding to the second address.
[0172] Step 220: Send the third data through the first bus.
[0173] In this embodiment, for any first read instruction sent by a bus connected to the coprocessor, the third data stored in the register corresponding to the second address can be directly obtained according to the second address carried in the first read instruction, and the third data is sent to the main processor through the first bus. When any bus needs to read the data in the second register bank, the corresponding data is directly obtained according to the address and returned to the bus, realizing the fast reading of the data stored in the coprocessor by the bus.
[0174] In some embodiments, for the process of allocating registers in step 203, there can be multiple implementation manners. Hereinafter, an exemplary implementation manner will be introduced. The registers in the idle state and the busy state in the first register bank can be recorded by setting an idle pointer and a busy pointer. Hereinafter, an exemplary introduction will be made on the fast allocation of registers through the idle pointer and the busy pointer.
[0175] In this example, the registers in the first register bank can be numbered. Assuming that there are 16 registers in the first register bank, the 16 registers can be numbered 0, 1, 2,..., and 15 respectively. To distinguish between the registers in the busy state and the idle state, two pointers are set, namely the idle pointer and the busy pointer. Among them, the idle pointer can be represented by idle_head, and the busy pointer can be represented by busy_head. idle_head points to the first register in the idle state, and busy_head points to the first register in the busy state. Initially, let busy_head = idle_tail = 0.
[0176] If data needs to be written into a register in the first register bank, write the data into the register pointed to by idle_head, and change the state of this register to busy, that is, let idle_head + 1.
[0177] If the source operand in the register has been sent to the computing unit, or the calculation result in the register has been read by the bus, the register needs to be released, that is, change the state of this register to the idle state. The processing is divided into the following two cases:
[0178] Case 1: If the register to be released is exactly the register pointed to by busy_head, then let busy_head + 1.
[0179] Case 2: The released register is not the register pointed to by busy_head. Assume that the register number pointed to by busy_head is X, the register to be released is Y, and the register pointed to by idle_head is Z. Then for the register with number i (Y ≤ i ≤ Z - 1), assign the value of register i + 1 to register i. After the assignment, register Z becomes idle, and let idle_head - 1.
[0180] If the general-purpose registers are full (idle_head + 1 = busy_head), then no new data is received from the bus, and new data is received when there is an empty space in the registers.
[0181] When busy_head and idle_head change, if an out-of-bounds situation occurs, that is, if the pointer = 15 and it needs to be incremented, then let the pointer = 0; if the pointer = 0 and it needs to be decremented, then let the pointer = 15.
[0182] Please refer to Figure 3 , Figure 3 a register scheduling schematic diagram provided by an embodiment of the present disclosure. In this embodiment, the first register bank is referred to as the general-purpose register. Figure 3 The shown scenario is as follows: At a certain moment, register R0, register R2, and register R3 are in a busy state, and the calculation module returns a calculation result, which needs to be stored in the first register bank. According to the position of idle_head, it can be known that register R4 is in an idle state. The calculation result obtained by the calculation unit can be written into register R4, the state of register R4 is changed to a busy state, and let idle_head + 1, that is, idle_head points to register R5.
[0183] Assume that at a certain moment, it is necessary to release register R0. Since register R0 is the register pointed to by busy_head, let busy_head + 1, that is, busy_head points to register R1.
[0184] Assume that at a certain moment, it is necessary to release register R1. Since register R1 is not the register pointed to by busy_head, assign the value of register R2 to register R1, assign the value of register R3 to register R2, and let idle_head - 1, that is, idle_head points to R3. Then after the assignment and moving the pointer, registers R0 - R2 are in a busy state, and registers R3 - R15 are in an idle state.
[0185] In this example, by setting two pointers, when a register needs to be allocated, the state of the register can be quickly obtained, the management of the register state can be realized, and thus the register can be quickly allocated, improving the allocation and processing efficiency.
[0186] Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of a coprocessor provided by an embodiment of the present disclosure. The coprocessor provided by this embodiment is connected to the main processor through a first bus and a second bus respectively. The coprocessor provided by this embodiment includes:
[0187] A first register bank 401 for storing data of a first data type, where the first data type includes source operand types; the first register bank corresponds to a first address range.
[0188] A receiving module 402 for receiving a first write instruction through the first bus, where the first write instruction includes a first address and a first data.
[0189] A scheduling module 403 for, if the first address belongs to the first address range, allocating a first register from the registers in the idle state in the first register bank; the registers in the idle state refer to the registers that do not store data; storing the first data in the first register; and changing the state of the first register to the busy state.
[0190] In some embodiments, the scheduling module 403 is further configured to:
[0191] If the first write instruction is the first write instruction of the calculation task corresponding to the first write instruction, start timing;
[0192] If the timing duration reaches a preset duration and no start calculation instruction corresponding to the first write instruction is received through the first bus during the timing process, change the states of all second registers to the idle state; the second registers are the registers that store the data in the second write instruction, and the second write instruction includes: the first write instruction and the write instructions received from the first bus after the first write instruction.
[0193] In some embodiments, the state of the register further includes: the busy state; the scheduling module 403 is further configured to:
[0194] If the states of all the registers in the first register bank are in the busy state, output a first handshake signal to all the buses respectively, and the first handshake signal is used to indicate that the current coprocessor cannot write data of the first data type.
[0195] In some embodiments, the scheduling module 403 is specifically configured to:
[0196] If there are registers in the idle state in the first register bank, output a second handshake signal to all the buses respectively, and the second handshake signal is used to indicate that the current coprocessor receives the written data.
[0197] In some embodiments, the scheduling module 403 is further configured to:
[0198] If a start calculation instruction corresponding to a first write instruction is received via the first bus and the timing duration has not reached the preset duration, then based on the data stored in all the second registers, execute the calculation task corresponding to the first write instruction to obtain a first calculation result.
[0199] In some embodiments, the first data type further includes a calculation result type; the scheduling module 403 is further configured to:
[0200] Allocate a third register for the first calculation result from the idle registers of the first register bank;
[0201] Store the first calculation result in the third register.
[0202] In some embodiments, the scheduling module 403 is further configured to:
[0203] If the current first bus indicates receiving data, then send the first calculation result via the first bus;
[0204] If the current first bus indicates not receiving data, then output a first handshake signal to the first bus, where the first handshake signal is used to indicate that the current coprocessor cannot write data of the first data type.
[0205] In some embodiments, the coprocessor further includes a second register bank, where the second register bank is used to store data of a second data type, and the second data type includes a configuration type; the second register bank corresponds to a second address range; the second address range has no intersection with the first address range;
[0206] The scheduling module 403 is further configured to:
[0207] If the first address belongs to the second address range and there is no other write instruction currently that needs to write to the first address, then store the first data in the register corresponding to the first address.
[0208] In some embodiments, the scheduling module 403 is further configured to:
[0209] Receive a third write instruction via the second bus, where the third write instruction includes a first address and a second data; two or more buses include the second bus, and the second bus is different from the first bus;
[0210] If the first address belongs to the second address range and there is a third write instruction currently that needs to write to the first address, then store the data included in the write instruction sent by the bus with a higher priority in the register corresponding to the first address, and reduce the priority of the bus with a higher priority so that the priority of the bus with a higher priority is lower than the priority of the bus with a lower priority; the bus with a higher priority refers to the bus with a higher priority among the first bus and the second bus.
[0211] In some embodiments, the receiving module is further configured to: receive a first read instruction through a first bus, where the first read instruction includes a second address;
[0212] The scheduling module 403 is further configured to: obtain third data stored in a register corresponding to the second address; send the third data through the first bus.
[0213] The coprocessor provided in this embodiment has a similar implementation principle and beneficial effects to those of the above embodiments, which will not be elaborated here.
[0214] Next, in combination with Figure 5 the structure of the coprocessor shown, the coprocessor provided by the present disclosure will be introduced exemplarily.
[0215] Please refer to Figure 5 , Figure 5 which is a schematic structural diagram of another coprocessor provided by an embodiment of the present disclosure. Figure 5 In the coprocessor shown, it is exemplarily shown that the coprocessor is connected to two buses, namely Bus 1 and Bus 2. The coprocessor provided in this embodiment includes a register bank and a computing unit, where the computing unit is represented by an ALU in Figure 5 this context.
[0216] The register bank includes a scheduling module, general-purpose registers, and special-purpose registers. The scheduling module corresponds to the scheduling module in the above embodiments. The general-purpose registers correspond to the first register bank in the above embodiments. The special-purpose registers correspond to the second register bank in the above embodiments.
[0217] The special-purpose registers store calculation-related configuration information, for example, the start calculation (START) signal used to start the calculation. The general-purpose registers are used to transfer the source operands of the calculation and store the calculation results obtained from the calculation. The scheduling module in the register bank is responsible for allocating general-purpose registers to different buses and handling special situations such as the register being full and address conflicts when multiple buses request to write.
[0218] If a bus needs to start a calculation task, it can write 1 to the special-purpose register START to indicate starting the calculation task. After detecting the START signal, the computing unit obtains the configuration and variable information required for the calculation from the register bank, starts to execute the calculation, and writes the calculation result back to the general-purpose register after the calculation is completed.
[0219] In practical applications, the coprocessor is connected to multiple peripheral buses, and each bus can request to read and write registers through the read-write register channel. The bus can read and write both special-purpose registers and general-purpose registers.
[0220] In this embodiment, a coprocessor architecture with two bus - shared register files is taken as an example to illustrate the structure of the coprocessor. The coprocessor is connected to two buses. The register file contains special - purpose registers and general - purpose registers. Each bus can read and write both special - purpose registers and general - purpose registers. For example, at a certain moment, register R0 is occupied by bus 1, and at another moment, R0 is occupied by bus 2. When a bus requests to read or write a general - purpose register, an idle general - purpose register is allocated for writing according to the usage situation of the register. For the case of address conflict (two buses request to write to the same special - purpose register), a polling arbitration method is adopted to ensure the fairness of arbitration as much as possible. Let the two buses take turns to win. The bus that wins in the arbitration can write to the special - purpose register first, blocking the write of the bus that does not win. This improves the utilization efficiency of the registers, avoids long - term idleness of the registers, and flexibly allocates general - purpose registers according to the requests of the buses.
[0221] The present disclosure provides a coprocessor, including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements the steps of the method in any of the above - mentioned embodiments.
[0222] The coprocessor provided in this embodiment has the same implementation principle and beneficial effects as those in the above - mentioned embodiments, which will not be elaborated here.
[0223] The present disclosure provides a processing system, including a main processor and a coprocessor; the main processor is respectively connected to the coprocessor through two or more buses; the coprocessor is the coprocessor as in the above - mentioned embodiment.
[0224] The processing system provided in this embodiment has the same implementation principle and beneficial effects as those in the above - mentioned embodiments, which will not be elaborated here.
[0225] Based on the data - processing method described in any of the above - mentioned embodiments, the embodiments of the present disclosure also provide a computer - readable storage medium. For example, a non - temporary computer - readable storage medium can be a read - only memory (ROM), a random - access memory (RAM), a CD - ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc. Computer instructions are stored on this storage medium for executing the data - processing method described in any of the above - mentioned embodiments, which will not be elaborated here.
[0226] Those of ordinary skill in the art can understand that all or part of the steps to implement the above - mentioned embodiments can be completed by hardware or by a program instructing relevant hardware. The program can be stored in a computer - readable storage medium. The above - mentioned storage medium can be a read - only memory, a magnetic disk, or an optical disc, etc.
[0227] Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only to be considered as exemplary, and the true scope and spirit of the present disclosure are pointed out by the following claims.
Claims
1. A data processing method, characterized in that: The invention is applied to a coprocessor, wherein the coprocessor is connected to a main processor through two or more buses respectively; the coprocessor comprises a first register file, wherein the first register file is used to store data of a first data type, wherein the first data type comprises a source operand type; the first register file corresponds to a first address range; the method comprises: receiving a first write instruction via a first bus, wherein the first write instruction includes a first address and first data; the two or more buses include the first bus; If the first address belongs to the first address range, allocating the first register from the registers in the first register stack in an idle state; the state of the register includes an idle state, and the register in the idle state refers to a register that does not store data; The first data is stored in the first register.
2. The method according to claim 1, characterized in that After allocating the first register from the registers in the idle state in the first register file, the method further includes: If the first write instruction is the first write instruction of the computing task corresponding to the first write instruction, start timing; If the timing duration reaches a preset duration and the start calculation instruction corresponding to the first write instruction is not received through the first bus during the timing process, the state of all second registers is changed to an idle state; the second register is a register that stores data in the second write instruction, and the second write instruction includes: the first write instruction and a write instruction after the first write instruction received from the first bus.
3. The method according to claim 1, characterized in that The state of the register further includes: a busy state; after storing the first data into the first register, the further includes: If the status of all registers in the first register file is busy, a first handshake signal is output to all buses respectively, where the first handshake signal is used to indicate that the current coprocessor cannot write data of the first data type.
4. The method according to claim 3, characterized in that The step of outputting the first handshake signal to all buses respectively comprises: If there are idle registers in the first register file, a second handshake signal is output to all buses respectively, where the second handshake signal is used to instruct the coprocessor to currently receive write data.
5. The method according to claim 2, characterized in that: The method further comprises: If a start calculation instruction corresponding to the first write instruction is received through the first bus and the timing duration does not reach the preset duration, the calculation task corresponding to the first write instruction is executed based on the data stored in all the second registers to obtain a first calculation result.
6. The method according to claim 5, characterized in that The first data type also includes a calculation result type; and after executing the calculation task corresponding to the first write instruction based on the data stored in all the second registers and obtaining the first calculation result, the method further includes: Allocate a third register for the first calculation result from a free register in the first register file; The first calculation result is stored in the third register.
7. The method according to claim 6, characterized in that After storing the first calculation result in the third register, the method further includes: If the first bus currently indicates receiving data, sending the first calculation result through the first bus; If the first bus currently indicates that no data is to be received, a first handshake signal is output to the first bus, where the first handshake signal is used to indicate that the current coprocessor cannot write data of the first data type.
8. The method according to claim 1, characterized in that The coprocessor further includes a second register file, the second register file is used to store data of a second data type, the second data type includes a configuration type; the second register file corresponds to a second address range; the second address range has no intersection with the first address range; the method further includes: If the first address belongs to the second address range and there is no other write instruction that needs to write to the first address, the first data is stored in the register corresponding to the first address.
9. The method according to claim 8, characterized in that The method further comprises: receiving a third write instruction via a second bus, wherein the third write instruction includes the first address and the second data; the two or more buses include the second bus, and the second bus is different from the first bus; If the first address belongs to the second address range and there is currently a third write instruction that needs to write to the first address, the data contained in the write instruction sent by the high-priority bus is stored in the register corresponding to the first address, and the priority of the high-priority bus is reduced so that the priority of the high-priority bus is lower than the priority of the low-priority bus; the high-priority bus refers to the bus with a higher priority between the first bus and the second bus.
10. The method according to claim 1, characterized in that The method further comprises: receiving a first read instruction via the first bus, wherein the first read instruction includes a second address; Acquire third data stored in the register corresponding to the second address; The third data is sent through the first bus.
11. A coprocessor, characterized in that: The coprocessor is connected to the main processor via a first bus and a second bus respectively; the coprocessor comprises: a first register file, for storing data of a first data type, the first data type comprising a source operand type; the first register file corresponds to a first address range; A receiving module, configured to receive a first write instruction via a first bus, wherein the first write instruction includes a first address and first data; A scheduling module is used to allocate a first register from an idle register in the first register stack if the first address belongs to the first address range; the idle register refers to a register that does not store data; store the first data in the first register; and change the state of the first register to a busy state.
12. A coprocessor, comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, characterized in that: When the processor executes the program, the steps of the method according to any one of claims 1 to 10 are implemented.
13. A processing system, characterized in that: It comprises a main processor and a coprocessor; the main processor is connected to the coprocessor via two or more buses respectively; the coprocessor is the coprocessor as claimed in claim 12.
14. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 10 are implemented.