A method and system for detecting data loss in a storage chip

Abstract

The present invention provides a data loss detection method and system for a memory chip, relating to the field of memory chip technology. The method comprises: obtaining an address mapping table of the memory chip; determining the fault coupling strength between each pair of memory cells in the memory chip based on the address mapping table; establishing a fault propagation model between different memory cells related to the probability of memory cell failure based on the fault coupling strength; calculating the steady-state solution of the fault propagation model and determining potential fault areas of the memory chip based on information entropy; generating differentiated detection paths for the potential fault areas; testing the memory chip according to the differentiated detection paths; repairing the detected faulty memory cells in the order in which they were detected; and outputting the data loss detection results of the memory chip based on the number of faulty memory cells that failed to be repaired. This method solves the problem of easily missed fault chains and coupling effects, and improves detection accuracy and efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of memory chips, and in particular to a data loss detection method and system for a memory chip. Background Art

[0002] Memory chips are hardware components used to store data in electronic devices and are widely used in computers, mobile phones, servers, and other devices. They are primarily categorized as volatile memory chips and non-volatile memory chips. Non-volatile memory chips, such as NAND Flash, EEPROM, and FRAM, retain stored data even after a power outage and are commonly used in solid-state drives (SSDs), USB flash drives, and mobile devices. These chips store information through charge storage or other physical mechanisms, eliminating the need for power to maintain data and providing durability.

[0003] Non-volatile memory chips are core components of modern electronic devices, responsible for long-term storage of critical data. However, due to repeated writes and erases, manufacturing defects, and environmental factors (such as high temperature and humidity), memory chips may fail, resulting in data loss or corruption. Promptly detecting these memory chip failures is crucial. Data loss detection can uncover potential memory cell errors, identify the faulty area, and repair them, thus preventing the loss of important data and ensuring system reliability and data security. This is particularly important in high-reliability applications such as data centers and medical equipment.

[0004] However, existing data loss detection schemes usually use a global traversal approach for fault detection, which results in severe damage to the storage chip, long detection time, and often ignores the fault propagation effect between storage cells in the storage chip. This makes it impossible to accurately identify fault chains and coupling effects, thereby missing some potential fault areas and reducing detection accuracy and efficiency. Summary of the Invention

[0005] In view of the above-mentioned deficiencies in the prior art, the purpose of the embodiments of the present invention is to provide a data loss detection method for a memory chip, which can solve the technical problems existing in the prior art that a global traversal method is usually used for fault detection, resulting in severe damage to the memory chip, a long detection time, and often ignoring the fault propagation effect between the various storage units in the memory chip, resulting in the inability to accurately identify the fault chain and coupling effect, thereby missing some potential fault areas and reducing the accuracy and efficiency of detection.

[0006] According to a first aspect of an embodiment of the present invention, a method for detecting data loss in a memory chip is provided, comprising:

[0007] S1: Get the address mapping table of the memory chip;

[0008] S2: Determine the fault coupling strength between any two memory cells in the memory chip in combination with the address mapping table;

[0009] S3: Combine the fault coupling strength to establish a fault propagation model between different storage units related to the failure probability of the storage unit;

[0010] S4: Calculate the steady-state solution of the fault propagation model and determine the potential fault areas of the memory chip based on information entropy;

[0011] S5: Generate differentiated detection paths for potential fault areas;

[0012] S6: Detect the memory chip according to the differentiated detection path;

[0013] S7: Repairing the detected faulty storage units in the order of detection;

[0014] S8: Outputting the data loss detection result of the storage chip according to the number of faulty storage units that failed to be repaired.

[0015] A second aspect of an embodiment of the present invention provides a data loss detection system for a storage chip, comprising: a processor and a memory;

[0016] The memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the data loss detection method for the memory chip of the first aspect are implemented.

[0017] According to a third aspect of an embodiment of the present invention, a readable storage medium is provided, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the data loss detection method for a storage chip according to the first aspect are implemented.

[0018] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0019] In the embodiment of the present invention, by introducing the fault coupling strength and fault propagation model, the traditional fault detection method of the prior art that only relies on global traversal is solved, and the inefficiency problem caused by too wide a scanning range and too long a detection time is avoided. First, by obtaining the address mapping table of the memory chip and determining the fault coupling strength between the memory cells, the potential impact between the cells can be accurately identified, providing a basis for subsequent fault propagation modeling. Secondly, by combining the fault propagation model to calculate the steady-state solution and using information entropy to determine the fault area, high-risk areas can be accurately identified, thereby generating differentiated detection paths in a targeted manner and avoiding blind comprehensive scanning. Finally, the faulty storage cells are repaired in order according to the detected sequence, and the effect of the fault repair is output in combination with the detection results. This method not only improves the detection accuracy, but also greatly improves the detection efficiency, solves the problem of easily missed fault chains and coupling effects, and ensures more efficient, less damaged and more accurate detection of memory chip data loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are only for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. Throughout the drawings, the same reference symbols represent the same components. Obviously, the drawings described below are only some embodiments of the present invention. It is clear that those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0021] Figure 1 This is a flow chart of a data loss detection method for a storage chip provided by an embodiment of the present invention;

[0022] Figure 2 The present invention is a schematic structural diagram of a data loss detection system for a storage chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are part of the embodiments of the present invention, rather than all of the embodiments. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work should fall within the scope of protection of the present invention.

[0024] The data loss detection method for a memory chip provided by the embodiment of the present invention will be described in detail below with reference to the accompanying drawings through specific embodiments and application scenarios.

[0025] Reference Manual Figure 1, shows a flow chart of a data loss detection method for a memory chip provided by an embodiment of the present invention.

[0026] An embodiment of the present invention provides a method for detecting data loss in a storage chip, which may include the following steps:

[0027] S1: Get the address mapping table of the memory chip.

[0028] The address mapping table is a table structure used within a memory chip to describe the relationship between logical addresses and physical addresses. In non-volatile memory chips, the logical address is the address used by the user or operating system to access data, while the physical address is the physical location where the data is actually stored in the memory cell. The address mapping table is typically maintained by the memory chip's controller, mapping logical addresses to physical addresses to ensure correct data storage and retrieval. By obtaining this mapping table, the layout of the memory cells and the distribution of data can be accurately identified, providing the necessary foundational data for subsequent fault detection and the development of fault propagation models.

[0029] S2: Determine the fault coupling strength between any two memory cells in the memory chip in conjunction with the address mapping table.

[0030] Among them, fault coupling strength refers to the degree of fault correlation between two storage units in a memory chip due to physical proximity or logical dependence, that is, the possibility that a failure in one storage unit will affect the failure of another unit.

[0031] It's important to note that combining an address mapping table to determine the fault coupling strength between memory cells in a memory chip accurately identifies the mutual impact between different memory cells. This approach avoids the inefficiencies of traditional global scanning, helps pinpoint fault propagation paths, and improves the accuracy and efficiency of fault detection, effectively reducing missed detection rates in complex fault scenarios.

[0032] In a possible implementation, S2 specifically includes:

[0033] S201: Acquire physical architecture information of a memory chip, wherein the physical architecture information includes a physical diffusion scale describing an influence range of a unit charge in a single memory cell.

[0034] Among them, the physical diffusion scale is related to the type of memory chip production process, that is, how many memory cells can be affected by the unit charge obtained in advance based on the production process.

[0035] Alternatively, the physical diffusion scale can be calculated directly in real time according to the formula, specifically as follows:

[0036] ;

[0037] in, represents the Boltzmann constant, Indicates the current temperature of the memory chip. Indicates the spacing between adjacent storage cells, Indicates the thickness of the insulation layer of the memory chip, represents pi, represents the material viscosity coefficient, Represents the physical diffusion scale.

[0038] It's important to note that the material viscosity coefficient specifically describes the resistance of the memory cell's insulating layer (e.g., SiO2, SiN, etc.) to charge diffusion. The insulating layer (e.g., SiO2, HfO2) is the core structure that isolates the memory cell, and its thickness directly affects the probability of charge tunneling.

[0039] S202: Determine the physical three-dimensional coordinates of each storage unit in the storage chip based on the physical architecture information.

[0040] Physical architecture information refers to data describing the internal structure and characteristics of a memory chip. It primarily includes the layout of memory cells, spacing between cells, isolation layer thickness, and electrical characteristics. It helps us understand the physical characteristics of a memory chip and its internal distribution. A memory cell is the basic unit used to store data in a memory chip. Each memory cell has a unique physical address, indicating its actual location within the chip. Physical three-dimensional coordinates are a coordinate system used to represent the spatial location of a memory cell within the memory chip, typically expressed in x, y, and z dimensions. These coordinates define the physical location of each memory cell within the chip, helping to identify the relative distances between cells and their potential interactions. By obtaining the physical architecture information of a memory chip, the physical three-dimensional coordinates of each memory cell can be accurately determined. This information helps understand the spatial layout of each memory cell within the chip, providing important data such as the relative positions between cells and potential electrical interference, laying the foundation for subsequent fault propagation models and detection paths.

[0041] S203: Establish a directed acyclic graph of the storage chip based on the address mapping table, wherein the nodes of the directed acyclic graph are the logical addresses of the storage units reflected in the address mapping table, the edges of the directed acyclic graph are the mapping relationships between different storage units in the address mapping table, and the edge attributes are the number of historical interactions between the two storage units.

[0042] Among them, the historical interaction times are recorded through the address mapping table and access log system of the storage chip controller, representing the interaction frequency between logical units.

[0043] S204: Calculate the fault coupling strength according to the physical diffusion scale of the memory chip and the directed acyclic graph.

[0044] The calculation method of fault coupling strength is as follows:

[0045] ;

[0046] in, represents the fault coupling strength between the i-th storage unit and the j-th storage unit, e represents a natural constant, and Represent the physical three-dimensional coordinates of the i-th storage unit and the j-th storage unit, represents the physical diffusion scale, Indicates the historical mapping times between the i-th storage unit and the j-th storage unit, i.e., the historical interaction times. Indicates the maximum logic jump length of the memory chip, log represents the logarithmic function, represents the squared Euclidean distance.

[0047] It's important to note that the formula for calculating fault coupling strength takes into account the impact of the physical distance between two storage cells, the number of historical interactions, and the length of logical transitions on fault propagation. The first term in the formula squares the physical distance between storage cells, accounting for the effect of physical proximity on fault coupling. Closer distances increase coupling strength. The second term reflects the enhanced effect of logical dependencies and access counts on fault propagation based on the historical frequency of interactions between storage cells. Higher interaction frequencies increase coupling strength. The overall calculation, combining these two terms, quantifies the potential for fault propagation between storage cells.

[0048] Specifically, by obtaining information about the physical architecture of the memory chip, the mutual influence between memory cells is described in detail. First, the physical diffusion scale is calculated. This scale determines the range of influence of a unit charge on adjacent memory cells. This calculation is performed in real time based on factors such as the chip's production process, temperature, and insulation layer thickness. Next, the physical three-dimensional coordinates of each memory cell are obtained, and a directed acyclic graph (DAG) is constructed based on the address mapping table. This graph shows the logical relationship between memory cells and the number of historical interactions between them, reflecting the access frequency between logical cells. By combining the physical diffusion scale and the directed acyclic graph, the fault coupling strength is calculated. This parameter quantifies the potential for fault propagation between two memory cells. Ultimately, the system can accurately identify the mutual influence between memory cells and the fault propagation path, improving the accuracy and efficiency of fault detection.

[0049] S3: Combined with the fault coupling strength, a fault propagation model between different storage units is established that is related to the failure probability of the storage unit.

[0050] The storage cell failure probability refers to the likelihood of a storage cell failing under specific conditions. It is typically calculated based on the storage cell's historical behavior, service life, environmental factors (such as temperature and humidity), and interactions with other cells. In this context, the storage cell failure probability is closely related to the strength of fault coupling. Calculating the storage cell failure probability provides quantitative input for fault propagation models, helping to more accurately predict where failures are likely to occur, thereby optimizing detection and repair strategies. By incorporating the strength of fault coupling into the fault propagation model, the propagation paths and probabilities of faults between different storage cells can be precisely described. This approach dynamically reflects the cascading effects and multi-level impacts of failures, avoiding the oversimplification of traditional methods. By combining the fault propagation model with the cell failure probability, the system can identify potential failure areas and prioritize high-risk areas, thereby improving detection accuracy, reducing missed detection rates, and enhancing overall detection efficiency.

[0051] In a possible implementation, S3 specifically includes:

[0052] S301: Calculate the three-dimensional Laplacian operator of the storage unit failure in the physical space to describe the physical layer diffusion intensity of the storage unit failure in the physical space.

[0053] The three-dimensional Laplace operator describes the curvature (i.e., diffusion rate) of storage unit failures in physical space. The physical layer diffusion intensity is calculated as follows:

[0054] ;

[0055] ;

[0056] in, represents the physical diffusion scale, represents the three-dimensional Laplacian operator, Represents the physical three-dimensional coordinates of the storage unit, represents the partial derivative, represents the probability of memory cell failure of the i-th memory cell in the memory chip, Indicates the physical layer diffusion strength.

[0057] It's important to note that the diffusion intensity of a memory cell fault in physical space is described by calculating the three-dimensional Laplace operator. The Laplace operator measures the rate of change of the fault probability in space, reflecting the degree of fault propagation among surrounding cells. The physical diffusion intensity, by calculating the curvature of the memory cell fault probability in three-dimensional space, assesses the spatial diffusion capacity of the fault and helps predict the fault propagation path within the memory chip.

[0058] S302: Determine the logical layer diffusion strength of the storage unit fault in the logical space, ie, the logical mapping table, based on the fault coupling strength.

[0059] The calculation method of the logic layer diffusion strength is as follows:

[0060] ;

[0061] ;

[0062] in, represents the logical fault driver, represents the fault coupling strength between the i-th storage unit and the k-th storage unit, Indicates the number of logical mapping operations per unit time, Indicates the maximum mapping operation frequency of the memory chip, Indicates the data retention period. represents the probability of memory cell failure describing the kth memory cell in the memory chip, Indicates the diffusion strength of the logic layer.

[0063] It's important to note that the logical layer diffusion strength is calculated by combining the fault coupling strength and the failure probability of each storage unit. This measure measures the propagation of faults in the logical space, taking into account the frequency of interactions between logical units and the factors driving faults. By calculating the coupling strength and failure probability of each storage unit with other units, combined with the number of logical mapping operations and storage retention time, we can accurately describe the propagation of faults in the logical mapping table.

[0064] S303: Determine the self-repair strength of the memory chip based on the error correction capability of the memory chip. The specific calculation formula for the self-repair strength is:

[0065] ;

[0066] ;

[0067] in, Indicates the ECC error correction capability of the memory chip. Represents the memory chip self-repair coefficient, Indicates the memory chip error correction response speed, Indicates the number of redundant blocks in the memory chip. Indicates the average repair delay of the storage chip, Indicates the self-repair strength.

[0068] The unit of ECC error correction capability is bit / page.

[0069] It's important to note that the self-repair strength of a memory chip is calculated by combining its ECC error correction capability, number of redundant blocks, and repair latency. This reflects the chip's ability to recover from a fault using ECC and redundant resources. By assessing the effectiveness of chip self-repair, we can optimize fault repair strategies.

[0070] S304: A fault propagation model is established by combining the physical layer diffusion strength, the logical layer diffusion strength, and the self-repair strength. The specific expression of the fault propagation model is:

[0071] ;

[0072] Where t represents the time variable.

[0073] Specifically, by combining multiple factors, including the physical layer, logical layer, and self-repair strength, the propagation of storage unit faults can be more accurately simulated. By calculating the diffusion strength of the physical layer and the diffusion strength of the logical layer, the system can capture the propagation patterns of faults in both physical and logical spaces. The introduction of self-repair strength further considers the error correction capabilities and redundant resources of the storage chip, improving the feasibility of fault repair. By integrating these factors, the overall model not only improves the accuracy of the fault propagation model, but also effectively predicts and identifies high-risk areas and optimizes detection paths, thereby achieving more accurate and efficient fault detection and repair, avoiding the misjudgments and missed detections that plague traditional methods.

[0074] S4: Calculate the steady-state solution of the fault propagation model and determine the potential fault areas of the memory chip based on the information entropy.

[0075] A steady-state solution refers to the stable state that a dynamic system ultimately reaches over time. In a fault propagation model, the steady-state solution represents the final stable value of the failure probability of all memory cells during the system's fault propagation process. The steady-state solution, which no longer changes over time, reflects the final state of the memory cells after long-term operation or multiple fault propagations. Information entropy is a measure of information uncertainty, indicating the degree of randomness or chaos within a system. In a fault propagation model, information entropy is used to quantify the uncertainty of the failure probability of each memory cell in a memory chip. A higher entropy value indicates a more uniform distribution of faults in the system, making it difficult to identify the faulty area. A lower entropy value indicates a more concentrated faulty area, making it easier to identify. Potential fault areas are areas in a memory chip where faults may occur. These areas have a higher probability of failure or are identified as high-risk areas based on the fault propagation model and information entropy calculations. Potential fault areas are typically identified as high-risk areas based on the steady-state solution and information entropy, and may be the focus of subsequent monitoring and repair.

[0076] It's important to note that by calculating the steady-state solution of the fault propagation model and combining it with information entropy, we can accurately identify potential fault areas within the memory chip. The steady-state solution allows the system to predict the final state of each memory cell's failure, while information entropy helps assess the uncertainty and concentration of the fault area, thereby improving the accuracy of fault area identification. This approach allows for more targeted focus on high-risk areas, reducing blind detection and improving detection efficiency and accuracy.

[0077] In a possible implementation, S4 specifically includes:

[0078] S401: Acquire a faulty storage unit in a storage chip.

[0079] S402: setting the storage unit failure probability of the faulty storage unit to 1 respectively, substituting the probability into the fault propagation model, and updating the fault propagation model.

[0080] S403: setting the updated fault propagation model equal to zero, and obtaining a steady-state solution corresponding to the faulty storage unit, wherein each steady-state solution constitutes a steady-state distribution.

[0081] S404: Determine the fault region discrimination threshold of the memory chip by combining the steady-state solution and using information entropy. The fault region discrimination threshold is calculated as follows:

[0082] ;

[0083] ;

[0084] ;

[0085] in, represents the fault area discrimination threshold, Indicates the total number of storage units in the memory chip, represents the information entropy that quantifies the uncertainty of the probability of failure of a storage unit, represents the steady-state solution corresponding to the i-th storage unit, Represents the maximum information entropy related to the total number of storage units.

[0086] It's important to note that by combining the steady-state solution and information entropy to determine the fault region discrimination threshold, we can quantify the uncertainty of the failure probability in the memory chip. Information entropy reflects the uniformity of the fault probability distribution. The lower the entropy value, the more concentrated the fault region, making it easier to identify. Calculating the threshold helps dynamically determine the criteria for distinguishing high-risk areas, avoiding misjudgments or missed detections caused by traditional fixed thresholds, and improving the accuracy and efficiency of fault region identification.

[0087] S405: retaining the target steady-state solution that is greater than the fault region discrimination threshold, and taking the connected domain formed by the storage units corresponding to the target steady-state solution as the potential fault region.

[0088] The connected domain is a region in space formed by all storage units whose failure probability is greater than the fault region discrimination threshold. In this region, there is a strong correlation or fault propagation possibility between storage units.

[0089] Specifically, the process accurately identifies potential fault areas in memory chips by gradually updating and calculating the fault propagation model. First, the faulty memory cells in the memory chip are obtained, and the failure probability of these faulty cells is set to 1. The fault propagation model is then substituted into the updated fault propagation model. Next, the steady-state solution is calculated using the updated model to obtain the final failure probability of each memory cell. By combining information entropy, the fault area discrimination threshold is calculated to determine which areas have a higher probability of failure. Finally, steady-state solutions greater than the discrimination threshold are retained, and the areas where these faulty cells are located are defined as potential fault areas through connected domain analysis. This process can effectively identify and focus on high-risk areas in memory chips, improving the accuracy and efficiency of fault detection.

[0090] S5: Generate differentiated detection paths for potential fault areas.

[0091] Differentiated inspection paths are targeted inspection routes designed based on the risk level, fault coupling strength, and fault propagation model of the fault area. Unlike traditional global traversal, differentiated inspection paths prioritize high-risk areas and potential fault zones, reducing unnecessary inspection work, optimizing inspection sequencing, and avoiding wasted time and resources.

[0092] In a possible implementation, the expression of the differential repair path is specifically:

[0093] ;

[0094] in, represents the differential detection path, Represents the set of candidate detection paths that maximize the function , Indicates the detection time from the detection timestamp of storage unit p to storage unit q in the potential fault area to the current timestamp. represents the time decay factor, It represents the fault coupling strength between p and q.

[0095] It's important to note that this differentiated repair path prioritizes repairs in areas with strong fault coupling and a long period of undetection by considering the strength and time decay of fault coupling between storage units. This approach dynamically adjusts the repair order based on the mutual influence between storage units, avoiding ineffective repairs and ensuring that the most critical faulty areas are repaired promptly. This improves repair efficiency, reduces resource waste, and enhances system reliability and repair capabilities.

[0096] Alternatively, if the environment is stable with periodic review, the time decay factor can be set to , if the fault propagates quickly in a high temperature / high load scenario, the time decay factor can be set to If the long-term stability requirement is high in a cold storage environment, the time decay factor can be set to .

[0097] S6: Detect the memory chip according to the differentiated detection path.

[0098] It's understandable that by testing memory chips along differentiated detection paths, we prioritize areas with higher failure probabilities and risks. Compared to traditional full-disk scans, this method is more accurate and efficient, enabling timely identification and location of potential faults, reducing unnecessary repeated scans, and improving the speed and accuracy of fault detection, thereby effectively saving testing time and resources.

[0099] In a possible implementation, S6 specifically includes:

[0100] The memory chip is tested according to a differentiated test path using test data, wherein the test data includes: interleaved bit pattern data, zero-one data, deinterleaved bit pattern data, row-by-row inversion data pattern, and pseudo-random filling data.

[0101] Interleaved bit patterns are fixed patterns of alternating 0s and 1s within each row or column. They are used to detect structural faults such as bit coupling, programming disturbance, and bit line disturbance, such as 01010101 and 10101010. Zero-one data is a static pattern filled with all 0s or 1s, used to detect stuck-at faults (stuck at 0s or 1s), such as 00000000 or 11111111. Deinterleaved bit patterns alternate between adjacent rows, with odd and even rows reversed, forming a checkerboard-like alternating structure, such as 0101, 1010, 0101, 1010, or 10101010 and 01010101. Row-by-row inversion data patterns start with the first row and invert the data bit by bit in each row relative to the previous row, i.e., 0s become 1s and 1s become 0s, such as 00000000 and 11111111. Pseudo-random padding data is data generated using a pseudo-random number generator (such as LFSR). The data pattern is close to the real workload and has a higher coverage, such as 11001100 and 10111001.

[0102] It's understandable that by using different types of test data (such as interleaved bit patterns and zero-one data) along differentiated detection paths, we can more comprehensively cover various memory chip fault types. This approach selects the appropriate test mode based on the characteristics of the faulty area, improving fault detection accuracy, avoiding ineffective scans, and effectively reducing test time and resource consumption, thereby improving overall detection efficiency and fault location accuracy.

[0103] S7: Repair the detected faulty storage units in the order in which they were detected.

[0104] It should be noted that by repairing in the order of detection, the possibility of fault spread can be minimized, and the normal function of the storage chip can be gradually restored according to the severity of the fault and the priority of the repair, thereby improving the repair efficiency and ensuring data integrity and system stability.

[0105] In a possible implementation, S7 specifically includes:

[0106] The ECC of the memory chip is used to repair the detected faulty memory cells in the order in which they are detected.

[0107] Error Correction Code (ECC) is a coding technology used to detect and correct errors in stored data. In memory chips, ECC detects and corrects bit errors by adding redundant bits to the data. It can automatically correct some correctable errors, ensuring the accuracy of stored data. Common ECC technologies include BCH codes and LDPC codes.

[0108] By using ECC to repair faulty storage cells sequentially in the order they were detected during the repair process, the risk of extended faults can be minimized, prioritizing repairs of high-priority faulty areas. ECC effectively repairs minor errors, preventing data loss while minimizing the impact on other parts of the system, improving the reliability and repair efficiency of storage chips.

[0109] S8: Outputting the data loss detection result of the storage chip according to the number of faulty storage units that failed to be repaired.

[0110] It's important to note that the health of the memory chip is determined by the number of failed memory cells that have failed repair. If the number of failed cells exceeds a preset threshold, the system determines data loss; otherwise, the memory chip is normal. This helps quickly determine whether a memory chip has experienced a serious failure or data loss, ensuring system reliability and data security.

[0111] In a possible implementation, S8 specifically includes:

[0112] S801: When the number of failed storage units exceeds a preset number of failed storage units, it is determined that data in the storage chip is lost; otherwise, it is determined that the storage chip is normal.

[0113] It should be noted that those skilled in the art can set the size of the preset number of fault storage units according to actual needs, and the present invention does not limit this.

[0114] Specifically, the preset number of failed storage units may be set to the maximum number of bad blocks allowed by the storage chip controller, that is, the maximum number of failed storage units.

[0115] S802: Outputting whether the storage chip data is lost or the storage chip is normal as a data loss detection result.

[0116] It's important to note that by setting a threshold for the number of faulty memory cells, it's possible to effectively determine whether a memory chip has experienced a serious failure or data loss. When the number of faulty cells exceeds the preset threshold, the system automatically determines data loss, ensuring timely detection of unrecoverable failures. By properly setting the threshold, this method avoids misjudgments caused by individual minor faults, improves the accuracy and reliability of judgments, and facilitates rapid troubleshooting, ensuring stable system operation.

[0117] In practical applications, the memory chip's address mapping table is first obtained to determine the relationships between memory cells and calculate the strength of fault coupling between them. Next, this information is combined to establish a fault propagation model to assess the probability of memory cell failure. By calculating the steady-state solution of the fault propagation model and incorporating information entropy, potential fault areas are identified. After generating a differentiated detection path, priority detection is performed along this path, focusing on high-risk areas. After detecting a faulty memory cell, repairs are performed sequentially according to the order in which the faults were detected. Finally, the health of the memory chip is determined based on the number of memory cells that failed repair. If the number of cells that failed repair exceeds a preset threshold, data loss is considered. This process ensures accurate identification of the fault area, optimizes detection efficiency, and minimizes data loss.

[0118] In the embodiment of the present invention, by introducing the fault coupling strength and fault propagation model, the traditional fault detection method of the prior art that only relies on global traversal is solved, and the inefficiency problem caused by too wide a scanning range and too long a detection time is avoided. First, by obtaining the address mapping table of the memory chip and determining the fault coupling strength between the memory cells, the potential impact between the cells can be accurately identified, providing a basis for subsequent fault propagation modeling. Secondly, by combining the fault propagation model to calculate the steady-state solution and using information entropy to determine the fault area, high-risk areas can be accurately identified, thereby generating differentiated detection paths in a targeted manner and avoiding blind comprehensive scanning. Finally, the faulty storage cells are repaired in order according to the detected sequence, and the effect of the fault repair is output in combination with the detection results. This method not only improves the detection accuracy, but also greatly improves the detection efficiency, solves the problem of easily missed fault chains and coupling effects, and ensures more efficient, less damaged and more accurate detection of memory chip data loss.

[0119] Reference Manual Figure 2 , shows a structural diagram of a data loss detection system for a storage chip provided by an embodiment of the present invention.

[0120] The embodiment of the present invention provides a data loss detection system 20 for a storage chip, comprising: a processor 201 and a memory 202;

[0121] The memory 202 stores programs or instructions that can be run on the processor 201. When the programs or instructions are executed by the processor 201, the steps of the above-mentioned data loss detection method for the storage chip are implemented, and the same technical effect can be achieved. To avoid repetition, the present invention will not be repeated.

[0122] It should be understood that the processor 201 in the embodiment of the present invention may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0123] It should also be understood that the memory 202 in the embodiments of the present invention may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory may be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0124] The above embodiments can be implemented in whole or in part via software, hardware (e.g., circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. When loaded or executed on a computer, the processes or functions described in accordance with the embodiments of the present invention are fully or partially performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired means (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server or data center that contains a collection of one or more available media. The available medium can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media. The semiconductor media can be a solid-state drive.

[0125] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0126] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0127] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described equipment, devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0128] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interface, indirect coupling or communication connection of the device or unit, which can be electrical, mechanical or other forms.

[0129] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0130] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0131] If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0132] An embodiment of the present invention provides a readable storage medium including: a program or instruction stored on the readable storage medium, and when the program or instruction is executed by a processor, the steps of the above-mentioned storage chip data loss detection method are implemented, and the same technical effect can be achieved. To avoid repetition, the present invention will not be described in detail.

[0133] Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the embodiments of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they may still modify the technical solutions described in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and such modifications or replacements do not deviate from the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or replacements that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be covered by the scope of protection of the present invention.

Claims

1. A method for detecting data loss in a memory chip, characterized in that: include: S1: Obtaining the address mapping table of the memory chip; S2: Determine the fault coupling strength between any two storage cells in the storage chip in combination with the address mapping table; S3: Based on the fault coupling strength, a fault propagation model between different storage units is established that is related to the failure probability of the storage unit; S4: Calculating a steady-state solution of the fault propagation model and determining a potential fault area of the memory chip in combination with information entropy; S5: generating a differentiated detection path for the potential fault area; S6: Testing the memory chip according to the differentiated testing path; S7: Repairing the detected faulty storage units in the order of detection; S8: Outputting a data loss detection result of the memory chip according to the number of faulty memory cells that failed to be repaired; Wherein, the S2 specifically includes: S201: Acquire physical architecture information of the memory chip, wherein the physical architecture information includes a physical diffusion scale describing an influence range of a unit charge in a single memory cell; S202: Determine the physical three-dimensional coordinates of each storage unit in the storage chip based on the physical architecture information; S203: Establishing a directed acyclic graph of the memory chip based on the address mapping table, wherein the nodes of the directed acyclic graph are logical addresses of the memory units reflected in the address mapping table, the edges of the directed acyclic graph are mapping relationships between different memory units in the address mapping table, and the edge attributes are the number of historical interactions between the two memory units; S204: Calculating the fault coupling strength according to the physical diffusion scale of the memory chip and the directed acyclic graph; Wherein, the S4 specifically includes: S401: Acquire a faulty storage unit in the storage chip; S402: setting the storage unit failure probability of the faulty storage unit to 1 and substituting it into the fault propagation model to update the fault propagation model; S403: setting the updated fault propagation model equal to zero to obtain a steady-state solution corresponding to the faulty storage unit, wherein each of the steady-state solutions constitutes a steady-state distribution; S404: Determine a fault area discrimination threshold of the memory chip based on information entropy in combination with the steady-state solution; S405: retaining a target steady-state solution that is greater than the fault region discrimination threshold, and using a connected domain formed by storage units corresponding to the target steady-state solution as the potential fault region; The expression of the differential detection path is specifically: ； in, represents the differential detection path, Represents the set of candidate detection paths when the function takes the maximum value , Indicates the detection time length from the detection timestamp of storage unit p to storage unit q in the potential fault area to the current timestamp, represents the time decay factor, It represents the fault coupling strength between p and q.

2. The data loss detection method for a memory chip according to claim 1, wherein: The S3 specifically includes: S301: Calculate the three-dimensional Laplacian operator of the storage unit failure in the physical space to describe the physical layer diffusion intensity of the storage unit failure in the physical space: S302: Determine the logical layer diffusion strength of the storage unit fault in the logical space based on the fault coupling strength; S303: Determine the self-repair strength of the memory chip based on the error correction capability of the memory chip; S304: Obtain the fault propagation model by combining the physical layer diffusion strength, the logical layer diffusion strength, and the self-repair strength.

3. The data loss detection method for a memory chip according to claim 1, wherein: The S6 is specifically: The memory chip is tested according to the differentiated test path using test data, wherein the test data includes interleaved bit pattern data, zero-one data, deinterleaved bit pattern data, row-by-row inversion data pattern, and pseudo-random filling data.

4. The data loss detection method for a memory chip according to claim 1, wherein: The S7 is specifically: The detected faulty storage units are repaired in sequence according to the detection sequence through the ECC of the storage chip.

5. The data loss detection method for a memory chip according to claim 1, wherein: The S8 specifically includes: S801: If the number of failed storage units exceeds a preset number of failed storage units, determine that the storage chip data is lost; otherwise, determine that the storage chip is normal; S802: Outputting the data loss of the storage chip and the normal state of the storage chip as the data loss detection result.

6. A data loss detection system for a memory chip, characterized in that: include: processor and memory; The memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the data loss detection method for a memory chip according to any one of claims 1 to 5 are implemented.

7. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the data loss detection method for a storage chip according to any one of claims 1 to 5 are implemented.

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