Data interaction control method and device in uninterrupted system, equipment and storage medium

Abstract

A data interaction control method, apparatus and device in an uninterrupted system and a storage medium relate to the technical field of communications, slave devices in an upgrade state communicate with a master device based on a serial peripheral interface (SPI) communication protocol, and the method comprises the following steps: when a synchronous clock signal sent by the master device is received, sending current frame data to the master device; if a target sDMAC completion flag bit used for representing that the current frame of data is completely sent is polled, receiving target data sent by the master device, completing preparation work of the next frame of data to be sent, and performing level flipping on a general input / output port; and synchronizing the level flipping result of the general input / output port to the master device, so that the master device performs interaction of next frame data with the slave device based on the level flipping result. According to the method and the device, normal data interaction between the master equipment such as the MCU chip and the slave equipment such as other integrated chips can be ensured under the condition that whether the polling time is changed or not.

Description

Technical Field

[0001] The present application relates to the field of communication technologies, and in particular, to a method, device, equipment, and storage medium for data interaction control in a non-interrupt system. Background Art

[0002] In the project of upgrading MCU (Microcontroller Unit) chips such as RH850, vector (which is a supplier of the automotive open system architecture Autosar) provides a non-interrupt system to ensure the stability and security of the upgrade process. Among them, when the MCU chip communicates with other integrated chips such as the SOC (System on Chip) during the upgrade process, data interaction is often achieved through the SPI (Serial Peripheral Interface) communication method. In SPI communication, the MCU chip usually acts as a slave device, while other integrated chips act as master devices.

[0003] In the related art, for the non-interrupt MCU chip upgrade scenario, when the MCU chip acts as a slave device and communicates with the master device through SPI, it is necessary to poll the completion flag bit of the sDMAC (Direct Memory Access Controller) at a preset polling time to determine whether to receive the current frame data and prepare the next frame of data to be sent according to the polling result. Among them, the polling time must be less than the sending time of the master device to ensure that when the master device sends the synchronous clock signal, the slave device has prepared the next frame of data. However, when the operating load in the system becomes high, it will cause the polling time to change, that is, there is a problem that the actual polling time is inconsistent with the preset polling time, resulting in the inability to timely prepare the next frame of data to be sent, and further causing errors in the SPI logic that cannot be recovered, thereby preventing normal data interaction between the slave device and the master device.

[0004] It can be seen that how to ensure that the MCU chip can perform normal data interaction with other integrated chips regardless of whether the polling time changes is an urgent problem to be solved currently. Summary of the Invention

[0005] The present application provides a method, device, equipment, and storage medium for data interaction control in a non-interrupt system, which can solve the technical problem in the prior art that normal data interaction between chips cannot be performed due to the change of the polling time.

[0006] In a first aspect, an embodiment of the present application provides a method for controlling data interaction in a non-interrupt system. The method for controlling data interaction in the non-interrupt system is applied to a slave device in an upgrade state. The slave device communicates with a master device based on the Serial Peripheral Interface (SPI) communication protocol. The method includes the following steps:

[0007] When receiving a synchronous clock signal sent by the master device, send the current frame data to the master device;

[0008] If the target sDMAC completion flag bit is polled, receive the target data sent by the master device and complete the preparation work for the next frame of data to be sent, and flip the level of the General-Purpose Input / Output (GPIO) port. The target sDMAC completion flag bit is used to indicate that the current frame of data has been sent;

[0009] Synchronize the level flip result of the General-Purpose Input / Output (GPIO) port to the master device for the master device to perform the interaction of the next frame of data with the slave device based on the level flip result.

[0010] In combination with the first aspect, in an implementation, the flipping of the level of the General-Purpose Input / Output (GPIO) port includes:

[0011] If the current level state of the General-Purpose Input / Output (GPIO) port is low level, flip the current level state from low level to high level;

[0012] If the current level state of the General-Purpose Input / Output (GPIO) port is high level, flip the current level state from high level to low level.

[0013] In combination with the first aspect, in an implementation, the master device performs the interaction of the next frame of data with the slave device based on the level flip result, including:

[0014] The master device determines whether the level flip result is the same as the previous level state;

[0015] If they are not the same, it is determined that the level of the General-Purpose Input / Output (GPIO) port has been flipped, and then send the next frame of target data and a new synchronous clock signal to the slave device for the slave device to control the sending of the next frame of data to be sent and the reception of the next frame of target data based on the new synchronous clock signal;

[0016] If they are the same, it is determined that the level of the General-Purpose Input / Output (GPIO) port has not been flipped, and then continue to obtain a new level flip result from the slave device.

[0017] Second aspect, an embodiment of the present application provides a data interaction control device in a non-interrupt system. The data interaction control device in the non-interrupt system includes a slave device in an upgrade state. The slave device communicates with a master device based on the Serial Peripheral Interface (SPI) communication protocol. The slave device is configured to:

[0018] When receiving a synchronous clock signal sent by the master device, send the current frame data to the master device;

[0019] If the target sDMAC completion flag bit is polled, receive the target data sent by the master device and complete the preparation work for the next frame of data to be sent, and perform a level inversion on the General-Purpose Input / Output (GPIO) port. The target sDMAC completion flag bit is used to indicate that the current frame of data has been sent;

[0020] Synchronize the level inversion result of the GPIO port to the master device for the master device to perform the interaction of the next frame of data with the slave device based on the level inversion result.

[0021] In combination with the second aspect, in an implementation, the slave device is specifically configured to:

[0022] If the current level state of the GPIO port is low level, invert the current level state from low level to high level;

[0023] If the current level state of the GPIO port is high level, invert the current level state from high level to low level.

[0024] In combination with the second aspect, in an implementation, the master device is specifically configured to:

[0025] Determine whether the level inversion result is the same as the previous level state;

[0026] If not the same, determine that the GPIO port has been level-inverted, and send the next frame of target data and a new synchronous clock signal to the slave device for the slave device to control the sending of the next frame of data to be sent and the reception of the next frame of target data based on the new synchronous clock signal;

[0027] If the same, determine that the GPIO port has not been level-inverted, and continue to obtain a new level inversion result from the slave device.

[0028] Third aspect, an embodiment of the present application provides a data interaction control method in a non-interrupt system. The data interaction control method in the non-interrupt system is applied to a master device. The master device communicates with a slave device in an upgrade state based on the Serial Peripheral Interface (SPI) communication protocol. The master device is configured to:

[0029] Send target data and a synchronization clock signal to the slave device for the slave device to send current frame data based on the synchronization clock signal, and when polling the target sDMAC completion flag bit, receive the target data and complete the preparation for the next frame of data to be sent, and at the same time perform a level inversion on the general-purpose input / output port, where the target sDMAC completion flag bit is used to indicate that the current frame of data has been sent;

[0030] When receiving the level inversion result of the general-purpose input / output port, perform the interaction of the next frame of data with the slave device based on the level inversion result.

[0031] Combined with the third aspect, in an embodiment, the performing a level inversion on the general-purpose input / output port includes:

[0032] If the current level state of the general-purpose input / output port is low level, the slave device controls the current level state to flip from low level to high level;

[0033] If the current level state of the general-purpose input / output port is high level, the slave device controls the current level state to flip from high level to low level.

[0034] Combined with the third aspect, in an embodiment, the performing the interaction of the next frame of data with the slave device based on the level inversion result includes:

[0035] Determine whether the level inversion result is the same as the previous level state;

[0036] If they are not the same, it is determined that the general-purpose input / output port has performed a level inversion, and then send the next frame of target data and a new synchronization clock signal to the slave device for the slave device to control the sending of the next frame of data to be sent and the reception of the next frame of target data based on the new synchronization clock signal;

[0037] If they are the same, it is determined that the general-purpose input / output port has not performed a level inversion, and then continue to obtain a new level inversion result from the slave device.

[0038] Fourth aspect, an embodiment of the present application provides a data interaction control device in a non-interrupt system. The data interaction control device in the non-interrupt system includes a master device. The master device communicates with a slave device in an upgrade state based on the Serial Peripheral Interface (SPI) communication protocol. The master device is used for:

[0039] Send target data and a synchronization clock signal to the slave device for the slave device to send current frame data based on the synchronization clock signal. When polling the target sDMAC completion flag bit, receive the target data and complete the preparation for the next frame of data to be sent, and at the same time perform a level inversion on the general-purpose input / output port. The target sDMAC completion flag bit is used to indicate that the current frame of data has been sent;

[0040] When receiving the level inversion result of the general-purpose input / output port, perform the interaction of the next frame of data with the slave device based on the level inversion result.

[0041] Combined with the fourth aspect, in an embodiment, the slave device is specifically configured to:

[0042] If the current level state of the general-purpose input / output port is low level, control the current level state to flip from low level to high level;

[0043] If the current level state of the general-purpose input / output port is high level, control the current level state to flip from high level to low level.

[0044] Combined with the fourth aspect, in an embodiment, the master device is specifically configured to:

[0045] Judge whether the level inversion result is the same as the previous level state;

[0046] If they are not the same, it is determined that the general-purpose input / output port has performed a level inversion, and then send the next frame of target data and a new synchronization clock signal to the slave device for the slave device to control the sending of the next frame of data to be sent and the reception of the next frame of target data based on the new synchronization clock signal;

[0047] If they are the same, it is determined that the general-purpose input / output port has not performed a level inversion, and then continue to obtain a new level inversion result from the slave device.

[0048] Fifth aspect, an embodiment of the present application provides a data interaction control device in a non-interrupt system. The data interaction control device in the non-interrupt system includes a processor, a memory, and a non-interrupt system data interaction control program stored on the memory and executable by the processor. When the non-interrupt system data interaction control program is executed by the processor, the steps of the non-interrupt system data interaction control method as described above are implemented.

[0049] Sixth aspect, an embodiment of the present application provides a computer-readable storage medium. A non-interrupt system data interaction control program is stored on the computer-readable storage medium. When the non-interrupt system data interaction control program is executed by a processor, the steps of the non-interrupt system data interaction control method as described above are implemented.

[0050] The beneficial effects brought by the technical solutions provided in the embodiments of the present application include:

[0051] For slave devices such as MCU chips that are upgraded based on a non-interrupt system, they communicate with master devices such as other integrated chips through the Serial Peripheral Interface (SPI) communication protocol. When receiving the synchronous clock signal sent by the master device, they send the current frame data to the master device; at the same time, they monitor whether the sending of the current frame data is completed. When polling the target sDMAC completion flag bit indicating that the current frame data has been sent, they receive the target data sent by the master device and complete the preparation work for the next frame of data to be sent, and flip the level of the General-Purpose Input / Output (GPIO) port to control the interaction of the next frame of data between the master device and the slave device through the level flip result; it can be seen that the master device in the present application must wait until receiving the level flip result indicating that the next frame of data to be sent is ready before interacting with the slave device for a new frame of data. Therefore, it is not necessary to require that the polling time must be less than the sending time of the master device, that is, whether the polling time changes will not affect the normal interaction between the master device and the slave device. Therefore, the present application controls the slave device to be ready for the next frame of data when the master device sends the synchronous clock signal through the flip of the GPIO, thereby ensuring that the MCU chip can perform normal data interaction with other integrated chips regardless of whether the polling time changes. Description of the Drawings

[0052] Figure 1 It is a schematic flowchart of the first embodiment of the data interaction control method in the non-interrupt system of the present application;

[0053] Figure 2 It is a schematic flowchart of the specific control process of data interaction in the non-interrupt system involved in the solution of the embodiment of the present application;

[0054] Figure 3 It is a schematic flowchart of the second embodiment of the data interaction control method in the non-interrupt system of the present application;

[0055] Figure 4 It is a schematic hardware structure diagram of the data interaction control device in the non-interrupt system involved in the solution of the embodiment of the present application. Detailed Embodiments

[0056] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the following will further describe the embodiments of this application in detail with reference to the accompanying drawings.

[0058] In a first aspect, an embodiment of this application provides a method for controlling data interaction in a non-interrupt system.

[0059] In one embodiment, referring to Figure 1 , Figure 1 is a schematic flowchart of the first embodiment of the method for controlling data interaction in the non-interrupt system of this application. As Figure 1 shown, the method for controlling data interaction in the non-interrupt system is applied to a slave device in an upgrade state. The slave device communicates with a master device based on the Serial Peripheral Interface (SPI) communication protocol, and includes the following steps:

[0060] Step S10: When receiving a synchronous clock signal sent by the master device, send the current frame data to the master device.

[0061] Exemplarily, it should be understood that the specific objects of the slave device and the master device in this embodiment can be determined according to actual needs, as long as it satisfies that the slave device is controlled for upgrade based on the non-interrupt system and needs to perform data interaction with the master device through SPI communication technology. For example, an MCU chip upgraded based on the non-interrupt system is used as the slave device, and another integrated chip (such as an SOC chip) that realizes interaction with the MCU chip based on SPI communication technology is used as the master device.

[0062] Referring to Figure 2 shown, since the master device and the slave device communicate through SPI, it is necessary to perform SPI initialization processing on the master device and the slave device respectively. It should be noted that the methods and principles of SPI initialization are well-known common knowledge in the art, and will not be elaborated here for the sake of simplicity of description. In addition, for the slave device, it will control the reception of data and the preparation of the next frame of data by configuring sDMAC. Therefore, sDMAC enable needs to be configured during SPI initialization; then initialize the functional modules, such as setting SPI to polling mode, and calling Autosar MCAL (Microcontroller Abstraction Layer) interfaces (such as Spi_SetupEB and Spi_AsyncTransmit, etc.) to prepare for data transmission, and the next transmission can be triggered through the callback mechanism in MCAL; at the same time, the current frame data to be sent to the master device needs to be prepared.

[0063] For the master device, after completing the SPI initialization, it will prepare to send data and send the target data to the slave device through SPI communication after the preparation is completed. Specifically, first, the CS (Chip Select) line is pulled low to request communication with the slave device, the target data is transmitted to the slave device through the MOSI (Master Out Slave In) line, and at the same time, a synchronous clock signal is sent to the slave device through the clock line CLK so that the slave device can transmit the current frame data to the master device based on this synchronous clock signal through the MISO (Master In Slave Out) line.

[0064] Step S20: If the target sDMAC completion flag bit is polled, receive the target data sent by the master device and complete the preparation for the next frame of data to be sent, and invert the level of the general-purpose input / output port. The target sDMAC completion flag bit is used to indicate that the current frame of data has been sent.

[0065] Exemplarily, it should be noted that during the above SPI communication process, when the slave device completes the transmission of the current frame of data, an sDMAC completion flag bit will be generated to indicate that the current frame of data has been sent. Therefore, in this embodiment, it will poll whether the target sDMAC completion flag bit is generated according to a preset polling time (such as 1 ms). If the target sDMAC completion flag bit is not polled, it means that the current frame of data has not been sent yet, and the polling continues. If the target sDMAC completion flag bit is polled, it means that the slave device has sent all the current frame of data to the master device. Then, receive the target data sent by the master device, prepare to re-call the Autosar MCAL interface, and at the same time prepare the next frame of data to be sent. It should be understood that the target data refers to the current frame of data that the master device needs to send to the slave device.

[0066] It should be understood that for a traditional master device, when it starts to send a synchronous clock signal to the slave device, it starts to receive the current frame of data sent by the slave device, and after the synchronous clock signal is sent, it ends the data reception. Then, it performs relevant processing such as parsing and verifying the received current frame of data and waits for a preset duration (such as 5 ms) to ensure that the data can be processed normally. For example, when the waiting duration reaches 5 ms, it means that the data has been processed, and then it will perform the interaction of the next frame of data, that is, start to send the next frame of data and a new synchronous clock signal to the slave device.

[0067] In summary, the time for the slave device to process SPI is the time when the synchronous clock signal is output and the polling time. And when there is a synchronous clock signal output from SPI, the slave device must prepare the next frame of data to be sent. Therefore, the polling time must be less than the transmission time on the master device side (i.e., the preset duration). Thus, in the traditional solution, the polling time is set to be less than the preset duration. Based on this, when the traditional master device performs the next frame of data interaction, it does not care whether the slave device has prepared the next frame of data to be sent, because it defaults that the polling time of the slave device is less than the transmission time of the master device, that is, the master device defaults that the slave device has prepared the next frame of data to be sent when it sends the synchronous clock signal. However, when the operating load in the system becomes high, it often causes the polling time to change, that is, there is a problem that the actual polling time is inconsistent with the preset polling time, so that the slave device cannot complete the preparation of the next frame of data to be sent in time. In other words, when the master device sends a new synchronous clock signal, the slave device has not prepared the next frame of data to be sent, which leads to an error in the SPI logic and cannot be recovered, thus resulting in abnormal data interaction between the slave device and the master device.

[0068] To solve the above problems, after the slave device in this embodiment completes the preparation of the next frame of data to be sent, it will invert the level of the GPIO to represent the processing ability of the slave device through the inversion of the GPIO, thereby avoiding the influence of the polling time on the next frame of data interaction. Specifically, if the GPIO level is inverted, it means that the slave device has prepared the next frame of data to be sent, and at this time, the master device can interact with the slave device for the next frame of data; if the GPIO level is not inverted, it means that the slave device has not prepared the next frame of data to be sent, and at this time, the master device does not interact with the slave device for the next frame of data. It should be understood that one level inversion represents that the slave device has processed one frame of data. Therefore, the processing speed of the slave device can be characterized by the number of level inversions within a time period, that is, the more the number of level inversions within a time period, the faster the processing speed of the slave device.

[0069] Further, in one embodiment, the inverting the level of the general-purpose input / output port includes:

[0070] If the current level state of the general-purpose input / output port is low level, then invert the current level state from low level to high level;

[0071] If the current level state of the general-purpose input / output port is high level, then invert the current level state from high level to low level.

[0072] Exemplarily, in this embodiment, for the GPIO level inversion operation, it is mainly to perform the conversion between high and low levels. That is, if the current level state of the GPIO is low level, then the current level state is inverted from low level to high level; and if the current level state of the GPIO is high level, then the current level state is inverted from high level to low level. For example, assume that the current level state of the GPIO is low level. If the slave device is ready for the next frame of data to be sent, it means that a level inversion is required, then the GPIO is pulled high so that the level state of the GPIO changes from low level to high level; and if the slave device has not been ready for the next frame of data to be sent, then the GPIO is not pulled high so that the GPIO remains in the low level state.

[0073] Step S30: Synchronize the level inversion result of the general-purpose input / output port to the master device for the master device to interact with the slave device for the next frame of data based on the level inversion result.

[0074] Exemplarily, in this embodiment, since the GPIO communication between the master device and the slave device is in a direct connection state, the master device will poll the level inversion result of the GPIO of the slave device, that is, the level state of the GPIO of the slave device will be synchronized to the master device in real time. Among them, after the master device waits for a preset duration of 5 ms, if it detects that the GPIO of the slave device has been level-inverted, it means that the slave device already has the ability to interact for the next frame of data, that is, the slave device is ready for the next frame of data to be sent. At this time, the master device will interact with the slave device for the next frame of data; and if it does not detect that the GPIO has been level-inverted, it means that the slave device does not yet have the ability to interact for the next frame of data, that is, the slave device is not ready for the next frame of data to be sent. At this time, the master device does not interact with the slave device for the next frame of data and continues to wait for the preset duration until it detects that the GPIO has been level-inverted and then interacts for the next frame of data to ensure that there are no errors in the SPI logic, so that normal data interaction can occur between the slave device and the master device.

[0075] It can be seen that the master device in this embodiment must receive the level inversion result indicating that the next frame of data to be sent is ready before interacting with the slave device for a new frame of data. Therefore, there is no need to require that the polling time must be less than the transmission time of the master device, that is, whether the polling time changes will not affect the normal interaction between the master device and the slave device. Therefore, in this embodiment, only one GPIO inversion can be used to control the slave device to be ready for the next frame of data when the master device sends a synchronous clock signal, thereby ensuring that the MCU chip can interact normally with other integrated chips regardless of whether the polling time changes, and effectively reducing the resource occupation of the GPIO on the master and slave devices.

[0076] Further, in one embodiment, the master device interacts with the slave device for the next frame of data based on the level inversion result, including:

[0077] The master device determines whether the level inversion result is the same as the previous level state;

[0078] If they are not the same, it is determined that the general-purpose input / output port has undergone a level inversion, and then the master device sends the next frame of target data and a new synchronization clock signal to the slave device, so that the slave device controls the transmission of the next frame of data to be sent and the reception of the next frame of target data based on the new synchronization clock signal;

[0079] If they are the same, it is determined that the general-purpose input / output port has not undergone a level inversion, and then the master device continues to obtain a new level inversion result from the slave device.

[0080] Exemplarily, as shown in Figure 2 The master device synchronously receives the GPIO level inversion result and compares it with the previous level state; if the two are not the same (for example, the currently received GPIO level inversion result is high level while the previous level state is low level), it indicates that the GPIO has undergone a level inversion, and then the master device sends the next frame of target data and a new synchronization clock signal to interact with the slave device for the next frame of data; while if the two are the same (for example, both the currently received GPIO level inversion result and the previous level state are low level), it indicates that the GPIO has not undergone a level inversion, and then the master device does not send the next frame of target data and a new synchronization clock signal to the slave device, but continues to wait for a preset duration and resynchronizes the GPIO level inversion result to ensure that there are no errors in the SPI logic.

[0081] In a second aspect, an embodiment of the present application further provides a data interaction control device in a non-interrupt system.

[0082] In one embodiment, the data interaction control device in the non-interrupt system includes a slave device in an upgrade state. The slave device communicates with the master device based on the Serial Peripheral Interface (SPI) communication protocol. The slave device is used for:

[0083] When receiving the synchronization clock signal sent by the master device, sending the current frame of data to the master device;

[0084] If the target sDMAC completion flag bit is polled, receiving the target data sent by the master device and completing the preparation work for the next frame of data to be sent, and performing a level inversion on the general-purpose input / output port. The target sDMAC completion flag bit is used to indicate that the current frame of data has been sent;

[0085] Synchronize the level inversion result of the general-purpose input / output port to the master device for the master device to interact with the slave device for the next frame of data based on the level inversion result.

[0086] Further, in one embodiment, the slave device is specifically configured to:

[0087] If the current level state of the general-purpose input / output port is low level, invert the current level state from low level to high level;

[0088] If the current level state of the general-purpose input / output port is high level, invert the current level state from high level to low level.

[0089] Further, in one embodiment, the master device is specifically configured to:

[0090] Determine whether the level inversion result is the same as the previous level state;

[0091] If not, determine that the general-purpose input / output port has undergone a level inversion, and send the next frame of target data and a new synchronization clock signal to the slave device for the slave device to control the transmission of the next frame of data to be sent and the reception of the next frame of target data based on the new synchronization clock signal;

[0092] If the same, determine that the general-purpose input / output port has not undergone a level inversion, and continue to obtain a new level inversion result from the slave device.

[0093] Wherein, the function implementation of each part in the data interaction control device in the above non-interrupt system corresponds to each step in the data interaction control method embodiment in the above non-interrupt system, and its function and implementation process will not be elaborated here one by one.

[0094] In a third aspect, an embodiment of the present application provides another data interaction control method in a non-interrupt system.

[0095] In one embodiment, refer to Figure 3 , Figure 3 is a schematic flowchart of the second embodiment of the data interaction control method in the non-interrupt system of the present application. As Figure 3 shown, the data interaction control method in the non-interrupt system is applied to a master device, and the master device communicates with a slave device in an upgrade state based on the Serial Peripheral Interface (SPI) communication protocol. The master device is used for:

[0096] Step N10: Send the target data and the synchronization clock signal to the slave device for the slave device to send the current frame of data based on the synchronization clock signal. When polling the target sDMAC completion flag bit, receive the target data and complete the preparation for the next frame of data to be sent, and at the same time perform a level inversion on the general-purpose input / output port. The target sDMAC completion flag bit is used to indicate that the current frame of data has been sent.

[0097] Exemplarily, it should be understood that the specific objects of the slave device and the master device in this embodiment can be determined according to actual needs, as long as the slave device is upgraded and controlled based on a non-interrupt system and needs to perform data interaction with the master device through SPI communication technology. For example, an MCU chip upgraded based on a non-interrupt system can be used as the slave device, and other integrated chips (such as an SOC chip) that implement interaction with the MCU chip based on SPI communication technology can be used as the master device.

[0098] See Figure 2 As shown, since the master device and the slave device communicate through SPI, the SPI initialization process needs to be performed on the master device and the slave device respectively. It should be noted that the methods and principles of SPI initialization are well-known common knowledge in the art and will not be elaborated here for the sake of simplicity. In addition, for the slave device, it will control the data reception and the preparation of the next frame of data by configuring sDMAC. Therefore, the sDMAC enable needs to be configured during SPI initialization; then initialize the functional modules, such as setting SPI to polling mode and calling Autosar MCAL (Microcontroller Abstraction Layer) interfaces (such as Spi_SetupEB and Spi_AsyncTransmit, etc.) to prepare for data transmission, and the next transmission can be triggered through the callback mechanism in MCAL; at the same time, the current frame of data to be sent to the master device needs to be prepared.

[0099] For the master device, after completing the SPI initialization, it will prepare to send data and send the target data to the slave device through SPI communication after the preparation is completed. It should be understood that the target data refers to the current frame of data that the master device needs to send to the slave device; specifically, first, pull down the CS line to request communication with the slave device, transmit the target data to the slave device through the MOSI line, and at the same time send the synchronization clock signal to the slave device through the clock line CLK so that the slave device can transmit the current frame of data to the master device based on this synchronization clock signal and through the MISO line.

[0100] After the slave device finishes sending the current frame of data, an sDMAC completion flag bit will be generated to indicate that the current frame of data has been sent; therefore, in this embodiment, it will poll at a preset polling time (such as 1 ms) to check whether the target sDMAC completion flag bit is generated. If the target sDMAC completion flag bit is not polled, it means that the current frame of data has not been sent yet, and then continue to poll; if the target sDMAC completion flag bit is polled, it means that the slave device has sent all the current frame of data to the master device, then receive the target data sent by the master device, and prepare to re - call the Autosar MCAL interface, and at the same time prepare the next frame of data to be sent.

[0101] It should be understood that when the master device starts to send the synchronous clock signal to the slave device, it starts to receive the current frame of data sent by the slave device, and after the synchronous clock signal is sent, it ends the data reception; then parse, verify and perform other related processing on the received current frame of data and wait for a preset duration (such as 5 ms) to ensure that the data can be processed normally.

[0102] To solve the technical problem that normal data interaction between chips cannot be carried out due to the change of the polling time, after the slave device in this embodiment finishes preparing the next frame of data to be sent, it will flip the level of the GPIO to represent the processing ability of the slave device through the flipping of the GPIO, thereby avoiding the influence of the polling time on the next - frame data interaction. Specifically, if the GPIO level is flipped, it means that the slave device has prepared the next frame of data to be sent, and at this time the master device can interact with the slave device for the next frame of data; if the GPIO level is not flipped, it means that the slave device has not prepared the next frame of data to be sent, and at this time the master device does not interact with the slave device for the next frame of data. It should be understood that one level flip represents that the slave device has processed one frame of data, so the processing speed of the slave device can be represented by the number of level flips within a time period, that is, the more the number of level flips within a time period, the faster the processing speed of the slave device.

[0103] Step N20: When receiving the level - flip result of the general - purpose input - output port, interact with the slave device for the next frame of data based on the level - flip result.

[0104] Exemplarily, in this embodiment, since the GPIO communication between the master device and the slave device is in a direct connection state, the master device polls the GPIO level inversion result of the slave device, that is, the GPIO level state of the slave device is synchronously updated to the master device in real time. Among them, after the master device waits for a preset duration of 5 ms, if it detects that the GPIO of the slave device has undergone a level inversion, it indicates that the slave device already has the ability to interact with the next frame of data, that is, the slave device is ready for the next frame of data to be sent. At this time, the master device will interact with the slave device for the next frame of data; if it does not detect that the GPIO has undergone a level inversion, it indicates that the slave device does not yet have the ability to interact with the next frame of data, that is, the slave device is not ready for the next frame of data to be sent. At this time, the master device does not interact with the slave device for the next frame of data and continues to wait for the preset duration until it detects that the GPIO has undergone a level inversion and then interacts with the next frame of data to ensure that there are no errors in the SPI logic, so that normal data interaction can occur between the slave device and the master device.

[0105] It can be seen that the master device in this embodiment must receive the level inversion result indicating that the next frame of data to be sent is ready before interacting with the slave device for a new frame of data. Therefore, there is no need to require that the polling time must be less than the transmission time of the master device, that is, whether the polling time changes will not affect the normal interaction between the master device and the slave device. Therefore, in this embodiment, only a GPIO inversion can be used to control the slave device to be ready for the next frame of data when the master device sends a synchronous clock signal, thereby ensuring that the MCU chip can interact normally with other integrated chips regardless of whether the polling time changes, and effectively reducing the resource occupancy of the GPIO on the master and slave devices.

[0106] Further, in one embodiment, the level inversion of the general-purpose input / output port includes:

[0107] If the current level state of the general-purpose input / output port is low level, the slave device controls the current level state to invert from low level to high level;

[0108] If the current level state of the general-purpose input / output port is high level, the slave device controls the current level state to invert from high level to low level.

[0109] Exemplarily, in this embodiment, for the level inversion operation of the GPIO, it is mainly to perform the conversion between high and low levels. That is, if the current level state of the GPIO is low level, then the current level state is inverted from low level to high level; and if the current level state of the GPIO is high level, then the current level state is inverted from high level to low level. For example, assume that the current level state of the GPIO is low level. If the slave device is ready for the next frame of data to be sent, it means that a level inversion is required, then the GPIO is pulled high so that the level state of the GPIO changes from low level to high level; and if the slave device has not been ready for the next frame of data to be sent, then the GPIO is not pulled high so that the GPIO remains in the low level state.

[0110] Further, in one embodiment, the interacting with the slave device for the next frame of data based on the level inversion result includes:

[0111] Determine whether the level inversion result is the same as the previous level state;

[0112] If they are not the same, it is determined that the general input / output port has undergone a level inversion, and then the next frame of target data and a new synchronization clock signal are sent to the slave device for the slave device to control the sending of the next frame of data to be sent and the reception of the next frame of target data based on the new synchronization clock signal;

[0113] If they are the same, it is determined that the general input / output port has not undergone a level inversion, and then continue to obtain a new level inversion result from the slave device.

[0114] Exemplarily, as shown in Figure 2 As shown, the master device synchronously receives the GPIO level inversion result and compares it with the previous level state; if the two are not the same (for example, the currently received GPIO level inversion result is high level while the previous level state is low level), it means that the GPIO has undergone a level inversion, then the next frame of target data and a new synchronization clock signal are sent to the slave device to interact with the slave device for the next frame of data; and if the two are the same (for example, both the currently received GPIO level inversion result and the previous level state are low level), it means that the GPIO has not undergone a level inversion, then the next frame of target data and a new synchronization clock signal are not sent to the slave device, but instead wait for a preset duration and resynchronize the GPIO level inversion result to ensure that there are no errors in the SPI logic.

[0115] Fourthly, the embodiments of the present application also provide another data interaction control device in a non-interrupt system.

[0116] In one embodiment, the data interaction control device in the interruption-free system includes a master device. The master device communicates with a slave device in an upgrade state based on the Serial Peripheral Interface (SPI) communication protocol. The master device is configured to:

[0117] Send target data and a synchronization clock signal to the slave device for the slave device to send current frame data based on the synchronization clock signal. When polling the target sDMAC completion flag bit, receive the target data and complete the preparation for the next frame of data to be sent, and at the same time, perform a level inversion on the general-purpose input / output port. The target sDMAC completion flag bit is used to indicate that the current frame of data has been sent.

[0118] When receiving the level inversion result of the general-purpose input / output port, perform the interaction of the next frame of data with the slave device based on the level inversion result.

[0119] Further, in one embodiment, the slave device is specifically configured to:

[0120] If the current level state of the general-purpose input / output port is low level, control the current level state to flip from low level to high level;

[0121] If the current level state of the general-purpose input / output port is high level, control the current level state to flip from high level to low level.

[0122] Further, in one embodiment, the master device is specifically configured to:

[0123] Judge whether the level inversion result is the same as the previous level state;

[0124] If not the same, it is determined that the general-purpose input / output port has performed a level inversion, and then send the next frame of target data and a new synchronization clock signal to the slave device for the slave device to control the sending of the next frame of data to be sent and the reception of the next frame of target data based on the new synchronization clock signal;

[0125] If the same, it is determined that the general-purpose input / output port has not performed a level inversion, and then continue to obtain a new level inversion result from the slave device.

[0126] Wherein, the function implementation of each part in the above data interaction control device in the interruption-free system corresponds to each step in the embodiment of the data interaction control method in the above interruption-free system, and its function and implementation process will not be elaborated here one by one.

[0127] Fifth aspect, an embodiment of the present application provides a data interaction control device in a non-interrupt system. The data interaction control device in the non-interrupt system can be a device with data processing functions such as a personal computer (PC), a laptop computer, a server, etc.

[0128] Referring to Figure 4 , Figure 4 FIG. is a schematic diagram of the hardware structure of the data interaction control device in the non-interrupt system involved in the embodiment solution of the present application. In the embodiment of the present application, the data interaction control device in the non-interrupt system may include a processor, a memory, a communication interface, and a communication bus.

[0129] Among them, the communication bus can be of any type and is used to interconnect the processor, the memory, and the communication interface.

[0130] The communication interface includes interfaces such as input / output (I / O) interfaces, physical interfaces, and logical interfaces for realizing the interconnection of internal devices of the data interaction control device in the non-interrupt system, and interfaces for realizing the interconnection of the data interaction control device in the non-interrupt system with other devices (such as other computing devices or user devices). The physical interface can be an Ethernet interface, an optical fiber interface, an ATM interface, etc.; the user device can be a display screen (Display), a keyboard (Keyboard), etc.

[0131] The memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical memory, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0132] The processor can be a general-purpose processor. The general-purpose processor can call the data interaction control program stored in the memory and execute the data interaction control method provided by the embodiment of the present application. For example, the general-purpose processor can be a central processing unit (CPU). Among them, the method executed when the data interaction control program in the non-interrupt system is called can refer to the various embodiments of the data interaction control method in the non-interrupt system of the present application, which will not be elaborated here.

[0133] Those skilled in the art can understand, Figure 4The hardware structure shown does not limit the present application, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0134] In a sixth aspect, an embodiment of the present application further provides a computer-readable storage medium.

[0135] A data interaction control program in the interruption-free system is stored on the readable storage medium of the present application. When the data interaction control program in the interruption-free system is executed by a processor, the steps of the data interaction control method in the interruption-free system as described above are implemented.

[0136] Among them, the method implemented when the data interaction control program in the interruption-free system is executed can refer to the various embodiments of the data interaction control method in the interruption-free system of the present application, which will not be elaborated here.

[0137] It should be noted that the serial numbers of the above embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments.

[0138] The terms "including" and "having" and any variations thereof in the description of the specification, claims and drawings of the present application are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or devices. The descriptions of terms such as "first", "second" and "third" are used to distinguish different objects, etc., and do not represent a sequence, nor do they limit that "first", "second" and "third" are different types.

[0139] In the description of the embodiments of the present application, terms such as "exemplary", "for example" or "for instance" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary", "for example" or "for instance" in the embodiments of the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of terms such as "exemplary", "for example" or "for instance" is intended to present relevant concepts in a specific manner.

[0140] In the description of the embodiments of the present application, unless otherwise specified, " / " means "or". For example, A / B may mean A or B; "and / or" in the text is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B may mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present application, "a plurality of" means two or more than two.

[0141] In some of the processes described in the embodiments of the present application, there are multiple operations or steps that appear in a specific order. However, it should be understood that these operations or steps may not be executed in the order in which they appear in the embodiments of the present application or may be executed in parallel. The serial numbers of the operations are only used to distinguish different operations, and the serial numbers themselves do not represent any order of execution. In addition, these processes may include more or fewer operations, and these operations or steps may be executed in sequence or in parallel, and these operations or steps may be combined.

[0142] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-described embodiment methods can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases, the former is a better implementation method. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art can be embodied in the form of a software product. This computer software product is stored in a storage medium as described above (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions for causing a terminal device to execute the methods described in the various embodiments of the present application.

[0143] The above are only the preferred embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A data interaction control method in an uninterrupted system, characterized in that: The data interaction control method in the non-interruptible system is applied to a slave device in an upgrade state, wherein the slave device communicates with the master device based on a serial peripheral interface SPI communication protocol, and the method comprises the following steps: When receiving the synchronization clock signal sent by the master device, sending the current frame data to the master device; If the target sDMAC completion flag is polled, the target data sent by the master device is received and the preparation work for the next frame of data to be sent is completed, and the level of the general input and output port is flipped. The target sDMAC completion flag is used to indicate that the current frame data has been sent; The level flip result of the general input / output port is synchronized to the master device, so that the master device interacts with the slave device for the next frame of data based on the level flip result.

2. The data interaction control method in the non-interruption system according to claim 1, characterized in that: The level flipping of the general input and output port includes: If the current level state of the general input / output port is a low level, flipping the current level state from a low level to a high level; If the current level state of the general input / output port is a high level, the current level state is flipped from a high level to a low level.

3. The data interaction control method in the non-interruption system according to claim 1, characterized in that: The master device interacts with the slave device for the next frame of data based on the level flip result, including: The master device determines whether the level flip result is the same as the previous level state; If they are not the same, it is determined that the universal input / output port has been level-flipped, and the next frame of target data and a new synchronization clock signal are sent to the slave device, so that the slave device can control the sending of the next frame of data to be sent and the receiving of the next frame of target data based on the new synchronization clock signal; If they are the same, it is determined that the universal input / output port has not been level-flipped, and a new level-flip result continues to be obtained from the slave device.

4. A data interaction control device in an uninterrupted system, characterized in that: The data interaction control device in the non-interruptible system includes a slave device in an upgrade state, the slave device communicates with the master device based on a serial peripheral interface SPI communication protocol, and the slave device is used to: When receiving the synchronization clock signal sent by the master device, sending the current frame data to the master device; If the target sDMAC completion flag is polled, the target data sent by the master device is received and the preparation work for the next frame of data to be sent is completed, and the level of the general input and output port is flipped. The target sDMAC completion flag is used to indicate that the current frame data has been sent; The level flip result of the general input / output port is synchronized to the master device, so that the master device interacts with the slave device for the next frame of data based on the level flip result.

5. A data interaction control method in an uninterrupted system, characterized in that: The data interaction control method in the non-interruptible system is applied to a master device, the master device communicates with a slave device in an upgrade state based on a serial peripheral interface SPI communication protocol, and the master device is used to: Sending target data and a synchronous clock signal to the slave device, so that the slave device can send the current frame data based on the synchronous clock signal, and when polling the target sDMAC completion flag, receiving the target data and completing the preparation of the next frame of data to be sent, and at the same time performing a level flip on the general input and output port, the target sDMAC completion flag is used to indicate that the current frame data has been sent; When the level flip result of the general input / output port is received, the next frame of data is interacted with the slave device based on the level flip result.

6. The data interaction control method in the non-interruption system according to claim 5, characterized in that: The level flipping of the general input and output port includes: If the current level state of the general input / output port is a low level, the slave device controls the current level state to flip from a low level to a high level; If the current level state of the general input / output port is a high level, the slave device controls the current level state to flip from a high level to a low level.

7. The data interaction control method in the non-interruption system according to claim 5, characterized in that: The interacting with the slave device for the next frame of data based on the level flip result includes: Determine whether the level flip result is the same as the previous level state; If they are not the same, it is determined that the universal input / output port has been level-flipped, and the next frame of target data and a new synchronization clock signal are sent to the slave device, so that the slave device can control the sending of the next frame of data to be sent and the receiving of the next frame of target data based on the new synchronization clock signal; If they are the same, it is determined that the universal input / output port has not been level-flipped, and a new level-flip result continues to be obtained from the slave device.

8. A data interaction control device in an uninterrupted system, characterized in that: The data interaction control device in the non-interruptible system includes a master device, the master device communicates with a slave device in an upgrade state based on a serial peripheral interface SPI communication protocol, and the master device is used to: Sending target data and a synchronous clock signal to the slave device, so that the slave device can send the current frame data based on the synchronous clock signal, and when polling the target sDMAC completion flag, receiving the target data and completing the preparation of the next frame of data to be sent, and at the same time performing a level flip on the general input and output port, the target sDMAC completion flag is used to indicate that the current frame data has been sent; When the level flip result of the general input / output port is received, the next frame of data is interacted with the slave device based on the level flip result.

9. A data interaction control device in an uninterrupted system, characterized in that: The data interaction control device in the non-interruption system includes a processor, a memory, and a data interaction control program in the non-interruption system stored in the memory and executable by the processor, wherein when the data interaction control program in the non-interruption system is executed by the processor, the steps of the data interaction control method in the non-interruption system as described in any one of claims 1 to 3 and 5 to 7 are implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a data interaction control program in an uninterruptible system, wherein when the data interaction control program in an uninterruptible system is executed by a processor, the steps of the data interaction control method in an uninterruptible system as described in any one of claims 1 to 3 and 5 to 7 are implemented.

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