Communication system for SPI (Serial Peripheral Interface) master device and multiple different slave devices

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By using a tri-state gate module and an enable signal generation module in the communication system between the SPI master device and multiple slave devices, only one slave device communicates with the master device MCU at any given time, while other slave devices remain in a high-impedance state. This solves the problems of communication complexity and low efficiency in the prior art and improves system efficiency.

CN223808730UActive Publication Date: 2026-01-16TIANJING AVIATION ELECTRO-MECHANICAL CO LTD

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Patent Information

Application Number: CN202520322076.X
Authority / Receiving Office: CN · China
Patent Type: Utility models(China)
Current Assignee / Owner
Filing Date: 2025-02-26
Publication Date: 2026-01-16
Estimated Expiration: 2035-02-26

AI Technical Summary

Technical Problem

Existing SPI master-slave device communication control methods are complex, have low device efficiency, and suffer from data interference problems.

Method used

A tri-state gate module is used to interlock the output signals of multiple slave devices, and an enable signal generation module is used to ensure that only one slave device communicates with the master device MCU at any given time, while other slave devices remain in a high-impedance state.

Benefits of technology

This effectively avoids mutual interference between data and improves the efficiency of the communication system.

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Abstract

The utility model belongs to the field of electrical technology, and particularly relates to a communication system of SPI (Serial Peripheral Interface) master equipment and a plurality of different slave equipment. Comprising a master device MCU, n slave devices, n three-state gates, n NOT gates and an enable signal generation module, and an SPICLK clock port of the master device MCU is connected with clock ports of the slave devices; the SPISIMO output port of the MCU of the master device is respectively connected with the input port of each slave device; an I / O port of the MCU of the master device is connected with an input port of the enable signal generation module for generating enable signals of the slave devices; the enabling port of each slave device is connected with the input end of the corresponding NOT gate, the output end of the NOT gate is connected with the enabling end of the corresponding three-state gate, and the output end of the slave device is connected with the input end of the three-state gate; and the output end of each three-state gate is connected with the SPISOMI input end of the main equipment MCU.

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Description

TECHNICAL FIELD

[0001] The utility model belongs to electrical technical field, more particularly to a kind of communication system of SPI master device and multiple different slave devices. BACKGROUND

[0002] SPI (Serial Peripheral Interface) is a kind of high-speed synchronous serial input / output interface, allow 1~16 bits of data stream to be exchanged between device and device, usually used for microcontroller and different peripheral device (for example, AD converter, 429 communication chip etc.) or different microcontroller communication. To effectively realize the communication of SPI master device and multiple different slave devices, the existing SPI master-slave device communication control method is more complex, and the device failure rate is high. UTILITY MODEL CONTENT

[0003] The utility model aims at providing a kind of communication system of SPI master device and multiple different slave devices, solve the problem that the existing SPI master-slave device communication control method is more complex, and the device failure rate is high.

[0004] Technical scheme:

[0005] A kind of communication system of SPI master device and multiple different slave devices, including master device MCU, n slave devices, n tristate gate, n non-gate and enable signal generation module, wherein, the clock port of master device MCU SPICLK is connected respectively with the clock port of each slave device;The input port of each slave device is connected respectively with the SPISIMO output port of master device MCU;The input port of enable signal generation module is connected with the I / O port of master device MCU for generating the enable signal of each slave device;The enable port of each slave device is connected with the input end of corresponding non-gate, the output end of non-gate is connected with the enable end of corresponding tristate gate, and the output end of tristate gate is connected with the input end of slave device;The output end of each tristate gate is connected with the SPISOMI input end of master device MCU.

[0006] Further, enable signal generation module is 1 or more decoder, realize only one slave device enable signal effective at the same time.

[0007] Further, enable signal generation module generates multiple enable signals by master device MCU, realizes only one slave device enable signal effective at the same time.

[0008] Further, tristate gate, non-gate, enable signal generation module are realized by programmable logic array.

[0009] Further, the model of tristate gate is 74HC125.

[0010] Further, the enable signal generation module signal is 54HC138.

[0011] Advantages:

[0012] The output signals of the plurality of different slave devices are interlocked and logically set by the tri-state gate module, so that only one slave device communicates with the master device MCU at the same time, and the outputs of other slave devices remain in a high impedance state, effectively avoiding mutual interference between data. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 A communication system of an SPI master device and a plurality of different slave devices. DETAILED DESCRIPTION

[0014] The utility model provides a kind of communication system of SPI master device and multiple different slave devices, the output signal of plurality of different slave devices is interlocked and logically set by tri-state gate module, guarantee only one slave device with master device MCU communication at the same time, and the output of other slave devices remains in a high impedance state, effectively avoid mutual interference between data.

[0015] As Figure 1 As shown in a kind of communication system of SPI master device and multiple different slave devices, including master device MCU, n slave devices, n tri-state gates, n non-gates and enable signal generation module, wherein the clock port of master device MCU SPICLK is respectively connected the clock port of each slave device;The input port of each slave device is respectively connected the SPISIMO output port of master device MCU;The input port of enable signal generation module is connected the I / O port of master device MCU for generating the enable signal of each slave device;The enable port of each slave device is connected the input end of corresponding non-gate, the output end of non-gate is connected the enable end of corresponding tri-state gate, and the output end of tri-state gate is connected the input end of slave device;The output end of each tri-state gate is connected the SPISOMI input end of master device MCU.

[0016] Specifically as Figure 1As shown, the SPICLK clock signal of the master MCU is connected to the clock signal CLK_1 of the slave device 1, the clock signal CLK_2 of the slave device 2, and the clock signal CLK_n of the slave device n; the SPISIMO output signal of the master MCU is connected to the input signal DI_1 of the slave device 1, the input signal DI_2 of the slave device 2, and the input signal DI_n of the slave device n; the enable signal CS_1 of the slave device 1, the enable signal CS_2 of the slave device 2, and the enable signal CS_n of the slave device n are generated by the master MCU control enable signal generation module; the enable signal CS_1 of the slave device 1 is connected to the tri-state gate module through the NOT gate module, and the output signal DO_1 of the slave device 1 is connected to the SPISOMI input signal of the master MCU through the tri-state gate module; the enable signal CS_2 of the slave device 2 is connected to the tri-state gate module through the NOT gate module, and the output signal DO_2 of the slave device 2 is connected to the SPISOMI input signal of the master MCU through the tri-state gate module; the enable signal CS_n of the slave device n is connected to the tri-state gate module through the NOT gate module, and the output signal DO_n of the slave device n is connected to the SPISOMI input signal of the master MCU through the tri-state gate module.

[0017] The NOT gate module performs a NOT logic operation on the enable signal of the slave device and connects the control enable end of the tri-state gate module, so that the control enable end of the tri-state gate module is high valid on the premise that the enable signal of the slave device is low valid.

[0018] The tri-state gate module connects the output signal of the slave device to the input signal of the master MCU through the tri-state gate module; when the enable signal of one of the slave devices is low valid, the control enable end of the tri-state gate module connected to the slave device is high valid through the NOT gate module, so that the output signal of the slave device is connected to the input signal of the master MCU, and only one slave device communicates with the master MCU at the same time, and the output of the other slave devices remains in a high impedance state.

[0019] The enable signal generation module generates the enable signal CS_1 of the slave device 1, the enable signal CS_2 of the slave device 2, and the enable signal CS_n of the slave device n by receiving the master MCU signal; the enable signal generation module is one or more decoders, or multiple enable signals generated by the master MCU, to ensure that only one enable signal of the slave device is valid at the same time.

[0020] As shown in Table 1, only when the enable signal CS_1 of the slave device 1 is valid, the SPISOMI input signal of the master MCU is the output signal DO_1 of the slave device 1.

[0021] Table 1: Truth table for communication with slave device 1

[0022]

[0023] As shown in Table 2, the SPISOMI input signal of the master MCU is the output signal DO_2 of the slave device 2 only when the enable signal CS_2 of the slave device 2 is valid.

[0024] Table 2 "Communication with slave device 2" truth table

[0025]

[0026] As shown in Table 3, the SPISOMI input signal of the master MCU is the output signal DO_n of the slave device n only when the enable signal CS_n of the slave device n is valid.

[0027] Table 3 "Communication with slave device n" truth table

[0028]

[0029] A communication method of an SPI master device and a plurality of different slave devices, the method being performed by means of the above-mentioned communication system of an SPI master device and a plurality of different slave devices, the method comprising:

[0030] Step 1: The enable signal generation module generates a plurality of enable signals to control each slave device respectively, and the plurality of enable signals realize that only one enable signal of a slave device is valid at the same time, and the valid enable signal is low;

[0031] Step 2: The control enable end of the tri-state gate connected to the slave device with a valid enable signal is high, and the output signal of the slave device with a valid enable signal is input to the input end of the master MCU,

[0032] The control enable end of the tri-state gate connected to the slave device with an invalid enable signal is low, and the output of the slave device with an invalid enable signal becomes a high impedance state;

[0033] Realize that only one slave device communicates with the master MCU at the same time, and the outputs of other slave devices remain in a high impedance state.

Claims

1. A communication system of an SPI master device with a plurality of different slave devices, characterized in that The master device MCU, n slave devices, n tri-state gates, n non-gates and an enable signal generation module are included, wherein the SPICLK clock port of the master device MCU is connected with the clock port of each slave device; the SPISIMO output port of the master device MCU is connected with the input port of each slave device; the I / O port of the master device MCU is connected with the input port of the enable signal generation module for generating the enable signal of each slave device; the enable port of each slave device is connected with the input port of the corresponding non-gate, the output port of the non-gate is connected with the enable port of the corresponding tri-state gate, and the output port of the slave device is connected with the input port of the tri-state gate; the output port of each tri-state gate is connected with the SPISOMI input port of the master device MCU.

2. The SPI master device and multiple different slave device communication system of claim 1, wherein, The enable signal generation module is one or more decoders, which realize that only one enable signal of the slave device is valid at the same time.

3. The SPI master device and multiple different slave device communication system of claim 1, wherein, The enable signal generation module generates multiple enable signals through the master device MCU, and realizes that only one enable signal of the slave device is valid at the same time.

4. The SPI master device and multiple different slave device communication system of claim 1, wherein, The tri-state gate, the non-gate and the enable signal generation module are realized through a programmable logic array.

5. The SPI master device and multiple different slave device communication system of claim 1, wherein, The model of the tri-state gate is 74HC125.

6. The SPI master device and multiple different slave device communication system of claim 1, wherein, The signal of the enable signal generation module is 54HC138.